sata_mv.c revision b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 434a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6) Add port multiplier support (intermediate) 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 454a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 464a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 728d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 74a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 75f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 76f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 78193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 796c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 831fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 96615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 97615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 98615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 103522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 104bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 105bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 121da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORTS_PER_HC = 4, 12520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 12620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 12731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_MASK = 3, 12920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 136c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 137bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 138bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 144e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 145c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 151c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 152c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 15931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 182646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_ERR = (1 << 0), /* shift by port # */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_DONE = (1 << 1), /* shift by port # */ 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 195fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 196fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 202fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 203e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 20520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 207fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 208fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 21531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_DMA_DONE = (1 << 0), /* shift by port # */ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2260c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 227e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 231e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 232e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 234e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 235c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 236c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 237c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 239bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 240bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2440c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2450c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2460c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2470c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2480c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 249e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 250e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2546c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2556c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2566c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2576c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 260c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 261c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 263c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 268646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 270646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 271646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 272646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 273646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2866c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 287c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 288c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX, 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 295bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 296bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 297bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 298bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3016c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 309e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3176c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 32631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3330ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3340ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3360ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 33720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 339bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 340bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 34131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 34231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 34347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 34447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 34547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 34647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 347e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3480ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3490ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3500ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 35102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 35220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 35331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3540ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 355721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 35620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 35720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 358ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 359ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 362bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 363095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 364baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 365baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 366baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 367baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 368095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3690ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3700ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3710ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 372095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 373095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3740ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 375095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 376095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 377095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 378522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 379522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 380522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 381522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 382522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 383522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 384e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 385e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 387522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 388522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 38931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 39031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 391e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 392e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 393e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 394e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 39531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 39620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 398e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 399e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 400e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 401e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 402e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 40531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 40631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 407e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 41020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 41120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 41331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 41831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 42131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 42431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 425eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 426eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 43131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 43231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 434bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 435bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 436bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 437bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 438bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 43902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 44002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 44102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 44202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 446f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 44702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 44802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 44902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 450da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 451da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 452da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 453da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 454da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 455da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 456da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 457da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 46047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4612a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4622a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 46347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 46447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 46547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 466c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 467c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 47047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 47147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 472da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 473da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 474da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 475da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 47631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 47831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 479e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4809a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 481a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_prereset(struct ata_link *link, unsigned long deadline); 482a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 483a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 484a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic void mv_postreset(struct ata_link *link, unsigned int *classes); 485bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 486bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 487f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 48820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4892a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 4902a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 49147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 49247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 49347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 494c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 495c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 496522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 4977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 49847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 4992a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5002a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 50347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 504c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 505c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 506522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 507f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 508f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 509f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 510f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 511f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 512f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 513f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 514f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 515f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 517e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 518c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 519e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 520b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 521e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 52247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 523eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 524eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 525eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 526eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 527c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 52868d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 529baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 530c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 531c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 532c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 533c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 53468d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 535138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 536baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 53720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 53820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 53920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 540029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 541029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 542c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 543c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 544c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 545c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 548a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .prereset = mv_prereset, 549a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 550a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .postreset = mv_postreset, 551a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 552029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 554c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 555c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 556c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 558c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 559c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 560c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 561029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 562029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 563138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .qc_defer = ata_std_qc_defer, 564029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = mv6_dev_config, 56520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 56620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 56720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 569029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 570029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 571029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 572e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 573e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 574e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 57598ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 57620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 577cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 57831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 579bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 580c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 58220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 583c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 58431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 585bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 586c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 58847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 589c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 59047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 591bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 592c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 59347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 595138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 596138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 59731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 598bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 599c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 602c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 603138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 60431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 605bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 606c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 608e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 609138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 610138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 611e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 612bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 613e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 614e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 616138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 617138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 618e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 619bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 621e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .flags = MV_COMMON_FLAGS | MV_FLAG_SOC, 624f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .pio_mask = 0x1f, /* pio0-4 */ 625f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .udma_mask = ATA_UDMA6, 626f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .port_ops = &mv_iie_ops, 627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 62820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 62920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6303b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6312d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6322d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6332d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6342d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 635cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 636cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 637cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6382d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6392d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6402d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6412d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6422d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6432d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6442d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6452d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6462d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 647d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 648d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 649d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 65002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6516a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6526a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 65302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 65402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 65502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 65602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6572d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 65820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 66047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 66147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 66247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 66347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 66447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 665522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 666522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 66747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 66847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 66947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 67047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 67147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 67247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 67347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 674522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 675522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 67647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 67747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 679f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 68720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 68820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 69220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 69420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 69520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 69620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 69820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 69920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 70020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 70120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 702c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 703c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 704c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 705c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 706c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 707c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 708c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 709c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 710c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 711c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 712c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 713c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 714c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 715c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 716c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 717c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 720c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7218b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 722c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 725e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 726e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 727e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 728e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 729e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 730e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 731e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 732e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 73920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 74020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 74220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 74320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 744cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 74531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 746cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 74731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 74831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 749c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 750c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 751c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 752c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 753bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 755c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 756c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 757c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 758bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 760c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 761c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 763c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 764c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 765c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 766bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 767c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 768c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 770c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 771c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 772c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 773c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; 775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 776c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 777c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 778c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 779c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 781c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 782c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 784c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 786c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 787c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 788c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 78905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 79005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 79105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 79205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 79305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 794beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 795beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 79605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 79705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 79805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 79905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8000c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 801721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 80220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 803721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 804721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 805721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 806721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 807721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 808b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 809721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8110c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 8120c58912e192fc3a4835d772aafa40b72552b819fMark Lord int hard_port = mv_hardport_from_port(ap->port_no); 8130c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 8140fca0d6f2ce3336022a22bc7fc2e009e599e63a4Saeed Bishara mv_host_base(ap->host), hard_port); 8150c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8160c58912e192fc3a4835d772aafa40b72552b819fMark Lord 817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 818f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8200c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8210c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 8220c58912e192fc3a4835d772aafa40b72552b819fMark Lord ipending = (DEV_IRQ << hard_port) | 8230c58912e192fc3a4835d772aafa40b72552b819fMark Lord (CRPB_DMA_DONE << hard_port); 8240c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8250c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8260c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8270c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8280c58912e192fc3a4835d772aafa40b72552b819fMark Lord 829e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8300c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8310c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8320c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8330c58912e192fc3a4835d772aafa40b72552b819fMark Lord 834f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 835bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 836f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 837afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 838afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 839f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 84020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 84120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 84205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 843e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 844b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 84505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 84705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 849b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 85020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 851b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 85231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 853b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 854b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 8558b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 856b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 857b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 858b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 8594537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 860b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 861b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 86231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 863b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 86420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 866e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 8670ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 868b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 869b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 8700ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 871b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 872b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 873b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 874b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 875b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 876b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 877b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 878b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 8790ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 8800ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 8818a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 88231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 88320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 88431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 88531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 88631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 88731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 8882dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 88931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 89031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 89131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 89231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 89331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 8948a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 8958a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 89631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 89731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 89831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 89931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 90031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 90131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 90231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 90331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9042dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9052dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 90631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 90731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 90831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 90931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 91131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 91231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 91331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 91431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 91531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9168b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 91731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 91831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 91931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 92231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 92331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 92431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 92731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 92831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 92931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9308b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 93231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 93331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 94031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 943d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 94431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 94531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9492dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 9512dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 95331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 95520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 95620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 95720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 95820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 95920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 96020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 96120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 96220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 96320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 96420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 96520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 96620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 96720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 96820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 96920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 97020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 97120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 97220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 97320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 97420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 97520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 97620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 977da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 97820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 97920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 98020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 981da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 982da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 983da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 984da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 985da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 98620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 98720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 988da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 98920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 99020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 99120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 992da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 99320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 994da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 995da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 996da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 99720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 99820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 999f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1000f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1001f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1002f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1003f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1004f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1005f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->flags & ATA_DFLAG_NCQ) 1006f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->max_sectors > ATA_MAX_SECTORS) 1007f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord adev->max_sectors = ATA_MAX_SECTORS; 1008f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1009f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1010e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1011e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10120c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1013e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1014e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1015e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1016e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1017e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 10180c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1019e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10200c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1021e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1022e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10230c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1024e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1025e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1026e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1027e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1028e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1029e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1030e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1031e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1032e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1033721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1034721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1035721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1036721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1037721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1038721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1039e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1040e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1041e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1042da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1043da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1044da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1045da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1046eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1047da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1048da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1049da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1050da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1051da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1052da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1053da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1054da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1055da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1056eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1057eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1058eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1059eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1060eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1061eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1062eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1063eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1064eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1065eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1066eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1067eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1068da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1069da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1070da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 107105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 107205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 107305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 107405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 107505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 107605b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 107705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 107805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 107905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 108005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 108131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 108231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1083cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1084cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 108531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 108631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 10870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik unsigned long flags; 1088dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 108931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 109024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 10916037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 109224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1093da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 109431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1095da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1096da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1097da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1098da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 109931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1100da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1101da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1102da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1103da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 110431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1105eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1106eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1107eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1108eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1109eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1110eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1111eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1112eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1113eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1114eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1115eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1116eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1117eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1118eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1119eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 112031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11210ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_lock_irqsave(&ap->host->lock, flags); 11220ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1123e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, 0); 1124c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik mv_set_edma_ptrs(port_mmio, hpriv, pp); 112531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_unlock_irqrestore(&ap->host->lock, flags); 11270ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 112831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Don't turn on EDMA here...do it before DMA commands only. Else 112931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * we'll be unable to send non-data, PIO, etc due to restricted access 113031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * to shadow regs. 113131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 113231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1133da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1134da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1135da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1136da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 113731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 113831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 113905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 114105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 114205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 114405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1146cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 114831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 114931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1150e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1151da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 115231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 115331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 115505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 115605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 115705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 115805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 115905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 116105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 116205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 11636c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 116431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 116531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1166972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 11673be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1168ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 116931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1170eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1171ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1172d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1173d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 117422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 11764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 11774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 117822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 11804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 11814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 11834007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 11846c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 11854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11864007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 11874007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 11884007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11893be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 11904007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 11914007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 119231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 11933be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 11943be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 11953be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 119631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 119731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11985796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 119931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1200559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 120131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1202559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 120331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 120431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 120505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 120605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 120705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 120805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 121005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 121105b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 121205b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 121305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 121505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 121605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 121731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 121831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 121931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 122031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1221e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 122231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 122331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1224a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1226138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1227138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 122831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 122920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 123131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1232e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 123331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1234beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 123631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1237bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1238bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1239a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1240a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1241eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1242a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1243eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1244a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 124531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1246a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 125420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 125531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1260c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 126231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 12658b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1290e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1291e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1292e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1293e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1294e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1295e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1296e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1297e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1298e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1299e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1300e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1301e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1302e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1303e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1304e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1305e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1306e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1307e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1308e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1309e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1311e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1312e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1313a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1314e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1315e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1316138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1317138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1318e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1319e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1320e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1321e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1322e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1323e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1324beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1325e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 13268c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1327e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1328bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1329bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1330a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1331a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1332eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1333eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1334e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1335e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1336e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1337e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1338e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1339e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1340e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1341e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1342e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1343e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1344e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1345e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1346e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1347e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1348e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1349e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1350e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1351e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1352e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 135931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 136031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 136131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 136231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 136305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 136405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 136505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 136605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 136705b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 136805b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 136905b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 137005b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 137105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 137305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 137405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13759a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 137631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1377c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1378c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1379c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 138131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1382138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1383138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 138431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* We're about to send a non-EDMA capable command to the 138531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 138631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 138731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1388b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 138931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return ata_qc_issue_prot(qc); 139031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 139131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1392721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1393bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1394bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->req_idx++; 139531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1396bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 139731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 139831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1399bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1400bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 140131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 140231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 140331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 140431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 140505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 140605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 140705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 14089b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 140905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 141005b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1411e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1412e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1413e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1414e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 141505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 141605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 141705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 141805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1419bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 142031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 142131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1423bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 14279af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 142820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 143020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1434bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1435936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1436936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 143720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause); 1442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * all generations share these EDMA error cause bits 1445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 14506c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1453cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1454b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1459b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1460cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1463ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1466bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 14675ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1469b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1470bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1472bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 14755ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1476bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1477b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1478bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1479bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1480bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1481936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1482936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1483bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1484cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1485bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1486afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 148720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 148820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 14893606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 149020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1491bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1492bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1493cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1495bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1496bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1497bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1498bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1502bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1504bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1505bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1507bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1510bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_pio(struct ata_port *ap) 1511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1512bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1513bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u8 ata_status; 1514bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1515bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* ignore spurious intr if drive still BUSY */ 1516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_status = readb(ap->ioaddr.status_addr); 1517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(ata_status & ATA_BUSY)) 1518bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1519bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1520bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get active ATA command */ 15219af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(!qc)) /* no active tag */ 1523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ 1525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= ac_err_mask(ata_status); 1529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_edma(struct ata_port *ap) 1533bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1537bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 out_index, in_index; 1539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get h/w response queue pointer */ 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1545bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik while (1) { 1546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u16 status; 15476c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1548bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get s/w response queue last-read pointer, and compare */ 1550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (in_index == out_index) 1552bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 1553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1554bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 50xx: get active ATA command */ 15550ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik if (IS_GEN_I(hpriv)) 15569af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik /* Gen II/IIE: get active ATA command via tag, to enable 15596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * support for queueing. this works transparently for 15606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * queued and non-queued modes. 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 15628c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord else 15638c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik qc = ata_qc_from_tag(ap, tag); 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1567cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord /* For non-NCQ mode, the lower 8 bits of status 1568cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * are from EDMA_ERR_IRQ_CAUSE_OFS, 1569cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * which should be zero if all went well. 1570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik status = le16_to_cpu(pp->crpb[out_index].flags); 1572cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) { 1579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= 1580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); 1581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15840ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* advance software response queue pointer, to 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * indicate (after the loop completes) to hardware 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * that we have consumed a response queue entry. 1587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->resp_idx++; 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik (out_index << EDMA_RSP_Q_PTR_SHIFT), 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 159620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 159720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 159805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 159905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1600cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 160105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @relevant: port error bits relevant to this host controller 160205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @hc: which host controller we're to look at 160305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 160405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read then write clear the HC interrupt status then walk each 160505b308e1df6d9d673daedb517969241f41278b52Brett Russ * port connected to the HC and see if it needs servicing. Port 160605b308e1df6d9d673daedb517969241f41278b52Brett Russ * success ints are reported in the HC interrupt status reg, the 160705b308e1df6d9d673daedb517969241f41278b52Brett Russ * port error ints are reported in the higher level main 160805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt status register and thus are passed in via the 160905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 'relevant' argument. 161005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 161105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 161205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 161305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1614cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 161520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 161820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 161920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 hc_irq_cause; 1620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int port, port0, last_port; 162120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1622351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik if (hc == 0) 162320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = 0; 1624351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik else 162520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = MV_PORTS_PER_HC; 162620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) 1628f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + MV_PORTS_PER_HC; 1629f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 1630f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + hpriv->n_ports; 163120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* we'll need the HC success int register in most cases */ 163220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!hc_irq_cause) 1634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 163720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 163820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 16392dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik hc, relevant, hc_irq_cause); 164020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16418f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu for (port = port0; port < last_port; port++) { 1642cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 16438f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik int have_err_bits, hard_port, shift; 164555d8ca4f8094246da6e71889a4e04bfafaa78b10Jeff Garzik 1646bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) 1647a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1648a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik 16498f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu pp = ap->private_data; 16508f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu 165131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ shift = port << 1; /* (port * 2) */ 1652e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord if (port >= MV_PORTS_PER_HC) 165320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ shift++; /* skip bit 8 in the HC Main IRQ reg */ 1654e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 1655bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik have_err_bits = ((PORT0_ERR << shift) & relevant); 1656bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1657bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(have_err_bits)) { 1658bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 16598b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 16609af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1663bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1664bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1666bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hard_port = mv_hardport_from_port(port); /* range 0..3 */ 1669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1670bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) 1672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_edma(ap); 1673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((DEV_IRQ << hard_port) & hc_irq_cause) 1675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_pio(ap); 167620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 167720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 167820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("EXIT\n"); 167920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 168020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1681bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1682bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 168302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1684bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 169002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1693bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1695bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1696bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1697bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 169802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1699bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1700bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1701bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1702936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17039af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1704bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1705bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1706bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1709cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17109af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1717bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1718bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1719bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1720bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 172105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1722c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 172305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 172405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 172505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 172605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 172705b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 172805b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 172905b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 173005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 17318b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1732cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 173305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 173405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17357d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 173620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1737cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 173920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int hc, handled = 0, n_hcs; 1740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 1741646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord u32 irq_stat, irq_mask; 174220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1743e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Note to self: &host->lock == &ap->host->lock == ap->lock */ 1744646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 1746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_stat = readl(hpriv->main_cause_reg_addr); 1747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_mask = readl(hpriv->main_mask_reg_addr); 174820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 174920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* check the cases where we either have nothing pending or have read 175020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * a bogus register value which can indicate HW removal or PCI fault 175120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1752646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat)) 1753646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord goto out_unlock; 175420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1755cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik n_hcs = mv_get_hc_count(host->ports[0]->flags); 175620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (unlikely((irq_stat & PCI_ERR) && HAS_PCI(host))) { 1758bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_pci_error(host, mmio); 1759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 1760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik goto out_unlock; /* skip all other HC irq handling */ 1761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 176320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hcs; hc++) { 176420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); 176520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ if (relevant) { 1766cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik mv_host_intr(host, relevant, hc); 1767bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 176820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 176920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1770615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikout_unlock: 1772cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 177320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 177420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 177520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 177620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1777c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1778c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1779c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1780c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1781c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1782c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1783c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1784c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1785c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1786c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1787c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1788c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1789c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1790c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1791c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1792c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1793c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1794da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1795c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1796f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1797f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 17980d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1799c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1800c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1801da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1802da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1803da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1804da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1805da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1806c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1807c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1808da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1809c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18120d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1813c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1814c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1815da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18160d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1817da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1818da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1819da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1820c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1821c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1823522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1825522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1826522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 182744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1828522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1829522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1830522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1831522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1832522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1833522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1834522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 18357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1836522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1837522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1838522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1839522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1840522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1841522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1842522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 184347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1844ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1845ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1846c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1847c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1848c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1849c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1850c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1851c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1853ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1854ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 185547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1856ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1857522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1858522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1859522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1860522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1861522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1862522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1863522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1864522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1865522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1866ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1867ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 18682a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 18692a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1870bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1872c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1873c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1874c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1875c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1876c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1877c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1880c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1881c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1882c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1883c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1884c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1892bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1893bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1895c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1896c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1897c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1898c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1899c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1900c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1901c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1902b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 1903b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 1904b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 1905b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 1906b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 1907b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma_engine(port_mmio); 1908e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1909c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1910c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1911c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1912c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1913c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1914c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1915c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1916c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1917c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1918c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1919c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1920c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1921c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1922c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1923c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1924c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1925c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1926c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1927c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1928c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 192947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 1930c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1931c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1932c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1933c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 1934c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 1935c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 1936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 1937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 1941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 1949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 195947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 196047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 1961101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1962101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 19637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 1964101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 196502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1966101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 1967101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1968101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 1969101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 1970101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 1971101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1972101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 1973101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 1974101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 1975101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 1976101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 197702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 197802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 1979101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 1980101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 1981101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 1982101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 1983101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 1984101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1985101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1986101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1987101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 1988101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 1989101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1990101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 1991101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1992101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 1993101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 1994101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 1995101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 1996101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 1997101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1998101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 1999101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2000101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2001101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2002101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2003101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2004101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2005101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2006101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2009101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2010101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2011101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2012101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2013101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2014101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2015101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2016101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2017101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2018101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2019101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2020101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2021101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2022101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20232dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2024101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2025101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2026101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2027101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2028101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2029101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2030101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2031101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2033101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2034101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2035101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2036101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2041101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2042101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2049101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 206247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2063ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2064ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2065ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2066ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2067ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2068ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2069ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 207047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2071ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2072ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2073ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2074ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2075ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2076ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2077ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2078ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2079ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2080ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2081ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 208247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2083ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 208447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2085ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2086ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 20882a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2089bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2090c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2091c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2092bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 209347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 209447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2095bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 209647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 209747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 209847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 209947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 210047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 210147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 210247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 210347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 210447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 210547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 210647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 210747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 210847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 210947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 211047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 211247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 211347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 211547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 211647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 211747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 211847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2119bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2120bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 212147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2122bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2123bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 212447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 212547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2126e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2127bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2128e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2129bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2130bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2131bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 213247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 213347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2135bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2136bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2137bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2138bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2139bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2140bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 21412a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 21422a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 214347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2144bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2145e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2146e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2147e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2148e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2149e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2150e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2151bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2152bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2153bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2154f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2155f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2156f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2157f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2158f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2159f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2160f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2161f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2165f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2166f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2168f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2169f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2173f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2178f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2179f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2180f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2181f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2182b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 2183b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 2184b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 2185b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 2186b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2187b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma_engine(port_mmio); 2188e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2191f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2192f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2193f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2195f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2196f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2197f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2202f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2203f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2204f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2210f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2214f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2215f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2216f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2217f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2245b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lordstatic void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2246b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 2247b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2248b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2249b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2250b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 2251b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2252b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2253b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2254b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2255b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord/* 2256b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * Caller must ensure that EDMA is not active, 2257b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * by first doing mv_stop_edma() where needed. 2258b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2259e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2260c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2261c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2262c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2263c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2264c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2265c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2266b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 2267b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* Enable 3.0gb/s link speed */ 2268b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord mv_setup_ifctl(port_mmio, 1); 2269c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2270b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 2271b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * Strobing ATA_RST here causes a hard reset of the SATA transport, 2272b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2273b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2274c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2275b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2276b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2277c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2278c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2279c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2280c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2281ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2282c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2283c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2284c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 228505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2286bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * mv_phy_reset - Perform eDMA reset followed by COMRESET 228705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 228805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 228905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Part of this is taken from __sata_phy_reset and modified to 229005b308e1df6d9d673daedb517969241f41278b52Brett Russ * not sleep since this routine gets called from interrupt level. 229105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 229205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 229305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. This is coded to safe to call at 229405b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt level, i.e. it does not sleep. 229531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 2296bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_phy_reset(struct ata_port *ap, unsigned int *class, 2297bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 229820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2299095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik struct mv_port_priv *pp = ap->private_data; 2300cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 230120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 230222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik int retry = 5; 230322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik u32 sstatus; 230420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 230520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); 230620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2307da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#ifdef DEBUG 2308da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo { 2309da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo u32 sstatus, serror, scontrol; 2310da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 2311da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_STATUS, &sstatus); 2312da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_ERROR, &serror); 2313da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_CONTROL, &scontrol); 2314da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " 23152d79ab8fd7a7bf3a45d0e948ae27b3dd95ce95eaSaeed Bishara "SCtrl 0x%08x\n", sstatus, serror, scontrol); 2316da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 2317da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#endif 231820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 231922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* Issue COMRESET via SControl */ 232022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzikcomreset_retry: 2321936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x301); 2322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(1); 232322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2324936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x300); 2325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(20); 232622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 232731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ do { 2328936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_STATUS, &sstatus); 232962f1d0e6de138b91d55fbd7d579c837ed62e9e31Andres Salomon if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0)) 233031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 233122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2332bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(1); 2333c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik } while (time_before(jiffies, deadline)); 233420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 233522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* work around errata */ 2336ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_II(hpriv) && 233722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && 233822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik (retry-- > 0)) 233922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik goto comreset_retry; 2340095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2341da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#ifdef DEBUG 2342da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo { 2343da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo u32 sstatus, serror, scontrol; 2344da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 2345da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_STATUS, &sstatus); 2346da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_ERROR, &serror); 2347da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_CONTROL, &scontrol); 2348da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " 2349da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo "SCtrl 0x%08x\n", sstatus, serror, scontrol); 2350da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 2351da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#endif 235231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2353936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (ata_link_offline(&ap->link)) { 2354bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik *class = ATA_DEV_NONE; 235520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return; 235620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 235720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 235822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* even after SStatus reflects that device is ready, 235922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * it seems to take a while for link to be fully 236022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * established (and thus Status no longer 0x80/0x7F), 236122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * so we poll a bit for that, here. 236222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik */ 236322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik retry = 20; 236422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik while (1) { 236522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik u8 drv_stat = ata_check_status(ap); 236622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik if ((drv_stat != 0x80) && (drv_stat != 0x7f)) 236722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik break; 2368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(500); 236922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik if (retry-- <= 0) 237022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik break; 2371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (time_after(jiffies, deadline)) 2372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 237322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 237422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: if we passed the deadline, the following 2376bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * code probably produces an invalid result 2377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 237820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* finally, read device signature from TF registers */ 23803f19859ee95a38c066a0420eb8a30c76ecd67a42Tejun Heo *class = ata_dev_try_classify(ap->link.device, 1, NULL); 2381095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2382095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2383095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2384bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik WARN_ON(pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2386bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik VPRINTK("EXIT\n"); 238720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 238820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2389cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_prereset(struct ata_link *link, unsigned long deadline) 239022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2391e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(link->ap); 2392cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo return 0; 239322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 239422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2395cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2396bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 239731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2398cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2399bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2400b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 240231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2403e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2404b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2405bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_phy_reset(ap, class, deadline); 2406bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2407bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return 0; 2408bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2409bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2410cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic void mv_postreset(struct ata_link *link, unsigned int *classes) 2411bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2412cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2413bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 serr; 2414bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2415bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* print link status */ 2416cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_print_link_status(link); 241731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2418bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear SError */ 2419cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_scr_read(link, SCR_ERROR, &serr); 2420cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_scr_write_flush(link, SCR_ERROR, serr); 2421bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* bail out if no device is present */ 2423bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 2424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("EXIT, no device\n"); 2425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 24269b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord } 2427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* set up device control */ 2429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik iowrite8(ap->ctl, ap->ioaddr.ctl_addr); 2430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2434f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask; 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift; 2438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) 2443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2448f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp & ~mask, hpriv->main_mask_reg_addr); 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2453bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2454f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2455f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask, hc_irq_cause; 2460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift, hc_port_no = ap->port_no; 2461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) { 2466bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_port_no -= 4; 2468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2469bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2470bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2472bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2475bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2476bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2477bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */ 2478bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */ 2479bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2480bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2481bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2482f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2483f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp | mask, hpriv->main_mask_reg_addr); 248431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 248531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 248605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 248705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 248805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 248905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 249005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 249105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 249205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 249305b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 249405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 249505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 249605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 249705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 249920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 25000d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 250231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 25038b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 250431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 250531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 25068b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 250731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 250831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 250931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 251031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 251131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 251231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 25138b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 251431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 251531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 251631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 251731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 251831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 25198d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 252020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 252131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 252231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 252331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 252431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 252531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2526646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2527646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 252820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25298b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 253031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 253131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 253231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 253320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 253420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25354447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25374447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2539bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2540bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25415796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 254247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 254347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2544ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 254547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 254644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 254747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 254847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 254947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 255447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 255547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 255647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 255947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2561bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2562bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 256347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2564ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2565bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 256644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 256747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 256847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 256947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 257247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 257447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 257547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 257647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 257747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2578bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2579bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2580bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2581bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2582bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 258347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2584ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 258547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 258644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 258747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 258847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 258947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 259047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 259147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2592bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2593bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2594bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 259547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 259647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2597bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2598bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2599bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2600bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2601e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 260202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2603306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2604306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2605306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 26064e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 26074e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 26084e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26094e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 26104e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 26114e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 26124e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26134e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 26144e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 26154e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 26164e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 26174e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 26184e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26194e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 26204e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26214e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 26224e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 26234e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26244e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26254e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26264e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26274e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26284e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26294e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26304e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2631306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2632e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2633e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2635e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 263644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2637e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2638e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2639e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2640e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2641e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2644e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2645e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2646e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2647e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2650f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2652f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2653f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2654e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2655bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2656f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26575796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2658bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2659bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2660bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2661bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 266202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 266302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 266402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 266502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 266602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 266702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 266802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 266902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 267002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2671bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2672bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2673bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2674bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 267505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 267647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26774447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 267905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 268005b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 268105b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 268205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 268305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 268405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 268505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 26864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 268720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 268820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 26894447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2690f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 269147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 26924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2693bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2694f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara goto done; 2695f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2696f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2697f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2698f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_IRQ_CAUSE_OFS; 2699f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS; 2700f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2701f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2702f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS; 2703f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + 2704f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS; 2705f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2706f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* global interrupt mask */ 2707f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2708bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27094447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2710bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 271247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 271320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2714c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 271547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 271620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 271720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2718522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 27197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 272047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 272120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2723cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 27242a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2725cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2726cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2727cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2729f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2730f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2731f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2732f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 273520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 273620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 273720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 273831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 273931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 274031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 274131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 274231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 274331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 274431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 274531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 274631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 274720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 274820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 275231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2753f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2759f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2760f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2761f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2762f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2770f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2772f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2774f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2775f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2776f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2777f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2778fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2779fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2780fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2781fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2782fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2783fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2784fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2785fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2786fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2787fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2788fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2789fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2790fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2791fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2792fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2793fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2794fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2795fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2796fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2797fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2798fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2799f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 281720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2818f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2819f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2820bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2822f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2824f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2849f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2850f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2851f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2852f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2853fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2854fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2855fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2856fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2857f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 288520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 288620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2892f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2893f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2894f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2895f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 28977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2898f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2899f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 29037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 29047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2905f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 29067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 29077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 29087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 29107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 29117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 29127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 29137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 29167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 29177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 29187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 29197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 294805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 294905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 295105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 295205b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 295305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 295405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 295505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 295605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 295831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 29594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 296144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2962c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 296331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 296431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 296531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 296631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 296731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 296831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 296931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 297031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 297131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 297231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2973c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2974c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2975c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2976c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2977c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2978c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2979c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2980c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2981c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2982c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 298331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2984a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2985c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2986c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 298731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 298831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 298931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 299005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2991f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 299205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 299305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 299405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 299505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 299605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 299705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 2998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 300020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30012dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 300220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 30034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 30044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 30054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 30064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 300720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3008a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3009a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 301020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 30124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 30134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30144447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 30154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 30164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 30174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 30184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 302224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 302324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 302420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 302520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30260d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30270d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 302824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30290d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 303024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30314447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 303320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3034d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3035d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3036d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3037d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3038da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3039da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3040da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3041da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 304220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30434447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 304424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 304524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 304620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 304731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30486a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 304931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 305020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30524447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 305320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30544447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3055ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3057c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 305820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 30597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 306020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3061f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3062f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3063f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 306420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 306520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 30677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3072f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3073f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3074f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3075f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3076f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 30777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 30787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 307920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 308120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 308220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 308420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 30857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3086f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 308720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 308920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 309020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 309120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 309220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 309320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 30942e7e1214defe7783c8187962bacdd0a87a7dbeeeMartin MichlmayrMODULE_ALIAS("platform:sata_mv"); 309520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3097ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3098ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 30997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3100ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 310120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 310220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3103