sata_mv.c revision c3b2889424c26f3b42962b6f39aabb4f1fd1b576
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#include <linux/clk.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 64f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 66c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 675a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/gfp.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 69193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 706c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 74cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord#define DRV_VERSION "1.28" 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1082b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 111615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 119cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord COAL_REG_BASE = 0x18000, 120cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 1212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 124cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 1312b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATAHC0_REG_BASE = 0x20000, 133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FLASH_CTL = 0x1046c, 134cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord GPIO_PORT_CTL = 0x104f0, 135cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord RESET_CFG = 0x180d8, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 14120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 151da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 157352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 158352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 163c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 16491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 165ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16691b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 17091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 17191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 172ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 175c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 176e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 177c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 18131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 183c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 184c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND = 0xc00, 191cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 192cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 194cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_MAIN_CMD_STS = 0xd30, 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 199cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_MODE = 0xd00, 2008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 2018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 204522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 205522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 206cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_XBAR_TMOUT = 0x1d04, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 210522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 211522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 212cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_CAUSE = 0x1d58, 213cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_MASK = 0x1d5c, 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 216cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_CAUSE = 0x1900, 217cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_MASK = 0x1910, 218646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2207368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 221cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 222cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_MASK = 0x1d64, 223cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 224cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_MASK = 0x20024, 22540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2302b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 23120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 24020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 241fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 242e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 245cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_CFG = 0x00, 24620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 247cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_CAUSE = 0x14, 248352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 249352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 259cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 260cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 2612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 262cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_LED_CTRL = 0x2c, 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 265000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 266000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 268cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_BLK = 0x100, 269cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 27020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 273cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_ACTIVE = 0x350, 274cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE = 0x364, 275cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 27617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 277cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord LTMODE = 0x30c, /* requires read-after-write */ 27817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 280cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE2 = 0x330, 28147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 282cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord 283cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE4 = 0x314, /* requires read-after-write */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 287ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 288ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 289cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCTL = 0x344, 290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_TESTCTL = 0x348, 291cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFSTAT = 0x34c, 292cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord VENDOR_UNIQUE_FIS = 0x35c, 29317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 294cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FISCFG = 0x360, 2958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 29829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN2 = 0x398, 29929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN1 = 0x39c, 30029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 30129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 302c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 303cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_LTMODE = 0x30, 304cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_PHY_CTL = 0x0C, 305cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCFG = 0x050, 306bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 307bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 310cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CFG = 0, 3110c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3120c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3130c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3140c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3150c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 316e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 317e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 319cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_CAUSE = 0x8, 320cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_MASK = 0xc, 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3266c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 327c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 328c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3296c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 330c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3316c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3326c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3336c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3346c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 335646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3366c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 337646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 338646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 340646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 341646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3426c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 343646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3446c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 345646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 346646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 347646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 348646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 349646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 350646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3516c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 352646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3536c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 354c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 355c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 356646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 357646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 358646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 359646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 36085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 361646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 376e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 382bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 383bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 385bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 386bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 387bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 389cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_BASE_HI = 0x10, 390cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 39131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 392cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_OUT_PTR = 0x18, 39331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 39431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 395cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_BASE_HI = 0x1c, 396cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_IN_PTR = 0x20, 397cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 39831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 400cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CMD = 0x28, /* EDMA command register */ 4010ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 4020ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 4038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 4048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 405cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_STATUS = 0x30, /* EDMA engine status */ 4068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4078e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 409cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_IORDY_TMOUT = 0x34, 410cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ARB_CFG = 0x38, 4118e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 412cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 413cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 414da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 415cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_CMD = 0x224, /* bmdma command register */ 416cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_STATUS = 0x228, /* bmdma status register */ 417cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 418cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 419da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 42031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 42131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 42247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 42347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 42447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 42547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4270ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4280ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 430616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4311f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 432000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 43320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 436721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 439d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 44020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 44120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 442ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 443ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 444e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4461f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 447bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 45015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 451095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 452baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 453baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 454baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 455baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 456095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4570ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4580ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4590ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 460095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 461095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 463095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 464095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 465095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 466522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 467522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 470522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 471522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 472e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 473e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 474f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 475522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 476522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 479e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 481e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 482e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 48331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 48420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 486e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 487e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 488e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 489e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 490e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 491e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 492e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 495e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 496e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 497e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 50131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 502e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 503e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 504e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 505e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 50631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 51008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 51108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 51308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 51408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 51508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 51608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 517c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 52031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 52131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 52231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 52331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 52431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 525eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 526eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 53131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 53208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 53329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 53431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 53531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 539bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 540bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 54102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 54202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 5431bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara unsigned int board_idx; 54496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 54502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 54602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 547f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 548f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5507368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 551cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_cause_offset; 552cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_mask_offset; 55302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 554c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 555c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 556c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct clk *clk; 557c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 558da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 559da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 560da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 561da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 562da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 563da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 564da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 565da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 56602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 56702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 56847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5692a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5702a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 57147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 57247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 57347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 576522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 57847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 57947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 58082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 58531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5863e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 58731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 588e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5899a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 590a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 591a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 594f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 59520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5962a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5972a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 60047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 602c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 603522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 6047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 60547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 6062a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 6072a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 60847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 60947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 61047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 612c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 613522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 618f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 62329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 62429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port); 6257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 626e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 627c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 628e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 629b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 63000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 63147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 632e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 633e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 634e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 635e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 636e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 63729d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 64047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 641da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 642da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 643da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 644da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 645da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 646da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 647d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 648da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 652eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 653c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 65468d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 655baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 656c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 657c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 658c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 659c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 66068d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 661138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 662baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 66320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 66420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 666029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 667029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 669c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 670c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6713e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 674c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 677a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 678bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 679c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 680c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 681c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 682c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 683c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 684c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 685c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 686029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 6878930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .inherits = &ata_bmdma_port_ops, 6888930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6898930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .lost_interrupt = ATA_OP_NULL, 6908930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6918930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_defer = mv_qc_defer, 6928930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_prep = mv_qc_prep, 6938930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_issue = mv_qc_issue, 6948930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 695f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 69620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6978930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .freeze = mv_eh_freeze, 6988930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .thaw = mv_eh_thaw, 6998930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .hardreset = mv_hardreset, 7008930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .softreset = mv_softreset, 701e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 702e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 70329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 704da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 7058930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_read = mv_scr_read, 7068930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_write = mv_scr_write, 7078930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 70840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 709da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 710da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 711da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 712da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 713da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 714da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 7158930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 7168930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_start = mv_port_start, 7178930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_stop = mv_port_stop, 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 720029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 721029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 722029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 723e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 724e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 725e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 72698ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 72891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 729c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 730bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 73220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 73491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 735c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 736bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 73820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 74091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 741c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 742bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 743c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 74447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 74520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 74691b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 747c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 748bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 749c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 75020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 75120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 75291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 753c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 754bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 755c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 75620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 757e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 75891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 759c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 760bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 761e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 762e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 763e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 76491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 765c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 766bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 767e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 768e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 77091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 771c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 77217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 77317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 774f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 77520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 77620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7773b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7782d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7792d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7802d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7812d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 78246c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 78346c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7844462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7854462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7862d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7872d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7882d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7892d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7902d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7912d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7922d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7932d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7942d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 795d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 796d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 797d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 79802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7996a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 8006a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 80102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 80202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 80302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 80402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 8052d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 80620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 80720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 80847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 80947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 81047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 81147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 81247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 813522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 814522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 81547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 81647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 81747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 81847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 81947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 82047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 82147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 822522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 823522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 82447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 82547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 83529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic const struct mv_hw_ops mv_soc_65n_ops = { 83629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .phy_errata = mv_soc_65n_phy_errata, 83729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .enable_leds = mv_soc_enable_leds, 83829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_hc = mv_soc_reset_hc, 83929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_flash = mv_soc_reset_flash, 84029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_bus = mv_soc_reset_bus, 84129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr}; 84229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 84320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 84420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 84520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 84620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 84720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 84820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 84920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 85020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 85120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 85220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 859c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 861c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 862c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8631cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8641cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8651cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8661cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8671cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8681cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8697368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8707368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8711cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8721cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8731cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8741cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8751cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8761cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8771cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8781cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8791cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8801cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 881352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 882352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 883cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 884352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 885352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 89220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 89320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8958b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 896c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 89720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 899e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 900e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 901e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 902e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 903e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 904e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 905e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 906e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 91320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 91420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 91620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 91720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 918cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 91931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 920cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 92231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 92308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 92408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 92508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 92608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 92708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 92808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 92908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 93008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 93108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 93208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 93308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 93408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 93508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 93608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 93708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 938cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG); 939cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.ltmode = readl(port_mmio + LTMODE); 940cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 941cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 94208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 94308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 94408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 94508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 94608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 94708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 94808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 94908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 95008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 95108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 95208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 95308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 95408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 95508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 95612f3b6d7551306c00cf834540a33184de67c9187Mark Lord unsigned long laddr; 95708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 95812f3b6d7551306c00cf834540a33184de67c9187Mark Lord /* 95912f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Workaround for 88SX60x1-B2 FEr SATA#13: 96012f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Read-after-write is needed to prevent generating 64-bit 96112f3b6d7551306c00cf834540a33184de67c9187Mark Lord * write cycles on the PCI bus for SATA interface registers 96212f3b6d7551306c00cf834540a33184de67c9187Mark Lord * at offsets ending in 0x4 or 0xc. 96312f3b6d7551306c00cf834540a33184de67c9187Mark Lord * 96412f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Looks like a lot of fuss, but it avoids an unnecessary 96512f3b6d7551306c00cf834540a33184de67c9187Mark Lord * +1 usec read-after-write delay for unaffected registers. 96612f3b6d7551306c00cf834540a33184de67c9187Mark Lord */ 96712f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr = (long)addr & 0xffff; 96812f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr >= 0x300 && laddr <= 0x33c) { 96912f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr &= 0x000f; 97012f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr == 0x4 || laddr == 0xc) { 97112f3b6d7551306c00cf834540a33184de67c9187Mark Lord writelfl(new, addr); /* read after write */ 97212f3b6d7551306c00cf834540a33184de67c9187Mark Lord return; 97312f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97412f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97512f3b6d7551306c00cf834540a33184de67c9187Mark Lord writel(new, addr); /* unaffected by the errata */ 97608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 97708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 97808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 979c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 980c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 981c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 982c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 983bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 984bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 985c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 986c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 987c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 988fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 989fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 990bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 991c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 992cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 993bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 994cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 995cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 996c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 997c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 998c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 999c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 1000fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1001fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 1002bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1003c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 1004cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 1005cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 1006bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 1007cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 1008c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 1009c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 10102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 10112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 10142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 10152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 10162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 10172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 10182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 10192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 10212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 10222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 10232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 10242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 10252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 10262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1027c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 1028c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 1029c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1030c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 1031c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 1032c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 103396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 1034c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 103596e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 103696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 10372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 103896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 1039c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1040c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1041c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 1042c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 1043c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1044c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 1045c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 1046c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1047c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1048c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1049c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1050c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 1051c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1052c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1053c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 105400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 105500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 105600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 105700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 105800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 105900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 106000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 106100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 106200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 106300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 106400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 1065cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 106600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 106700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 106800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1069cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 107000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 107200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 1073cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + FIS_IRQ_CAUSE); 107400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 107600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 107700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10792b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10802b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10812b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10856abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 10962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 10972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 10982b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 10992b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 11026abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 11032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11046abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 11052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11066abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 11076abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 11082b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1109cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1110cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 11112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 1112cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 11136abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11146abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 11156abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 11162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11176abf4678261218938ccdac90767d34ce9937634fMark Lord 11182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 11202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 11212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 1122cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1124cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11256abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11266abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 11276abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 11282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1131cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11326abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11336abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 11342b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11352b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11366abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 11372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 11382b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 11392b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 114005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 114205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 114305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 114405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1145beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1146beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 114905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 115005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 115100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1152721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 115320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1154721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1155721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1156721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1157721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1158721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1159b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1160721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1161c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11620c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11630c58912e192fc3a4835d772aafa40b72552b819fMark Lord 116400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11650c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1166f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 116700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1168bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1169cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1170afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1171afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 117220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 117320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11749b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11759b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11769b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11779b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11789b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11799b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11809b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11819b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11829b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1183c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1184c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1185c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1186c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11879b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11889b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 1189cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS); 11909b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11919b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11929b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11939b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 11949b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 11959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 11969b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 119705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1198e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1199b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 120005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 120205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 120305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1204b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 120520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1206b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 120731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1208b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1209cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD); 12108b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1211b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1212b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1213cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + EDMA_CMD); 12144537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1215b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1216b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 121731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1218b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 121920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 122020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1221e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 12220ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1223b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1224b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 122566e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 12260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1227b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1228b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1229b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 12309b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1231b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1232b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 123366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1234b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 123566e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 123666e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 12370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 12380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 12398a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 124031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 124120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 124331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 124531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12462dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12528a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12538a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 125531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12622dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12632dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12748b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12888b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 129931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 130031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1301d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 130231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 130631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 13072dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 130831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 13092dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 131231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 131320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 131420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 131620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 131720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 131820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 132020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 132120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 132220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 1323cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 132420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 132520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 1326cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_ACTIVE; /* active is not with the others */ 132720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 132820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 132920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 133020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 133120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 133220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 133320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 133420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 133582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 133620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 133720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 133820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1339da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 134082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1341da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1342da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1343da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 134420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 134520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 134682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 134720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 134820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 134920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1350da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 13512009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13522009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13532009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13542009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13552009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13562009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * COMRESETs have to take care not to accidently 13572009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13582009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13592009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13602009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13612009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13622009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13632009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13642009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13652009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13662009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13672009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13682009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13692009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1370da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1371da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1372da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 137320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 137420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1375f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1376f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1377f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1378e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1379e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1380e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1381e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1382f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1383e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1384352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1385e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1386352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1387352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1388352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1389e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1390f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1391f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13923e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13933e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13943e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13953e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 13963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 13973e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13983e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 139929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 140029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 140129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 140229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 140329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 1404159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 1405159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou /* PIO commands need exclusive link: no other commands [DMA or PIO] 1406159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * can run concurrently. 1407159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * set excl_link when we want to send a PIO command in DMA mode 1408159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * or a non-NCQ command in NCQ mode. 1409159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * When we receive a command from that link, and there are no 1410159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * outstanding commands, mark a flag to clear excl_link and let 1411159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * the command go through. 1412159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou */ 1413159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (unlikely(ap->excl_link)) { 1414159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (link == ap->excl_link) { 1415159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ap->nr_active_links) 1416159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1417159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1418159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1419159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } else 1420159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1421159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1422159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 142329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 14243e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 14253e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 14263e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 14273e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 14283e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 14294bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 14304bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 14314bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 14324bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 14334bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 14344bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 14354bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1436159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1437159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ata_is_ncq(qc->tf.protocol)) 1438159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1439159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou else { 1440159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou ap->excl_link = link; 1441159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1442159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1443159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 14444bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 14453e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 14463e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 14473e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 144808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1449e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 145008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 145108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 145200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 145408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 145508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 145600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 145808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 145900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 146000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 146108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 146208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 14634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 146408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 14654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 146608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 146708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 146808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1469e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 147000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 147108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 1472cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1473cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1474cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1475f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1476f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1477dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1478dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1479dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1480dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1481dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1482dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1483cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old = readl(hpriv->base + GPIO_PORT_CTL); 1484dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1485dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1486dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1487dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1488dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1489cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(new, hpriv->base + GPIO_PORT_CTL); 1490dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1491dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1492c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 149340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 149440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1495c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1496c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1497c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1498c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1499c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1500c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1501c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1502c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1503c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1504c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1505c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1506c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1507c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1508c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1509c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1510c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1511c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1512c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1513cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1514c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1515c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1516000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1517000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1518000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1519000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1520000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1521000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1522000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1523000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1524000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1525000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1526000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1527000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1528000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1529000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1530000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1531000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1532000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1533000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1534000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1535000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1536000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1537000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1538000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1539000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1540000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1541cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1542cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1543000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1544000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1545000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1546000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1547000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1548000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1549000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1550000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1551000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1552000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1553000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1554000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1555000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1556000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1557000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1558000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1559000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1560000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1561000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1562000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1563000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1564000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1565000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1566000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1567cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1568cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1569000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1570000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 157100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1572e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 15730c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1574e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1575e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1576e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1577e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1578e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15790c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1580d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1581d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1582e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15830c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1584e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1585e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1586dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1587e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1588dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1589e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1590dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 159100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 159200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 159300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 159400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 159500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 159600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 159700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 159800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 159900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 160000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 160100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 160300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 160500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 160600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 160700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 160800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1609e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 161000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 161100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 161200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 161300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 161400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1615616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1616616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1617c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1618000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1619000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1620000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1621000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1622000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1623000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1624000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1625e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1626e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1627721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1628721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1629721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 163000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1631721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1632cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cfg, port_mmio + EDMA_CFG); 1633e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1635da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1636da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1637da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1638da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1639eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1640da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1641da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1642da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1643da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1644da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1645da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1646da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1647da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1648da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1652eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1653eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1654eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1655eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1656eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1657eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1658eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1659eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1660eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1661da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1662da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1663da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 166405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 166505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 166605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 166705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 166805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 166905b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 167431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 167531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1676cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1677cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 167831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1679933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1680dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 168131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 168224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16836037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 168424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1685da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 168631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1687da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1688da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1689da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1690da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 169131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1692da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1693da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1694da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1695da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 169631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16973bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 16983bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 16993bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1700eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1701eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1702eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1703eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1704eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1705eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1706eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1707eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1708eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1709eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1710eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1711eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1712eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1713eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1714eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1715933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1716933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 171708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 171866e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1719933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1720933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 172131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1722da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1723da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1724da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1725da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 172631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 172731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 172805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 172905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 173005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 173105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 173305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1735cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 173605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 173731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 173831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1739933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1740933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1741933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1742e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 174388e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1744933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1745da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 174631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 174731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 174805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 174905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 175005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 175105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 175305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 175505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 175605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17576c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 175831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 175931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1760972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 17613be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1762ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 176331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1764eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1765ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1766d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1767d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 176822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 17694007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 17704007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 17714007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 177222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 177332cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 17744007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 17754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17786c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 177932cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17834007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17843be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17864007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 178731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17883be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17893be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17903be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 179132cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 179231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 179331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17945796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 179531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1796559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 179731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1798559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 179931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 180031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 180105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1802da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1803da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1804da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1805da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1808da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1810da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1818da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1822da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1824da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1831da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1845da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1850da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1852da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1861da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1862cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + BMDMA_CMD); 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1864da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1865da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1866cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_HIGH); 1867da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1868cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_LOW); 1869da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1870da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1871da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1872da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1873da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1874da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1875da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1876da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1877da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1878da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1879da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1880da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1881da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1882da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1883da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1884da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1885da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1886da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1887da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1888da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1889cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1890da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1891da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1892da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1893da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1894da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1895da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1896da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1897da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1898da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1899da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1900da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1901da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1902da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1903da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1904da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1905da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1906da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1907da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1908cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord cmd = readl(port_mmio + BMDMA_CMD); 1909da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1910cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1911da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1912da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1913da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1914da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1915da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1916da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1917da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1918da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1919da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1920da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1921da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1922da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1923da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1924da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1925da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1926da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1927da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1928da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1929da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1930da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1931da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1932da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1933da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1934cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(port_mmio + BMDMA_STATUS); 1935da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1936da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1937da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1938da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1939da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1940da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1941da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1942299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lordstatic void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1943299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord{ 1944299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord struct ata_taskfile *tf = &qc->tf; 1945299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* 1946299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Workaround for 88SX60x1 FEr SATA#24. 1947299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1948299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Chip may corrupt WRITEs if multi_count >= 4kB. 1949299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Note that READs are unaffected. 1950299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1951299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * It's not clear if this errata really means "4K bytes", 1952299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * or if it always happens for multi_count > 7 1953299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * regardless of device sector_size. 1954299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1955299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * So, for safety, any write with multi_count > 7 1956299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * gets converted here into a regular PIO write instead: 1957299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord */ 1958299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1959299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if (qc->dev->multi_count > 7) { 1960299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->command) { 1961299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI: 1962299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE; 1963299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1964299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_FUA_EXT: 1965299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1966299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* fall through */ 1967299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_EXT: 1968299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE_EXT; 1969299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1970299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1971299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1972299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1973299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord} 1974299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord 1975da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 197605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 197705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 197805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 197905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 198005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 198105b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 198205b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 198305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 198405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 198505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 198605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 198731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 198831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 198931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 199031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1991e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 19928d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 199331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1994a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 199531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1996299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->protocol) { 1997299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_DMA: 1998299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_NCQ: 1999299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; /* continue below */ 2000299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_PIO: 2001299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord mv_rw_multi_errata_sata24(qc); 200231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 2003299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord default: 2004299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord return; 2005299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 200620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 200731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 200831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 20098d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 201031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 2011beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 201231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 2013e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 201431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2015bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2016fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2017a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2018a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 2019eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2020a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 2021eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2022a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 202331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2024a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 202531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 202631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 202731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 202831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 202931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 2030cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 2031cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 203220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 203331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 203431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 203531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 203631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 203731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 2038c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 203931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 204031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 204131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 204231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 20438b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 204431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 204531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 204631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 204731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 204831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 204931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 205031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 205131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 205231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 205331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 205431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 205531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 205631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 205731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 205831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 205931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 206031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 206131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 206231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 206331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 206431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 206531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 206631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 206731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2068e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2069e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2070e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 2071e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 2072e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2073e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 2074e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 2075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 2076e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2077e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 2078e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 2079e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 2080e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 2081e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2082e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 2083e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 2084e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 2085e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2086e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 2087e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 2088e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 2089e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 20908d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 2091a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 2092e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 2093e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 20948d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if ((tf->protocol != ATA_PROT_DMA) && 20958d2b450d0f9233f221d545f26720eebbc468e857Mark Lord (tf->protocol != ATA_PROT_NCQ)) 2096e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2097e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2098e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 20998d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 2100e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 2101e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2102beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2103e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 21048c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2105e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2106e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2107bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2108fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2109a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2110a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2111eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2112eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2113e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 2114e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2115e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2116e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2117e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2118e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2119e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2120e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2121e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2122e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2123e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2124e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2125e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2126e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2127e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2128e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2129e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2130e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2131e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2132e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2133e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2134e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2135e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2136e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 213731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 213831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 213931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 214031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 214105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2142d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2143d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2144d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2145d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2146d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2147d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2148d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2149d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2150d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2151d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2152d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2153d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2154d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2155d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2156d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2157d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2158d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2159d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2160d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2161d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2162d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2163d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2164d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2165d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2166d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2167d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2168d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 216970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 217070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 217170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 217270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 217370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 217470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 217570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 217670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 217770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 217870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 217970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 2180cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old_ifctl = readl(port_mmio + SATA_IFCTL); 218170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 2182cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl, port_mmio + SATA_IFCTL); 218370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 218570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 2186cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 218770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 2189cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 219170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 219270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 219370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 219470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 219570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 219670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 2197cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ifstat = readl(port_mmio + SATA_IFSTAT); 219870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 219970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 2201cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL); 220270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 220470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 220570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_port_printk(ap, KERN_WARNING, 220670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord "%s transmission error, ifstat=%08x\n", 220770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord __func__, ifstat); 220870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 220970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 221070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 221170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 221270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 221370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 221470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 221570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 221670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 221770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 221870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 221970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 222070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 222270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 222470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 222570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 222670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 222870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 222970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 223070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 223170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 223270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 223370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 223470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 223570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 223670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 223770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 223870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 22394c4a90fd2b9d1f5c0d33df3fcfaa8a3dae9abc53Thiago Farina err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 224070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 224170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 224270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 224370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 224470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 224570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 224670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 224770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 224870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 224970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 225070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 225170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 225270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 225370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 225470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 225570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 225670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 225770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 225870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 225970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 226070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 226170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 226270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 2263c429137a67b82788d24682153bb9c96501a9ef34Tejun Heo ata_sff_queue_pio_task(ap, 0); 226470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 226570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 226670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 226770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 226805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 226905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 227005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 227105b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 227205b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 227305b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 227405b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 227505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 227605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 227705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 227805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 22799a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 228031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2281f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2282c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2283c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2284c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2285bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 228642ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2287f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2288d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2289d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2290f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2291f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 2292f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2293f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2294f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2295f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2296f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2297f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2298f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2299cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 2300f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 230131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2302f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2303c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2304c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2305c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2306c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2307c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2308c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2309c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2310c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2311c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2312c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2313c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2314c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2315c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2316c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2317c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 2318c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 2319c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2320f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 232142ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2322f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 232342ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 232442ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 232542ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 232642ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 232731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 232842ed893d8011264f9945c2f54055b47c298ac53eMark Lord 232942ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 233042ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 233142ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 233242ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 233342ed893d8011264f9945c2f54055b47c298ac53eMark Lord 233442ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 233542ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 233642ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 233742ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 233842ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 233942ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 234042ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 234142ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 234270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 234370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 234470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 234570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 234670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 234740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 234870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 234970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 235070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 235170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 235270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 235370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 235470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 235570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 235670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 235770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 235870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 2359360ff7833098e944e5003618b03894251e937802Tejun Heo return ata_bmdma_qc_issue(qc); 236031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 236131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23628f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 23638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 23648f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 23658f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 23668f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 23678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 23688f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 23698f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 23703e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 23713e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return qc; 23723e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return NULL; 23738f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 23748f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 237529d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 237629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 237729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 237829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 237929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 238029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 238129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 238229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 238329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 238429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 238529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 238629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 238729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 238829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 238929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 239029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 239129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 239229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 239329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 239429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 239529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 239629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 239729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 239829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 239929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 240029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 240129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 24024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 24034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 24054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2406cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return readl(port_mmio + SATA_TESTCTL) >> 16; 24074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 24104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 24124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 24134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 24164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 24184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 24194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 24204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 24214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 24224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 24244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 24254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 24264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 24274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 24284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 24294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 243406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 243506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 243606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 243706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 243806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 2439cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 244006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2441cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 244206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 244306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 244406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 244506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 24464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 24474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 24504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 24514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 24544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 24564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 24574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 24584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 24594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 24614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 24624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 24634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 24654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 24664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 24684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 24694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 24704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2471c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 24724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 24744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 24754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 24764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 24774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 24784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 247906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 24804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 24814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 24824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 24834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 24844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 24874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 24914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 24944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 24964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 24974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 24994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 25014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 25024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 25074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 25084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 25094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 25114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 25124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 25134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 25144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 25164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 25174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 25184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 25194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 25204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 25224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 25244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 25254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 25284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 25294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 25304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 25314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 25344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 25354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 25374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 25384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 25414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 25424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 25434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 25444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 25474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2551a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 25528f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 25538f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2554a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 25558f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 25568f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 25573e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (edma_was_enabled) { 2558a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 25598f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 25608f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 25618f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2562a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 25638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2564a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 25658f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 25668f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 25678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 25688f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 25698f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 257005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 257105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 257205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 257305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 25748d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 25758d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 25768d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 257705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 257805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 257905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 258005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 258137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 258231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 258331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2585e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 25899af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 259037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 259137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 259220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25938d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 259437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2595e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2596e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 25978d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 259837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 259937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 260037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2601cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2602e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2603cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2604cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2605e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 2606cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 26084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 26094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 26104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 26114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 26124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 26134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 26144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 26154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 26164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 261737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 261837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 261937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 262037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2621e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2622c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2623e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2624cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (fis_cause & FIS_IRQ_CAUSE_AN) { 2625c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2626c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2627c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2628c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2629c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2630c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2631c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2632c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2634352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 263637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 263837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 263937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 264037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 26426c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2643bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2645cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2646b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2651b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2652cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2653bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2654bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2655352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2656352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2657352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2658352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2659ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2660bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2663b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2664bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2666bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2669b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2670bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 26728d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 26738d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2674cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2676afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 267720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2678bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2679bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2680cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2681bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2682bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2683bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2684bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 269137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 269237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 269337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 269437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 269537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 269637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 269737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 269837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 269937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 270037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 270137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 270237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2703bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 270437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 270537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 270637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 270737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 270837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 270937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 271037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 271137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 271237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 271337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2716fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2717fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2718fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2719fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2720fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2721fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2722fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2723fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2724fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2725fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2726cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2727fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2728fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2729fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2730fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2731fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2732fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2733fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2734fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2735fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2736fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2737fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2738fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2739fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 274037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 274137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 274237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2743fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2744fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2745fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2746fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2747fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2748fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2749fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2750bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2751bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2752bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2753fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2755fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2756bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2757fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2758cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2761fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2762fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 27636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2764fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2765bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2766fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2767bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2768fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2769fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 27709af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2771fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2772fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2773fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2775fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2779352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2781bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2782fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2783cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 278420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 278520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2786a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2787a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2788a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2789a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2790a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2791a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2792a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2793a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2794a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2795a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2796a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2797a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2798a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2799a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2800a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2801a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2802a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 28034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 28044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2805a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2806a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2807a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2808a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2809a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2810a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2811a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2812a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2813a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2814c3b2889424c26f3b42962b6f39aabb4f1fd1b576Tejun Heo ata_bmdma_port_intr(ap, qc); 2815a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2816a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2817a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2818a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2819a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 282005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 282105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2822cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 28237368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 282405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 282505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 282605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 282705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 28287368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 282920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2831eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2832a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 283320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28342b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 28352b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 2836cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 28372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2838a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2839cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2840eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2841eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2842a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2843a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2844eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2845eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2846a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2847eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2848eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2849eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2850eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2851eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2852eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2853eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2854eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2855eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2856eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2857eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2858eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2859eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2860eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2861eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2862eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2863eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2864eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2865eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2866eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2867eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2868eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2869eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 28702b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 28712b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2872eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2873eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2874eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2875eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2876eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2877eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2878eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2879a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2880cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2881a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2882a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 28838f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2884a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 28858f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2886a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2887a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2888a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 288920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2890a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 289120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 289220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2893a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2894bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 289502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2896bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2897bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2898bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2899bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2900bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2901bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2902cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord err_cause = readl(mmio + hpriv->irq_cause_offset); 2903bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2904bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2905bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2906bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2907bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2908bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2909bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2910cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 2911bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2912bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2913bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2914936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 29159af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2916bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2917bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2918bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2919bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2920bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2921cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 29229af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2923bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2924bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2925bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2926bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2927bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2928bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2929bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2930bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2931a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2932bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2933bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 293405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2935c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 293605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 293705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 293805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 293905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 294005b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 294105b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 294205b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 294305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 29448b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2945cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 294605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 294705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29487d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 294920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2950cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2951f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2952a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 29536d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 295496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 295520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2956646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 29576d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29586d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 29596d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 29616d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29627368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 296396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2964352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2965352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2966352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 296720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2968a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 29691f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2970a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2971a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2972a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2973bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 29746d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29756d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 29766d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29772b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 29786d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29799d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 29809d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 298120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 298220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 298320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2984c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2985c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 300182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 300382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3004f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 300582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3008da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 3009da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 3010da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3011da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3012da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 301582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 301782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 301982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3022da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 30230d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 3024da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3025da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3026da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3028c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 30297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3030522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 30317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 3032522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 3033522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 303444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3035522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3036522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 3037522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3038522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 3039522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3040522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 3041522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 30427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 3043522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3044522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3045522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3046522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 3047cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x0fcfffff, mmio + FLASH_CTL); 3048522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3049522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 305047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3051ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3052ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3053c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3054c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3055c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3056c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3057c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3058c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3059c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3060ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3061ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 306247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3063ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3064522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 3065522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3066cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, mmio + GPIO_PORT_CTL); 3067522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3068522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3069522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3070522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3071522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 3072522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3073ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3074ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 30752a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 30762a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3077bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3078c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3079c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3080c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3082c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 3084cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_LTMODE); 3085c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 3086cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_LTMODE); 3087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3088cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_PHY_CTL); 3089c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 3090c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 3091cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_PHY_CTL); 3092c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3095c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 3096c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 3097c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 3098c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 3099bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3100bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3101c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 3104c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3109e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3110c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3111c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3112cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x11f, port_mmio + EDMA_CFG); 3113c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3114c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3115c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3116c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3117c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3118c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3119c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3120c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3121c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3122c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 3123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3124c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3125c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3126c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3127c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3128c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3129c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 313047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3131c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3132c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3133c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3134c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3135c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3136c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3137c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3138c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3139c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3140c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3141c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3142c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3143c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3144c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3145c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3146c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3147c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3148c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3149c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3150c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3151c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3152c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3153c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3154c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3155c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3156c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3157c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3158c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3159c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 316047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 316147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3162101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3163101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 31647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3165101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 316602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3167101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3168101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3169cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + MV_PCI_MODE); 3170101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 3171cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + MV_PCI_MODE); 3172101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3173101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3174101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 3175cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3176101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 3177cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_cause_offset); 3178cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_mask_offset); 3179101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3180101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3181101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3182101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3183101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3184101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3185101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3186101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3188101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3189101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3191101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3192cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + GPIO_PORT_CTL); 3193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3194101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 3195cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + GPIO_PORT_CTL); 3196101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3199101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3200101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3202101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3203101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3204101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3207c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3208c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3210cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3211101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3212101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3214101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3215101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3216101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3217101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3218101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3219101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3220101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3221101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3222101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 32232dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3224101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3225101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3226101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3227101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3228101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3229101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3230101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3231101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3232101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3233101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3234101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3235101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3236101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3237101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3238101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3239101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3240101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3241101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3242101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3243101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3244101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3245101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3246101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3247101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3248101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3249101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3250101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3251101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3252101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3253101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3254101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3255101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3256101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3257101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3258101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3259101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3260101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3261101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 326247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3263ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3264ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3265ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3266ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3267ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3268cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + RESET_CFG); 3269ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 327047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3271ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3272ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3273ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3274ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3275ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3276ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3277ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3278ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3279ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3280ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3281ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 328247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3283ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3284cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x00000060, mmio + GPIO_PORT_CTL); 3285ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3286ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3287c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 32882a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3289bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3290c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3291c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3292bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 329347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 329447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3295bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 329647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 32978c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 329847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 329947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 330047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 330147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 330247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 330347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 330447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 330547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 330647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 330747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 330847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 330947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 331047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 331147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 331247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 331347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 33148c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 33158c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 33168c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 33178c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 33188c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 33198c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3320bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 33210388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 33220388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 33230388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 33240388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3325bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3326ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3327ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3328ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3329ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3330ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3331ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 33328c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3333ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3334ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3335ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 33368c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3337bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3338b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3339b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3340b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3341b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3342ba68460b8e019dfd9c73ab69f5ed163a8b24e296Mark Lord * Or ensure we use writelfl() when writing PHY_MODE4. 3343b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3344b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3345bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3346bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3347bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3348bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3349bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 33502a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 33512a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 335247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3353bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3360bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3361bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3362bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3363f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3365f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3377f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3378f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3384f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3385f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3391e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3394cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x101f, port_mmio + EDMA_CFG); 3395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3398f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 3405d7b0c143693bcbf391d2be235e150b97bfd8f9baSaeed Bishara writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3407f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3409f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3410f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3411f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3412f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3414f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3415f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3416f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3417f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3418f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3419f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3420f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3421f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3422f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3423f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3424f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3425f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3426f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3427f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3429f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3430f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3431f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3433f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3434f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3435f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3436f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3437f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3438f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3439f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3440f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3441f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3446f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3447f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 344829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 344929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port) 345029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 345129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port_mmio = mv_port_base(mmio, port); 345229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr u32 reg; 345329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 345429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE3); 345529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 345629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 27); 345729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 345829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 29); 345929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE3); 346029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 346129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE4); 346229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 346329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 16); 346429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE4); 346529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 346629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN2); 346729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 346829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 346929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 347029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN2); 347129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 347229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN1); 347329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 347429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 347529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 347629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN1); 347729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 347829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 347929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr/** 348029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * soc_is_65 - check if the soc is 65 nano device 348129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * 348229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 348329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * register, this register should contain non-zero value and it exists only 348429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * in the 65 nano devices, when reading it from older devices we get 0. 348529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr */ 348629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic bool soc_is_65n(struct mv_host_priv *hpriv) 348729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 348829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 348929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 349029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (readl(port0_mmio + PHYCFG_OFS)) 349129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return true; 349229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return false; 349329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 349429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 34958e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3496b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 3497cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3498b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 34998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3500b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 35018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 3502cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifcfg, port_mmio + SATA_IFCFG); 3503b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3504b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3505e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3506c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3507c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3508c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3509c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 35108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 35118e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 35128e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 35138e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 35148e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 35150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 3516cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3517c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3518b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 35198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 35208e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3521c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3522b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 35238e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3524b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3525cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3526c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 3527cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3528b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3529cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_CMD); 3530c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3531c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3532c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3533ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3534c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3535c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3536c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3537e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 353820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3539e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3540e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3541cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + SATA_IFCTL); 3542e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 354322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3544e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3545e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3546cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg, port_mmio + SATA_IFCTL); 3547e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 354822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 354920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 355020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3551e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3552e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 355322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3554e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3555e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3556e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3558e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3559e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3560e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3561e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3562e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 356322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 356422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3565cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 356731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3568cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3570b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3571f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 35720d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 35730d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 35740d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 357531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3576e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3577b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3578d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3579d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 35810d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 35820d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 358317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 358417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 358617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 358717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 35889dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 358917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 35900d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 35910d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 35920d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 35930d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 35948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 35950d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 35960d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 35970d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 35980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 359908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 360066e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 360217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3604bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 36071cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3608c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3613f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3614c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3615c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 36161cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3617bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3618c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3619bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3620bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3621cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3622bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3624cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3625cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 362788e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 362831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 362931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 363005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 363105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 363205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 363305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 363405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 363505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 363605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 363705b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 363805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 363905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 364005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 364105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 364231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 364320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3644cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 364531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 36468b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 364731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 364831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 36498b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 365031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 365131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 365231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 365331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 365431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 365531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 36568b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 365731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 365831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 3659cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 366031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 366131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 3662cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord serr = port_mmio + mv_scr_offset(SCR_ERROR); 3663cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(readl(serr), serr); 3664cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 366531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3666646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3667cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 366820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36698b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3670cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_CFG), 3671cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3672cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_MASK)); 367320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 367420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3675616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3676616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3677616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3678616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3679616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3680616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 36811f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3682616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3683cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_MODE); 3684616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3685616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3686616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3687616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3688616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3689616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3690616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3691616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3692616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3693616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3694616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3695616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3696cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_COMMAND); 3697cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (reg & MV_PCI_COMMAND_MRDTRIG) 3698616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3699616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3700616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3701616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3702616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 370365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 370465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 370565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 370665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 370765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 370865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 370965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 3710cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(mmio + MV_PCI_COMMAND); 3711cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 371265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 371365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 371465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 37154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3716bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 37174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 37184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3719bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3720bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37215796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 372247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 372347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3724ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 372547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 372644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 372747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 372847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 372947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 373047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 373147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 373247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 373347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 373447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 373547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 373647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 373747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 373847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 373947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 374047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3741bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3742bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 374347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3744ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3745bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 374644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 374747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 374847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 374947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 375147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 375247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 375447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 375547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 375647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 375747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3758bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3759bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3760bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3761bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3762bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 376347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3764ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 376547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 376644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 376747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 376865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 376947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 377047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 377147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 377247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3773bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3774bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3775bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 377647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 377747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3778bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3779bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3780bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3781bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3782e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3783616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3784306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3785306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3786306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 37874e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 37884e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 37894e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37904e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 37914e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 37924e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 37934e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37944e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 37954e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 37964e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 37974e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 37984e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 37994e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38004e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 38014e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38024e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 38034e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 38044e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 38054e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 38064e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 38074e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 38084e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 38094e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 38104e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 38114e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3812306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 38138e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3814e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3815e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3816e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3817616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3818616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3819e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 382044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 38215cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3822e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3823e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3824e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3825e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3826e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3827e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3828e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3829e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3830e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 383229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (soc_is_65n(hpriv)) 383329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_65n_ops; 383429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr else 383529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_ops; 3836eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3837eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3839e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3840bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 38425796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3843bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3844bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3845bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3846bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 384702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 3848cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3849cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCIE_IRQ_MASK; 385002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 385102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 3852cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3853cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCI_IRQ_MASK; 385402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 385502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3856bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3857bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3858bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3859bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 386005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 386147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 38624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 386305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 386405b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 386505b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 386605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 386705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 386805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 386905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 38701bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bisharastatic int mv_init_host(struct ata_host *host) 387120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 387220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 38734447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 387547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 38761bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_chip_id(host, hpriv->board_idx); 3877bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3878352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 38801f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 3881cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3882cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 38831f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 3884cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3885cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3887352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 38885d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 38895d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 38905d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3891352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3892c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3893bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3895bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 389729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (hpriv->ops->read_preamp) 389829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops->read_preamp(hpriv, port, mmio); 389920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3900c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 390147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 390220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 390320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3904522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 39057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 390647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 390720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 39084447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3909cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 39102a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3911cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3912cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 391320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 391420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 391520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 391631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 391731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 391831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 391931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 3920cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_CFG), 3921cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_IRQ_CAUSE)); 392231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 392331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 3924cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, hc_mmio + HC_IRQ_CAUSE); 392520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 392620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 392744c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 392844c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 3929cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 393031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 393144c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 3932cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 393344c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 393451de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 39356be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 39366be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 39376be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 39386be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 39396be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 39402b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 39412b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3944f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3945fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3946fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3947fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3948fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3949fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3950fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3951fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3952fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3953fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3954fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3955fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3956fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3957fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3958fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3959fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3960fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3961fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3962fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3963fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3964fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3965fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 396615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 396715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 396815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 396915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 397015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 397115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 397215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 397315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 397415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 397515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 397615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 397715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 397815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 397915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 398015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 398115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 398215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 398315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 398415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 398515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 398615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3987f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3988f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3989f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3990f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3991f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3992f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3993f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3994f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3996f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 4000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 4001f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 4002f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 4003f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 4004f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 400520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 4007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 4008bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 4009f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4010f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 4011f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 4013f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 4014f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4015f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 4016f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4017f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 4019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4021f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 4022f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4023f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4024f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 4025f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 4026f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 4027f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4028f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4029f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4030f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4031f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 4032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 4033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 4034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 40351bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = chip_soc; 4036f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 4038f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 4039041b5eac254107cd3ba60034c38a411531cc64eeJulia Lawall resource_size(res)); 4040cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->base -= SATAHC0_REG_BASE; 4041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4042c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4043c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara hpriv->clk = clk_get(&pdev->dev, NULL); 4044c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (IS_ERR(hpriv->clk)) 4045c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara dev_notice(&pdev->dev, "cannot get clkdev\n"); 4046c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara else 4047c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_enable(hpriv->clk); 4048c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4049c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 405015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 405115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 405215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 405315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 405415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 405515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 4056fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 4057fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 4058c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4059fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 4060f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 40611bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 4062f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 4063c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4064f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4065f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 4066f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 4067f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 4068f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 4070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 4071c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bisharaerr: 4072c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4073c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4074c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4075c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4076c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4077c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4078c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4079c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara return rc; 4080f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 4081f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4082f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 4083f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4084f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 4085f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 4086f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4087f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 4088f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 4089f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4090f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 4091f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4092f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 4093f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 4094c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4095c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 4096c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4097f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 4098c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4099c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4100c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4101c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4102c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4103c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4104c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4105f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 410620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 410720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41086481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#ifdef CONFIG_PM 41096481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 41106481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 41116481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 41126481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) 41136481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ata_host_suspend(host, state); 41146481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara else 41156481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41166481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41176481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41186481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_resume(struct platform_device *pdev) 41196481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 41206481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 41216481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara int ret; 41226481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41236481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) { 41246481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 41256481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara const struct mv_sata_platform_data *mv_platform_data = \ 41266481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara pdev->dev.platform_data; 41276481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* 41286481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara * (Re-)program MBUS remapping windows if we are asked to. 41296481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara */ 41306481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (mv_platform_data->dram != NULL) 41316481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 41326481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41336481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* initialize adapter */ 41341bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara ret = mv_init_host(host); 41356481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (ret) { 41366481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 41376481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ret; 41386481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41396481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara ata_host_resume(host); 41406481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41416481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41426481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41436481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41446481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#else 41456481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_suspend NULL 41466481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_resume NULL 41476481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#endif 41486481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 4149f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 4150f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 4151f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 41526481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .suspend = mv_platform_suspend, 41536481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .resume = mv_platform_resume, 4154f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 4155f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 4156f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 4157f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 4158f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 4159f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4160f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 4162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 4164b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4165b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev); 4166b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 41707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 41717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 4172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 41737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 4174b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4175b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .suspend = ata_pci_device_suspend, 4176b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .resume = mv_pci_device_resume, 4177b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4178b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 41797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 41807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 41827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 41837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 41847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 41857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41866a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 41876a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 41887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4189284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 41907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 41917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 41927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 41937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 41947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 41957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 41967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 4197284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 41987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 41997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 42007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 42017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 4203284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 42047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 42057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 42067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 42077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 42117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 42137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 421405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 421505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 42164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 421705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 421805b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 421905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 422005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 422105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 422205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 42234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 422431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 42254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 42264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 422744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4228c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 422931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 423031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 423131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 423231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 423331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 423431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 423531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 423631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 423731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 423831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4239c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4240c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4241c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4242c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4243c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4244c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4245c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4246c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4247c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4248c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 424931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4250a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 4251c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4252c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 425331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 425431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 425531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 425605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 425805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 425905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 426005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 426105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 426205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 426305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 426620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 42672dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 426820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 42694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 42704447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 42714447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 4272c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara int n_ports, port, rc; 427320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4274a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 4275a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 427620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42774447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 42784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 42794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 42804447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 42814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 42824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 42834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 42844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4285f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 42861bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = board_idx; 42874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 42884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 428924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 429024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 429120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 429220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42930d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 42940d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 429524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 42960d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 429724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 42984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4299f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 430020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4301d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4302d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4303d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4304d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4305da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4306da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4307da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4308da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 4309c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara for (port = 0; port < host->n_ports; port++) { 4310c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara struct ata_port *ap = host->ports[port]; 4311c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4312c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara unsigned int offset = port_mmio - hpriv->base; 4313c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 4314c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4315c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4316c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara } 4317c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 431820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 43191bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 432024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 432124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 432220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43236d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 43246d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 43256d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 432620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 432731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 43284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 432920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43304447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4331ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 43324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4333c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 433420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 4335b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4336b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4337b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev) 4338b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara{ 4339b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 4340b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara int rc; 4341b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4342b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = ata_pci_device_do_resume(pdev); 4343b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4344b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4345b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4346b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara /* initialize adapter */ 4347b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = mv_init_host(host); 4348b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4349b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4350b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4351b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara ata_host_resume(host); 4352b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4353b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return 0; 4354b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara} 4355b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 43567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 435720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4358f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4359f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4360f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 436120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 436220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 43637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 43647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 43657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 43747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 43757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 437620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 437720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 437820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 437920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 43807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 438120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 43827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 438420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 438520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 438620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 438720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 438820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 438920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 439020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 439117c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 439220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 439320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 439420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 4395