sata_mv.c revision d16ab3f633b75aac1cf42b00355cd9aa65033dcc
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 2785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 2885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Errata workaround for NCQ device errors. 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> More errata workarounds for PCI-X. 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Complete a full errata audit for all chipsets to identify others. 3385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, low priority] Investigate interrupt coalescing. 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Quite often, especially with PCI Message Signalled Interrupts (MSI), 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * the overhead reduced by interrupt mitigation is quite often not 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * worth the latency cost. 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 4285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 4385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 4485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 568d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 58a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 59f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 60f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 62c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 64193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 656c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 69da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord#define DRV_VERSION "1.26" 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 7420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 7620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 7820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 82615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 83615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 84615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 85615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 86615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 87615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 898e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 908e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 918e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 9931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 10031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 10131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 10231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 10331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 10431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 10531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 10631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 107da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 10831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 10931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 110352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 112352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 113352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 114352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 11520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 11720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 11820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 120c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 12191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 122ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 12391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 12591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE | 126ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 127da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ATA_FLAG_NCQ, 12891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 12991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 130ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 13131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 13231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 133c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 135c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 13631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 13731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 13831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 13931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 141c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 142c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 14720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 1498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 15220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 15420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1568e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1578e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1588e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 159522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 160522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 161522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 162522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 1638e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 164522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 16902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 17402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 175646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 17602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 1777368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 1787368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 1797368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 1807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 1817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 182352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 183352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 18420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 189fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 190fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 196fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 197e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 203352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 204352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 20520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 20831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 20931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2140c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 215c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 21617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 217e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 21817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 21917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 22047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 221bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 222ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 223ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 224ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 225ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 226ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 227bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 228e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2298e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 230e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 231e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2338e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2348e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 23617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 237c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 241bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 242bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2460c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2470c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2480c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2490c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2500c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 251e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 252e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2566c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2576c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 262c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 263c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 265c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 270646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 272646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 273646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 275646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2796c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2866c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2886c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 289c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 290c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 29585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 297bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 298bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 301bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3036c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 311e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3196c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3360ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 3428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 34320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 3458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 3468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 348c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */ 349da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 350da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_CMD_OFS = 0x224, /* bmdma command register */ 351da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_STATUS_OFS = 0x228, /* bmdma status register */ 352da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */ 353da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */ 354da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 35531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 36047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 3610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3630ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 365616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 3661f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 36720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3690ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 370721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 37100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 37229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 373d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 37420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 376ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 377ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 378e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 3801f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 381bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 38315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 38415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 386baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 387baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 388baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 389baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 390095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3920ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3930ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 394095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 395095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3960ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 397095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 398095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 399095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 401522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 402522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 403522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 404522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 405522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 406e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 409522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 410522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 41131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 413e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 420e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 421e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 422e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 423e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 425e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 426e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 429e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 430e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 431e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 43220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 436e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 437e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 438e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 439e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 44120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 44208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 44308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 44408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 44508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 44608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 44708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 44808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 44908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 45008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 451c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 45208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 45308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 45431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 45531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 45631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 45731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 45831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 459eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 460eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 46531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 46608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 46729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 46831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 46931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 470bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 471bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 472bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 473bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 474bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 47502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 47602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 47796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 47802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 47902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 480f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 481f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 4827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 4837368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 48402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 48502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 48602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 487da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 488da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 489da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 490da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 491da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 492da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 493da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 494da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 49502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 49602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 49747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4982a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4992a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 50147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 50247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 503c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 504c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 505522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 50747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 50847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 50982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 51082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 51182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 51282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 51331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 51431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5153e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 51631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 517e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5189a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 519a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 520a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 523f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 52420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5252a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5262a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 52747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 52847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 52947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 530c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 531c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 532522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 53447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5352a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5362a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 53747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 53847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 53947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 540c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 541c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 542522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 543f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 544f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 545f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 546f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 547f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 548f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 549f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 550f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 551f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 553e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 554c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 555e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 556b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 55700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 55847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 559e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 560e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 561e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 562e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 563e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 56429d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 5654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 5664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 56747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 568da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 569da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 570da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 571da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 572da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 573da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 574d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 575da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 576eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 577eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 578eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 579eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 580c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 58168d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 582baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 583c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 584c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 585c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 586c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 58768d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 588138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 589baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 59020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 59120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 59220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 593029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 594029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 595c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 5963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 597c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 598c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 599c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 600bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 602a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 603a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 604029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 606c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 607c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 608c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 609c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 610c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 612c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 613029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 614029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 615f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 61620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 61720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 61820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 619e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 620e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 621e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 62229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 623da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 624d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord .sff_check_status = mv_sff_check_status, 625da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 626da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 627da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 628da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 629da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 630da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 63120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 63220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 633029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 634029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 635029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 636e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 637e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 638e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 63998ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 64020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 64191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 64231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 643bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 644c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 64520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 64620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 64791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 64831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 649bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 650c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 65120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 65247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 65391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 65447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 655bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 656c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 65747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 65820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 65991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 66031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 661bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 662c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 66320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 66420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 66591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 66631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 667bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 66920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 670e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 67191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 672e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 673bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 674e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 675e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 676e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 67791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 678e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 679bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 680e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 681e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 68391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 68417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 68517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 68617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 687f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 68820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6903b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6912d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6922d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6932d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6942d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 69546c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 69646c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 6974462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 6984462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 6992d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7002d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7012d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7022d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7032d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7042d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7052d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7062d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7072d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 708d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 709d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 710d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 71102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7126a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 7136a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 71402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 71502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 71602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 71702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 7182d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 72247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 72347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 72447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 72547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 726522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 727522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 72847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 72947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 73047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 73147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 73247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 73347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 73447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 735522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 736522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 73747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 73847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 742f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 74820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 74920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 75020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 75120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 75220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 75320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 75420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 75520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 75620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 75720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 758c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 759c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 760c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 761c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 762c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 763c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 764c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 765c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 766c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 767c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7681cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7691cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7701cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7711cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7721cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7731cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7747368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 7757368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 7761cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7771cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7781cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7791cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7801cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7811cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7821cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7831cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7841cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7851cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 786352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 787352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 788352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 789352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 790352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 791c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 792c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 793c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 794c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 795c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 796c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 79720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 79820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 799c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8008b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 801c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 80220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 80320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 804e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 805e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 806e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 807e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 808e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 809e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 810e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 811e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 817f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 81820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 81920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 82120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 82220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 823cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 82431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 825cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 82631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 82731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 82808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 82908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 83008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 83108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 83208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 83308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 83408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 83508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 83608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 83708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 83808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 83908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 84008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 84108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 84208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 84308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS); 84408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.ltmode = readl(port_mmio + LTMODE_OFS); 84508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 846c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS); 84708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 84808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 84908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 85008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 85108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 85208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 85308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 85408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 85508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 85608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 85708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 85808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 85908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 86008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 86108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 86208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord writel(new, addr); 86308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 86408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 86508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 866c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 867c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 868c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 869c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 871bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 872c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 873c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 874c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 875fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 876fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 877bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 878c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 879c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 880bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 881c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 8825cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 883c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 884c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 885c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 886c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 887fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 888fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 889bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 890c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 891c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 8925cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 893bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 894c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 895c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 896c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 897c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 898c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 899c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 900c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 901c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 902c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 90396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 904c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 90596e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 90696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 907c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord writelfl(new_mask, hpriv->main_irq_mask_addr); 90896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 909c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 910c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 911c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 912c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 913c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 914c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 915c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 916c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 917c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 918c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 919c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 920c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 921c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 922c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 923c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 92400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 92500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 92600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 92700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 92800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 92900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 93000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 93100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 93200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 93300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 93400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 93500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 93600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 93700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 93800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 93900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 94000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 94100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 94200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 94300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 94400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 94500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 94600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 94700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 94805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 94900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 95005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 95105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 95205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 953beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 954beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 95505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 95605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 95705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 95805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 95900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 960721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 96120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 962721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 963721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 964721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 965721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 966721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 967b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 968721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 969c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 9700c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 9710c58912e192fc3a4835d772aafa40b72552b819fMark Lord 97200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 9730c58912e192fc3a4835d772aafa40b72552b819fMark Lord 974f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 97500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 976bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 977f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 978afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 979afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 98020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 98120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9829b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 9839b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 9849b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 9859b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 9869b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 9879b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 9889b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 9899b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 9909b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 991c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 992c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 993c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 994c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 9959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 9969b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 9979b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 9989b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 9999b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 10009b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 10019b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 10029b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 10039b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 10049b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 100505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1006e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1007b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 100805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 100905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 101005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 101105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1012b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 101320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1014b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 101531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1016b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1017b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 10188b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1019b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1020b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1021b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 10224537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1023b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1024b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 102531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1026b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 102720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1029e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 10300ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1031b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1032b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 103366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 10340ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1035b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1036b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1037b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 10389b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1039b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1040b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 104166e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1042b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 104366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 104466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 10450ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 10460ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 10478a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 104831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 104920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 105031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 105131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 105231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 105331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 10542dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 105531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 105631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 105731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 105831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 105931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 10608a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 10618a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 106231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 106331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 106431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 106531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 106631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 106731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 106831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 106931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 10702dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 10712dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 107231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 107331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 107431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 107531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 107631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 107731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 107831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 107931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 108031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 108131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 10828b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 108331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 108431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 108531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 108631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 108731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 108831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 108931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 109031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 109131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 109231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 109331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 109431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 109531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 10968b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 109731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 109831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 109931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 110031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 110131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 110231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 110331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 110431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 110531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 110631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 110731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 110831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1109d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 111031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 111131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 111231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 111331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 111431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 11152dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 111631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 11172dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 111831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 111931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 112031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 112120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 112220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 112320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 112420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 112520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 112620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 112720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 112820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 112920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 113020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 113120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 113220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 113320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 113420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 113520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 113620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 113720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 113820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 113920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 114020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 114120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 114220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 114382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 114420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 114520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 114620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1147da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 114882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1149da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1150da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1151da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 115220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 115320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 115482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 115520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 115620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 115720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1158da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 115982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo writelfl(val, mv_ap_base(link->ap) + ofs); 1160da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1161da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1162da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 116320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 116420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1165f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1166f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1167f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1168e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1169e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1170e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1171e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1172f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1173e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1174352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1175e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1176352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1177352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1178352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1179e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1180f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1181f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 11823e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 11833e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 11843e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 11853e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 11863e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 11873e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11883e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 118929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 119029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 119129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 119229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 119329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 119429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 11953e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 11963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11973e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 11983e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11993e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 12004bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 12014bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 12024bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 12034bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 12044bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 12054bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 12064bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 12074bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 12084bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo return 0; 12094bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 12103e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 12113e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 12123e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 121308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1214e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 121508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 121608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 121700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 121808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 121908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 122008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 122100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 122208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 122308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 122400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 122500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 122608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 122708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 12284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 122908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 12304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 123108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 123208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 123308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1234e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 123500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 123608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 123708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg); 123808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode); 123908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond); 1240f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1241f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1242dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1243dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1244dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1245dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1246dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1247dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1248dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1249dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1250dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1251dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1252dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1253dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1254dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1255dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1256dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1257c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 1258c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 1259c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * @ap: Port being initialized 1260c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1261c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1262c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1263c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1264c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1265c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1266c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1267c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1268c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1269c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1270c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1271c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1272c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1273c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1274c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1275c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1276c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1277c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1278c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new); 1279c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1280c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 128100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1282e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 12830c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1284e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1285e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1286e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1287e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1288e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 12890c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1290d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1291d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1292e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 12930c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1294e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1295e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1296dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1297e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1298dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1299e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1300dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 130100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 130200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 130300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 130400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 130500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 130600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 130700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 130800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 130900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 131000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 131100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 131208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 131300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 131400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 131500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 131600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 131700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 131800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1319e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 132000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 132100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 132200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 132300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 132400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1325616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1326616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1327c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1328e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1329e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1330721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1331721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1332721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 133300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1334721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1335e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1336e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1337e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1338da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1339da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1340da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1341da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1342eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1343da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1344da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1345da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1346da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1347da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1348da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1349da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1350da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1351da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1352eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1353eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1354eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1355eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1356eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1357eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1358eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1359eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1360eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1361eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1362eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1363eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1364da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1365da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1366da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 136705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 136805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 136905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 137005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 137205b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 137305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 137505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 137605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 137731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 137831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1379cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1380cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 138131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1382dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 138331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 138424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 13856037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 138624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1387da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 138831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1389da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1390da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1391da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1392da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 139331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1394da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1395da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1396da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1397da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 139831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 13993bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 14003bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 14013bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1402eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1403eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1404eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1405eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1406eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1407eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1408eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1409eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1410eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1411eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1412eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1413eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1414eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1415eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1416eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 141708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 141866e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 141931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1420da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1421da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1422da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1423da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 142431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 142531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 142605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 142705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 142805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 142905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 143105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1433cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 143405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 143531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 143631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1437e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 143888e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1439da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 144131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 144205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 144305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 144405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 144505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 144605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 144705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 144805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 144905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 145005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 14516c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 145231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 145331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1454972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 14553be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1456ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 145731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1458eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1459ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1460d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1461d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 146222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 14634007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 14644007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 14654007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 146622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 146732cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 14684007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 14694007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 14704007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 14714007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 14726c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 147332cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 14744007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 14754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 14764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 14774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 14783be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 14794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 14804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 148131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 14823be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 14833be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 14843be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 148532cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 148631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 148731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14885796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 148931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1490559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 149131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1492559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 149331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 149431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 149505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1496da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1497da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1498da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1499da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1500da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1501da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1502da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1503da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1504da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1505da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1506da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1507da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1508da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1509da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1510da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1511da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1512da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1513da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1514da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1515da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1516da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1517da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1518da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1519da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1520da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1521da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1522da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1523da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1524da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1525da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1526da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1527da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1528da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1529da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1530da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1531da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1532da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1533da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1534da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1535da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1536da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1537da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1538da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1539da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1540da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1541da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1542da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1543da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1544da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1545da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1546da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1547da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1548da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1549da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1550da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1551da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1552da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1553da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1554da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1555da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1556da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel(0, port_mmio + BMDMA_CMD_OFS); 1557da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1558da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1559da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1560da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord port_mmio + BMDMA_PRD_HIGH_OFS); 1561da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1562da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord port_mmio + BMDMA_PRD_LOW_OFS); 1563da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1564da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1565da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1566da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1567da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1568da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1569da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1570da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1571da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1572da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1573da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1574da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1575da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1576da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1577da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1578da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1579da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1580da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1581da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1582da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1583da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(cmd, port_mmio + BMDMA_CMD_OFS); 1584da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1585da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1586da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1587da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1588da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1589da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1590da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1591da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1592da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1593da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1594da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1595da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1596da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1597da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1598da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1599da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1600da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1601da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1602da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd = readl(port_mmio + BMDMA_CMD_OFS); 1603da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1604da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(cmd, port_mmio + BMDMA_CMD_OFS); 1605da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1606da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1607da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1608da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1609da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1610da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1611da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1612da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1613da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1614da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1615da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1616da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1617da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1618da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1619da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1620da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1621da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1622da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1623da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1624da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1625da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1626da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1627da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1628da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord reg = readl(port_mmio + BMDMA_STATUS_OFS); 1629da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1630da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1631da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1632da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1633da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1634da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1635da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1636da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 163705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 163805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 163905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 164005b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 164105b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 164205b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 164305b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 164405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 164505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 164605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 164705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 164831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 164931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 165031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 165131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1652e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 165331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 165431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1655a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 165631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1657138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1658138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 165931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 166020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 166131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 166231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1663e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 166431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1665beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 166631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1667e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 166831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1670fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1671a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1672a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1673eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1674a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1675eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1676a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 167731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1678a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 167931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 168031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 168131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 168231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 168331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 168431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 1685cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 1686cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 168720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 168831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 168931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 169031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 169131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 169231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1693c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 169431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 169531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 169631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 169731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 16988b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 169931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 170031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 170131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 170231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 170331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 170431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 170531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 170631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 170731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 170831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 170931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 171031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 171131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 171231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 171331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 171431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 171531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 171631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 171731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 171831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 171931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 172031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 172131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 172231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1723e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1724e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1725e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1726e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1727e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1728e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1729e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1730e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1731e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1732e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1733e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1734e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1735e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1736e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1737e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1738e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1739e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1740e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1741e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1742e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1743e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1744e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1745e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1746a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1747e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1748e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1749138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1750138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1751e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1752e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1753e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1754e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1755e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1756e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1757beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1758e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 17598c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1760e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1761e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1763fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1764a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1765a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1766eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1767eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1768e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1769e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1770e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1771e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1772e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1773e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1774e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1775e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1776e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1777e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1778e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1779e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1780e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1781e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1782e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1783e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1784e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1785e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1786e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1787e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1788e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1789e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1790e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1791e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1792e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 179331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 179431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 179531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 179631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 179705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1798d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 1799d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 1800d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 1801d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 1802d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 1803d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 1804d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 1805d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 1806d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 1807d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 1808d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 1809d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 1810d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 1811d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 1812d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 1813d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 1814d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 1815d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 1816d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 1817d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 1818d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 1819d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 1820d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 1821d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 1822d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 1823d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 1824d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 182505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 182605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 182705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 182805b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 182905b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 183005b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 183105b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 183205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 183305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 183405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 183505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 18369a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 183731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1838f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 1839c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1840c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1841c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1842bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 184342ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 1844f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 1845d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 1846d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 1847f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 1848f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 1849f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 1850f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 1851f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1852f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 1853f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 1854f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 1855f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1856f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 1857f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 185831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1859f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 1860c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 1861c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 1862c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 1863c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 1864c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 1865c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 1866c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 1867c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 1868c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 1869c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 1870c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 1871c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 1872c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 1873c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 1874c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 1875c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 1876c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 1877f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 187842ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 1879f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 188042ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 188142ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 188242ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 188342ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 188431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 188542ed893d8011264f9945c2f54055b47c298ac53eMark Lord 188642ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 188742ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 188842ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 188942ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 189042ed893d8011264f9945c2f54055b47c298ac53eMark Lord 189142ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 189242ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 189342ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 189442ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 189542ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 189642ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 189742ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 189842ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 189942ed893d8011264f9945c2f54055b47c298ac53eMark Lord return ata_sff_qc_issue(qc); 190031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 190131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 19028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 19038f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 19048f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 19058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 19068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 19078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 19088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 19098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 191095db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc) { 191195db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 191295db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 191395db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) 191495db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 191595db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord } 19168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 19178f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 19188f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 191929d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 192029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 192129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 192229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 192329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 192429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 192529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 192629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 192729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 192829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 192929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 193029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 193129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 193229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 193329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 193429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 193529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 193629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 193729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 193829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 193929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 194029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 194129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 194229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 194329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 194429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 194529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 19464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 19474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 19484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 19494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 19504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 19514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 19524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 19534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 19544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 19554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 19564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 19574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 19584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 19594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 19604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 19614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 19624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 19634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 19644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 19654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 19664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 19674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 19684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 19694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 19704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 19714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 19724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 19734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 19744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 19754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 19764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 19774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 197806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 197906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 198006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 198106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 198206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 198306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) 198406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 198506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) 198606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 198706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 198806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 198906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 19904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 19914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 19924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 19934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 19944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 19954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 19964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 19974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 19984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 19994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 20004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 20014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 20024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 20034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 20044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 20054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 20064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 20074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 20084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 20094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 20104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 20124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 20134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 20144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2015c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 20164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 20184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 20194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 20204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 20214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 20224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 202306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 20244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 20254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 20264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 20274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 20284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 20294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 20304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 20314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 20324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 20334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 20354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 20364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 20374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 20384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 20394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 20404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 20414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 20424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 20434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 20444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 20454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 20464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 20474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 20484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 20494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 20514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 20524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 20534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 20554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 20564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 20574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 20584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 20604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 20614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 20624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 20634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 20644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 20654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 20664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 20674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 20684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 20694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 20704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 20714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 20724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 20734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 20744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 20754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 20764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 20774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 20784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 20794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 20804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 20814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 20824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 20834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 20844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 20854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 20864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 20874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 20884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 20894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 20904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 20914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 20924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 20934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 20944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2095a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 20968f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 20978f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2098a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 20998f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 21008f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 2101a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2102a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 2103a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 2104a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 21058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 21068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 21078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2108a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 21098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2110a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 21118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 21128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 21138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 21148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 21158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 211605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 211705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 211805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 211905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 21208d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 21218d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 21228d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 212305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 212405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 212505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 212605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 212737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 212831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 212931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2130bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2131e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2132bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2133bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2134bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 21359af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 213637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 213737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 213820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21398d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 214037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2141e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2142e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 21438d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 214437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 214537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 214637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2147bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2148e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2149e40060772d85f3534d3d517197696e24bb01f45bMark Lord fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 2150e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 2151e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 21528d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2153bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 21544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 21554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 21564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 21574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 21584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 21594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 21604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 21614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 21624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 216337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 216437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 216537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 216637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2167e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2168c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2169e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2170c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (fis_cause & SATA_FIS_IRQ_AN) { 2171c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2172c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2173c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2174c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2175c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2176c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2177c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2178c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2179bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2180352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2181bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 218237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2183bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 218437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 218537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 218637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2187bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 21886c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2189bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2190bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2191cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2192b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2193bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2194bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2195bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2196bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2197b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2198cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2199bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2200bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2201352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2202352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2203352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2204352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2205ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2206bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2207bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2208bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2209b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2210bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2211bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2212bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2213bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2214bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2215b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2216bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2217bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 22188d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 22198d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2220cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2221bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2222afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 222320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2224bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2225bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2226cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2227bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2228bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2229bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2230bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2231bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2232bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2233bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2234bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2235bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2236bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 223737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 223837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 223937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 224037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 224137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 224237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 224337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 224437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 224537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 224637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 224737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 224837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2249bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 225037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 225137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 225237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 225337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 225437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 225537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 225637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 225737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 225837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 225937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2260bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2261bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2262fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2263fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2264fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2265fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2266fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2267fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2268fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2269fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2270fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2271fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2272fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 2273fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2274fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2275fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2276fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2277fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2278fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2279fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2280fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2281fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2282fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2283fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2284fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2285fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 228637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 228737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 228837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2289fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2290fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2291fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2292fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2293fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2294fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2295fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2296bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2297bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2298bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2299fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2301fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2303fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 2305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2307fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2308fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 23096c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2310fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2312fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2314fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2315fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 23169af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2317fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2318fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2319fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2321fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2325352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2328fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2329bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 233020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 233120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2332a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2333a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2334a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2335a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2336a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2337a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2338a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2339a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2340a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2341a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2342a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2343a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2344a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2345a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2346a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2347a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2348a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2349a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2350a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2351a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2352a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 23534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 23544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2355a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2356a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2357a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2358a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2359a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2360a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2361a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2362a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2363a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2364a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2365a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2366a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2367a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2368a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2369a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 237005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 237105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2372cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 23737368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 237405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 237505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 237605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 237705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 23787368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 237920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2381eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2382a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 238320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2384a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2385cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2386eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2387eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2388a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2389a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2390eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2391eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2392a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2393eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2394eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2395eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2396eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2397eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2398eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2399eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2400eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2401eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2402eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2403eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2404eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2405eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2406eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2407eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2408eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2409eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2410eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2411eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2412eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2413eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2414eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2415eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 2416eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2417eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2418eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2419eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2420eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2421eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2422eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2423a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2424eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2425a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2426a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 24278f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2428a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 24298f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2430a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2431a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2432a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 243320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2434a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 243520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 243620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2437a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 243902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 244602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2453bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 245402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2458936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 24599af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2465cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 24669af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2469bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2470bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2472bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2475a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2476bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2477bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 247805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2479c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 248005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 248105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 248205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 248305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 248405b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 248505b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 248605b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 248705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 24888b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2489cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 249005b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 249105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 24927d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 249320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2494cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2495f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2496a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 24976d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 249896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 249920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2500646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 25016d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 25026d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 25036d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 25046d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord writel(0, hpriv->main_irq_mask_addr); 25056d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 25067368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 250796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2508352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2509352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2510352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 251120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2512a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 25131f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2514a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2515a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2516a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 25186d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 25196d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 25206d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 25216d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr); 25226d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 25239d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 25249d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 252520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 252620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 252720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2528c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2529c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2530c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2531c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2532c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2533c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2534c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2535c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2536c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2537c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2538c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2539c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2540c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2541c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2542c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2543c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2544c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 254582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2546c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 254782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2548f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 254982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2550c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2551c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2552da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2553da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2554da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2555da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2556da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2558c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 255982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2560c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 256182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2562f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 256382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2564c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2565c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2566da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 25670d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2568da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2569da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2570da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2571c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2572c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 25737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2574522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 25757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2576522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2577522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 257844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2579522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2580522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2581522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2582522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2583522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2584522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2585522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 25867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2587522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2588522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2589522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2590522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 25918e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2592522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2593522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 259447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2595ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2596ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2597c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2598c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2599c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2600c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2602c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2603c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2604ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2605ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 260647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2607ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2608522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 2609522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 26108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2611522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2612522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2613522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2614522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2615522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 2616522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2617ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2618ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 26192a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 26202a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2621bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2622c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2623c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2624c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2625c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2626c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2627c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 26288e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2629c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 26308e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2631c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 26328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2633c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 2634c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 26358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2636c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2637c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2638c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2639c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 2640c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 2641c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 2642c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 2643bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2644bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2645c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2646c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2647c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 2648c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2649c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 2650c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2651c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2652c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2653e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2654c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2655c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 2656c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 2657c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 2658c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 2659c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 2660c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 2661c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 2662c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 2663c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 2664c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 2665c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 2666c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 26678e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2669c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2670c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2671c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 2672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 267447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2675c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2676c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2677c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2678c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2679c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2680c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2681c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2682c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2683c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2684c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2685c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2686c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2687c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2688c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2689c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2690c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2691c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2692c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2693c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2694c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2695c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2696c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2697c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2698c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2699c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2700c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2701c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2702c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2703c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 270447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 270547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2706101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2707101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 27087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2709101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 271002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2711101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2712101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 27138e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 2714101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 27158e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 2716101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2717101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2718101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 27198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 2720101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 272102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 272202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2723101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2724101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2725101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2726101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2727101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2728101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2729101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2730101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2731101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2732101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2733101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2734101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2735101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 27368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2737101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2738101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 27398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2740101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2741101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2742101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2743101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2744101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2745101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2746101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2747101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2748101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2749101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2750101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2751c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2752c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2753101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2754101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2755101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2756101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2757101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2758101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2759101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2760101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2761101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2762101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2763101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2764101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2765101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2766101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 27672dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2768101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2769101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2770101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2771101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2772101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2773101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2774101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2775101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2776101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2777101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2778101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2779101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2780101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2781101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2782101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2783101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2784101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2785101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2786101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2787101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2788101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2789101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2790101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2791101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2792101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2793101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2794101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2795101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2796101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2797101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2798101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2799101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2800101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2801101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2802101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2803101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2804101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2805101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 280647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2807ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2808ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2809ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2810ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2811ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 28128e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 2813ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 281447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2815ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2816ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2817ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2818ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2819ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2820ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2821ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2822ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2823ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2824ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2825ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 282647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2827ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 28288e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2829ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2830ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2831c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 28322a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2833bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2834c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2835c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2836bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 283747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 283847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2839bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 284047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 28418c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 284247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 284347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 284447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 284547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 284647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 284747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 284847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 284947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 285047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 285147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 285247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 285347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 285447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 285547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 285647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 285747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 28588c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 28598c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 28608c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 28618c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 28628c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 28638c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 2864bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 28650388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 28660388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 28670388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 28680388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 2869bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 2870ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 2871ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 2872ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 2873ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 2874ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 2875ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 28768c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 2877ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 2878ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 2879ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 28808c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 2881bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2882b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 2883b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 2884b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 2885b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 2886b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 2887b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 2888bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2889bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2890bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2891bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2892bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 28932a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 28942a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 289547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2896bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2897e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2898e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2899e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2900e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2901e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2902e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2903bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2904bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2905bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2916f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2917f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2918f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2919f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2920f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2921f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2923f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2924f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2925f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2926f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2927f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2928f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2929f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2930f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2931f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2932f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2933f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2934e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2935f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2936f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2937f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2938f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2939f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2940f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2941f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2944f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2945f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2946f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2947f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 29488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2949f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2950f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2951f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2952f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2953f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2954f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2955f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2956f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2957f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2958f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2959f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2960f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2961f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2962f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2963f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2964f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2965f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2967f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2968f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2969f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2971f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2972f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2973f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2974f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2975f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2977f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2978f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2979f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2980f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2981f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2982f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2983f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2985f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2986f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2987f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2988f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2989f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2990f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29918e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2992b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 29938e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2994b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 29958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2996b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 29978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 29988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2999b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3000b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3001e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 30068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 30078e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 30088e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 30098e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 30108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 30110d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 30128e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 3013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3014b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 30158e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 30168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3018b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 30198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3020b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3021b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 3022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 30238e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 3024b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 3026c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3028c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3029ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3030c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3033e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 303420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3035e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3036e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3037e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 3038e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 303922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3040e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3041e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3042e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 3043e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 304422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 304520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 304620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3047e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3048e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 304922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3050e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3051e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3052e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3053bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3054e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3055e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3056e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3057e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3058e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 305922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 306022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3061cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3062bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 306331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3064cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3065bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3066b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3067f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 30680d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 30690d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 30700d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 307131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3072e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3073b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3074d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3075d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3076bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 30770d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 30780d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 307917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 308017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3081bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 308217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 308317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 30849dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 308517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 30860d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 30870d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 30880d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 30890d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 30908e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 30910d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 30920d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 30930d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 30940d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 309508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 309666e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3097bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 309817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3099bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3100bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3101bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3102bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 31031cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3104c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3105bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3106bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3107bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3108bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3109f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3110c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3111c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 31121cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3113bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3114c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3115bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3116bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3117bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 3118bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3119bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3120cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 31211cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 3122bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 312388e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 312431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 312531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 312605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 312705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 312805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 312905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 313005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 313105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 313205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 313305b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 313405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 313505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 313605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 313705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 313831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 313920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 31400d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 314131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 314231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 31438b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 314431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 314531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 31468b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 314731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 314831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 314931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 315031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 315131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 315231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 31538b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 315431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 315531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 315631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 315731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 315831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 31598d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 316020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 316131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 316231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 316331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 316431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 316531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3166646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3167646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 316820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31698b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 317031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 317131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 317231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 317320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 317420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3175616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3176616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3177616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3178616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3179616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3180616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 31811f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3182616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3183616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 3184616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3185616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3186616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3187616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3188616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3189616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3190616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3191616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3192616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3193616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3194616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3195616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3196616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 3197616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 3198616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3199616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3200616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3201616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3202616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 32034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3204bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 32054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 32064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3207bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3208bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 32095796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 321047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 321147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3212ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 321347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 321444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 321547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 321647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 321747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 321847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 321947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 322047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 322147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 322247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 322347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 322447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 322547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 322647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 322747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 322847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 323147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3232ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3233bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 323444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 323547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 323647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 323747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 323847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 323947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 324047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 324147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 324247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 324347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 324447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 324547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3246bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3247bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3248bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3249bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3250bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 325147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3252ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 325347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 325444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 325547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 325647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 325747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 325847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 325947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3260bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3261bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3262bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 326347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 326447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3265bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3266bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3267bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3268bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3269e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3270616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3271306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3272306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3273306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 32744e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 32754e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 32764e5200334e03e5620aa19d538300c13db270a063Mark Lord * 32774e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 32784e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 32794e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 32804e5200334e03e5620aa19d538300c13db270a063Mark Lord * 32814e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 32824e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 32834e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 32844e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 32854e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 32864e5200334e03e5620aa19d538300c13db270a063Mark Lord * 32874e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 32884e5200334e03e5620aa19d538300c13db270a063Mark Lord * 32894e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 32904e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 32914e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 32924e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 32934e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 32944e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 32954e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 32964e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 32974e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 32984e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3299306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 33008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3301e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3302e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3303e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3304616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3305616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3306e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 330744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 33085cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3309e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3311e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3312e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3313e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3314e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3315e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3316e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3317e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3318f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 3319f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 3320eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3321eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3322f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3323e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3324bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3325f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 33265796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3327bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3328bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3329bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3330bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 333102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 333202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 333302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 333402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 333502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 333602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 333702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 333802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 333902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3340bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3341bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3342bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3343bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 334405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 334547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 33464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 33474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 334805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 334905b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 335005b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 335105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 335205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 335305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 335405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 33554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 335620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 335720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 33584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3359f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 336047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 33614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3362bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3363352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 33651f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 33667368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 33677368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 33681f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 33691f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 33701f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3372352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 33735d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 33745d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 33755d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3376352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3377c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3378bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 33794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3380bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 33814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 338247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 338320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3384c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 338547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 338620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 338720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3388522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 33897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 339047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 339120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3393cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 33942a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3395cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3396cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3397cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 33987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 33991f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 34047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 340520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 340620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 340720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 340831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 340931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 341031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 341131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 341231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 341331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 341431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 341531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 341631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 341720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 341820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34196be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* Clear any currently outstanding host interrupt conditions */ 34206be96ac15e4d913e1f48299db083ada5321803b2Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 342131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 34226be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* and unmask interrupt generation for host regs */ 34236be96ac15e4d913e1f48299db083ada5321803b2Mark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 342451de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 34256be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 34266be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 34276be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 34286be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 34296be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 3430f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3431f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3433fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3434fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3435fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3436fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3437fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3438fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3439fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3440fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3441fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3442fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3443fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3444fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3445fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3446fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3447fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3448fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3449fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3450fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3451fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3452fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3453fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 345415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 345515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 345615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 345715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 345815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 345915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 346015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 346115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 346215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 346315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 346415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 346515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 346615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 346715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 346815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 346915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 347015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 347115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 347215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 347315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 347415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3475f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3476f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3477f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3478f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3479f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3480f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3481f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3482f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3483f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3484f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3485f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3486f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3487f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3488f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3489f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3490f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3491f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3492f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 349320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3494f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3495f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3496bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3497f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3498f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3499f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3500f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3501f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3502f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3503f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3504f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3505f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3506f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3507f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3508f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3509f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 3510f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3511f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3512f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 3513f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 3514f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 3515f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3516f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3517f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3518f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3519f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 3520f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 3521f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 3522f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 3523f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3524f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 3525f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 3526f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 3527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 3528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 352915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 353015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 353115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 353215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 353315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 353415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3535fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 3536fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 3537fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 3538fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3539f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 3540f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 3541f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 3542f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3543f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3544f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3545f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3546f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3547f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3548f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3549f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3550f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3551f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3552f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3553f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3554f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3555f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3556f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3557f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3558f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3559f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3560f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3561f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3562f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3563f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3564f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3565f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3566f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 356720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 356820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3569f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3570f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3571f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3572f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3573f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3574f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 3575f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 3576f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 3577f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3578f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 35797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3580f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3581f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 3582f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 35837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 35847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 35857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 35867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 3587f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 35887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 35897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 35907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 35917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 35927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 35937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 35947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 35957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 35967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 35977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 35987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 35997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 36007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 36017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 36027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 36037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 36047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 36057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 36067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 36077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 36087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 36097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 36107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 36117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 36127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 36137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 36147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 36157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 36167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 36177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 36187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 36197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 36207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 36217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 36227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 36237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 36247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 36257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 36267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 36277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 36287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 36297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 363005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 363105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 36324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 363305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 363405b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 363505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 363605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 363705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 363805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 36394447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 364031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 36414447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 36424447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 364344c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 3644c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 364531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 364631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 364731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 364831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 364931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 365031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 365131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 365231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 365331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 365431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 3655c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 3656c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 3657c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 3658c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 3659c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 3660c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 3661c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 3662c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 3663c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 3664c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 366531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3666a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 3667c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3668c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 366931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 367031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 367131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 367205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 3673f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 367405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 367505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 367605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 367705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 367805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 367905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 368220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 36832dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 368420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 36854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 36864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 36874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 36884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 368920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3690a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3691a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 369220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 36944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 36954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 36964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 36974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 36984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 36994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 37004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3701f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 37024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 37034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 370424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 370524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 370620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 370720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 37080d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 37090d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 371024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 37110d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 371224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 37134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 371520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3716d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3717d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3718d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3719d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3720da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3721da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3722da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3723da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 372420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 37254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 372624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 372724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 372820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 37296d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 37306d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 37316d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 373220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 373331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 37344447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 373520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 37364447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3737ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 37384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3739c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 374020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 37417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 374220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 374620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 374720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 37487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 37497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 37507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3752f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3753f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 37597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 37607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 376120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 376220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 376320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 376420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 37657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 376620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 37677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 376920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 377020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 377120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 377220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 377320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 377420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 377520f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 377617c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 377720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 37787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3779ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3780ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 37817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3782ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 378320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 378420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3785