sata_mv.c revision e12bef50b7660cf7c19d1cd3eac381b9eff734d7
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 434a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6) Add port multiplier support (intermediate) 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 454a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 464a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 728d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 74a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 75f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 76f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 78193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 796c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 831fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 96615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 97615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 98615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 103522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 104bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 105bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 121da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORTS_PER_HC = 4, 12520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 12620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 12731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_MASK = 3, 12920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 136c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 137bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 138bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 144e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 145c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 151c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 152c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 15931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 182646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_ERR = (1 << 0), /* shift by port # */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_DONE = (1 << 1), /* shift by port # */ 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 195fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 196fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 202fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 203e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 20520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 207fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 208fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 21531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_DMA_DONE = (1 << 0), /* shift by port # */ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2260c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 227e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 231e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 232e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 234e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 235c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 236c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 237c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 239bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 240bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2440c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2450c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2460c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2470c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2480c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 249e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 250e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2546c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2556c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2566c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2576c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 260c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 261c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 263c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 268646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 270646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 271646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 272646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 273646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2866c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 287c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 288c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX, 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 295bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 296bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 297bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 298bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3016c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 309e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3176c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 32631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3330ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3340ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3360ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 33720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 339bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 340bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 34131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 34231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 34347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 34447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 34547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 34647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 347e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3480ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3490ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3500ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 35102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 35220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 35331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3540ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 355721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 35620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 35720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 358ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 359ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 362bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 363095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 364baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 365baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 366baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 367baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 368095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3690ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3700ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3710ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 372095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 373095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3740ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 375095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 376095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 377095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 378522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 379522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 380522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 381522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 382522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 383522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 384e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 385e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 387522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 388522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 38931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 39031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 391e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 392e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 393e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 394e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 39531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 39620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 398e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 399e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 400e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 401e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 402e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 40531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 40631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 407e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 41020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 41120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 41331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 41831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 42131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 42431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 425eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 426eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 43131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 43231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 434bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 435bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 436bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 437bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 438bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 43902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 44002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 44102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 44202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 446f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 44702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 44802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 44902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 450da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 451da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 452da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 453da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 454da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 455da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 456da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 457da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 46047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4612a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4622a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 46347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 46447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 46547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 466c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 467c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 47047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 47147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 472da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 473da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 474da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 475da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 47631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 47831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 479e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4809a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 481a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_prereset(struct ata_link *link, unsigned long deadline); 482a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 483a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 484a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic void mv_postreset(struct ata_link *link, unsigned int *classes); 485bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 486bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 487f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 48820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4892a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 4902a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 49147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 49247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 49347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 494c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 495c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 496522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 4977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 49847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 4992a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5002a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 50347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 504c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 505c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 506522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 507f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 508f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 509f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 510f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 511f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 512f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 513f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 514f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 515f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 517e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 518c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 519e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 520e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma_engine(struct ata_port *ap); 521e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 52247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 523eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 524eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 525eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 526eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 527c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 52868d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 529baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 530c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 531c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 532c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 533c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 53468d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 535138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 536baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 53720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 53820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 53920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 540029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 541029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 542c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 543c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 544c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 545c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 548a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .prereset = mv_prereset, 549a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 550a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .postreset = mv_postreset, 551a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 552029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 554c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 555c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 556c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 558c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 559c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 560c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 561029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 562029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 563138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .qc_defer = ata_std_qc_defer, 564029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = mv6_dev_config, 56520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 56620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 56720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 569029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 570029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 571029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 572e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 573e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 574e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 57598ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 57620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 577cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 57831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 579bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 580c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 58220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 583c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 58431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 585bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 586c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 58847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 589c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 59047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 591bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 592c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 59347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 595138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 596138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 59731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 598bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 599c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 602c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 603138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 60431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 605bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 606c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 608e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 609138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 610138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 611e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 612bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 613e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 614e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 616138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 617138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 618e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 619bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 621e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .flags = MV_COMMON_FLAGS | MV_FLAG_SOC, 624f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .pio_mask = 0x1f, /* pio0-4 */ 625f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .udma_mask = ATA_UDMA6, 626f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .port_ops = &mv_iie_ops, 627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 62820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 62920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6303b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6312d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6322d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6332d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6342d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 635cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 636cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 637cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6382d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6392d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6402d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6412d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6422d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6432d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6442d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6452d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6462d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 647d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 648d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 649d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 65002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6516a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6526a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 65302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 65402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 65502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 65602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6572d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 65820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 66047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 66147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 66247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 66347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 66447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 665522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 666522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 66747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 66847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 66947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 67047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 67147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 67247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 67347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 674522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 675522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 67647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 67747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 679f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 68720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 68820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 69220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 69420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 69520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 69620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 69820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 69920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 70020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 70120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 702c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 703c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 704c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 705c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 706c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 707c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 708c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 709c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 710c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 711c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 712c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 713c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 714c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 715c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 716c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 717c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 720c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7218b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 722c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 725e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 726e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 727e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 728e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 729e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 730e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 731e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 732e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 73920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 74020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 74220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 74320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 744cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 74531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 746cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 74731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 74831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 749c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 750c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 751c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 752c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 753bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 755c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 756c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 757c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 758bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 760c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 761c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 763c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 764c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 765c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 766bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 767c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 768c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 770c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 771c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 772c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 773c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; 775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 776c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 777c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 778c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 779c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 781c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 782c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 784c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 786c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 787c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 788c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 78905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 79005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 79105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 79205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 79305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 794beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 795beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 79605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 79705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 79805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 79905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8000c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 801721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 80220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 803721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 804721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 805721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 806721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 807721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 808e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma_engine(ap); 809721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8110c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 8120c58912e192fc3a4835d772aafa40b72552b819fMark Lord int hard_port = mv_hardport_from_port(ap->port_no); 8130c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 8140fca0d6f2ce3336022a22bc7fc2e009e599e63a4Saeed Bishara mv_host_base(ap->host), hard_port); 8150c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8160c58912e192fc3a4835d772aafa40b72552b819fMark Lord 817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 818f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8200c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8210c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 8220c58912e192fc3a4835d772aafa40b72552b819fMark Lord ipending = (DEV_IRQ << hard_port) | 8230c58912e192fc3a4835d772aafa40b72552b819fMark Lord (CRPB_DMA_DONE << hard_port); 8240c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8250c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8260c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8270c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8280c58912e192fc3a4835d772aafa40b72552b819fMark Lord 829e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8300c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8310c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8320c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8330c58912e192fc3a4835d772aafa40b72552b819fMark Lord 834f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 835bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 836f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 837afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 838afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 839f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 84020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 84120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 84205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 843e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 84405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 84505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 846beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 847beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 852e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma_engine(struct ata_port *ap) 85320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 85431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 85531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 85631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 reg; 857c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik int i, err = 0; 85831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 8594537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 860afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ /* Disable EDMA if active. The disable bit auto clears. 86131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 86231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 86331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 864afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } else { 865beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)); 8662dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik } 8678b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 86831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* now properly wait for the eDMA to stop */ 86931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (i = 1000; i > 0; i--) { 87031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ reg = readl(port_mmio + EDMA_CMD_OFS); 8714537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 87231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 8734537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik 87431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ udelay(100); 87531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 87631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 877c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (reg & EDMA_EN) { 878f15a1dafed22d5037e0feea7528e1eeb28a1a7a3Tejun Heo ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 879c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik err = -EIO; 88031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 881c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 882c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik return err; 88320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 88420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 885e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 8860ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 8870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik unsigned long flags; 8880ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik int rc; 8890ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 8900ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_lock_irqsave(&ap->host->lock, flags); 891e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord rc = mv_stop_edma_engine(ap); 8920ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_unlock_irqrestore(&ap->host->lock, flags); 8930ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 8940ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik return rc; 8950ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 8960ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 8978a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 89831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 89920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 90031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 90131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 90231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 90331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9042dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 90531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 90631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 90731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 90831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 90931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9108a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9118a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 91231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 91331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 91431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 91531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 91631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 91731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 91831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 91931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9202dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9212dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 92231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 92331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 92431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 92731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 92831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 92931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 93031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9328b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 93331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 93731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 94031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 94331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 94431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 94531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9468b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 94931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 95131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 95331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 95731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 95831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 959d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 96431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9652dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 9672dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 97120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 97220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 97320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 97420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 97520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 97620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 97720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 97820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 97920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 98020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 98120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 98220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 98320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 98420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 98520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 98620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 98720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 98820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 98920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 99020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 99120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 99220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 993da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 99420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 99520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 99620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 997da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 998da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 999da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1000da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1001da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 100220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 100320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1004da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 100520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 100620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 100720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1008da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 100920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1010da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1011da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1012da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 101320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 101420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1015f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1016f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1017f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1018f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1019f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1020f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1021f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->flags & ATA_DFLAG_NCQ) 1022f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->max_sectors > ATA_MAX_SECTORS) 1023f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord adev->max_sectors = ATA_MAX_SECTORS; 1024f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1025f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1026e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1027e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10280c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1029e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1030e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1031e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1032e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1033e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 10340c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1035e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10360c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1037e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1038e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10390c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1040e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1041e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1042e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1043e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1044e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1045e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1046e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1047e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1048e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1049721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1050721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1051721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1052721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1053721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1054721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1055e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1056e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1057e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1058da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1059da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1060da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1061da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1062eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1063da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1064da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1065da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1066da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1067da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1068da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1069da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1070da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1071da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1072eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1073eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1074eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1075eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1076eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1077eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1078eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1079eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1080eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1081eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1082eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1083eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1084da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1085da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1086da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 108705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 108805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 108905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 109005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 109105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 109205b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 109305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 109405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 109505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 109605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 109731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 109831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1099cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1100cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 110131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 110231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 11030ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik unsigned long flags; 1104dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 110531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 110624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 11076037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 110824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1109da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 111031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1111da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1112da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1113da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1114da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 111531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1116da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1117da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1118da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1119da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 112031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1121eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1122eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1123eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1124eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1125eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1126eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1127eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1128eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1129eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1130eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1131eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1132eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1133eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1134eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1135eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 113631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_lock_irqsave(&ap->host->lock, flags); 11380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1139e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, 0); 1140c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik mv_set_edma_ptrs(port_mmio, hpriv, pp); 114131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11420ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_unlock_irqrestore(&ap->host->lock, flags); 11430ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 114431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Don't turn on EDMA here...do it before DMA commands only. Else 114531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * we'll be unable to send non-data, PIO, etc due to restricted access 114631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * to shadow regs. 114731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 114831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1149da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1150da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1151da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1152da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 115331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 115431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 115605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 115705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 115805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 115905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 116005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1162cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 116305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 116431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 116531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1166e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1167da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 116831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 116931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 117005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 117105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 117205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 117305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 117405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 117505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 117605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 117705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 117805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 11796c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 118031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 118131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1182972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 11833be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1184ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 118531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1186eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1187ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1188d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1189d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 119022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11914007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 11924007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 11934007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 119422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11954007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 11964007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 11974007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11984007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 11994007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 12006c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 12014007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12024007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 12034007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 12044007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12053be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 12064007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 12074007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 120831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12093be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 12103be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 12113be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 121231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 121331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12145796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 121531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1216559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 121731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1218559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 121931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 122031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 122105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 122205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 122305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 122405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 122505b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 122605b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 122705b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 122805b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 122905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 123005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 123105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 123205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 123331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 123431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 123631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1237e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 123931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1240a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 124131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1242138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1243138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 124520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1248e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1250beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1253bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1254bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1255a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1256a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1257eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1258a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1259eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1260a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1262a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 127020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1276c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 12818b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 129931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 130031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 130131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 130231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1306e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1307e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1308e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1309e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1311e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1312e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1313e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1314e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1315e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1316e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1317e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1318e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1319e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1320e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1321e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1322e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1323e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1324e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1325e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1326e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1327e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1328e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1329a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1330e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1331e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1332138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1333138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1334e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1335e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1336e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1337e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1338e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1339e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1340beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1341e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 13428c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1343e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1344bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1345bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1346a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1347a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1348eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1349eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1350e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1351e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1352e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1361e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1362e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1363e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1364e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1365e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1366e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1367e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1368e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1369e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1370e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1371e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1372e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1374e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 137531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 137631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 137731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 137831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 137905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 138005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 138105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 138205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 138305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 138405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 138505b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 138605b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 138705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 138805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 138905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 139005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13919a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 139231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1393c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1394c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1395c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1396bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 139731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1398138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1399138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 140031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* We're about to send a non-EDMA capable command to the 140131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 140231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 140331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1404e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma_engine(ap); 140531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return ata_qc_issue_prot(qc); 140631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 140731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1408721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1409bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1410bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->req_idx++; 141131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1412bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 141331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 141431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1415bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1416bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 141731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 141831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 141931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 142031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 142105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 142205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 142305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 14249b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 142505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 142605b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1427e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1428e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1429e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1430e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 143105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 143305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 143405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 143631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 143731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 14439af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 144420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 144620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1451936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1452936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 145320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause); 1458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * all generations share these EDMA error cause bits 1461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 14666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1469cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1470b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1472bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1475b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1476cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1477bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1478bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1479ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1480bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1481bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1482bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 14835ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1484bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1485b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1486bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1487bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1488bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1489bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1490bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 14915ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1492bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1493b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1495bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1496bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1497936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1498936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1500cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1502afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 150320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 150420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 15053606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 150620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1507bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1509cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1510bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1512bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1513bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1514bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1515bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1518bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1519bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1520bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_pio(struct ata_port *ap) 1527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u8 ata_status; 1530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* ignore spurious intr if drive still BUSY */ 1532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_status = readb(ap->ioaddr.status_addr); 1533bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(ata_status & ATA_BUSY)) 1534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get active ATA command */ 15379af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(!qc)) /* no active tag */ 1539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ 1541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= ac_err_mask(ata_status); 1545bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1548bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_edma(struct ata_port *ap) 1549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1552bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1554bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 out_index, in_index; 1555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get h/w response queue pointer */ 1558bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1559bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik while (1) { 1562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u16 status; 15636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1565bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get s/w response queue last-read pointer, and compare */ 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (in_index == out_index) 1568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 1569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 50xx: get active ATA command */ 15710ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik if (IS_GEN_I(hpriv)) 15729af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik /* Gen II/IIE: get active ATA command via tag, to enable 15756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * support for queueing. this works transparently for 15766c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * queued and non-queued modes. 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 15788c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord else 15798c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; 1580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15816c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik qc = ata_qc_from_tag(ap, tag); 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1583cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord /* For non-NCQ mode, the lower 8 bits of status 1584cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * are from EDMA_ERR_IRQ_CAUSE_OFS, 1585cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * which should be zero if all went well. 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik status = le16_to_cpu(pp->crpb[out_index].flags); 1588cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) { 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); 1597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1598bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1599bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16000ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* advance software response queue pointer, to 1601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * indicate (after the loop completes) to hardware 1602bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * that we have consumed a response queue entry. 1603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1604bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->resp_idx++; 1606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik (out_index << EDMA_RSP_Q_PTR_SHIFT), 1611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 161220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 161320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 161405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 161505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1616cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 161705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @relevant: port error bits relevant to this host controller 161805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @hc: which host controller we're to look at 161905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 162005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read then write clear the HC interrupt status then walk each 162105b308e1df6d9d673daedb517969241f41278b52Brett Russ * port connected to the HC and see if it needs servicing. Port 162205b308e1df6d9d673daedb517969241f41278b52Brett Russ * success ints are reported in the HC interrupt status reg, the 162305b308e1df6d9d673daedb517969241f41278b52Brett Russ * port error ints are reported in the higher level main 162405b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt status register and thus are passed in via the 162505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 'relevant' argument. 162605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 162705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 162805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 162905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1630cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 163120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 163420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 163520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 hc_irq_cause; 1636f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int port, port0, last_port; 163720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1638351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik if (hc == 0) 163920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = 0; 1640351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik else 164120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = MV_PORTS_PER_HC; 164220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1643f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) 1644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + MV_PORTS_PER_HC; 1645f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 1646f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + hpriv->n_ports; 164720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* we'll need the HC success int register in most cases */ 164820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!hc_irq_cause) 1650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 165320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 165420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 16552dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik hc, relevant, hc_irq_cause); 165620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16578f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu for (port = port0; port < last_port; port++) { 1658cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 16598f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1660bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik int have_err_bits, hard_port, shift; 166155d8ca4f8094246da6e71889a4e04bfafaa78b10Jeff Garzik 1662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) 1663a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1664a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik 16658f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu pp = ap->private_data; 16668f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu 166731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ shift = port << 1; /* (port * 2) */ 1668e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord if (port >= MV_PORTS_PER_HC) 166920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ shift++; /* skip bit 8 in the HC Main IRQ reg */ 1670e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 1671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik have_err_bits = ((PORT0_ERR << shift) & relevant); 1672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(have_err_bits)) { 1674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 16758b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 16769af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1677bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1678bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1679bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1680bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1681bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1682bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1683bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1684bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hard_port = mv_hardport_from_port(port); /* range 0..3 */ 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) 1688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_edma(ap); 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((DEV_IRQ << hard_port) & hc_irq_cause) 1691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_pio(ap); 169220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 169320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 169420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("EXIT\n"); 169520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 169620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1697bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1698bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 169902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1700bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1701bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1702bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1703bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1704bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1705bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 170602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 171402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1717bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1718936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17199af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1720bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1721bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1723bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1724bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1725cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17269af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1727bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1728bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1730bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1731bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1732bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1733bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1734bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1735bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1736bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 173705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1738c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 173905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 174005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 174105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 174205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 174305b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 174405b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 174505b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 174605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 17478b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1748cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 174905b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 175005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17517d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 175220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1753cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 175520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int hc, handled = 0, n_hcs; 1756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 1757646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord u32 irq_stat, irq_mask; 175820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1759e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Note to self: &host->lock == &ap->host->lock == ap->lock */ 1760646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1761f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 1762f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_stat = readl(hpriv->main_cause_reg_addr); 1763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_mask = readl(hpriv->main_mask_reg_addr); 176420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 176520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* check the cases where we either have nothing pending or have read 176620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * a bogus register value which can indicate HW removal or PCI fault 176720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1768646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat)) 1769646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord goto out_unlock; 177020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1771cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik n_hcs = mv_get_hc_count(host->ports[0]->flags); 177220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (unlikely((irq_stat & PCI_ERR) && HAS_PCI(host))) { 1774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_pci_error(host, mmio); 1775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 1776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik goto out_unlock; /* skip all other HC irq handling */ 1777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 177920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hcs; hc++) { 178020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); 178120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ if (relevant) { 1782cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik mv_host_intr(host, relevant, hc); 1783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 178420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 178520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1786615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1787bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikout_unlock: 1788cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 178920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 179020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 179120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 179220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1793c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1794c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1795c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1796c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1797c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1798c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1799c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1800c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1801c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1802c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1803c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1804c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1805c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1806c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1807c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1808c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1809c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1810da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1811c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18140d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1815c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1816c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1817da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1818da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1819da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1820da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1821da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1822c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1823c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1824da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1825c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18280d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1829c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1830c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1831da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18320d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1833da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1834da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1835da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1836c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1837c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1839522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1841522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1842522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 184344c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1844522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1845522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1846522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1847522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1848522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1849522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1850522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 18517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1852522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1853522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1854522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1855522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1856522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1857522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1858522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 185947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1860ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1861ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1862c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1863c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1864c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1865c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1866c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1867c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1868c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1869ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1870ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 187147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1872ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1873522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1874522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1875522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1876522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1877522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1878522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1879522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1880522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1881522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1882ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1883ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 18842a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 18852a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1886bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1895c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1896c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1897c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1898c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1899c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1900c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1901c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1902c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1903c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1904c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1905c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1906c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1907c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1908bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1909bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1910c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1911c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1912c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1913c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1914c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1915c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1916c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1917c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1918c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 1919c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1920e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1921c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1922c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1923c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1924c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1925c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1926c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1927c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1928c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1929c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1930c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1931c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1932c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1933c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1934c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1935c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 194147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 1949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 1959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1960c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 1961c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1962c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 1963c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 1964c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 1965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1967c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 1968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1969c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1970c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 197147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 197247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 1973101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1974101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 19757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 1976101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 197702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1978101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 1979101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1980101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 1981101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 1982101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 1983101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1984101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 1985101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 1986101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 1987101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 1988101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 198902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 199002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 1991101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 1992101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 1993101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 1994101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 1995101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 1996101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1997101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1998101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1999101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2000101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2001101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2002101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2003101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2004101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 2005101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2006101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 2007101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 2008101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2009101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2010101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2011101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2012101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2013101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2014101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2015101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2016101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2017101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2018101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2021101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2022101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2023101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2024101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2025101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2026101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2027101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2028101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2029101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2030101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2031101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2033101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2034101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20352dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2036101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2041101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2042101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2049101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2063101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2064101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2066101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2070101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2071101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2072101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2073101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 207447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2075ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2076ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2077ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2078ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2079ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2080ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2081ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 208247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2083ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2084ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2085ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2086ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2087ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2088ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2089ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2090ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2091ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2092ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2093ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 209447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2095ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 209647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2097ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2098ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2099c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 21002a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2101bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2104bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 210547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 210647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2107bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 210847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 210947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 211047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 211247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 211347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 211447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 211547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 211647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 211847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 212047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 212147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 212247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 212347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 212447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 212547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 212647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 212747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 212847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 212947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 213047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2131bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2132bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 213347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2134bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2135bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 213647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 213747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2138e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2139bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2140e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2141bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2142bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2143bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 214447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 214547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2146e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2147bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2148bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2149bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2150bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2151bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2152bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 21532a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 21542a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 215547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2156bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2157e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2158e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2159e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2160e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2161e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2162e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2163bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2164bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2165bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2166f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2168f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2169f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2173f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2178f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2179f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2180f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2181f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2182f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2183f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2184f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2185f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2188f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2191f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2192f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2193f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 2195f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2196e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2197f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2202f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2203f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2204f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2210f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2214f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2215f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2216f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2217f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2246f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2247f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2248f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2249f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2250f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2253e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2254c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2255c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2256c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2257c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2258c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2259c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2260ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_II(hpriv)) { 2261e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2262eb46d684600ac145501805a294c94675e82eab2eMark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2263eb46d684600ac145501805a294c94675e82eab2eMark Lord ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ 2264e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2265c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2266c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2267c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik udelay(25); /* allow reset propagation */ 2268c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2269c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik /* Spec never mentions clearing the bit. Marvell's driver does 2270c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik * clear the bit, however. 2271c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2272c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2273c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2274c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2275c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2276ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2277c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2278c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2279c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 228005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2281bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * mv_phy_reset - Perform eDMA reset followed by COMRESET 228205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 228305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 228405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Part of this is taken from __sata_phy_reset and modified to 228505b308e1df6d9d673daedb517969241f41278b52Brett Russ * not sleep since this routine gets called from interrupt level. 228605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 228705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 228805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. This is coded to safe to call at 228905b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt level, i.e. it does not sleep. 229031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 2291bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_phy_reset(struct ata_port *ap, unsigned int *class, 2292bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 229320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2294095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik struct mv_port_priv *pp = ap->private_data; 2295cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 229620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 229722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik int retry = 5; 229822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik u32 sstatus; 229920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 230020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); 230120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2302da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#ifdef DEBUG 2303da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo { 2304da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo u32 sstatus, serror, scontrol; 2305da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 2306da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_STATUS, &sstatus); 2307da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_ERROR, &serror); 2308da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_CONTROL, &scontrol); 2309da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " 23102d79ab8fd7a7bf3a45d0e948ae27b3dd95ce95eaSaeed Bishara "SCtrl 0x%08x\n", sstatus, serror, scontrol); 2311da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 2312da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#endif 231320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 231422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* Issue COMRESET via SControl */ 231522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzikcomreset_retry: 2316936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x301); 2317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(1); 231822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2319936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x300); 2320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(20); 232122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 232231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ do { 2323936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_STATUS, &sstatus); 232462f1d0e6de138b91d55fbd7d579c837ed62e9e31Andres Salomon if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0)) 232531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 232622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(1); 2328c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik } while (time_before(jiffies, deadline)); 232920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 233022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* work around errata */ 2331ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_II(hpriv) && 233222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && 233322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik (retry-- > 0)) 233422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik goto comreset_retry; 2335095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2336da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#ifdef DEBUG 2337da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo { 2338da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo u32 sstatus, serror, scontrol; 2339da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 2340da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_STATUS, &sstatus); 2341da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_ERROR, &serror); 2342da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo mv_scr_read(ap, SCR_CONTROL, &scontrol); 2343da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " 2344da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo "SCtrl 0x%08x\n", sstatus, serror, scontrol); 2345da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 2346da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo#endif 234731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2348936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (ata_link_offline(&ap->link)) { 2349bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik *class = ATA_DEV_NONE; 235020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return; 235120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 235220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 235322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik /* even after SStatus reflects that device is ready, 235422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * it seems to take a while for link to be fully 235522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * established (and thus Status no longer 0x80/0x7F), 235622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik * so we poll a bit for that, here. 235722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik */ 235822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik retry = 20; 235922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik while (1) { 236022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik u8 drv_stat = ata_check_status(ap); 236122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik if ((drv_stat != 0x80) && (drv_stat != 0x7f)) 236222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik break; 2363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik msleep(500); 236422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik if (retry-- <= 0) 236522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik break; 2366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (time_after(jiffies, deadline)) 2367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 236822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 236922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: if we passed the deadline, the following 2371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * code probably produces an invalid result 2372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 237320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* finally, read device signature from TF registers */ 23753f19859ee95a38c066a0420eb8a30c76ecd67a42Tejun Heo *class = ata_dev_try_classify(ap->link.device, 1, NULL); 2376095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2377095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2378095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik WARN_ON(pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2380095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 2381bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik VPRINTK("EXIT\n"); 238220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 238320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2384cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_prereset(struct ata_link *link, unsigned long deadline) 238522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2386e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(link->ap); 2387cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo return 0; 238822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 238922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2390cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2391bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 239231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2393cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2394bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 239631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2397e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 2398e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2399bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_phy_reset(ap, class, deadline); 2400bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2401bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return 0; 2402bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2403bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2404cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic void mv_postreset(struct ata_link *link, unsigned int *classes) 2405bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2406cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2407bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 serr; 2408bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2409bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* print link status */ 2410cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_print_link_status(link); 241131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2412bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear SError */ 2413cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_scr_read(link, SCR_ERROR, &serr); 2414cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo sata_scr_write_flush(link, SCR_ERROR, serr); 2415bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2416bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* bail out if no device is present */ 2417bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 2418bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("EXIT, no device\n"); 2419bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 24209b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord } 2421bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* set up device control */ 2423bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik iowrite8(ap->ctl, ap->ioaddr.ctl_addr); 2424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask; 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift; 2432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2434bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp & ~mask, hpriv->main_mask_reg_addr); 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2448f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2453bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask, hc_irq_cause; 2454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift, hc_port_no = ap->port_no; 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) { 2460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_port_no -= 4; 2462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2466bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2469bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2470bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */ 2472bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */ 2473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2475bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2476f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2477f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp | mask, hpriv->main_mask_reg_addr); 247831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 247931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 248005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 248105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 248205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 248305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 248405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 248505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 248605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 248705b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 248805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 248905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 249005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 249105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 249320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 24940d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 249531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 249631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 24978b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 249931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 25008b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 250231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 250331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 250431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 250531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 250631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 25078b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 250831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 250931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 251031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 251131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 251231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 25138d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 251420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 251531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 251631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 251731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 251831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 251931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2520646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2521646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 252220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25238b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 252431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 252531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 252631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 252720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 252820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25294447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2530bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25314447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2533bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2534bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25355796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 253647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 253747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2538ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 253947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 254044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 254147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 254247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 254347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 254547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 254647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 254847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 254947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2555bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2556bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2558ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2559bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 256044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 256147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 256247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 256347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 256547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 256647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 256847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 256947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 257047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2572bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2573bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2574bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2575bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2576bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 257747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2578ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 257947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 258044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 258147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 258247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 258347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 258447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 258547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2586bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2587bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2588bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 258947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 259047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2591bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2592bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2593bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2594bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2595e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 259602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2597306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2598306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2599306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 26004e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 26014e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 26024e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26034e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 26044e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 26054e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 26064e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26074e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 26084e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 26094e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 26104e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 26114e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 26124e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26134e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 26144e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26154e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 26164e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 26174e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26184e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26194e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26204e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26214e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26224e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26234e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26244e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2625306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2626e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2627e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2628e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2629e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 263044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2631e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2632e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2633e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2635e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2636e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2637e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2638e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2639e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2640e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2641e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2645f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2646f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2647f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2649bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2650f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26515796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2652bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2653bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2654bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2655bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 265602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 265702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 265802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 265902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 266002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 266102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 266202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 266302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 266402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2665bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2666bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2667bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2668bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 266905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 267047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26714447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26724447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 267305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 267405b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 267505b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 267605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 267705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 267805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 267905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 26804447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 268120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 268220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 26834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 268547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 26864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2687bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2688f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara goto done; 2689f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2690f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2691f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2692f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_IRQ_CAUSE_OFS; 2693f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS; 2694f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2695f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2696f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS; 2697f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + 2698f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS; 2699f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2700f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* global interrupt mask */ 2701f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2702bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2704bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 270647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 270720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2708c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 270947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 271020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 271120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2712522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 27137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 271447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 271520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2717ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_II(hpriv)) { 2718c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2719c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2720e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2721eb46d684600ac145501805a294c94675e82eab2eMark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2722eb46d684600ac145501805a294c94675e82eab2eMark Lord ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ 2723e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 27242a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik } 27252a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik 2726c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port); 27272a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik } 27282a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik 27294447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2730cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 27312a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2732cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2733cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2734cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 274220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 274320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 274420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 274531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 274631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 274731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 274831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 274931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 275031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 275131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 275231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 275331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 275420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 275520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 275931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2760f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2761f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2762f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2770f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2772f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2774f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2775f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2776f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2777f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2778f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2779f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2780f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2781f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2785fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2786fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2787fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2788fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2789fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2790fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2791fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2792fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2793fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2794fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2795fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2796fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2797fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2798fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2799fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2800fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2801fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2802fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2803fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2804fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2805fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2817f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2818f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2819f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2822f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 282420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2827bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2850f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2851f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2852f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2854f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2855f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2856f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2857f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2860fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2861fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2862fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2863fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 289220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 289320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2894f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2895f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2897f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2898f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2899f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2901f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2902f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2905f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 29107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 29117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 29137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 29147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 29157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 29177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 29187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 29197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 29207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 29237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 29257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 295505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 295605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 295805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 295905b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 296005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 296105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 296205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 296305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 296531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 29664447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29674447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 296844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2969c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 297031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 297131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 297231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 297331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 297431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 297531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 297631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 297731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 297831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 297931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2980c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2981c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2982c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2983c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2984c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2985c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2986c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2987c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2988c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2989c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 299031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2991a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2992c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2993c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 299431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 299531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 299631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 299705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 299905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 300005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 300105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 300205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 300305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 300405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3005f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 300720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30082dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 300920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 30104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 30114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 30124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 30134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 301420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3015a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3016a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 301720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 30194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 30204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 30224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 30234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 30244447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 30254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3026f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 302924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 303024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 303120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 303220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30330d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30340d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 303524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30360d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 303724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3039f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 304020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3041d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3042d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3043d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3044d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3045da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3046da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3047da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3048da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 304920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 305124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 305224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 305320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30556a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 305631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 305720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 306020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3062ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30634447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3064c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 306520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 30667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 306720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3068f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 307120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 307220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 30747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3076f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3077f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3078f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3079f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3080f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3081f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3082f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3083f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 30847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 30857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 308620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 308920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 309120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 30927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3093f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 309420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 309520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 309620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 309720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 309820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 309920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 310020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 31012e7e1214defe7783c8187962bacdd0a87a7dbeeeMartin MichlmayrMODULE_ALIAS("platform:sata_mv"); 310220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3104ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3105ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 31067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3107ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 310820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 310920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3110