sata_mv.c revision e40060772d85f3534d3d517197696e24bb01f45b
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 2785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 2885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Errata workaround for NCQ device errors. 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> More errata workarounds for PCI-X. 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Complete a full errata audit for all chipsets to identify others. 3385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, low priority] Investigate interrupt coalescing. 4385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Quite often, especially with PCI Message Signalled Interrupts (MSI), 4485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * the overhead reduced by interrupt mitigation is quite often not 4585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * worth the latency cost. 4685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 4885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 4985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 5085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 5185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 5285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 5385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 6120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 628d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 64a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 65f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 66f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 68c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 70193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 716c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 751fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 7620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 7820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 88615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 89615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 90615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 91615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 92615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 93615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 10320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 10531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 10631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 10731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 10831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 10931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 11031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 11231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 113da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 116352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 11720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 118352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 119352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 120352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 12120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 12220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 12320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 126e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 128c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 129bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 130bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 13431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 135c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 136e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 137c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 13831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 13931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 144c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 14920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 1518e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 15420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1588e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1598e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1608e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 161522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 162522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 163522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 164522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 1658e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 17602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 177646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 17802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 1797368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 1807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 1817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 1827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 1837368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 184352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 185352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 191fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 192fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 198fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 199e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2008b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 201f9f7fe014fc7197a5f36f9d9859cbb27c3bdd2abMark Lord PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 204fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 205fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 20920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 212352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 213352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 21731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 21831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2230c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 22417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 225e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 22717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 22847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 231e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 234e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2378e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 23917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 240c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 244bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 245bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2490c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2500c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2510c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2530c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 254e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 255e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 265c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 266c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 268c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2706c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 273646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 275646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2806c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2826c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2896c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2916c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 292c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 293c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 295646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 297646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 29885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 301bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3066c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 314e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3390ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3400ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 3458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 34620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 3488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 3498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 351bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 352352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 353352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3630ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 365616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 36620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3680ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 369721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 37000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 37129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 37220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 374ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 375ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 376e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3778e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 3787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 379bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 38115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 38215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 383095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 384baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 385baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 386baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 387baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 388095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3890ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3900ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 392095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 393095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3940ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 395095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 396095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 397095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 399522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 401522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 402522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 403522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 405e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 407522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 408522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 40931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 41031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 411e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 412e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 413e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 417e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 419e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 420e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 421e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 422e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 423e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 424e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 427e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 428e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 429e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 43020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 434e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 435e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 436e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 437e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 44131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 44231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 44331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 445eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 446eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 45131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 45229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 45331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 45431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 455bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 456bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 457bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 458bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 459bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 46002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 46102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 46202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 46302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 464f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 465f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 4667368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 4677368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 46802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 46902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 47002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 471da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 472da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 473da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 474da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 475da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 476da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 477da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 478da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 47902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 48002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4822a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4832a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 48447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 487c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 488c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 489522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 49147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 49247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 493da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 494da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 495da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 496da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 49731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 49831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 4993e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 501e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5029a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 503a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 504a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 505bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 507f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 50820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5092a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5102a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 51347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 514c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 515c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 516522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 51847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5192a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5202a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 52147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 52247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 52347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 524c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 525c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 526522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 529f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 530f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 531f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 532f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 533f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 534f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 535f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 537e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 538c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 539e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 540b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 541e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 54247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 543e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 544e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 545e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 546e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 547e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 54829d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 5494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 5504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 55147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 552eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 553eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 554eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 555eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 556c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 55768d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 558baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 559c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 560c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 561c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 562c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 56368d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 564138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 565baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 56620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 56720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 569029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 570029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 571c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 5723e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 573c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 578a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 579a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 580029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 582c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 583c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 584c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 585c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 586c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 587c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 588c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 589029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 590029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 591f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 59220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 59320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 595e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 596e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 597e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 59829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 59920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 60020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 601029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 602029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 603029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 604e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 605e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 606e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 60798ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 60820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 609cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 61031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 611bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 612c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 615c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 617bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 618c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 621c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 62247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 623bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 624c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 62547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 62620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 627138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 628e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 629138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 63031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 631bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 632c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 63420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 635c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 636e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 637138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 63831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 639bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 640c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 64120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 643138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 644e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 645138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 646e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 647bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 651138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 652e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 653138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 654e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 655bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 656e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 657e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 658f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 65902c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 660e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 66102c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 66217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 66317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 66417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 665f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 66620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6683b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 673cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 674cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 675cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6782d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6792d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6802d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6812d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6822d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6832d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6842d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 685d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 686d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 687d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6896a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6906a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 69102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 69202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 69302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 69402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6952d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 69620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 703522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 704522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 70547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 70747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 71047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 71147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 712522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 713522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 71447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 71547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 718f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 719f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 720f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 721f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 722f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 723f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 724f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 73020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 73220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 73320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 73420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 738c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 739c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 740c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 741c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 742c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 743c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 744c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7481cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7491cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7517368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 7527368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 7531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7561cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7571cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7581cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7591cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7601cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7611cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7621cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 763352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 764352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 765352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 766352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 767352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 768c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 769c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 770c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 771c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 772c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 773c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 77420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 77520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 776c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7778b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 778c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 77920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 78020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 781e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 782e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 783e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 784e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 785e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 786e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 787e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 788e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 789f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 791f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 792f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 793f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 794f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 79520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 79620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 797f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 79820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 79920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 800cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 80131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 802cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 80331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 80431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 807c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 808c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 810bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 813c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 814fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 815fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 817c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 818c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 820c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 821c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 822c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 823bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 824c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 825c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 826bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 827c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 828c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 829c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 831fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 832fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 833bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 834c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 835c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 836c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 837c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 838bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 839c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 840c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 841bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 842c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 843bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 844c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 845c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 846c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 84705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 85105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 852beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 853beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 85405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 85505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 85605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8580c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 859721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 86020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 861721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 862721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 863721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 864721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 865721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 866b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 867721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 868c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8690c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 870352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8710c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 872352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8730c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8740c58912e192fc3a4835d772aafa40b72552b819fMark Lord 875bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 876f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 877bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8780c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8790c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 880352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8810c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8820c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8830c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8840c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8850c58912e192fc3a4835d772aafa40b72552b819fMark Lord 886e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8870c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8880c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 889e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv)) 890e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8910c58912e192fc3a4835d772aafa40b72552b819fMark Lord 892f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 893bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 894f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 895afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 896afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 89720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8999b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 9009b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 9019b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 9029b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 9039b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 9049b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 9059b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 9069b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 9079b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 908c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 909c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 910c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 911c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 9129b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 9139b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 9149b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 9159b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 9169b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 9179b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 9189b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 9199b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 9209b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 9219b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 92205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 923e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 924b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 92505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 92605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 92705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 92805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 929b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 93020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 931b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 93231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 933b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 934b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 9358b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 936b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 937b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 938b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 9394537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 940b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 941b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 943b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 94420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 94520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 946e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 9470ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 948b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 949b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 9500ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 951b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 952b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 953b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 9549b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 955b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 956b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 957b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 958b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 959b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9628a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 96420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 96531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 96731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9692dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 97131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 97331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9758a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9768a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 97931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 98331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 98431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9852dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9862dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 98731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 98831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 99031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 99131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 99231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 99331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 99431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 99531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 99631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9978b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 99831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 99931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 100031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 100131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 100231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 100331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 100431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 100531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 100631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 100731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 100831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 100931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 101031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 10118b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 101231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 101331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 101431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 101531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 101631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 101731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 101831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 101931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 102031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 102131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 102231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 102331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1024d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 102531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 102631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 102731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 102831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 102931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 10302dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 103131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 10322dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 103331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 103431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 103531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 103620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 103720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 103820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 103920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 104020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 104120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 104220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 104320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 104420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 104520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 104620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 104720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 104820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 104920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 105020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 105120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 105220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 105320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 105420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 105520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 105620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 105720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1058da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 105920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 106020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 106120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1062da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1063da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1064da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1065da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1066da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 106720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 106820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1069da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 107020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 107120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 107220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1073da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 107420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1075da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1076da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1077da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 107820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 107920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1080f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1081f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1082f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1083e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1084e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1085e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1086e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1087e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1088f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1089f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1090f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1091e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1092352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1093e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1094352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1095352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1096352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1097352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1098352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1099352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1100352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1101352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1102e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1103f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1104f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 11053e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 11063e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 11073e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 11083e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 11093e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 11103e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11113e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 111229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 111329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 111429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 111529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 111629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 111729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 11183e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 11193e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11203e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 11213e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11223e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11233e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 11243e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11253e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The port is operating in host queuing mode (EDMA). 11263e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * It can accomodate a new qc if the qc protocol 11273e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * is compatible with the current host queue mode. 11283e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11293e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 11303e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11313e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in NCQ mode. 11323e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also an NCQ command, 11333e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11343e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11353e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_NCQ) 11363e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11373e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } else { 11383e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11393e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in non-NCQ, DMA mode. 11403e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also a non-NCQ, DMA command, 11413e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11423e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11433e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_DMA) 11443e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11453e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11463e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11473e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 11483e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 11493e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 115000f42eabb204c68fa64ef72de834e74aca15c81fMark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs) 1151e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 115200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_fiscfg, old_fiscfg; 115300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_ltmode, old_ltmode; 115400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_haltcond, old_haltcond; 115500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 115600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_fiscfg = readl(port_mmio + FISCFG_OFS); 115700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 115800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 115900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 116000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 116100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 116200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_haltcond = old_haltcond | EDMA_ERR_DEV; 116300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 116400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 116500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 116600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 11674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 11684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_haltcond &= ~EDMA_ERR_DEV; 11694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 11704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_fiscfg |= FISCFG_WAIT_DEV_ERR; 1171e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 117200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 11738e7decdb8b132ee970a2636931b7653dec6af472Mark Lord if (new_fiscfg != old_fiscfg) 11748e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1175e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1176e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 117700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (new_haltcond != old_haltcond) 117800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS); 1179f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1180f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1181dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1182dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1183dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1184dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1185dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1186dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1187dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1188dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1189dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1190dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1191dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1192dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1193dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1194dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1195dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1196e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1197e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 11980c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1199e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1200e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1201e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1202e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1203e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 12040c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 120500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags &= ~MV_PP_FLAG_FBS_EN; 1206e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 12070c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1208e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1209e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1210dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1211e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1212dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1213e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1214dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 121500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 121600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 121700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 121800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 121900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 122000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 122100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 122200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 122300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 122400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 122500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 122600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord mv_config_fbs(port_mmio, want_ncq, want_fbs); 122700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 122800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 122900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 123000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 123100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 123200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1233e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1234e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1235616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (HAS_PCI(ap->host)) 1236616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 18); /* enab early completion */ 1237616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1238616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1239e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1240e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1241721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1242721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1243721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1244721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1245721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1246721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1247e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1248e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1249e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1250da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1251da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1252da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1253da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1254eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1255da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1256da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1257da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1258da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1259da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1260da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1261da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1262da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1263da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1264eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1265eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1266eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1267eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1268eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1269eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1270eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1271eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1272eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1273eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1274eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1275eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1276da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1277da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1278da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 127905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 128005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 128105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 128205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 128305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 128405b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 128505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 128605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 128705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 128805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1291cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1292cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1294dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 129624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 12976037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 129824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1299da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 130031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1301da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1302da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1303da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1304da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1306da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1307da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1308da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1309da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1311eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1312eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1313eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1314eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1315eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1316eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1317eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1318eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1319eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1320eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1321eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1322eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1323eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1324eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1325eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 132631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1327da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1328da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1329da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1330da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 133131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 133231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 133305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 133405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 133505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 133605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 133705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 133805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 133905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1340cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 134105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 134231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 134331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1344e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1345da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 134631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 134731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 134805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 134905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 135005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 135105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 135205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 135305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 135405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 135505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 135605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13576c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 135831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 135931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1360972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 13613be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1362ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 136331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1364eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1365ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1366d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1367d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 136822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13694007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 13704007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 13714007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 137222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13734007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 13744007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 13754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 13774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 13786c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 13794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 13814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 13824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13833be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 13844007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 13854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 138631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 13873be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 13883be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 13893be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 139031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 139131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 13925796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 139331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1394559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 139531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1396559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 139731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 139831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 139905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 140005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 140105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 140205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 140305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 140405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 140505b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 140605b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 140705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 140805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 140905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 141005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 141131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 141231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 141331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 141431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 141631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 141731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1418a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 141931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1420138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1421138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 142231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 142320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 142431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 142531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1426e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 142731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1428beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 142931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1430e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 143131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1433fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1434a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1435a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1436eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1437a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1438eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1439a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1441a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 144231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 144331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 144431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 144531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 144631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 144731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 144831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 144920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 145031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 145131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 145231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 145331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 145431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1455c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 145631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 145731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 145831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 145931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 14608b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 146131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 146431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 146531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 146631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 146731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 146831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 146931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 147031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 147131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 147231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 147331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 147431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 147531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 147631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 147731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 147831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 147931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 148031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 148131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 148231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 148331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 148431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1486e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1487e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1488e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1489e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1490e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1491e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1492e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1493e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1494e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1495e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1496e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1497e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1498e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1499e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1500e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1501e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1502e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1503e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1504e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1505e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1506e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1507e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1508a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1509e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1510e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1511138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1512138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1513e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1514e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1515e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1516e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1517e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1518e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1519beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1520e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 15218c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1522e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1523e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1525fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1526a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1527a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1528eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1529eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1530e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1531e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1532e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1533e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1534e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1535e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1536e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1537e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1538e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1539e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1540e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1541e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1542e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1543e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1544e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1545e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1546e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1547e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1548e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1549e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1550e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1551e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1552e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1553e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1554e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 155531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 155631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 155731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 155831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 155905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 156005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 156105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 156205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 156305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 156405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 156505b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 156605b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 156705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 156805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 156905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 157005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 15719a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 157231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1573c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1574c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1575c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 157731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1578138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1579138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 158017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 158117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 158231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 158331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 158431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1585b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1586e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 15879363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 158831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 158931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1590721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1592fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1593fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 159431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 159531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 159831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 159931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 160031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 160131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 16038f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 16048f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 16058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 16068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 16078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 16088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 16098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 16108f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 16118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = NULL; 16128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 16138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 16148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 161529d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 161629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 161729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 161829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 161929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 162029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 162129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 162229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 162329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 162429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 162529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 162629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 162729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 162829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 162929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 163029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 163129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 163229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 163329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 163429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 163529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 163629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 163729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 163829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 163929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 164029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 164129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 16424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 16434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 16444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 16454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 16474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 16484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 16504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 16514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 16524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 16534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 16554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 16564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 16574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 16584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 16594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 16604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 16614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 16624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 16644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 16654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 16664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 16674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 16684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 16694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 16704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 16714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 16724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 16734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 16754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 16764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 16774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 16784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 16794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 16814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 16824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 16834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 16844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 16854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 16864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 16874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 16884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 16894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 16904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 16914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 16924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 16934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 16944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 16964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 16974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 16984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 1699c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 17004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 17024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 17034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 17044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 17054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 17064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (ap->nr_active_links <= failed_links) { 17084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 17094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 17104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 17114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 17124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 17134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 17154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 17164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 17174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 17194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 17204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 17224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 17244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 17254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 17274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 17294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 17304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 17334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 17354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 17364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 17374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 17394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 17404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 17414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 17424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 17444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 17454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 17464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 17474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 17484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 17504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 17524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 17534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 17544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 17564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 17574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 17584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 17594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 17624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 17634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 17654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 17664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 17674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 17694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 17704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 17714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 17724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 17754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 17784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 1779a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 17808f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 17818f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 1782a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 17838f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 17848f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 1785a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 1786a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 1787a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 1788a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 17898f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 17908f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 17918f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1792a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 17938f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 1794a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 17958f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 17968f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 17978f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 17988f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 17998f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 180005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 180105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 180205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 18038d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * @qc: affected command (non-NCQ), or NULL 180405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 18058d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 18068d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 18078d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 180805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 180905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 181005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 181105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 181237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 181331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 181431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1815bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1816e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 1817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1818bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 18209af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 182137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 182237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 182320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18248d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 182537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 1826e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 1827e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 18288d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 182937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 183037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 183137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 1832bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1833e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1834e40060772d85f3534d3d517197696e24bb01f45bMark Lord fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1835e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1836e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 18378d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1838bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 18394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 18404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 18414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 18424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 18434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 18444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 18454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 18464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 18474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 184837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 184937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 185037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 185137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 1852e40060772d85f3534d3d517197696e24bb01f45bMark Lord 1853e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) 1854e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 1855bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1856352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1857bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 185837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 1859bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 186037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 186137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 186237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1863bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 18646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1865bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1866bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1867cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1868b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1869bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1871bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1872bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1873b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1874cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1875bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1876bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1877352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1878352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1879352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1880352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1881ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1882bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1883bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1884bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1885b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1886bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1887bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1888bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1889bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1890bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1891b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1892bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1893bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 18948d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 18958d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 1896cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1897bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1898afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 189920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1900bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1901bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1902cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1903bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1904bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1905bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1906bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1907bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1908bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1909bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1910bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1911bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1912bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 191337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 191437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 191537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 191637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 191737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 191837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 191937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 192037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 192137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 192237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 192337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 192437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 1925bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 192637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 192737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 192837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 192937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 193037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 193137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 193237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 193337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 193437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 193537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1936bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1937bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1938fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 1939fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1940fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 1941fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1942fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1943fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 1944fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 1945fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 1946fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1947fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 1948fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1949fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 1950fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1951fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 1952fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1953fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 1954fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1955fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 1956fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 1957fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1958fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 1959fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1960fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1961fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 196237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 196337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 196437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 1965fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1966fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 1967fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 1968fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1969fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 1970fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1971fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 1972bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1973bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1974bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1975fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 1976bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1977fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 1978bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1979fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 1980bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1981bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1982bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1983fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 1984fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 19856c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1986fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 1987bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1988fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1989bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1990fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 1991fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 19929af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1993fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1994fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 1995fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 1996bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1997fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 1998bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1999bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2000bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2001352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2002bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2003bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2004fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2005bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 200620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 200720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2008a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2009a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2010a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2011a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2012a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2013a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2014a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2015a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2016a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2017a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2018a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2019a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2020a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2021a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2022a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2023a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2024a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2025a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2026a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2027a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2028a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 20294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 20304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2031a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2032a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2033a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2034a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2035a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2036a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2037a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2038a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2039a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2040a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2041a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2042a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2043a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2044a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2045a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 204605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 204705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2048cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 20497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 205005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 205105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 205205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 205305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 20547368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 205520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2056f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2057eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2058a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 205920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2060a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2061cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2062eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2063eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2064a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2065a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2066eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2067eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2068a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2069eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2070eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2071eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2072eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2073eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2074eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2075eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2076eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2077eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2078eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2079eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2080eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2081eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2082eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2083eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2084eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2085eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2086eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2087eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2088eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2089eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2090eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2091eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 2092eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2093eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2094eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2095eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2096eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2097eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2098eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2099a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2100eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2101a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2102a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 21038f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2104a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 21058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2106a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2107a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2108a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 210920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2110a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 211120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 211220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2113a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2114bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 211502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2116bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2117bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2118bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2119bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2120bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2121bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 212202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 2123bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2124bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2125bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2126bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2127bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2128bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2129bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 213002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 2131bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2132bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2133bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2134936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 21359af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2136bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2137bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2138bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2139bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2140bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2141cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 21429af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2143bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2144bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2145bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2146bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2147bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2148bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2149bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2150bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2151a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2152bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2153bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 215405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2155c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 215605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 215705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 215805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 215905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 216005b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 216105b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 216205b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 216305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 21648b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2165cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 216605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 216705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 21687d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 216920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2170cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2172a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 21737368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_cause, main_irq_mask; 217420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2175646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 21767368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 21777368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 2178352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2179352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2180352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 218120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 21827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) { 21837368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host))) 2184a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2185a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 21867368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord handled = mv_host_intr(host, main_irq_cause); 2187bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2188cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 218920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 219020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 219120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2192c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2193c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2194c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2195c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2196c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2197c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2198c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2199c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2200c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2201c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2202c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2203c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2204c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2205c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2206c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2207c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2208c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2209da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 2210c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 22130d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2214c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2215c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2216da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2217da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2218da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2219da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2220da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2221c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2222c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2223da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 2224c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 22270d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2228c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2229c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2230da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 22310d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2232da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2233da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2234da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2235c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2236c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 22377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2238522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 22397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2240522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2241522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 224244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2243522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2244522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2245522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2246522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2247522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2248522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2249522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 22507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2251522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2252522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2253522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2254522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 22558e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2256522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2257522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 225847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2259ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2260ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2261c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2262c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2263c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2264c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2265c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2266c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2267c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2268ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2269ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 227047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2271ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2272522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 2273522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 22748e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2275522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2276522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2277522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2278522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2279522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 2280522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2281ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2282ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 22832a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 22842a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2285bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2286c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2287c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2288c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2289c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2290c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2291c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 22928e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2293c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 22948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2295c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 22968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2297c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 2298c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 22998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2300c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2301c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2302c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2303c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 2304c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 2305c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 2306c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 2307bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2308bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2309c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2310c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2311c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 2312c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2313c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 2314c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2315c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2316c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2317e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2318c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2319c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 2320c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 2321c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 2322c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 2323c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 2324c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 2325c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 2326c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 2327c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 2328c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 2329c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 2330c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 23318e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2332c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2333c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2334c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2335c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 2336c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2337c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 233847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2339c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2340c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2341c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2342c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2343c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2344c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2345c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2346c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2347c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2348c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2349c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2350c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2351c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2352c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2353c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2354c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2355c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2356c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2357c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2358c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2359c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2360c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2361c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2362c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2363c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2364c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2365c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2366c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2367c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 236847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 236947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2370101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2371101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 23727bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2373101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 237402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2375101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2376101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 23778e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 2378101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 23798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 2380101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2381101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2382101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 23838e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 23847368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord ZERO(PCI_HC_MAIN_IRQ_MASK_OFS); 2385101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 238602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 238702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2388101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2389101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2390101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2391101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2392101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2393101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2394101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2395101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2396101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2397101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2398101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2399101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2400101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 24018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2402101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2403101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 24048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2405101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2406101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2407101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2408101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2409101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2410101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2411101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2412101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2413101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2414101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2415101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2416c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2417c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2418101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2419101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2420101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2421101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2422101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2423101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2424101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2425101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2426101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2427101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2428101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2429101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2430101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2431101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 24322dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2433101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2434101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2435101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2436101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2437101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2438101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2439101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2440101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2441101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2442101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2443101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2444101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2445101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2446101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2447101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2448101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2449101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2450101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2451101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2452101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2453101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2454101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2455101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2456101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2457101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2458101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2459101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2460101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2461101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2462101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2463101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2464101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2465101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2466101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2467101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2468101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2469101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2470101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 247147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2472ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2473ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2474ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2475ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2476ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 24778e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 2478ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 247947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2480ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2481ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2482ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2483ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2484ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2485ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2486ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2487ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2488ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2489ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2490ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 249147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2492ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 24938e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2494ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2495ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2496c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 24972a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2498bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2499c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2500c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2501bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 250247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 250347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2504bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 250547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 250647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 250747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 250847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 250947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 251047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 251147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 251247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 251347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 251447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 251547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 251647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 251747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 251847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 251947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 252047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 252147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 252247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 252347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 252447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 252547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 252647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 252747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2528bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2529bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 253047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2531bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2532bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 253347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 253447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2535e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2537e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2539bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2540bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 254147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 254247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2543e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2544bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2545bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2546bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2547bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2548bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2549bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 25502a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 25512a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2553bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2554e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2555e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2556e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2557e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2558e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2559e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2560bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2561bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2562bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2563f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2564f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2565f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2566f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2567f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2568f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2569f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2570f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2571f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2572f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2573f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2574f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2575f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2576f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2577f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2578f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2579f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2580f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2581f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2582f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2583f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2584f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2585f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2586f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2587f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2588f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2589f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2590f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2591e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2592f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2593f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2594f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2595f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2596f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2597f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2598f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2599f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2600f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2601f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2602f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2603f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2604f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 26058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2606f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2607f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2608f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2609f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2610f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2611f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2612f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2613f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2618f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2624f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2625f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2626f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2628f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2629f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2630f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2631f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2634f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2635f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2636f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2637f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2638f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2639f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2640f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2641f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2642f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2643f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2645f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2646f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2647f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 26488e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2649b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 26508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2651b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 26528e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2653b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 26548e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 26558e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2656b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2657b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2658e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2659c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2660c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2661c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2662c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 26638e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 26648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 26658e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 26668e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 26678e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 26680d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 26698e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2670c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2671b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 26728e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 26738e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 2674c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2675b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 26768e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2677b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2678b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2679c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 26808e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2681b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2682c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2683c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2684c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2685c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2686ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2687c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2688c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2689c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2690e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 269120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2692e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2693e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2694e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2695e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 269622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2697e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2698e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2699e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2700e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 270122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 270220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 270320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2704e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2705e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 270622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2707e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2708e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2709e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2711e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2712e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2713e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2714e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2715e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 271622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 271722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2718cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2719bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 272031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2721cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2723b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2724f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 27250d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 27260d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 27270d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 272831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2729e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2730b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2731bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 27320d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 27330d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 273417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 273517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2736bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 273717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 273817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 27399dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 274017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 27410d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 27420d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 27430d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 27440d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 27458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 27460d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 27470d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 27480d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 27490d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2750bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 275117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2752bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2753bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2755bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 27571cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 27587368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask; 2759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 27621cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 27631cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2765bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 27667368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 27677368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); 27687368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 2769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2770bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2772bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 27741cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 27751cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 27777368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask, hc_irq_cause; 2778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2779bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 27811cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2786bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2787bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 27881cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 27891cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2790bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2791bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 27927368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 27937368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift); 27947368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 279531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 279631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 279705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 279805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 279905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 280005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 280105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 280205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 280305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 280405b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 280505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 280605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 280705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 280805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 280931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 281020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 28110d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 281231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 281331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 28148b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 281531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 281631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 28178b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 281831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 281931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 282031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 282131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 282231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 282331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 28248b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 282531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 282631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 282731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 282831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 282931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 28308d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 283120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 283231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 283331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 283431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 283531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 283631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2837646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2838646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 283920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28408b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 284131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 284231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 284331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 284420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 284520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2846616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 2847616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2848616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2849616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2850616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2851616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2852616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!HAS_PCI(host) || !IS_PCIE(hpriv)) 2853616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 2854616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 2855616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 2856616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 2857616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 2858616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2859616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2860616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 2861616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2862616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2863616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2864616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2865616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2866616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 2867616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 2868616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 2869616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 2870616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 2871616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 2872616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2873616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 28744447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2875bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 28764447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 28774447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2878bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2879bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 28805796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 288147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 288247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2883ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 288447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 288544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 288647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 288747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 288847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 288947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 289047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 289147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 289247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 289347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 289447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 289547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 289647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 289747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 289847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 289947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2900bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2901bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 290247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2903ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2904bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 290544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 290647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 290747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 290847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 290947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 291047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 291147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 291247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 291347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 291447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 291547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 291647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2917bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2918bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2919bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2920bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2921bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 292247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2923ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 292447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 292544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 292647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 292747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 292847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 292947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 293047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2931bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2932bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2933bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 293447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 293547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2936bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2937bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2938bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2939bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2940e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 2941616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2942306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2943306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2944306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 29454e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 29464e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 29474e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29484e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 29494e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 29504e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 29514e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29524e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 29534e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 29544e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 29554e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 29564e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 29574e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29584e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 29594e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29604e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 29614e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 29624e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 29634e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 29644e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 29654e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 29664e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 29674e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 29684e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 29694e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2970306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 29718e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 2972e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2973e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2974e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2975616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 2976616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 2977e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 297844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2979e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2980e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2981e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2982e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2983e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2984e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2985e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2986e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2987e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2988e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2989e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2990e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2991e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2992f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2993f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2994f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2996e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2997bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 29995796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3000bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3001bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3002bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3003bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 300402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 300502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 300602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 300702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 300802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 300902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 301002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 301102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 301202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3013bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3014bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3015bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3016bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 301705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 301847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 30194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 30204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 302105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 302205b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 302305b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 302405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 302505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 302605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 302705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 30284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 302920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 303020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 30314447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 303347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 30344447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3035bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3036352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3038f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 30397368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 30407368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 30427368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 30437368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 3044f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3045352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 3046352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 30477368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writel(0, hpriv->main_irq_mask_addr); 3048bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 30494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3050bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 30514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 305247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 305320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3054c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 305547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 305620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 305720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3058522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 30597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 306047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 306120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3063cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 30642a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3065cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3066cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3067cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 30687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 3070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3072f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3073f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 30747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 307520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 307620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 307720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 307831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 307931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 308031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 308131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 308231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 308331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 308431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 308531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 308631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 308720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3089f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 3090f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 3091f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 309231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3093f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 3094f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 3095f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 3096f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 30977368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 3098f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 3099f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 31007368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 3101f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3102f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 3103f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 31047368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 31057368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr), 3106f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 3107f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 3108f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 3109f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 31107368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 3111f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 31127368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 31137368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr)); 3114f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3115f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3116f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3117f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3118fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3119fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3120fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3121fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3122fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3123fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3124fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3125fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3126fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3127fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3128fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3129fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3130fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3131fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3132fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3133fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3134fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3135fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3136fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3137fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3138fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 313915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 314015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 314115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 314215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 314315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 314415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 314515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 314615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 314715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 314815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 314915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 315015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 315115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 315215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 315315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 315415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 315515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 315615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 315715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 315815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 315915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3160f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3161f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3165f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3166f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3168f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3169f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3173f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 317820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3179f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3180f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3181bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3182f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3183f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3184f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3185f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3188f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3191f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3192f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3193f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 3195f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3196f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3197f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 3198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 3199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 3200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3202f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3203f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3204f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 3205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 3206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 3207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 3208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 3210f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 3211f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 3212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 3213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 321415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 321515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 321615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 321715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 321815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 321915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3220fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 3221fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 3222fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 3223fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 3225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 3226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 3227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3246f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3247f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3248f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3249f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3250f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 325220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 325320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 3260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 3261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 3262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 32647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 3267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 32687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 32707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 32717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 3272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 32737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 32747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 32757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 32777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 32787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 32797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 32807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 32837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 32847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 32857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 32867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 32887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 32897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 32907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 32917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 32927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 32937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 32947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 32957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 32967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 32977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 32987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 32997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 33017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 33027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 33057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 33077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 33087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 33127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 33147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 331505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 331605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 33174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 331805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 331905b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 332005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 332105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 332205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 332305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 33244447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 332531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 33264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 33274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 332844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 3329c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 333031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 333131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 333231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 333331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 333431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 333531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 333631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 333731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 333831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 333931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 3340c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 3341c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 3342c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 3343c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 3344c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 3345c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 3346c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 3347c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 3348c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 3349c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 335031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3351a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 3352c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3353c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 335431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 335531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 335631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 335705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 3358f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 335905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 336005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 336105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 336205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 336305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 336405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3365f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 336720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 33682dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 336920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 33704447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 33714447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 33724447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 33734447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 337420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3375a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3376a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 337720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 33794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 33804447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 33814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 33824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 33834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 33844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 33854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 33874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 33884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 338924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 339024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 339120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 339220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33930d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 33940d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 339524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 33960d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 339724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 33984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 340020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3401d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3402d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3403d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3404d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3405da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3406da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3407da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3408da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 340920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 34104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 341124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 341224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 341320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 341431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 34156a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 341631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 341720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 341831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 34194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 342020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3422ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 34234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3424c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 342520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 34267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 342720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3429f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3430f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 343120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 343220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 34337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 34347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 34357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3436f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3437f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3438f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3439f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3440f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3441f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 34447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 34457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 344620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 344720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 344820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 344920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 34507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 345120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 34527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3453f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 345420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 345520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 345620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 345720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 345820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 345920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 346020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 346117c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 346220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3464ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3465ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 34667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3467ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 346820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 346920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3470