sata_mv.c revision e49856d82a887ce365637176f9f99ab68076eae8
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 43e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 6) Cache frequently-accessed registers in mv_port_priv to reduce overhead. 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4540f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord 7) Fix/reenable hot plug/unplug (should happen as a side-effect of (2) above). 4640f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 654a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 664a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 748d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 76a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 77f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 78f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 80193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 816c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 851fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 98615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 102615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 103615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 105522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 106bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 107bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 12131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 123da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORTS_PER_HC = 4, 12720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 12931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ 13020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_MASK = 3, 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 136e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 138c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 139bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 140bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 14147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 145c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 146e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 147c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 153c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 154c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 16131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 176522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 177522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 18020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 18120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 184646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 188f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_ERR = (1 << 0), /* shift by port # */ 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_DONE = (1 << 1), /* shift by port # */ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 197fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 198fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 204fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 205e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2068b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 209fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 210fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 21731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_DMA_DONE = (1 << 0), /* shift by port # */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 22020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2280c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 22917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 230e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 23117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 23217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 23347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 234bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 235bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 236e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 237e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 240e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 24117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 24217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 243c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 244c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 245c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 246e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 247bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 248bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2530c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2540c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2550c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2560c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 257e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 258e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 26120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 268c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 269c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2706c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 271c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2836c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2856c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2926c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2946c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 295c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 296c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 297646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 300646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 30140f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord EDMA_ERR_LNK_CTRL_TX | 30240f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord /* temporary, until we fix hotplug: */ 30340f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON), 304646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3116c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 319e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3276c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 328bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 329bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 330bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 33120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 34031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 34131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 34231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3430ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3440ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3450ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3460ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 34720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 348c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 349bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 35131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3580ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3590ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 36220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3640ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 365721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 36620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 36720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 368ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 369ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 370e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 372bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 373095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 374baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 375baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 376baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 377baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 378095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3790ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3800ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3810ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 382095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 383095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3840ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 386095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 387095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 388522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 389522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 390522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 391522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 392522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 393522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 394e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 395e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 397522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 39931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 40031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 401e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 402e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 403e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 404e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 40531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 40620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 410e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 411e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 412e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 413e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 41531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 41631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 419e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 42020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 42120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 425e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 426e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 427e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 42920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 43131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 43231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 43331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 435eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 436eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 44131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 44231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 44331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 444bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 445bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 446bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 447bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 448bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 45002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 45102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 45202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 453f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 454f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 455f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 456f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 45702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 460da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 461da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 462da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 463da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 464da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 465da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 466da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 467da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 46802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 46902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 47047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4712a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4722a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 47347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 47447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 47547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 476c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 477c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 478522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 48047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 482da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 483da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 484da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 485da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 48631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 48731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 48831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 489e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4909a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 491a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 492a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 493bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 495f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 49620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4972a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 4982a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 49947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 50147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 502c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 503c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 504522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 50647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5072a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5082a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 51147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 512c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 513c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 514522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 515f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 516f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 517f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 518f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 519f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 520f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 521f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 522f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 523f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 525e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 526c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 527e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 528b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 529e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 53047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 531e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 532e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 533e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 534e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 535e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 536e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 537eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 538eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 539eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 540eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 541c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 54268d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 543baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 544c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 545c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 546c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 547c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 54868d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 549138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 550baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 55120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 55220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 55320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 554029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 555029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 556c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 558c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 559c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 562a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 563a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 564029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 565bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 566c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 567c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 568c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 569c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 570c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 571c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 572c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 573029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 574029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 575e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = sata_pmp_qc_defer_cmd_switch, 576029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = mv6_dev_config, 57720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 57820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 579e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 580e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 581e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 582e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 583e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .error_handler = sata_pmp_error_handler, 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 58520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 586029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 587029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 588e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = ata_std_qc_defer, /* FIS-based switching */ 589029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 590e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 591e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 592e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 59398ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 595cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 59631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 597bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 598c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 59920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 601c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 60231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 603bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 604c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 60520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 607c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 60847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 609bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 610c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 61220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 613138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 614e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 615138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 61631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 617bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 618c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 61920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 621c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 622e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 623138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 62431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 625bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 626c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 62720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 628e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 629138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 630e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 631138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 632e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 633bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 635e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 636e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 637138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 638e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 639138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 640e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 641bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 64502c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 646e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 64702c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 64817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 64917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 65017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 65220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6543b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6552d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6562d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6572d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6582d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 659cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 660cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 661cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6662d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6672d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 671d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 672d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 673d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 67402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6756a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6766a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 67702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 67802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 67902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 68002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6812d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 68220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 68320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 68447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 68547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 68647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 68747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 68847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 689522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 690522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 69147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 69247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 69347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 69447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 69547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 69647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 69747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 698522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 699522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 702f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 703f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 704f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 705f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 706f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 707f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 708f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 71120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 71220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 71320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 71420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 71520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 71620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 71720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 726c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 727c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 728c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 738c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 739c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 740c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 741c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 74220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 74320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 744c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7458b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 746c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 74720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 74820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 749e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 750e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 751e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 752e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 753e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 754e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 755e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 756e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 759f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 760f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 761f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 762f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 76320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 76420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 76620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 76720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 768cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 76931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 770cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 77131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 77231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 773c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 774c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 775c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 776c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 779c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 780c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 781c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 784c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 785c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 786bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 787c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 788c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 789c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 790bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 791c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 792c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 793bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 794c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 795c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 796c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 797c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 798bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; 799bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 800c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 801c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 802c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 803c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 808c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 81305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 81405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 81505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 81605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 81705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 818beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 819beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 82005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 82105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 82205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 82305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8240c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 825721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 82620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 827721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 828721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 829721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 830721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 831721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 832b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 833721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 834c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8350c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 8360c58912e192fc3a4835d772aafa40b72552b819fMark Lord int hard_port = mv_hardport_from_port(ap->port_no); 8370c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 8380fca0d6f2ce3336022a22bc7fc2e009e599e63a4Saeed Bishara mv_host_base(ap->host), hard_port); 8390c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8400c58912e192fc3a4835d772aafa40b72552b819fMark Lord 841bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 842f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 843bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8440c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8450c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 8460c58912e192fc3a4835d772aafa40b72552b819fMark Lord ipending = (DEV_IRQ << hard_port) | 8470c58912e192fc3a4835d772aafa40b72552b819fMark Lord (CRPB_DMA_DONE << hard_port); 8480c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8490c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8500c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8510c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8520c58912e192fc3a4835d772aafa40b72552b819fMark Lord 853e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8540c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8550c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8560c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8570c58912e192fc3a4835d772aafa40b72552b819fMark Lord 858f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 859bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 860f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 861afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 862afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 863f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 86420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 86605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 867e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 868b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 86905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 87005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 87105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 87205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 873b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 87420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 875b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 87631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 877b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 878b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 8798b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 880b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 881b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 882b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 8834537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 884b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 885b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 88631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 887b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 88820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 88920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 890e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 8910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 892b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 893b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 8940ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 895b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 896b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 897b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 898b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 899b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 900b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 901b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 902b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9030ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9040ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9058a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 90631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 90720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 90831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 90931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 91031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 91131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9122dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 91331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 91431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 91631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9188a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9198a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 92231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 92331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 92431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 92731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9282dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9292dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 93031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 93331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 93731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9408b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 94331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 94431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 94531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 94931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 95131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 95331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9548b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 95731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 95831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 95931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 96431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 96531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 967d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9732dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 97431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 9752dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 97631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 97920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 98020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 98120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 98220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 98320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 98420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 98520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 98620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 98720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 98820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 98920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 99020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 99120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 99220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 99320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 99420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 99520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 99620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 99720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 99820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 99920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 100020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1001da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 100220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 100320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 100420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1005da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1006da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1007da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1008da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1009da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 101020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 101120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1012da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 101320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 101420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 101520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1016da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 101720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1018da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1019da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1020da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 102120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1023f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1024f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1025f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1026e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1027e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1028e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1029e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1030e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1031f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1032f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1033f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1034e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1035e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_attached(adev->link->ap)) 1036e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1037e49856d82a887ce365637176f9f99ab68076eae8Mark Lord else if (adev->max_sectors > ATA_MAX_SECTORS) 1038f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord adev->max_sectors = ATA_MAX_SECTORS; 1039e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1040e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 1041e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 1042e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) 1043e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 1044e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; 1045e49856d82a887ce365637176f9f99ab68076eae8Mark Lord /* 1046e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Various bit settings required for operation 1047e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * in FIS-based switching (fbs) mode on GenIIe: 1048e49856d82a887ce365637176f9f99ab68076eae8Mark Lord */ 1049e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_fcfg = readl(port_mmio + FIS_CFG_OFS); 1050e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 1051e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (enable_fbs) { 1052e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; 1053e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 1054e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { /* disable fbs */ 1055e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; 1056e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 1057e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1058e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_fcfg != old_fcfg) 1059e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); 1060e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1061e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1062f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1063f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1064e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1065e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10660c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1067e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1068e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1069e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1070e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1071e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 10720c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1073e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10740c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1076e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10770c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1078e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1079e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1080e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1081e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1082e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1083e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1084e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1085e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 1086e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (want_ncq && sata_pmp_attached(ap)) { 1087e49856d82a887ce365637176f9f99ab68076eae8Mark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1088e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 1); 1089e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { 1090e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 0); 1091e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1092e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1093e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1094721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1095721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1096721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1097721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1098721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1099721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1100e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1101e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1102e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1103da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1104da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1105da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1106da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1107eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1108da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1109da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1110da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1111da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1112da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1113da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1114da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1115da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1116da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1117eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1118eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1119eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1120eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1121eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1122eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1123eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1124eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1125eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1126eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1127eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1128eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1129da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1130da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1131da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 113205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 113305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 113405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 113505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 113605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 113705b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 113805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 113905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 114005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 114105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 114231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 114331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1144cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1145cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 114631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 114731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 11480ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik unsigned long flags; 1149dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 115031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 11526037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 115324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1154da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 115531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1156da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1157da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1158da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1159da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 116031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1161da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1162da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1163da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1164da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 116531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1166eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1167eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1168eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1169eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1170eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1171eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1172eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1173eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1174eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1175eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1176eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1177eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1178eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1179eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1180eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 118131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11820ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_lock_irqsave(&ap->host->lock, flags); 11830ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1184e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, 0); 1185c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik mv_set_edma_ptrs(port_mmio, hpriv, pp); 118631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_unlock_irqrestore(&ap->host->lock, flags); 11880ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 118931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Don't turn on EDMA here...do it before DMA commands only. Else 119031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * we'll be unable to send non-data, PIO, etc due to restricted access 119131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * to shadow regs. 119231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 119331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1194da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1195da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1196da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1197da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 119831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 119931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 120005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 120105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 120205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 120305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 120505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1207cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 120805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 120931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 121031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1211e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1212da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 121331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 121431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 121505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 121605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 121705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 121805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 122005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 122105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 122205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 122305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 12246c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1227972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 12283be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1229ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1231eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1232ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1233d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1234d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 123522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12364007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 12374007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 12384007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 123922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12404007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 12414007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 12424007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12434007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 12444007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 12456c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 12464007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12474007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 12484007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 12494007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12503be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 12514007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 12524007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12543be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 12553be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 12563be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12595796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1261559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 126231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1263559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 126605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 126705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 126805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 126905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 127005b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 127105b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 127205b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 127305b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 127405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 127505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 127605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 127705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1282e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1285a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1287138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1288138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 129020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1293e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1295beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1297e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1301a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1302a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1303eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1304a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1305eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1306a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 130731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1308a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 131231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 131331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 131431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 131531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 131620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 131731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 131831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 131931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 132031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 132131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1322c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 132331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 132431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 132531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 132631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 13278b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 132831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 132931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 133031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 133131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 133231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 133331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 133431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 133531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 133631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 133731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 133831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 133931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 134031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 134131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 134231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 134331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 134431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 134531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 134631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 134731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 134831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 134931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 135031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 135131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1352e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1361e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1362e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1363e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1364e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1365e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1366e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1367e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1368e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1369e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1370e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1371e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1372e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1374e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1375a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1376e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1377e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1378138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1379138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1380e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1381e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1382e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1383e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1384e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1385e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1386beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1387e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 13888c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1389e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1390e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1391bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1392bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1393a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1394a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1395eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1396eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1398e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1399e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1400e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1405e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1406e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1408e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1409e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1410e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1411e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1412e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1413e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1415e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1416e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1417e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1418e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1421e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 142231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 142331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 142431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 142531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 142605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 142705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 142805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 142905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143005b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 143105b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 143205b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 143305b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 143405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 143605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 143705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 14389a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 143931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1440c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1441c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1442c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 144431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1445138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1446138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 144717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 144817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 144931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 145031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 145131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1452b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1453e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 14549363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 145531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 145631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1457721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->req_idx++; 146031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 146631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 146831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 146931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 147005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 147105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 147205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 14739b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 147405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 147505b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1476e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1477e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1478e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1479e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 148005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 148105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 148205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 148305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1484bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 148531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 148631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1487bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1488bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1489bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1490bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1491bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 14929af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 149320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 149520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1496bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1497bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1498bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1500936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1501936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 150220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1504bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1505bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause); 1507bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * all generations share these EDMA error cause bits 1510bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1512bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1513bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1514bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 15156c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1518cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1519b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1520bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1524b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1525cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1528ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 15325ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1533bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1534b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1537bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 15405ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1542b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1545bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1546936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1547936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1548bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1549cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1551afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 155220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 155320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 15543606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 155520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1558cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1559bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1563bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1565bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_pio(struct ata_port *ap) 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u8 ata_status; 1579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* ignore spurious intr if drive still BUSY */ 1581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_status = readb(ap->ioaddr.status_addr); 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(ata_status & ATA_BUSY)) 1583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get active ATA command */ 15869af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(!qc)) /* no active tag */ 1588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= ac_err_mask(ata_status); 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_edma(struct ata_port *ap) 1598bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1599bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1600bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1602bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 out_index, in_index; 1604bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get h/w response queue pointer */ 1607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik while (1) { 1611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u16 status; 16126c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1614bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get s/w response queue last-read pointer, and compare */ 1615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (in_index == out_index) 1617bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 1618bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1619bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 50xx: get active ATA command */ 16200ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik if (IS_GEN_I(hpriv)) 16219af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1622bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik /* Gen II/IIE: get active ATA command via tag, to enable 16246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * support for queueing. this works transparently for 16256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * queued and non-queued modes. 1626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 16278c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord else 16288c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; 1629bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16306c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik qc = ata_qc_from_tag(ap, tag); 1631bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1632cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord /* For non-NCQ mode, the lower 8 bits of status 1633cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * are from EDMA_ERR_IRQ_CAUSE_OFS, 1634cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * which should be zero if all went well. 1635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik status = le16_to_cpu(pp->crpb[out_index].flags); 1637cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1638bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1639bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1640bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1642bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1643bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) { 1644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= 1645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); 1646bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16490ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* advance software response queue pointer, to 1650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * indicate (after the loop completes) to hardware 1651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * that we have consumed a response queue entry. 1652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1653bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1654bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->resp_idx++; 1655bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1656bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1657bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1658bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1659bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik (out_index << EDMA_RSP_Q_PTR_SHIFT), 1660bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 166120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 166220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 166305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 166405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1665cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 166605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @relevant: port error bits relevant to this host controller 166705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @hc: which host controller we're to look at 166805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 166905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read then write clear the HC interrupt status then walk each 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ * port connected to the HC and see if it needs servicing. Port 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * success ints are reported in the HC interrupt status reg, the 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * port error ints are reported in the higher level main 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt status register and thus are passed in via the 167405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 'relevant' argument. 167505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1679cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 168020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 168320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 168420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 hc_irq_cause; 1685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int port, port0, last_port; 168620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1687351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik if (hc == 0) 168820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = 0; 1689351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik else 169020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = MV_PORTS_PER_HC; 169120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1692f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) 1693f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + MV_PORTS_PER_HC; 1694f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 1695f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + hpriv->n_ports; 169620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* we'll need the HC success int register in most cases */ 169720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1698bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!hc_irq_cause) 1699bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1700bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1701bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 170220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 170320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 17042dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik hc, relevant, hc_irq_cause); 170520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17068f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu for (port = port0; port < last_port; port++) { 1707cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 17088f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik int have_err_bits, hard_port, shift; 171055d8ca4f8094246da6e71889a4e04bfafaa78b10Jeff Garzik 1711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) 1712a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1713a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik 17148f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu pp = ap->private_data; 17158f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu 171631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ shift = port << 1; /* (port * 2) */ 1717e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord if (port >= MV_PORTS_PER_HC) 171820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ shift++; /* skip bit 8 in the HC Main IRQ reg */ 1719e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 1720bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik have_err_bits = ((PORT0_ERR << shift) & relevant); 1721bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(have_err_bits)) { 1723bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 17248b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 17259af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1726bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1727bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1728bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1730bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1731bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1732bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1733bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hard_port = mv_hardport_from_port(port); /* range 0..3 */ 1734bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1735bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1736bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) 1737bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_edma(ap); 1738bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1739bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((DEV_IRQ << hard_port) & hc_irq_cause) 1740bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_pio(ap); 174120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 174220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 174320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("EXIT\n"); 174420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 174520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1746bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1747bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 174802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1749bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1750bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1751bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1752bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1753bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 175502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1756bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1757bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1758bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 176302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1765bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1766bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1767936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17689af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1770bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1772bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1773bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1774cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17759af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1779bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1781bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 178605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1787c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 178805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 178905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 179005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 179105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 179205b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 179305b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 179405b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 179505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 17968b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1797cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 179805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 179905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 18007d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 180120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1802cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 180420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int hc, handled = 0, n_hcs; 1805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 1806646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord u32 irq_stat, irq_mask; 180720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1808e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Note to self: &host->lock == &ap->host->lock == ap->lock */ 1809646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 1811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_stat = readl(hpriv->main_cause_reg_addr); 1812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_mask = readl(hpriv->main_mask_reg_addr); 181320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 181420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* check the cases where we either have nothing pending or have read 181520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * a bogus register value which can indicate HW removal or PCI fault 181620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1817646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat)) 1818646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord goto out_unlock; 181920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1820cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik n_hcs = mv_get_hc_count(host->ports[0]->flags); 182120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (unlikely((irq_stat & PCI_ERR) && HAS_PCI(host))) { 1823bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_pci_error(host, mmio); 1824bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 1825bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik goto out_unlock; /* skip all other HC irq handling */ 1826bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1827bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 182820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hcs; hc++) { 182920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); 183020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ if (relevant) { 1831cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik mv_host_intr(host, relevant, hc); 1832bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 183320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 183420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1835615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1836bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikout_unlock: 1837cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 183820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 183920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 184020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 184120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1842c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1843c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1844c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1845c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1846c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1847c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1848c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1849c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1850c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1851c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1859da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18630d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1864c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1865c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1866da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1867da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1868da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1869da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1870da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1872c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1873da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1874c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18770d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1880da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18810d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1882da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1883da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1884da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1888522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1890522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1891522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 189244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1893522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1894522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1895522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1896522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1897522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1898522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1899522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 19007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1901522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1902522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1903522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1904522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1905522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1906522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1907522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 190847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1909ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1910ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1911c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1912c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1913c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1914c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1915c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1916c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1917c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1918ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1919ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 192047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1921ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1922522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1923522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1924522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1925522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1926522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1927522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1928522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1929522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1930522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1931ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1932ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 19332a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 19342a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1935bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1957bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1958bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1960c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1961c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1962c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1963c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1964c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1967b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 1968b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 1969b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 1970b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 1971b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 1972e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1974c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1975c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1976c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1977c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1978c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1981c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1983c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1984c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1985c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 199347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 1994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 1998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 1999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2015c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2018c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 202347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 202447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2025101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2026101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 20277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2028101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 202902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2030101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2031101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 2033101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 2034101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 2035101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2036101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 204102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 204202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2049101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2063101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2064101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2066101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2070101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2071c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2072c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2073101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2074101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2075101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2076101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2077101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2078101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2079101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2080101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2081101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2082101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2083101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2084101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2085101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2086101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20872dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2088101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2089101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2090101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2091101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2092101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2093101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2094101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2095101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2096101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2097101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2098101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2099101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2100101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2101101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2102101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2103101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2104101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2105101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2106101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2107101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2108101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2109101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2110101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2111101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2112101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2113101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2114101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2115101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2116101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2117101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2118101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2119101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2120101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2121101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2123101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2125101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 212647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2127ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2128ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2129ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2130ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2131ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2132ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2133ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 213447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2135ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2136ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2137ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2138ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2139ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2140ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2141ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2142ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2143ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2144ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2145ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 214647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2147ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 214847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2149ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2150ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2151c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 21522a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2153bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2154c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2155c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2156bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 215747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 215847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2159bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 216047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 216147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 216247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 216347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 216447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 216547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 216647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 216747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 216847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 216947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 217047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 217247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 217347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 217447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 217647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 217747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 217947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 218047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 218147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 218247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2183bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2184bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 218547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2186bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2187bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 218847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2190e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2191bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2192e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2193bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2194bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2195bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 219647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2198e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2199bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2200bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2201bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2202bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2203bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2204bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 22052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 22062a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 220747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2208bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2209e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2210e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2211e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2212e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2213e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2214e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2215bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2216bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2217bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2246b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 2247b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 2248b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 2249b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 2250b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2251e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2253f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2278f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2282f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2283f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2284f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2285f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2287f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2288f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2291f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2292f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2294f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2295f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2296f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2297f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2298f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2299f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2300f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2301f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2302f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2304f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2305f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2306f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2307f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2308b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lordstatic void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2309b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 2310b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2311b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2312b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2313b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 2314b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2315b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2316b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2317b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2318b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord/* 2319b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * Caller must ensure that EDMA is not active, 2320b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * by first doing mv_stop_edma() where needed. 2321b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2322e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2323c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2324c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2325c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2326c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 23270d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 2328c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2329c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2330b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 2331b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* Enable 3.0gb/s link speed */ 2332b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord mv_setup_ifctl(port_mmio, 1); 2333c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2334b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 2335b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * Strobing ATA_RST here causes a hard reset of the SATA transport, 2336b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2337b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2339b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2340b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2341c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2342c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2343c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2344c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2345ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2346c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2347c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2348c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2349e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 2350e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2351e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2352e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2353e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2354e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 2355e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 2356e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2357e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2358e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2359e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 2360e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 2361e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2362e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 2363e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2364e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2365e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2366e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2367e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2368e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2369e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 2370e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2371e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2372e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2373e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2374e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 2375e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2376e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 2377cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 237931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2380cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2382b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 23840d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 23850d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 23860d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 238731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2388e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2389b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2390bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 23910d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 23920d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 239317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 239417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2395bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 239617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 239717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 239817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 23990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 24000d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 24010d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 24020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 24030d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_setup_ifctl(mv_ap_base(ap), 0); 24040d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 24050d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 24060d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 24070d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2408bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 240917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2410bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2411bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2412bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2413bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2414f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2415bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2416bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask; 2417bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift; 2418bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2419bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2420bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2421bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) 2423bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2429f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp & ~mask, hpriv->main_mask_reg_addr); 2430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2434f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2435f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2438bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask, hc_irq_cause; 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift, hc_port_no = ap->port_no; 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) { 2446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_port_no -= 4; 2448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2453bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */ 2458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */ 2459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2462f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2463f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp | mask, hpriv->main_mask_reg_addr); 246431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 246531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 246605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 246705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 246805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 246905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 247005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 247205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 247305b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 247405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 247605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 247705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 247831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 247920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 24800d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 248131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 248231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 24838b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 248431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 248531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 24868b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 248731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 248831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 248931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 249031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 249131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 24938b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 249431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 249531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 249631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 249731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 24998d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 250020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 250231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 250331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 250431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 250531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2506646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2507646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 250820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25098b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 251031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 251131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 251231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 251320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 251420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2516bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2519bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2520bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25215796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 252247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 252347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2524ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 252547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 252644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 252747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 252847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 252947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 253147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 253247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 253447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 253547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 253647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 253747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 253947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2541bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2542bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 254347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2544ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2545bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 254644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 254747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 254847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 254947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 255447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 255547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 255647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2558bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2559bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2560bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2561bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2562bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 256347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2564ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 256547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 256644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 256747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 256847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 256947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2572bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2573bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2574bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 257547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 257647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2577bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2578bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2579bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2580bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2581e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 258202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2583306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2584306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2585306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 25864e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 25874e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 25884e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25894e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 25904e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 25914e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 25924e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25934e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 25944e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 25954e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 25964e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 25974e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 25984e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25994e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 26004e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26014e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 26024e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 26034e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26044e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26054e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26064e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26074e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26084e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26094e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26104e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2611306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2612e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2613e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2614e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 261644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2617e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2618e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2619e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2621e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2622e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2623e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2624e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2625e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2626e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2627e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2628e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2629e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2630f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2631f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2635bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2636f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26375796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2638bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2639bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2640bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2641bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 264202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 264302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 264402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 264502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 264602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 264702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 264802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 264902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 265002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2651bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2652bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2653bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2654bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 265505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 265647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 265905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 266005b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 266105b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 266205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 266305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 266405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 266505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 26664447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 266720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 266820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 26694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2670f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 267147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 26724447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2673bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2674f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara goto done; 2675f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2676f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2677f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_IRQ_CAUSE_OFS; 2679f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS; 2680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS; 2683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + 2684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS; 2685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* global interrupt mask */ 2687f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2688bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26894447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2690bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26914447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 269247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 269320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2694c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 269547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 269620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 269720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2698522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 26997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 270047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 270120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2703cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 27042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2705cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2706cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2707cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 271520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 271620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 271720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 271831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 271931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 272031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 272131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 272231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 272331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 272431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 272531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 272631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 272720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 272820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2729f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2730f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2731f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 273231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2742f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2752f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2753f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2758fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2759fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2760fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2761fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2762fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2763fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2764fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2765fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2766fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2767fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2768fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2769fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2770fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2771fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2772fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2773fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2774fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2775fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2776fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2777fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2778fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2779f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2780f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2781f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2788f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2789f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2791f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2792f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2793f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2794f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2795f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2796f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 279720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2798f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2799f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2800bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2817f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2818f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2819f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2822f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2824f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2829f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2830f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2833fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2834fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2835fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2836fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2850f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2851f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2852f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2854f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2855f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2857f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 286520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 286620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 28777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 28817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 28837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 28847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 28867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 28877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 28887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 28907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 28917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 28927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 28937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 28967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 28977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 28987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 28997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 292805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 292905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29304447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 293105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 293205b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 293305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 293405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 293505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 293605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29374447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 293831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 29394447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29404447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 294144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2942c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 294331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 294431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 294531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 294631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 294731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 294831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 294931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 295031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 295131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 295231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2953c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2954c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2955c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2956c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2957c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2958c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2959c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2960c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2961c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2962c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 296331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2964a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2965c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2966c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 296731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 296831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 296931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 297005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2971f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 297205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 297305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 297405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 297505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 297605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 297705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 2978f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2979f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 298020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 29812dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 298220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 29834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 29844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 29854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 29864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 298720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2988a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 2989a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 299020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 29914447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 29924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 29934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 29944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 29954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 29964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 29974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 29984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 2999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 300224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 300324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 300420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 300520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30060d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30070d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 300824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30090d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 301024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 301320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3014d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3015d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3016d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3017d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3018da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3019da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3020da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3021da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 302220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 302424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 302524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 302620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 302731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30286a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 302931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 303020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 303131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 303320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30344447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3035ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30364447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3037c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 303820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 30397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 304020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3042f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 304420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 304520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 30477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3049f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3050f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3051f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3052f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3053f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3054f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3055f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3056f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 30577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 30587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 305920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 306020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 306120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 306220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 306420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 30657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3066f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 306720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 306820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 306920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 307020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 307120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 307220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 307320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 307417c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 307520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3077ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3078ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 30797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3080ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 308120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 308220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3083