sata_sil.c revision 82ef04fb4c82542b3eda81cca461f0594ce9cd0b
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sata_sil.c - Silicon Image SATA 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Maintained by: Jeff Garzik <jgarzik@pobox.com> 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Please ALWAYS copy linux-ide@vger.kernel.org 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * on emails. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * Copyright 2003-2005 Red Hat, Inc. 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2003 Benjamin Herrenschmidt 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 12af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * This program is free software; you can redistribute it and/or modify 13af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * it under the terms of the GNU General Public License as published by 14af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * the Free Software Foundation; either version 2, or (at your option) 15af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * any later version. 16af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 17af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * This program is distributed in the hope that it will be useful, 18af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * but WITHOUT ANY WARRANTY; without even the implied warranty of 19af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * GNU General Public License for more details. 21af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 22af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * You should have received a copy of the GNU General Public License 23af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * along with this program; see the file COPYING. If not, write to 24af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 26af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 27af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * libata documentation is available via 'make {ps|pdf}docs', 28af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * as Documentation/DocBook/libata.* 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 30953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * Documentation for SiI 3112: 31953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 32953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * 33953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * Other errata and documentation available under NDA. 34953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/kernel.h> 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/module.h> 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/blkdev.h> 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/delay.h> 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/interrupt.h> 44a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <scsi/scsi_host.h> 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/libata.h> 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DRV_NAME "sata_sil" 492a3103ce4357a09c2289405f969acec0edf4398fJeff Garzik#define DRV_VERSION "2.3" 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsenum { 520d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo SIL_MMIO_BAR = 5, 530d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo 54e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 55e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * host flags 56e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 57201ce85946504ea0e6bd9a365de26684b437121eTejun Heo SIL_FLAG_NO_SATA_IRQ = (1 << 28), 58e4e10e3e7995f5bd481d2720bf30d3a661d110caTejun Heo SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), 59e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo SIL_FLAG_MOD15WRITE = (1 << 30), 6020888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 61cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 620c88758b5a6325428aaadab619886242db20ceaeTejun Heo ATA_FLAG_MMIO, 63e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo 64e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 65e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Controller IDs 66e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sil_3112 = 0, 68201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3112_no_sata_irq = 1, 69201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3512 = 2, 70201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3114 = 3, 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 72e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 73e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Register offsets 74e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_SYSCFG = 0x48, 76e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo 77e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 78e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Register bits 79e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 80e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* SYSCFG */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE0_INT = (1 << 22), 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE1_INT = (1 << 23), 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE2_INT = (1 << 24), 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE3_INT = (1 << 25), 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_4PORT = SIL_MASK_2PORT | 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 89e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* BMDMA/BMDMA2 */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_INTR_STEERING = (1 << 1), 91e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo 9220888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ 9320888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ 9420888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ 9520888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ 9620888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ 9720888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ 9820888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ 9920888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ 10020888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ 10120888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ 10220888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 10320888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo /* SIEN */ 10420888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ 10520888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 106e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 107e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Others 108e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_QUIRK_MOD15WRITE = (1 << 0), 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_QUIRK_UDMA5MAX = (1 << 1), 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1135796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 114281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 115afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heostatic int sil_pci_device_resume(struct pci_dev *pdev); 116281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 117cd0d3bbcdd650651b7ccfaf55d107e3fc237d95aAlan Coxstatic void sil_dev_config(struct ata_device *dev); 11882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 11982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 1200260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heostatic int sil_set_mode(struct ata_link *link, struct ata_device **r_failed); 121f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_freeze(struct ata_port *ap); 122f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_thaw(struct ata_port *ap); 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 124374b1873571bf80dc0c1fcceaaad067980f3b9deJeff Garzik 1253b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id sil_pci_tbl[] = { 12654bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, 12754bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, 12854bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, 12954bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, 13054bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, 13154bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, 13254bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, 13354bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { } /* terminate list */ 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TODO firmware versions should be added - eric */ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic const struct sil_drivelist { 1405796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik const char *product; 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int quirk; 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} sil_blacklist [] = { 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST320012AS", SIL_QUIRK_MOD15WRITE }, 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST330013AS", SIL_QUIRK_MOD15WRITE }, 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST340017AS", SIL_QUIRK_MOD15WRITE }, 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST360015AS", SIL_QUIRK_MOD15WRITE }, 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST380023AS", SIL_QUIRK_MOD15WRITE }, 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { } 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic struct pci_driver sil_pci_driver = { 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = DRV_NAME, 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .id_table = sil_pci_tbl, 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .probe = sil_init_one, 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .remove = ata_pci_remove_one, 163281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 164afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo .suspend = ata_pci_device_suspend, 165afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo .resume = sil_pci_device_resume, 166281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 169193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzikstatic struct scsi_host_template sil_sht = { 17068d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BMDMA_SHT(DRV_NAME), 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 173029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations sil_ops = { 174029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_bmdma_port_ops, 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .dev_config = sil_dev_config, 1769d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox .set_mode = sil_set_mode, 177f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .freeze = sil_freeze, 178f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .thaw = sil_thaw, 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .scr_read = sil_scr_read, 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .scr_write = sil_scr_write, 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18398ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info sil_port_info[] = { 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* sil_3112 */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 186cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 187e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .pio_mask = 0x1f, /* pio0-4 */ 188e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 189bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 190e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .port_ops = &sil_ops, 1910ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo }, 192201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* sil_3112_no_sata_irq */ 193201ce85946504ea0e6bd9a365de26684b437121eTejun Heo { 194cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 195201ce85946504ea0e6bd9a365de26684b437121eTejun Heo SIL_FLAG_NO_SATA_IRQ, 196201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .pio_mask = 0x1f, /* pio0-4 */ 197201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 198bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 199201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .port_ops = &sil_ops, 200201ce85946504ea0e6bd9a365de26684b437121eTejun Heo }, 2010ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo /* sil_3512 */ 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 203cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 2040ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .pio_mask = 0x1f, /* pio0-4 */ 2050ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 206bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 2070ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .port_ops = &sil_ops, 2080ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo }, 2090ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo /* sil_3114 */ 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 211cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .pio_mask = 0x1f, /* pio0-4 */ 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .mwdma_mask = 0x07, /* mwdma0-2 */ 214bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .port_ops = &sil_ops, 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* per-port register offsets */ 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TODO: we can probably calculate rather than use a table */ 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic const struct { 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long tf; /* ATA taskfile register block */ 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long ctl; /* ATA control/altstatus register block */ 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long bmdma; /* DMA register block */ 22520888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo unsigned long bmdma2; /* DMA register block #2 */ 22648d4ef2a1df9867c67b515d66732ba028a73735dTejun Heo unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long scr; /* SATA control register block */ 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long sien; /* SATA Interrupt Enable register */ 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long xfer_mode;/* data transfer mode register */ 230e4e10e3e7995f5bd481d2720bf30d3a661d110caTejun Heo unsigned long sfis_cfg; /* SATA FIS reception config register */ 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} sil_port[] = { 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* port 0 ... */ 2335bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */ 2345bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, 2355bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, 23620888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, 23720888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* ... port 3 */ 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_AUTHOR("Jeff Garzik"); 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_LICENSE("GPL"); 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DEVICE_TABLE(pci, sil_pci_tbl); 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_VERSION(DRV_VERSION); 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2475796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic int slow_down; 24851e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzikmodule_param(slow_down, int, 0444); 24951e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff GarzikMODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); 25051e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik 251374b1873571bf80dc0c1fcceaaad067980f3b9deJeff Garzik 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic unsigned char sil_get_device_cache_line(struct pci_dev *pdev) 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 cache_line = 0; 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return cache_line; 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2599d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox/** 2609d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * sil_set_mode - wrap set_mode functions 2610260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo * @link: link to set up 2629d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * @r_failed: returned device when we fail 2639d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * 2649d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * Wrap the libata method for device setup as after the setup we need 2659d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * to inspect the results and do some configuration work 2669d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox */ 2679d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox 2680260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heostatic int sil_set_mode(struct ata_link *link, struct ata_device **r_failed) 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2700260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo struct ata_port *ap = link->ap; 2710260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 2720d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; 2730260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo struct ata_device *dev; 274f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo u32 tmp, dev_mode[2] = { }; 2759d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox int rc; 276a617c09f6d646b60f31efc8afd9f81b752bf21b7Jeff Garzik 2770260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo rc = ata_do_set_mode(link, r_failed); 2789d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox if (rc) 2799d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox return rc; 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2810260731f0187840e272bfa10d3ba0f3e417976f5Tejun Heo ata_link_for_each_dev(dev, link) { 282e1211e3fa7fd05ff0d4f597fd37e40de8acc6784Tejun Heo if (!ata_dev_enabled(dev)) 283f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 0; /* PIO0/1/2 */ 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else if (dev->flags & ATA_DFLAG_PIO) 285f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 1; /* PIO3/4 */ 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 287f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 3; /* UDMA */ 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* value 2 indicates MDMA */ 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = readl(addr); 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= dev_mode[0]; 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= (dev_mode[1] << 4); 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds writel(tmp, addr); 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds readl(addr); /* flush */ 2979d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox return 0; 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3005796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic inline void __iomem *sil_scr_addr(struct ata_port *ap, 3015796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik unsigned int sc_reg) 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3030d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *offset = ap->ioaddr.scr_addr; 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (sc_reg) { 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_STATUS: 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset + 4; 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_ERROR: 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset + 8; 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_CONTROL: 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset; 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* do nothing */ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3178d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap return NULL; 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 32082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 32282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); 323da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 324da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (mmio) { 325da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mmio); 326da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 327da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 328da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 33182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 33382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); 334da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 335da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (mmio) { 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds writel(val, mmio); 337da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 338da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 339da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 342cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heostatic void sil_host_intr(struct ata_port *ap, u32 bmdma2) 343cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo{ 3449af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 3459af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 346cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo u8 status; 347cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 348e573890b00426189e1e223967a2c46fb758bf06eTejun Heo if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { 349d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo u32 serror; 350d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 351d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo /* SIEN doesn't mask SATA IRQs on some 3112s. Those 352d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * controllers continue to assert IRQ as long as 353d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * SError bits are pending. Clear SError immediately. 354d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo */ 35582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo sil_scr_read(&ap->link, SCR_ERROR, &serror); 35682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo sil_scr_write(&ap->link, SCR_ERROR, serror); 357d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 3588cf32ac6578a70025be1103466da9d1d6141429eTejun Heo /* Sometimes spurious interrupts occur, double check 3598cf32ac6578a70025be1103466da9d1d6141429eTejun Heo * it's PHYRDY CHG. 360d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo */ 3618cf32ac6578a70025be1103466da9d1d6141429eTejun Heo if (serror & SERR_PHYRDY_CHG) { 362f7fe7ad4bcaba17f05d5cbf1119772c645783b08Tejun Heo ap->link.eh_info.serror |= serror; 3638cf32ac6578a70025be1103466da9d1d6141429eTejun Heo goto freeze; 364d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo } 365d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 3668cf32ac6578a70025be1103466da9d1d6141429eTejun Heo if (!(bmdma2 & SIL_DMA_COMPLETE)) 3678cf32ac6578a70025be1103466da9d1d6141429eTejun Heo return; 368e573890b00426189e1e223967a2c46fb758bf06eTejun Heo } 369e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 3708cf32ac6578a70025be1103466da9d1d6141429eTejun Heo if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { 371e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo /* this sometimes happens, just clear IRQ */ 3725682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_check_status(ap); 373e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo return; 374e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo } 375e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo 376cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Check whether we are expecting interrupt in this state */ 377cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo switch (ap->hsm_task_state) { 378cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST_FIRST: 379cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Some pre-ATAPI-4 devices assert INTRQ 380cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo * at this state when ready to receive CDB. 381cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo */ 382cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 383cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 384405e66b38797875e80669eaf72d313dbb76533c3Tejun Heo * The flag was turned on only for atapi devices. No 385405e66b38797875e80669eaf72d313dbb76533c3Tejun Heo * need to check ata_is_atapi(qc->tf.protocol) again. 386cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo */ 387cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 388cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 389cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 390cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST_LAST: 391405e66b38797875e80669eaf72d313dbb76533c3Tejun Heo if (ata_is_dma(qc->tf.protocol)) { 392cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* clear DMA-Start bit */ 393cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ap->ops->bmdma_stop(qc); 394cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 395cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (bmdma2 & SIL_DMA_ERROR) { 396cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo qc->err_mask |= AC_ERR_HOST_BUS; 397cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ap->hsm_task_state = HSM_ST_ERR; 398cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 399cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 400cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 401cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST: 402cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 403cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo default: 404cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 405cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 406cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 407cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* check main status, clearing INTRQ */ 4085682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo status = ap->ops->sff_check_status(ap); 409cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (unlikely(status & ATA_BUSY)) 410cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 411cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 412cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* ack bmdma irq events */ 4139363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_irq_clear(ap); 414cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 415cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* kick HSM in the ass */ 4169363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_hsm_move(ap, qc, status, 0); 417cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 418405e66b38797875e80669eaf72d313dbb76533c3Tejun Heo if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) 419ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); 420ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo 421cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo return; 422cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 423cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo err_hsm: 424cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo qc->err_mask |= AC_ERR_HSM; 425cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo freeze: 426cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ata_port_freeze(ap); 427cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo} 428cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 4297d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t sil_interrupt(int irq, void *dev_instance) 430cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo{ 431cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 4320d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 433cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo int handled = 0; 434cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo int i; 435cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 436cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_lock(&host->lock); 437cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 438cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik for (i = 0; i < host->n_ports; i++) { 439cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[i]; 440cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 441cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 442cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) 443cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo continue; 444cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 445201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* turn off SATA_IRQ if not supported */ 446201ce85946504ea0e6bd9a365de26684b437121eTejun Heo if (ap->flags & SIL_FLAG_NO_SATA_IRQ) 447201ce85946504ea0e6bd9a365de26684b437121eTejun Heo bmdma2 &= ~SIL_DMA_SATA_IRQ; 448201ce85946504ea0e6bd9a365de26684b437121eTejun Heo 44923fa9618094975f803ed0c6a44604b16747b9637Tejun Heo if (bmdma2 == 0xffffffff || 45023fa9618094975f803ed0c6a44604b16747b9637Tejun Heo !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) 451cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo continue; 452cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 453cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo sil_host_intr(ap, bmdma2); 454cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo handled = 1; 455cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 456cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 457cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 458cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 459cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo return IRQ_RETVAL(handled); 460cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo} 461cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 462f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_freeze(struct ata_port *ap) 463f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo{ 4640d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 465f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo u32 tmp; 466f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 467e573890b00426189e1e223967a2c46fb758bf06eTejun Heo /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ 468e573890b00426189e1e223967a2c46fb758bf06eTejun Heo writel(0, mmio_base + sil_port[ap->port_no].sien); 469e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 470f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* plug IRQ */ 471f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp = readl(mmio_base + SIL_SYSCFG); 472f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp |= SIL_MASK_IDE0_INT << ap->port_no; 473f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo writel(tmp, mmio_base + SIL_SYSCFG); 474f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo readl(mmio_base + SIL_SYSCFG); /* flush */ 475f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo} 476f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 477f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_thaw(struct ata_port *ap) 478f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo{ 4790d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 480f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo u32 tmp; 481f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 482f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* clear IRQ */ 4835682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_check_status(ap); 4849363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_irq_clear(ap); 485f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 486201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* turn on SATA IRQ if supported */ 487201ce85946504ea0e6bd9a365de26684b437121eTejun Heo if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) 488201ce85946504ea0e6bd9a365de26684b437121eTejun Heo writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); 489e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 490f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* turn on IRQ */ 491f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp = readl(mmio_base + SIL_SYSCFG); 492f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); 493f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo writel(tmp, mmio_base + SIL_SYSCFG); 494f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo} 495f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sil_dev_config - Apply device/host-specific errata fixups 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @dev: Device to be examined 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * After the IDENTIFY [PACKET] DEVICE step is complete, and a 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * device is known to be present, this function is called. 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We apply two errata fixups which are specific to Silicon Image, 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a Seagate and a Maxtor fixup. 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For certain Seagate devices, we must limit the maximum sectors 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to under 8K. 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For certain Maxtor devices, we must not program the drive 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * beyond udma5. 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Both fixups are unfairly pessimistic. As soon as I get more 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * information on these errata, I will create a more exhaustive 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * list, and apply the fixups to only the specific 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * devices/hosts/firmwares that need it. 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The Maxtor quirk is in the blacklist, but I'm keeping the original 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pessimistic fix for the following reasons... 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - There seems to be less info on it, only one device gleaned off the 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Windows driver, maybe only one is affected. More info would be greatly 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * appreciated. 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - But then again UDMA5 is hardly anything to complain about 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 524cd0d3bbcdd650651b7ccfaf55d107e3fc237d95aAlan Coxstatic void sil_dev_config(struct ata_device *dev) 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 5269af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_port *ap = dev->link->ap; 5279af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO; 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int n, quirks = 0; 529a0cf733b333eeeafb7324e2897448006c693c26cTejun Heo unsigned char model_num[ATA_ID_PROD_LEN + 1]; 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 531a0cf733b333eeeafb7324e2897448006c693c26cTejun Heo ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5338a60a07129fad60bba779a2a4038c7518b167fc7Jeff Garzik for (n = 0; sil_blacklist[n].product; n++) 5342e02671daa2cd69d93c828c40579bbe953f17210Tejun Heo if (!strcmp(sil_blacklist[n].product, model_num)) { 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds quirks = sil_blacklist[n].quirk; 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5388a60a07129fad60bba779a2a4038c7518b167fc7Jeff Garzik 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* limit requests to 15 sectors */ 54051e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik if (slow_down || 54151e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik ((ap->flags & SIL_FLAG_MOD15WRITE) && 54251e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik (quirks & SIL_QUIRK_MOD15WRITE))) { 543efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo if (print_info) 544efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo ata_dev_printk(dev, KERN_INFO, "applying Seagate " 545efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo "errata fix (mod15write workaround)\n"); 546b00eec1d58ee71131375bfeb86e64bceec3f5618Tejun Heo dev->max_sectors = 15; 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* limit to udma5 */ 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (quirks & SIL_QUIRK_UDMA5MAX) { 552efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo if (print_info) 553efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo ata_dev_printk(dev, KERN_INFO, "applying Maxtor " 554efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo "errata fix %s\n", model_num); 5555a529139554f12cb265715117a2153c936286294Tejun Heo dev->udma_mask &= ATA_UDMA5; 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void sil_init_controller(struct ata_host *host) 5613d8ec91352099b32a400f1952112dc076da28106Tejun Heo{ 5624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 5634447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 5643d8ec91352099b32a400f1952112dc076da28106Tejun Heo u8 cls; 5653d8ec91352099b32a400f1952112dc076da28106Tejun Heo u32 tmp; 5663d8ec91352099b32a400f1952112dc076da28106Tejun Heo int i; 5673d8ec91352099b32a400f1952112dc076da28106Tejun Heo 5683d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* Initialize FIFO PCI bus arbitration */ 5693d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls = sil_get_device_cache_line(pdev); 5703d8ec91352099b32a400f1952112dc076da28106Tejun Heo if (cls) { 5713d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls >>= 3; 5723d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls++; /* cls = (line_size/8)+1 */ 5734447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0; i < host->n_ports; i++) 5743d8ec91352099b32a400f1952112dc076da28106Tejun Heo writew(cls << 8 | cls, 5753d8ec91352099b32a400f1952112dc076da28106Tejun Heo mmio_base + sil_port[i].fifo_cfg); 5763d8ec91352099b32a400f1952112dc076da28106Tejun Heo } else 5773d8ec91352099b32a400f1952112dc076da28106Tejun Heo dev_printk(KERN_WARNING, &pdev->dev, 5783d8ec91352099b32a400f1952112dc076da28106Tejun Heo "cache line size not set. Driver may not function\n"); 5793d8ec91352099b32a400f1952112dc076da28106Tejun Heo 5803d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* Apply R_ERR on DMA activate FIS errata workaround */ 5814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { 5823d8ec91352099b32a400f1952112dc076da28106Tejun Heo int cnt; 5833d8ec91352099b32a400f1952112dc076da28106Tejun Heo 5844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0, cnt = 0; i < host->n_ports; i++) { 5853d8ec91352099b32a400f1952112dc076da28106Tejun Heo tmp = readl(mmio_base + sil_port[i].sfis_cfg); 5863d8ec91352099b32a400f1952112dc076da28106Tejun Heo if ((tmp & 0x3) != 0x01) 5873d8ec91352099b32a400f1952112dc076da28106Tejun Heo continue; 5883d8ec91352099b32a400f1952112dc076da28106Tejun Heo if (!cnt) 5893d8ec91352099b32a400f1952112dc076da28106Tejun Heo dev_printk(KERN_INFO, &pdev->dev, 5903d8ec91352099b32a400f1952112dc076da28106Tejun Heo "Applying R_ERR on DMA activate " 5913d8ec91352099b32a400f1952112dc076da28106Tejun Heo "FIS errata fix\n"); 5923d8ec91352099b32a400f1952112dc076da28106Tejun Heo writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); 5933d8ec91352099b32a400f1952112dc076da28106Tejun Heo cnt++; 5943d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 5953d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 5963d8ec91352099b32a400f1952112dc076da28106Tejun Heo 5974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (host->n_ports == 4) { 5983d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* flip the magic "make 4 ports work" bit */ 5993d8ec91352099b32a400f1952112dc076da28106Tejun Heo tmp = readl(mmio_base + sil_port[2].bmdma); 6003d8ec91352099b32a400f1952112dc076da28106Tejun Heo if ((tmp & SIL_INTR_STEERING) == 0) 6013d8ec91352099b32a400f1952112dc076da28106Tejun Heo writel(tmp | SIL_INTR_STEERING, 6023d8ec91352099b32a400f1952112dc076da28106Tejun Heo mmio_base + sil_port[2].bmdma); 6033d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 6043d8ec91352099b32a400f1952112dc076da28106Tejun Heo} 6053d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6065796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds static int printed_version; 6094447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int board_id = ent->driver_data; 6104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL }; 6114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 612ea6ba10bbb88e106f9e2db7dc253993bb3bbbe3bJeff Garzik void __iomem *mmio_base; 6134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int i; 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!printed_version++) 617a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 6204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = 2; 6214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (board_id == sil_3114) 6224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = 4; 6234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6244447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 6254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host) 6264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 6274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources and fill host */ 62924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return rc; 6321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6330d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); 6340d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 63524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 6360d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 63724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 64224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 64524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mmio_base = host->iomap[SIL_MMIO_BAR]; 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0; i < host->n_ports; i++) { 650cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[i]; 651cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_ioports *ioaddr = &ap->ioaddr; 6524447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->cmd_addr = mmio_base + sil_port[i].tf; 6544447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->altstatus_addr = 6554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; 6564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; 6574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->scr_addr = mmio_base + sil_port[i].scr; 6589363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_std_ports(ioaddr); 659cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 660cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio"); 661cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf"); 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* initialize and activate */ 6654447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo sil_init_controller(host); 6661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_set_master(pdev); 6684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, 6694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo &sil_sht); 6701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 672281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 673afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heostatic int sil_pci_device_resume(struct pci_dev *pdev) 674afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo{ 675cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_get_drvdata(&pdev->dev); 676553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo int rc; 677553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo 678553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo rc = ata_pci_device_do_resume(pdev); 679553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo if (rc) 680553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo return rc; 681afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 6824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo sil_init_controller(host); 683cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik ata_host_resume(host); 684afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 685afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo return 0; 686afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo} 687281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 688afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 6891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic int __init sil_init(void) 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 691b7887196e38da54ff893897b80875d632d1a1114Pavel Roskin return pci_register_driver(&sil_pci_driver); 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic void __exit sil_exit(void) 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_unregister_driver(&sil_pci_driver); 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_init(sil_init); 7011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_exit(sil_exit); 702