sata_sil.c revision f58229f8060055b08b34008ea08f31de1e2f003c
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sata_sil.c - Silicon Image SATA 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Maintained by: Jeff Garzik <jgarzik@pobox.com> 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Please ALWAYS copy linux-ide@vger.kernel.org 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * on emails. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * Copyright 2003-2005 Red Hat, Inc. 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2003 Benjamin Herrenschmidt 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 12af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * This program is free software; you can redistribute it and/or modify 13af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * it under the terms of the GNU General Public License as published by 14af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * the Free Software Foundation; either version 2, or (at your option) 15af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * any later version. 16af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 17af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * This program is distributed in the hope that it will be useful, 18af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * but WITHOUT ANY WARRANTY; without even the implied warranty of 19af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * GNU General Public License for more details. 21af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 22af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * You should have received a copy of the GNU General Public License 23af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * along with this program; see the file COPYING. If not, write to 24af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 26af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * 27af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * libata documentation is available via 'make {ps|pdf}docs', 28af36d7f0df56de3e3e4bbfb15d0915097ecb8cabJeff Garzik * as Documentation/DocBook/libata.* 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 30953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * Documentation for SiI 3112: 31953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 32953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * 33953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * Other errata and documentation available under NDA. 34953d1137fc4aba16deace262e93974913596dcfeJeff Garzik * 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/kernel.h> 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/module.h> 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/blkdev.h> 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/delay.h> 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/interrupt.h> 44a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <scsi/scsi_host.h> 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/libata.h> 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DRV_NAME "sata_sil" 492a3103ce4357a09c2289405f969acec0edf4398fJeff Garzik#define DRV_VERSION "2.3" 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsenum { 520d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo SIL_MMIO_BAR = 5, 530d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo 54e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 55e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * host flags 56e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 57201ce85946504ea0e6bd9a365de26684b437121eTejun Heo SIL_FLAG_NO_SATA_IRQ = (1 << 28), 58e4e10e3e7995f5bd481d2720bf30d3a661d110caTejun Heo SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), 59e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo SIL_FLAG_MOD15WRITE = (1 << 30), 6020888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 61cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 62e573890b00426189e1e223967a2c46fb758bf06eTejun Heo ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, 63e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo 64e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 65e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Controller IDs 66e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sil_3112 = 0, 68201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3112_no_sata_irq = 1, 69201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3512 = 2, 70201ce85946504ea0e6bd9a365de26684b437121eTejun Heo sil_3114 = 3, 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 72e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 73e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Register offsets 74e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_SYSCFG = 0x48, 76e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo 77e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 78e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Register bits 79e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 80e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* SYSCFG */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE0_INT = (1 << 22), 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE1_INT = (1 << 23), 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE2_INT = (1 << 24), 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE3_INT = (1 << 25), 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_4PORT = SIL_MASK_2PORT | 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 89e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* BMDMA/BMDMA2 */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_INTR_STEERING = (1 << 1), 91e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo 9220888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ 9320888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ 9420888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ 9520888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ 9620888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ 9720888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ 9820888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ 9920888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ 10020888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ 10120888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ 10220888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 10320888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo /* SIEN */ 10420888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ 10520888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo 106e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo /* 107e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo * Others 108e653a1e6131d0a819288a2e2de654627233604e0Tejun Heo */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_QUIRK_MOD15WRITE = (1 << 0), 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds SIL_QUIRK_UDMA5MAX = (1 << 1), 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 114281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 115afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heostatic int sil_pci_device_resume(struct pci_dev *pdev); 116281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 117cd0d3bbcdd650651b7ccfaf55d107e3fc237d95aAlan Coxstatic void sil_dev_config(struct ata_device *dev); 118da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 119da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 1209d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Coxstatic int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed); 121f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_freeze(struct ata_port *ap); 122f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_thaw(struct ata_port *ap); 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 124374b1873571bf80dc0c1fcceaaad067980f3b9deJeff Garzik 1253b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id sil_pci_tbl[] = { 12654bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, 12754bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, 12854bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, 12954bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, 13054bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, 13154bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, 13254bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, 13354bb3a94b192be09feb85993b664ff118d6433d0Jeff Garzik 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { } /* terminate list */ 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TODO firmware versions should be added - eric */ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic const struct sil_drivelist { 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds const char * product; 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int quirk; 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} sil_blacklist [] = { 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST320012AS", SIL_QUIRK_MOD15WRITE }, 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST330013AS", SIL_QUIRK_MOD15WRITE }, 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST340017AS", SIL_QUIRK_MOD15WRITE }, 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST360015AS", SIL_QUIRK_MOD15WRITE }, 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST380023AS", SIL_QUIRK_MOD15WRITE }, 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { } 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic struct pci_driver sil_pci_driver = { 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = DRV_NAME, 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .id_table = sil_pci_tbl, 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .probe = sil_init_one, 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .remove = ata_pci_remove_one, 163281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 164afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo .suspend = ata_pci_device_suspend, 165afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo .resume = sil_pci_device_resume, 166281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 169193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzikstatic struct scsi_host_template sil_sht = { 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .module = THIS_MODULE, 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = DRV_NAME, 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ioctl = ata_scsi_ioctl, 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .queuecommand = ata_scsi_queuecmd, 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .can_queue = ATA_DEF_QUEUE, 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .this_id = ATA_SHT_THIS_ID, 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sg_tablesize = LIBATA_MAX_PRD, 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .emulated = ATA_SHT_EMULATED, 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .use_clustering = ATA_SHT_USE_CLUSTERING, 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .proc_name = DRV_NAME, 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .dma_boundary = ATA_DMA_BOUNDARY, 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .slave_configure = ata_scsi_slave_config, 183ccf68c3405fca11386004674377d951b9b18e756Tejun Heo .slave_destroy = ata_scsi_slave_destroy, 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .bios_param = ata_std_bios_param, 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 187057ace5e79da9ebf2aa82833cfea825533ac06fbJeff Garzikstatic const struct ata_port_operations sil_ops = { 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .port_disable = ata_port_disable, 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .dev_config = sil_dev_config, 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .tf_load = ata_tf_load, 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .tf_read = ata_tf_read, 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .check_status = ata_check_status, 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .exec_command = ata_exec_command, 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .dev_select = ata_std_dev_select, 1959d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox .set_mode = sil_set_mode, 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .bmdma_setup = ata_bmdma_setup, 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .bmdma_start = ata_bmdma_start, 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .bmdma_stop = ata_bmdma_stop, 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .bmdma_status = ata_bmdma_status, 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .qc_prep = ata_qc_prep, 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .qc_issue = ata_qc_issue_prot, 2020d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo .data_xfer = ata_data_xfer, 203f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .freeze = sil_freeze, 204f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .thaw = sil_thaw, 205f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .error_handler = ata_bmdma_error_handler, 206f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo .post_internal_cmd = ata_bmdma_post_internal_cmd, 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .irq_clear = ata_bmdma_irq_clear, 208246ce3b675843e0369643cceb4faeb6cf6d19a30Akira Iguchi .irq_on = ata_irq_on, 209246ce3b675843e0369643cceb4faeb6cf6d19a30Akira Iguchi .irq_ack = ata_irq_ack, 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .scr_read = sil_scr_read, 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .scr_write = sil_scr_write, 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .port_start = ata_port_start, 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21598ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info sil_port_info[] = { 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* sil_3112 */ 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 218cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 219e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .pio_mask = 0x1f, /* pio0-4 */ 220e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 221bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 222e4deec6304cbd5fd08bf573eccc68787945071c2Tejun Heo .port_ops = &sil_ops, 2230ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo }, 224201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* sil_3112_no_sata_irq */ 225201ce85946504ea0e6bd9a365de26684b437121eTejun Heo { 226cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 227201ce85946504ea0e6bd9a365de26684b437121eTejun Heo SIL_FLAG_NO_SATA_IRQ, 228201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .pio_mask = 0x1f, /* pio0-4 */ 229201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 230bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 231201ce85946504ea0e6bd9a365de26684b437121eTejun Heo .port_ops = &sil_ops, 232201ce85946504ea0e6bd9a365de26684b437121eTejun Heo }, 2330ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo /* sil_3512 */ 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 235cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 2360ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .pio_mask = 0x1f, /* pio0-4 */ 2370ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .mwdma_mask = 0x07, /* mwdma0-2 */ 238bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 2390ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo .port_ops = &sil_ops, 2400ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo }, 2410ee304d5802dc62746f13f12d4cb4ec4ed285f66Tejun Heo /* sil_3114 */ 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 243cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .pio_mask = 0x1f, /* pio0-4 */ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .mwdma_mask = 0x07, /* mwdma0-2 */ 246bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA5, 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .port_ops = &sil_ops, 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* per-port register offsets */ 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TODO: we can probably calculate rather than use a table */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic const struct { 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long tf; /* ATA taskfile register block */ 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long ctl; /* ATA control/altstatus register block */ 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long bmdma; /* DMA register block */ 25720888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo unsigned long bmdma2; /* DMA register block #2 */ 25848d4ef2a1df9867c67b515d66732ba028a73735dTejun Heo unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long scr; /* SATA control register block */ 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long sien; /* SATA Interrupt Enable register */ 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long xfer_mode;/* data transfer mode register */ 262e4e10e3e7995f5bd481d2720bf30d3a661d110caTejun Heo unsigned long sfis_cfg; /* SATA FIS reception config register */ 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} sil_port[] = { 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* port 0 ... */ 2655bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */ 2665bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, 2675bcd7a00a464fd81b4b68847b9b811a635a15b61Jeff Garzik { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, 26820888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, 26920888d83687d5cb374cdb5b0afa746ab79666f4eTejun Heo { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* ... port 3 */ 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_AUTHOR("Jeff Garzik"); 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_LICENSE("GPL"); 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DEVICE_TABLE(pci, sil_pci_tbl); 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_VERSION(DRV_VERSION); 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27951e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzikstatic int slow_down = 0; 28051e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzikmodule_param(slow_down, int, 0444); 28151e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff GarzikMODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); 28251e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik 283374b1873571bf80dc0c1fcceaaad067980f3b9deJeff Garzik 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic unsigned char sil_get_device_cache_line(struct pci_dev *pdev) 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 cache_line = 0; 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return cache_line; 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2919d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox/** 2929d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * sil_set_mode - wrap set_mode functions 2939d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * @ap: port to set up 2949d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * @r_failed: returned device when we fail 2959d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * 2969d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * Wrap the libata method for device setup as after the setup we need 2979d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox * to inspect the results and do some configuration work 2989d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox */ 2999d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox 3009d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Coxstatic int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed) 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 302cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = ap->host; 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct ata_device *dev; 3040d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 3050d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; 306f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo u32 tmp, dev_mode[2] = { }; 3079d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox int rc; 308a617c09f6d646b60f31efc8afd9f81b752bf21b7Jeff Garzik 3099d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox rc = ata_do_set_mode(ap, r_failed); 3109d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox if (rc) 3119d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox return rc; 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 313f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo ata_link_for_each_dev(dev, &ap->link) { 314e1211e3fa7fd05ff0d4f597fd37e40de8acc6784Tejun Heo if (!ata_dev_enabled(dev)) 315f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 0; /* PIO0/1/2 */ 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else if (dev->flags & ATA_DFLAG_PIO) 317f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 1; /* PIO3/4 */ 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 319f58229f8060055b08b34008ea08f31de1e2f003cTejun Heo dev_mode[dev->devno] = 3; /* UDMA */ 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* value 2 indicates MDMA */ 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = readl(addr); 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= dev_mode[0]; 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= (dev_mode[1] << 4); 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds writel(tmp, addr); 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds readl(addr); /* flush */ 3299d2c7c75f889a3eefad016c71f651b0796e0a6e9Alan Cox return 0; 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3320d5ff566779f894ca9937231a181eb31e4adff0eTejun Heostatic inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3340d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *offset = ap->ioaddr.scr_addr; 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (sc_reg) { 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_STATUS: 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset + 4; 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_ERROR: 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset + 8; 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SCR_CONTROL: 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return offset; 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* do nothing */ 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3488d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap return NULL; 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 351da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3530d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio = sil_scr_addr(ap, sc_reg); 354da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 355da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (mmio) { 356da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mmio); 357da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 358da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 359da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 362da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 3640d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio = sil_scr_addr(ap, sc_reg); 365da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo 366da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (mmio) { 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds writel(val, mmio); 368da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 369da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } 370da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 373cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heostatic void sil_host_intr(struct ata_port *ap, u32 bmdma2) 374cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo{ 3759af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 3769af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 377cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo u8 status; 378cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 379e573890b00426189e1e223967a2c46fb758bf06eTejun Heo if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { 380d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo u32 serror; 381d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 382d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo /* SIEN doesn't mask SATA IRQs on some 3112s. Those 383d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * controllers continue to assert IRQ as long as 384d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * SError bits are pending. Clear SError immediately. 385d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo */ 386da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo sil_scr_read(ap, SCR_ERROR, &serror); 387d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo sil_scr_write(ap, SCR_ERROR, serror); 388d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 389d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo /* Trigger hotplug and accumulate SError only if the 390d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * port isn't already frozen. Otherwise, PHY events 391d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * during hardreset makes controllers with broken SIEN 392d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo * repeat probing needlessly. 393d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo */ 394b51e9e5db0e36239f786692f1cac6e435ed30c66Tejun Heo if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 3959af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ata_ehi_hotplugged(&ap->link.eh_info); 3969af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ap->link.eh_info.serror |= serror; 397d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo } 398d4c85325a817d3351e61c4be64b437116e8483b4Tejun Heo 399e573890b00426189e1e223967a2c46fb758bf06eTejun Heo goto freeze; 400e573890b00426189e1e223967a2c46fb758bf06eTejun Heo } 401e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 402e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo if (unlikely(!qc)) 403cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto freeze; 404cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 405e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) { 406e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo /* this sometimes happens, just clear IRQ */ 407e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo ata_chk_status(ap); 408e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo return; 409e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo } 410e2f8fb72144a9f38d44ccf3f939e939392eda659Tejun Heo 411cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Check whether we are expecting interrupt in this state */ 412cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo switch (ap->hsm_task_state) { 413cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST_FIRST: 414cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Some pre-ATAPI-4 devices assert INTRQ 415cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo * at this state when ready to receive CDB. 416cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo */ 417cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 418cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 419cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo * The flag was turned on only for atapi devices. 420cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo * No need to check is_atapi_taskfile(&qc->tf) again. 421cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo */ 422cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 423cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 424cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 425cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST_LAST: 426cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (qc->tf.protocol == ATA_PROT_DMA || 427cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo qc->tf.protocol == ATA_PROT_ATAPI_DMA) { 428cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* clear DMA-Start bit */ 429cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ap->ops->bmdma_stop(qc); 430cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 431cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (bmdma2 & SIL_DMA_ERROR) { 432cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo qc->err_mask |= AC_ERR_HOST_BUS; 433cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ap->hsm_task_state = HSM_ST_ERR; 434cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 435cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 436cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 437cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo case HSM_ST: 438cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo break; 439cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo default: 440cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 441cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 442cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 443cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* check main status, clearing INTRQ */ 444cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo status = ata_chk_status(ap); 445cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (unlikely(status & ATA_BUSY)) 446cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo goto err_hsm; 447cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 448cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* ack bmdma irq events */ 449cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ata_bmdma_irq_clear(ap); 450cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 451cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo /* kick HSM in the ass */ 452cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ata_hsm_move(ap, qc, status, 0); 453cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 454ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 455ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo qc->tf.protocol == ATA_PROT_ATAPI_DMA)) 456ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); 457ea54763f8a7c51b9f8fcb14431812ae63fcbaf96Tejun Heo 458cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo return; 459cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 460cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo err_hsm: 461cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo qc->err_mask |= AC_ERR_HSM; 462cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo freeze: 463cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo ata_port_freeze(ap); 464cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo} 465cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 4667d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t sil_interrupt(int irq, void *dev_instance) 467cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo{ 468cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 4690d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 470cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo int handled = 0; 471cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo int i; 472cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 473cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_lock(&host->lock); 474cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 475cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik for (i = 0; i < host->n_ports; i++) { 476cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[i]; 477cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 478cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 479cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) 480cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo continue; 481cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 482201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* turn off SATA_IRQ if not supported */ 483201ce85946504ea0e6bd9a365de26684b437121eTejun Heo if (ap->flags & SIL_FLAG_NO_SATA_IRQ) 484201ce85946504ea0e6bd9a365de26684b437121eTejun Heo bmdma2 &= ~SIL_DMA_SATA_IRQ; 485201ce85946504ea0e6bd9a365de26684b437121eTejun Heo 48623fa9618094975f803ed0c6a44604b16747b9637Tejun Heo if (bmdma2 == 0xffffffff || 48723fa9618094975f803ed0c6a44604b16747b9637Tejun Heo !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) 488cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo continue; 489cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 490cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo sil_host_intr(ap, bmdma2); 491cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo handled = 1; 492cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo } 493cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 494cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 495cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 496cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo return IRQ_RETVAL(handled); 497cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo} 498cbe88fbc72d9e1aa4a6f994cb6e19fa08ae5a0baTejun Heo 499f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_freeze(struct ata_port *ap) 500f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo{ 5010d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 502f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo u32 tmp; 503f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 504e573890b00426189e1e223967a2c46fb758bf06eTejun Heo /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ 505e573890b00426189e1e223967a2c46fb758bf06eTejun Heo writel(0, mmio_base + sil_port[ap->port_no].sien); 506e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 507f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* plug IRQ */ 508f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp = readl(mmio_base + SIL_SYSCFG); 509f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp |= SIL_MASK_IDE0_INT << ap->port_no; 510f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo writel(tmp, mmio_base + SIL_SYSCFG); 511f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo readl(mmio_base + SIL_SYSCFG); /* flush */ 512f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo} 513f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 514f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heostatic void sil_thaw(struct ata_port *ap) 515f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo{ 5160d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 517f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo u32 tmp; 518f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 519f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* clear IRQ */ 520f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo ata_chk_status(ap); 521f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo ata_bmdma_irq_clear(ap); 522f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 523201ce85946504ea0e6bd9a365de26684b437121eTejun Heo /* turn on SATA IRQ if supported */ 524201ce85946504ea0e6bd9a365de26684b437121eTejun Heo if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) 525201ce85946504ea0e6bd9a365de26684b437121eTejun Heo writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); 526e573890b00426189e1e223967a2c46fb758bf06eTejun Heo 527f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo /* turn on IRQ */ 528f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp = readl(mmio_base + SIL_SYSCFG); 529f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); 530f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo writel(tmp, mmio_base + SIL_SYSCFG); 531f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo} 532f6aae27ed002ba9c0a98aff811dbde32ce749d28Tejun Heo 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sil_dev_config - Apply device/host-specific errata fixups 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @dev: Device to be examined 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * After the IDENTIFY [PACKET] DEVICE step is complete, and a 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * device is known to be present, this function is called. 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We apply two errata fixups which are specific to Silicon Image, 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a Seagate and a Maxtor fixup. 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For certain Seagate devices, we must limit the maximum sectors 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to under 8K. 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For certain Maxtor devices, we must not program the drive 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * beyond udma5. 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Both fixups are unfairly pessimistic. As soon as I get more 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * information on these errata, I will create a more exhaustive 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * list, and apply the fixups to only the specific 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * devices/hosts/firmwares that need it. 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The Maxtor quirk is in the blacklist, but I'm keeping the original 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pessimistic fix for the following reasons... 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - There seems to be less info on it, only one device gleaned off the 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Windows driver, maybe only one is affected. More info would be greatly 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * appreciated. 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - But then again UDMA5 is hardly anything to complain about 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 561cd0d3bbcdd650651b7ccfaf55d107e3fc237d95aAlan Coxstatic void sil_dev_config(struct ata_device *dev) 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 5639af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_port *ap = dev->link->ap; 5649af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO; 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int n, quirks = 0; 566a0cf733b333eeeafb7324e2897448006c693c26cTejun Heo unsigned char model_num[ATA_ID_PROD_LEN + 1]; 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 568a0cf733b333eeeafb7324e2897448006c693c26cTejun Heo ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5708a60a07129fad60bba779a2a4038c7518b167fc7Jeff Garzik for (n = 0; sil_blacklist[n].product; n++) 5712e02671daa2cd69d93c828c40579bbe953f17210Tejun Heo if (!strcmp(sil_blacklist[n].product, model_num)) { 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds quirks = sil_blacklist[n].quirk; 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5758a60a07129fad60bba779a2a4038c7518b167fc7Jeff Garzik 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* limit requests to 15 sectors */ 57751e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik if (slow_down || 57851e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik ((ap->flags & SIL_FLAG_MOD15WRITE) && 57951e9f2ff83df6b1c81c5c44f4486c68ed87aa20eJeff Garzik (quirks & SIL_QUIRK_MOD15WRITE))) { 580efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo if (print_info) 581efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo ata_dev_printk(dev, KERN_INFO, "applying Seagate " 582efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo "errata fix (mod15write workaround)\n"); 583b00eec1d58ee71131375bfeb86e64bceec3f5618Tejun Heo dev->max_sectors = 15; 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* limit to udma5 */ 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (quirks & SIL_QUIRK_UDMA5MAX) { 589efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo if (print_info) 590efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo ata_dev_printk(dev, KERN_INFO, "applying Maxtor " 591efdaedc443e935eda82e9e78a6e65d1f993d242fTejun Heo "errata fix %s\n", model_num); 5925a529139554f12cb265715117a2153c936286294Tejun Heo dev->udma_mask &= ATA_UDMA5; 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void sil_init_controller(struct ata_host *host) 5983d8ec91352099b32a400f1952112dc076da28106Tejun Heo{ 5994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 6004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 6013d8ec91352099b32a400f1952112dc076da28106Tejun Heo u8 cls; 6023d8ec91352099b32a400f1952112dc076da28106Tejun Heo u32 tmp; 6033d8ec91352099b32a400f1952112dc076da28106Tejun Heo int i; 6043d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6053d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* Initialize FIFO PCI bus arbitration */ 6063d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls = sil_get_device_cache_line(pdev); 6073d8ec91352099b32a400f1952112dc076da28106Tejun Heo if (cls) { 6083d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls >>= 3; 6093d8ec91352099b32a400f1952112dc076da28106Tejun Heo cls++; /* cls = (line_size/8)+1 */ 6104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0; i < host->n_ports; i++) 6113d8ec91352099b32a400f1952112dc076da28106Tejun Heo writew(cls << 8 | cls, 6123d8ec91352099b32a400f1952112dc076da28106Tejun Heo mmio_base + sil_port[i].fifo_cfg); 6133d8ec91352099b32a400f1952112dc076da28106Tejun Heo } else 6143d8ec91352099b32a400f1952112dc076da28106Tejun Heo dev_printk(KERN_WARNING, &pdev->dev, 6153d8ec91352099b32a400f1952112dc076da28106Tejun Heo "cache line size not set. Driver may not function\n"); 6163d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6173d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* Apply R_ERR on DMA activate FIS errata workaround */ 6184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { 6193d8ec91352099b32a400f1952112dc076da28106Tejun Heo int cnt; 6203d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0, cnt = 0; i < host->n_ports; i++) { 6223d8ec91352099b32a400f1952112dc076da28106Tejun Heo tmp = readl(mmio_base + sil_port[i].sfis_cfg); 6233d8ec91352099b32a400f1952112dc076da28106Tejun Heo if ((tmp & 0x3) != 0x01) 6243d8ec91352099b32a400f1952112dc076da28106Tejun Heo continue; 6253d8ec91352099b32a400f1952112dc076da28106Tejun Heo if (!cnt) 6263d8ec91352099b32a400f1952112dc076da28106Tejun Heo dev_printk(KERN_INFO, &pdev->dev, 6273d8ec91352099b32a400f1952112dc076da28106Tejun Heo "Applying R_ERR on DMA activate " 6283d8ec91352099b32a400f1952112dc076da28106Tejun Heo "FIS errata fix\n"); 6293d8ec91352099b32a400f1952112dc076da28106Tejun Heo writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); 6303d8ec91352099b32a400f1952112dc076da28106Tejun Heo cnt++; 6313d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 6323d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 6333d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6344447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (host->n_ports == 4) { 6353d8ec91352099b32a400f1952112dc076da28106Tejun Heo /* flip the magic "make 4 ports work" bit */ 6363d8ec91352099b32a400f1952112dc076da28106Tejun Heo tmp = readl(mmio_base + sil_port[2].bmdma); 6373d8ec91352099b32a400f1952112dc076da28106Tejun Heo if ((tmp & SIL_INTR_STEERING) == 0) 6383d8ec91352099b32a400f1952112dc076da28106Tejun Heo writel(tmp | SIL_INTR_STEERING, 6393d8ec91352099b32a400f1952112dc076da28106Tejun Heo mmio_base + sil_port[2].bmdma); 6403d8ec91352099b32a400f1952112dc076da28106Tejun Heo } 6413d8ec91352099b32a400f1952112dc076da28106Tejun Heo} 6423d8ec91352099b32a400f1952112dc076da28106Tejun Heo 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds static int printed_version; 6464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int board_id = ent->driver_data; 6474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL }; 6484447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 649ea6ba10bbb88e106f9e2db7dc253993bb3bbbe3bJeff Garzik void __iomem *mmio_base; 6504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int i; 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!printed_version++) 654a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 6574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = 2; 6584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (board_id == sil_3114) 6594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = 4; 6604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 6624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host) 6634447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 6644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6654447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources and fill host */ 66624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 6671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 6681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return rc; 6691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6700d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); 6710d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 67224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 6730d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 67424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6754447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 6761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 6781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 67924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (rc) 68224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mmio_base = host->iomap[SIL_MMIO_BAR]; 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (i = 0; i < host->n_ports; i++) { 6874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_ioports *ioaddr = &host->ports[i]->ioaddr; 6884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 6894447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->cmd_addr = mmio_base + sil_port[i].tf; 6904447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->altstatus_addr = 6914447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; 6924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; 6934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ioaddr->scr_addr = mmio_base + sil_port[i].scr; 6944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo ata_std_ports(ioaddr); 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* initialize and activate */ 6984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo sil_init_controller(host); 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_set_master(pdev); 7014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, 7024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo &sil_sht); 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 705281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#ifdef CONFIG_PM 706afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heostatic int sil_pci_device_resume(struct pci_dev *pdev) 707afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo{ 708cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_get_drvdata(&pdev->dev); 709553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo int rc; 710553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo 711553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo rc = ata_pci_device_do_resume(pdev); 712553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo if (rc) 713553c4aa630af7bc885e056d0436e4eb7f238579bTejun Heo return rc; 714afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 7154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo sil_init_controller(host); 716cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik ata_host_resume(host); 717afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 718afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo return 0; 719afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo} 720281d426c7e64286f433645e27862e7744b1e9310Alexey Dobriyan#endif 721afb5a7cb84b1ea8b6045945e3d288303e6b71336Tejun Heo 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic int __init sil_init(void) 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 724b7887196e38da54ff893897b80875d632d1a1114Pavel Roskin return pci_register_driver(&sil_pci_driver); 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic void __exit sil_exit(void) 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_unregister_driver(&sil_pci_driver); 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_init(sil_init); 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_exit(sil_exit); 735