amd64-agp.c revision 43ed41f648554c9fecaf7597d25e05da63ec7290
1/* 2 * Copyright 2001-2003 SuSE Labs. 3 * Distributed under the GNU public license, v2. 4 * 5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. 6 * It also includes support for the AMD 8151 AGP bridge, 7 * although it doesn't actually do much, as all the real 8 * work is done in the northbridge(s). 9 */ 10 11#include <linux/module.h> 12#include <linux/pci.h> 13#include <linux/init.h> 14#include <linux/agp_backend.h> 15#include <linux/mmzone.h> 16#include <asm/page.h> /* PAGE_SIZE */ 17#include <asm/k8.h> 18#include "agp.h" 19 20/* PTE bits. */ 21#define GPTE_VALID 1 22#define GPTE_COHERENT 2 23 24/* Aperture control register bits. */ 25#define GARTEN (1<<0) 26#define DISGARTCPU (1<<4) 27#define DISGARTIO (1<<5) 28 29/* GART cache control register bits. */ 30#define INVGART (1<<0) 31#define GARTPTEERR (1<<1) 32 33/* K8 On-cpu GART registers */ 34#define AMD64_GARTAPERTURECTL 0x90 35#define AMD64_GARTAPERTUREBASE 0x94 36#define AMD64_GARTTABLEBASE 0x98 37#define AMD64_GARTCACHECTL 0x9c 38#define AMD64_GARTEN (1<<0) 39 40/* NVIDIA K8 registers */ 41#define NVIDIA_X86_64_0_APBASE 0x10 42#define NVIDIA_X86_64_1_APBASE1 0x50 43#define NVIDIA_X86_64_1_APLIMIT1 0x54 44#define NVIDIA_X86_64_1_APSIZE 0xa8 45#define NVIDIA_X86_64_1_APBASE2 0xd8 46#define NVIDIA_X86_64_1_APLIMIT2 0xdc 47 48/* ULi K8 registers */ 49#define ULI_X86_64_BASE_ADDR 0x10 50#define ULI_X86_64_HTT_FEA_REG 0x50 51#define ULI_X86_64_ENU_SCR_REG 0x54 52 53static struct resource *aperture_resource; 54static int __initdata agp_try_unsupported = 1; 55 56static void amd64_tlbflush(struct agp_memory *temp) 57{ 58 k8_flush_garts(); 59} 60 61static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 62{ 63 int i, j, num_entries; 64 long long tmp; 65 u32 pte; 66 67 num_entries = agp_num_entries(); 68 69 if (type != 0 || mem->type != 0) 70 return -EINVAL; 71 72 /* Make sure we can fit the range in the gatt table. */ 73 /* FIXME: could wrap */ 74 if (((unsigned long)pg_start + mem->page_count) > num_entries) 75 return -EINVAL; 76 77 j = pg_start; 78 79 /* gatt table should be empty. */ 80 while (j < (pg_start + mem->page_count)) { 81 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 82 return -EBUSY; 83 j++; 84 } 85 86 if (mem->is_flushed == FALSE) { 87 global_cache_flush(); 88 mem->is_flushed = TRUE; 89 } 90 91 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 92 tmp = agp_bridge->driver->mask_memory(agp_bridge, 93 mem->memory[i], mem->type); 94 95 BUG_ON(tmp & 0xffffff0000000ffcULL); 96 pte = (tmp & 0x000000ff00000000ULL) >> 28; 97 pte |=(tmp & 0x00000000fffff000ULL); 98 pte |= GPTE_VALID | GPTE_COHERENT; 99 100 writel(pte, agp_bridge->gatt_table+j); 101 readl(agp_bridge->gatt_table+j); /* PCI Posting. */ 102 } 103 amd64_tlbflush(mem); 104 return 0; 105} 106 107/* 108 * This hack alters the order element according 109 * to the size of a long. It sucks. I totally disown this, even 110 * though it does appear to work for the most part. 111 */ 112static struct aper_size_info_32 amd64_aperture_sizes[7] = 113{ 114 {32, 8192, 3+(sizeof(long)/8), 0 }, 115 {64, 16384, 4+(sizeof(long)/8), 1<<1 }, 116 {128, 32768, 5+(sizeof(long)/8), 1<<2 }, 117 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, 118 {512, 131072, 7+(sizeof(long)/8), 1<<3 }, 119 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, 120 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} 121}; 122 123 124/* 125 * Get the current Aperture size from the x86-64. 126 * Note, that there may be multiple x86-64's, but we just return 127 * the value from the first one we find. The set_size functions 128 * keep the rest coherent anyway. Or at least should do. 129 */ 130static int amd64_fetch_size(void) 131{ 132 struct pci_dev *dev; 133 int i; 134 u32 temp; 135 struct aper_size_info_32 *values; 136 137 dev = k8_northbridges[0]; 138 if (dev==NULL) 139 return 0; 140 141 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); 142 temp = (temp & 0xe); 143 values = A_SIZE_32(amd64_aperture_sizes); 144 145 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 146 if (temp == values[i].size_value) { 147 agp_bridge->previous_size = 148 agp_bridge->current_size = (void *) (values + i); 149 150 agp_bridge->aperture_size_idx = i; 151 return values[i].size; 152 } 153 } 154 return 0; 155} 156 157/* 158 * In a multiprocessor x86-64 system, this function gets 159 * called once for each CPU. 160 */ 161static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) 162{ 163 u64 aperturebase; 164 u32 tmp; 165 u64 addr, aper_base; 166 167 /* Address to map to */ 168 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); 169 aperturebase = tmp << 25; 170 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 171 172 /* address of the mappings table */ 173 addr = (u64) gatt_table; 174 addr >>= 12; 175 tmp = (u32) addr<<4; 176 tmp &= ~0xf; 177 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); 178 179 /* Enable GART translation for this hammer. */ 180 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); 181 tmp |= GARTEN; 182 tmp &= ~(DISGARTCPU | DISGARTIO); 183 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); 184 185 return aper_base; 186} 187 188 189static struct aper_size_info_32 amd_8151_sizes[7] = 190{ 191 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ 192 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ 193 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ 194 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ 195 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ 196 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ 197 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ 198}; 199 200static int amd_8151_configure(void) 201{ 202 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); 203 int i; 204 205 /* Configure AGP regs in each x86-64 host bridge. */ 206 for (i = 0; i < num_k8_northbridges; i++) { 207 agp_bridge->gart_bus_addr = 208 amd64_configure(k8_northbridges[i], gatt_bus); 209 } 210 k8_flush_garts(); 211 return 0; 212} 213 214 215static void amd64_cleanup(void) 216{ 217 u32 tmp; 218 int i; 219 for (i = 0; i < num_k8_northbridges; i++) { 220 struct pci_dev *dev = k8_northbridges[i]; 221 /* disable gart translation */ 222 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); 223 tmp &= ~AMD64_GARTEN; 224 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); 225 } 226} 227 228 229static struct agp_bridge_driver amd_8151_driver = { 230 .owner = THIS_MODULE, 231 .aperture_sizes = amd_8151_sizes, 232 .size_type = U32_APER_SIZE, 233 .num_aperture_sizes = 7, 234 .configure = amd_8151_configure, 235 .fetch_size = amd64_fetch_size, 236 .cleanup = amd64_cleanup, 237 .tlb_flush = amd64_tlbflush, 238 .mask_memory = agp_generic_mask_memory, 239 .masks = NULL, 240 .agp_enable = agp_generic_enable, 241 .cache_flush = global_cache_flush, 242 .create_gatt_table = agp_generic_create_gatt_table, 243 .free_gatt_table = agp_generic_free_gatt_table, 244 .insert_memory = amd64_insert_memory, 245 .remove_memory = agp_generic_remove_memory, 246 .alloc_by_type = agp_generic_alloc_by_type, 247 .free_by_type = agp_generic_free_by_type, 248 .agp_alloc_page = agp_generic_alloc_page, 249 .agp_destroy_page = agp_generic_destroy_page, 250}; 251 252/* Some basic sanity checks for the aperture. */ 253static int __devinit aperture_valid(u64 aper, u32 size) 254{ 255 u32 pfn, c; 256 if (aper == 0) { 257 printk(KERN_ERR PFX "No aperture\n"); 258 return 0; 259 } 260 if (size < 32*1024*1024) { 261 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); 262 return 0; 263 } 264 if (aper + size > 0xffffffff) { 265 printk(KERN_ERR PFX "Aperture out of bounds\n"); 266 return 0; 267 } 268 pfn = aper >> PAGE_SHIFT; 269 for (c = 0; c < size/PAGE_SIZE; c++) { 270 if (!pfn_valid(pfn + c)) 271 break; 272 if (!PageReserved(pfn_to_page(pfn + c))) { 273 printk(KERN_ERR PFX "Aperture pointing to RAM\n"); 274 return 0; 275 } 276 } 277 278 /* Request the Aperture. This catches cases when someone else 279 already put a mapping in there - happens with some very broken BIOS 280 281 Maybe better to use pci_assign_resource/pci_enable_device instead 282 trusting the bridges? */ 283 if (!aperture_resource && 284 !(aperture_resource = request_mem_region(aper, size, "aperture"))) { 285 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); 286 return 0; 287 } 288 return 1; 289} 290 291/* 292 * W*s centric BIOS sometimes only set up the aperture in the AGP 293 * bridge, not the northbridge. On AMD64 this is handled early 294 * in aperture.c, but when IOMMU is not enabled or we run 295 * on a 32bit kernel this needs to be redone. 296 * Unfortunately it is impossible to fix the aperture here because it's too late 297 * to allocate that much memory. But at least error out cleanly instead of 298 * crashing. 299 */ 300static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, 301 u16 cap) 302{ 303 u32 aper_low, aper_hi; 304 u64 aper, nb_aper; 305 int order = 0; 306 u32 nb_order, nb_base; 307 u16 apsize; 308 309 pci_read_config_dword(nb, 0x90, &nb_order); 310 nb_order = (nb_order >> 1) & 7; 311 pci_read_config_dword(nb, 0x94, &nb_base); 312 nb_aper = nb_base << 25; 313 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { 314 return 0; 315 } 316 317 /* Northbridge seems to contain crap. Try the AGP bridge. */ 318 319 pci_read_config_word(agp, cap+0x14, &apsize); 320 if (apsize == 0xffff) 321 return -1; 322 323 apsize &= 0xfff; 324 /* Some BIOS use weird encodings not in the AGPv3 table. */ 325 if (apsize & 0xff) 326 apsize |= 0xf00; 327 order = 7 - hweight16(apsize); 328 329 pci_read_config_dword(agp, 0x10, &aper_low); 330 pci_read_config_dword(agp, 0x14, &aper_hi); 331 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 332 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); 333 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) 334 return -1; 335 336 pci_write_config_dword(nb, 0x90, order << 1); 337 pci_write_config_dword(nb, 0x94, aper >> 25); 338 339 return 0; 340} 341 342static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 343{ 344 int i; 345 346 if (cache_k8_northbridges() < 0) 347 return -ENODEV; 348 349 i = 0; 350 for (i = 0; i < num_k8_northbridges; i++) { 351 struct pci_dev *dev = k8_northbridges[i]; 352 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 353 printk(KERN_ERR PFX "No usable aperture found.\n"); 354#ifdef __x86_64__ 355 /* should port this to i386 */ 356 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); 357#endif 358 return -1; 359 } 360 } 361 return 0; 362} 363 364/* Handle AMD 8151 quirks */ 365static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) 366{ 367 char *revstring; 368 u8 rev_id; 369 370 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 371 switch (rev_id) { 372 case 0x01: revstring="A0"; break; 373 case 0x02: revstring="A1"; break; 374 case 0x11: revstring="B0"; break; 375 case 0x12: revstring="B1"; break; 376 case 0x13: revstring="B2"; break; 377 case 0x14: revstring="B3"; break; 378 default: revstring="??"; break; 379 } 380 381 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); 382 383 /* 384 * Work around errata. 385 * Chips before B2 stepping incorrectly reporting v3.5 386 */ 387 if (rev_id < 0x13) { 388 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); 389 bridge->major_version = 3; 390 bridge->minor_version = 0; 391 } 392} 393 394 395static const struct aper_size_info_32 uli_sizes[7] = 396{ 397 {256, 65536, 6, 10}, 398 {128, 32768, 5, 9}, 399 {64, 16384, 4, 8}, 400 {32, 8192, 3, 7}, 401 {16, 4096, 2, 6}, 402 {8, 2048, 1, 4}, 403 {4, 1024, 0, 3} 404}; 405static int __devinit uli_agp_init(struct pci_dev *pdev) 406{ 407 u32 httfea,baseaddr,enuscr; 408 struct pci_dev *dev1; 409 int i; 410 unsigned size = amd64_fetch_size(); 411 printk(KERN_INFO "Setting up ULi AGP.\n"); 412 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); 413 if (dev1 == NULL) { 414 printk(KERN_INFO PFX "Detected a ULi chipset, " 415 "but could not fine the secondary device.\n"); 416 return -ENODEV; 417 } 418 419 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) 420 if (uli_sizes[i].size == size) 421 break; 422 423 if (i == ARRAY_SIZE(uli_sizes)) { 424 printk(KERN_INFO PFX "No ULi size found for %d\n", size); 425 return -ENODEV; 426 } 427 428 /* shadow x86-64 registers into ULi registers */ 429 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 430 431 /* if x86-64 aperture base is beyond 4G, exit here */ 432 if ((httfea & 0x7fff) >> (32 - 25)) 433 return -ENODEV; 434 435 httfea = (httfea& 0x7fff) << 25; 436 437 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); 438 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; 439 baseaddr|= httfea; 440 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); 441 442 enuscr= httfea+ (size * 1024 * 1024) - 1; 443 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); 444 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); 445 446 pci_dev_put(dev1); 447 return 0; 448} 449 450 451static const struct aper_size_info_32 nforce3_sizes[5] = 452{ 453 {512, 131072, 7, 0x00000000 }, 454 {256, 65536, 6, 0x00000008 }, 455 {128, 32768, 5, 0x0000000C }, 456 {64, 16384, 4, 0x0000000E }, 457 {32, 8192, 3, 0x0000000F } 458}; 459 460/* Handle shadow device of the Nvidia NForce3 */ 461/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ 462static int nforce3_agp_init(struct pci_dev *pdev) 463{ 464 u32 tmp, apbase, apbar, aplimit; 465 struct pci_dev *dev1; 466 int i; 467 unsigned size = amd64_fetch_size(); 468 469 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); 470 471 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); 472 if (dev1 == NULL) { 473 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " 474 "nForce3 chipset, but could not find " 475 "the secondary device.\n"); 476 return -ENODEV; 477 } 478 479 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) 480 if (nforce3_sizes[i].size == size) 481 break; 482 483 if (i == ARRAY_SIZE(nforce3_sizes)) { 484 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); 485 return -ENODEV; 486 } 487 488 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); 489 tmp &= ~(0xf); 490 tmp |= nforce3_sizes[i].size_value; 491 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 492 493 /* shadow x86-64 registers into NVIDIA registers */ 494 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 495 496 /* if x86-64 aperture base is beyond 4G, exit here */ 497 if ( (apbase & 0x7fff) >> (32 - 25) ) { 498 printk(KERN_INFO PFX "aperture base > 4G\n"); 499 return -ENODEV; 500 } 501 502 apbase = (apbase & 0x7fff) << 25; 503 504 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); 505 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; 506 apbar |= apbase; 507 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); 508 509 aplimit = apbase + (size * 1024 * 1024) - 1; 510 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); 511 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); 512 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); 513 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); 514 515 pci_dev_put(dev1); 516 517 return 0; 518} 519 520static int __devinit agp_amd64_probe(struct pci_dev *pdev, 521 const struct pci_device_id *ent) 522{ 523 struct agp_bridge_data *bridge; 524 u8 cap_ptr; 525 526 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 527 if (!cap_ptr) 528 return -ENODEV; 529 530 /* Could check for AGPv3 here */ 531 532 bridge = agp_alloc_bridge(); 533 if (!bridge) 534 return -ENOMEM; 535 536 if (pdev->vendor == PCI_VENDOR_ID_AMD && 537 pdev->device == PCI_DEVICE_ID_AMD_8151_0) { 538 amd8151_init(pdev, bridge); 539 } else { 540 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); 541 } 542 543 bridge->driver = &amd_8151_driver; 544 bridge->dev = pdev; 545 bridge->capndx = cap_ptr; 546 547 /* Fill in the mode register */ 548 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 549 550 if (cache_nbs(pdev, cap_ptr) == -1) { 551 agp_put_bridge(bridge); 552 return -ENODEV; 553 } 554 555 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { 556 int ret = nforce3_agp_init(pdev); 557 if (ret) { 558 agp_put_bridge(bridge); 559 return ret; 560 } 561 } 562 563 if (pdev->vendor == PCI_VENDOR_ID_AL) { 564 int ret = uli_agp_init(pdev); 565 if (ret) { 566 agp_put_bridge(bridge); 567 return ret; 568 } 569 } 570 571 pci_set_drvdata(pdev, bridge); 572 return agp_add_bridge(bridge); 573} 574 575static void __devexit agp_amd64_remove(struct pci_dev *pdev) 576{ 577 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 578 579 release_mem_region(virt_to_gart(bridge->gatt_table_real), 580 amd64_aperture_sizes[bridge->aperture_size_idx].size); 581 agp_remove_bridge(bridge); 582 agp_put_bridge(bridge); 583} 584 585#ifdef CONFIG_PM 586 587static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) 588{ 589 pci_save_state(pdev); 590 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 591 592 return 0; 593} 594 595static int agp_amd64_resume(struct pci_dev *pdev) 596{ 597 pci_set_power_state(pdev, PCI_D0); 598 pci_restore_state(pdev); 599 600 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) 601 nforce3_agp_init(pdev); 602 603 return amd_8151_configure(); 604} 605 606#endif /* CONFIG_PM */ 607 608static struct pci_device_id agp_amd64_pci_table[] = { 609 { 610 .class = (PCI_CLASS_BRIDGE_HOST << 8), 611 .class_mask = ~0, 612 .vendor = PCI_VENDOR_ID_AMD, 613 .device = PCI_DEVICE_ID_AMD_8151_0, 614 .subvendor = PCI_ANY_ID, 615 .subdevice = PCI_ANY_ID, 616 }, 617 /* ULi M1689 */ 618 { 619 .class = (PCI_CLASS_BRIDGE_HOST << 8), 620 .class_mask = ~0, 621 .vendor = PCI_VENDOR_ID_AL, 622 .device = PCI_DEVICE_ID_AL_M1689, 623 .subvendor = PCI_ANY_ID, 624 .subdevice = PCI_ANY_ID, 625 }, 626 /* VIA K8T800Pro */ 627 { 628 .class = (PCI_CLASS_BRIDGE_HOST << 8), 629 .class_mask = ~0, 630 .vendor = PCI_VENDOR_ID_VIA, 631 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, 632 .subvendor = PCI_ANY_ID, 633 .subdevice = PCI_ANY_ID, 634 }, 635 /* VIA K8T800 */ 636 { 637 .class = (PCI_CLASS_BRIDGE_HOST << 8), 638 .class_mask = ~0, 639 .vendor = PCI_VENDOR_ID_VIA, 640 .device = PCI_DEVICE_ID_VIA_8385_0, 641 .subvendor = PCI_ANY_ID, 642 .subdevice = PCI_ANY_ID, 643 }, 644 /* VIA K8M800 / K8N800 */ 645 { 646 .class = (PCI_CLASS_BRIDGE_HOST << 8), 647 .class_mask = ~0, 648 .vendor = PCI_VENDOR_ID_VIA, 649 .device = PCI_DEVICE_ID_VIA_8380_0, 650 .subvendor = PCI_ANY_ID, 651 .subdevice = PCI_ANY_ID, 652 }, 653 /* VIA K8M890 / K8N890 */ 654 { 655 .class = (PCI_CLASS_BRIDGE_HOST << 8), 656 .class_mask = ~0, 657 .vendor = PCI_VENDOR_ID_VIA, 658 .device = PCI_DEVICE_ID_VIA_VT3336, 659 .subvendor = PCI_ANY_ID, 660 .subdevice = PCI_ANY_ID, 661 }, 662 /* VIA K8T890 */ 663 { 664 .class = (PCI_CLASS_BRIDGE_HOST << 8), 665 .class_mask = ~0, 666 .vendor = PCI_VENDOR_ID_VIA, 667 .device = PCI_DEVICE_ID_VIA_3238_0, 668 .subvendor = PCI_ANY_ID, 669 .subdevice = PCI_ANY_ID, 670 }, 671 /* VIA K8T800/K8M800/K8N800 */ 672 { 673 .class = (PCI_CLASS_BRIDGE_HOST << 8), 674 .class_mask = ~0, 675 .vendor = PCI_VENDOR_ID_VIA, 676 .device = PCI_DEVICE_ID_VIA_838X_1, 677 .subvendor = PCI_ANY_ID, 678 .subdevice = PCI_ANY_ID, 679 }, 680 /* NForce3 */ 681 { 682 .class = (PCI_CLASS_BRIDGE_HOST << 8), 683 .class_mask = ~0, 684 .vendor = PCI_VENDOR_ID_NVIDIA, 685 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, 686 .subvendor = PCI_ANY_ID, 687 .subdevice = PCI_ANY_ID, 688 }, 689 { 690 .class = (PCI_CLASS_BRIDGE_HOST << 8), 691 .class_mask = ~0, 692 .vendor = PCI_VENDOR_ID_NVIDIA, 693 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, 694 .subvendor = PCI_ANY_ID, 695 .subdevice = PCI_ANY_ID, 696 }, 697 /* SIS 755 */ 698 { 699 .class = (PCI_CLASS_BRIDGE_HOST << 8), 700 .class_mask = ~0, 701 .vendor = PCI_VENDOR_ID_SI, 702 .device = PCI_DEVICE_ID_SI_755, 703 .subvendor = PCI_ANY_ID, 704 .subdevice = PCI_ANY_ID, 705 }, 706 /* SIS 760 */ 707 { 708 .class = (PCI_CLASS_BRIDGE_HOST << 8), 709 .class_mask = ~0, 710 .vendor = PCI_VENDOR_ID_SI, 711 .device = PCI_DEVICE_ID_SI_760, 712 .subvendor = PCI_ANY_ID, 713 .subdevice = PCI_ANY_ID, 714 }, 715 /* ALI/ULI M1695 */ 716 { 717 .class = (PCI_CLASS_BRIDGE_HOST << 8), 718 .class_mask = ~0, 719 .vendor = PCI_VENDOR_ID_AL, 720 .device = 0x1695, 721 .subvendor = PCI_ANY_ID, 722 .subdevice = PCI_ANY_ID, 723 }, 724 725 { } 726}; 727 728MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); 729 730static struct pci_driver agp_amd64_pci_driver = { 731 .name = "agpgart-amd64", 732 .id_table = agp_amd64_pci_table, 733 .probe = agp_amd64_probe, 734 .remove = agp_amd64_remove, 735#ifdef CONFIG_PM 736 .suspend = agp_amd64_suspend, 737 .resume = agp_amd64_resume, 738#endif 739}; 740 741 742/* Not static due to IOMMU code calling it early. */ 743int __init agp_amd64_init(void) 744{ 745 int err = 0; 746 747 if (agp_off) 748 return -EINVAL; 749 if (pci_register_driver(&agp_amd64_pci_driver) < 0) { 750 struct pci_dev *dev; 751 if (!agp_try_unsupported && !agp_try_unsupported_boot) { 752 printk(KERN_INFO PFX "No supported AGP bridge found.\n"); 753#ifdef MODULE 754 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); 755#else 756 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 757#endif 758 return -ENODEV; 759 } 760 761 /* First check that we have at least one AMD64 NB */ 762 if (!pci_dev_present(k8_nb_ids)) 763 return -ENODEV; 764 765 /* Look for any AGP bridge */ 766 dev = NULL; 767 err = -ENODEV; 768 for_each_pci_dev(dev) { 769 if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) 770 continue; 771 /* Only one bridge supported right now */ 772 if (agp_amd64_probe(dev, NULL) == 0) { 773 err = 0; 774 break; 775 } 776 } 777 } 778 return err; 779} 780 781static void __exit agp_amd64_cleanup(void) 782{ 783 if (aperture_resource) 784 release_resource(aperture_resource); 785 pci_unregister_driver(&agp_amd64_pci_driver); 786} 787 788/* On AMD64 the PCI driver needs to initialize this driver early 789 for the IOMMU, so it has to be called via a backdoor. */ 790#ifndef CONFIG_IOMMU 791module_init(agp_amd64_init); 792module_exit(agp_amd64_cleanup); 793#endif 794 795MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen"); 796module_param(agp_try_unsupported, bool, 0); 797MODULE_LICENSE("GPL"); 798