amd64-agp.c revision b92e9fac400d4ae5bc7a75c568e9844ec53ea329
1/* 2 * Copyright 2001-2003 SuSE Labs. 3 * Distributed under the GNU public license, v2. 4 * 5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. 6 * It also includes support for the AMD 8151 AGP bridge, 7 * although it doesn't actually do much, as all the real 8 * work is done in the northbridge(s). 9 */ 10 11#include <linux/module.h> 12#include <linux/pci.h> 13#include <linux/init.h> 14#include <linux/agp_backend.h> 15#include <linux/mmzone.h> 16#include <asm/page.h> /* PAGE_SIZE */ 17#include <asm/e820.h> 18#include <asm/k8.h> 19#include "agp.h" 20 21/* PTE bits. */ 22#define GPTE_VALID 1 23#define GPTE_COHERENT 2 24 25/* Aperture control register bits. */ 26#define GARTEN (1<<0) 27#define DISGARTCPU (1<<4) 28#define DISGARTIO (1<<5) 29 30/* GART cache control register bits. */ 31#define INVGART (1<<0) 32#define GARTPTEERR (1<<1) 33 34/* K8 On-cpu GART registers */ 35#define AMD64_GARTAPERTURECTL 0x90 36#define AMD64_GARTAPERTUREBASE 0x94 37#define AMD64_GARTTABLEBASE 0x98 38#define AMD64_GARTCACHECTL 0x9c 39#define AMD64_GARTEN (1<<0) 40 41/* NVIDIA K8 registers */ 42#define NVIDIA_X86_64_0_APBASE 0x10 43#define NVIDIA_X86_64_1_APBASE1 0x50 44#define NVIDIA_X86_64_1_APLIMIT1 0x54 45#define NVIDIA_X86_64_1_APSIZE 0xa8 46#define NVIDIA_X86_64_1_APBASE2 0xd8 47#define NVIDIA_X86_64_1_APLIMIT2 0xdc 48 49/* ULi K8 registers */ 50#define ULI_X86_64_BASE_ADDR 0x10 51#define ULI_X86_64_HTT_FEA_REG 0x50 52#define ULI_X86_64_ENU_SCR_REG 0x54 53 54static struct resource *aperture_resource; 55static int __initdata agp_try_unsupported = 1; 56 57static void amd64_tlbflush(struct agp_memory *temp) 58{ 59 k8_flush_garts(); 60} 61 62static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 63{ 64 int i, j, num_entries; 65 long long tmp; 66 int mask_type; 67 struct agp_bridge_data *bridge = mem->bridge; 68 u32 pte; 69 70 num_entries = agp_num_entries(); 71 72 if (type != mem->type) 73 return -EINVAL; 74 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); 75 if (mask_type != 0) 76 return -EINVAL; 77 78 79 /* Make sure we can fit the range in the gatt table. */ 80 /* FIXME: could wrap */ 81 if (((unsigned long)pg_start + mem->page_count) > num_entries) 82 return -EINVAL; 83 84 j = pg_start; 85 86 /* gatt table should be empty. */ 87 while (j < (pg_start + mem->page_count)) { 88 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 89 return -EBUSY; 90 j++; 91 } 92 93 if (mem->is_flushed == FALSE) { 94 global_cache_flush(); 95 mem->is_flushed = TRUE; 96 } 97 98 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 99 tmp = agp_bridge->driver->mask_memory(agp_bridge, 100 mem->memory[i], mask_type); 101 102 BUG_ON(tmp & 0xffffff0000000ffcULL); 103 pte = (tmp & 0x000000ff00000000ULL) >> 28; 104 pte |=(tmp & 0x00000000fffff000ULL); 105 pte |= GPTE_VALID | GPTE_COHERENT; 106 107 writel(pte, agp_bridge->gatt_table+j); 108 readl(agp_bridge->gatt_table+j); /* PCI Posting. */ 109 } 110 amd64_tlbflush(mem); 111 return 0; 112} 113 114/* 115 * This hack alters the order element according 116 * to the size of a long. It sucks. I totally disown this, even 117 * though it does appear to work for the most part. 118 */ 119static struct aper_size_info_32 amd64_aperture_sizes[7] = 120{ 121 {32, 8192, 3+(sizeof(long)/8), 0 }, 122 {64, 16384, 4+(sizeof(long)/8), 1<<1 }, 123 {128, 32768, 5+(sizeof(long)/8), 1<<2 }, 124 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, 125 {512, 131072, 7+(sizeof(long)/8), 1<<3 }, 126 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, 127 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} 128}; 129 130 131/* 132 * Get the current Aperture size from the x86-64. 133 * Note, that there may be multiple x86-64's, but we just return 134 * the value from the first one we find. The set_size functions 135 * keep the rest coherent anyway. Or at least should do. 136 */ 137static int amd64_fetch_size(void) 138{ 139 struct pci_dev *dev; 140 int i; 141 u32 temp; 142 struct aper_size_info_32 *values; 143 144 dev = k8_northbridges[0]; 145 if (dev==NULL) 146 return 0; 147 148 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); 149 temp = (temp & 0xe); 150 values = A_SIZE_32(amd64_aperture_sizes); 151 152 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 153 if (temp == values[i].size_value) { 154 agp_bridge->previous_size = 155 agp_bridge->current_size = (void *) (values + i); 156 157 agp_bridge->aperture_size_idx = i; 158 return values[i].size; 159 } 160 } 161 return 0; 162} 163 164/* 165 * In a multiprocessor x86-64 system, this function gets 166 * called once for each CPU. 167 */ 168static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) 169{ 170 u64 aperturebase; 171 u32 tmp; 172 u64 addr, aper_base; 173 174 /* Address to map to */ 175 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); 176 aperturebase = tmp << 25; 177 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 178 179 /* address of the mappings table */ 180 addr = (u64) gatt_table; 181 addr >>= 12; 182 tmp = (u32) addr<<4; 183 tmp &= ~0xf; 184 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); 185 186 /* Enable GART translation for this hammer. */ 187 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); 188 tmp |= GARTEN; 189 tmp &= ~(DISGARTCPU | DISGARTIO); 190 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); 191 192 return aper_base; 193} 194 195 196static const struct aper_size_info_32 amd_8151_sizes[7] = 197{ 198 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ 199 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ 200 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ 201 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ 202 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ 203 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ 204 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ 205}; 206 207static int amd_8151_configure(void) 208{ 209 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); 210 int i; 211 212 /* Configure AGP regs in each x86-64 host bridge. */ 213 for (i = 0; i < num_k8_northbridges; i++) { 214 agp_bridge->gart_bus_addr = 215 amd64_configure(k8_northbridges[i], gatt_bus); 216 } 217 k8_flush_garts(); 218 return 0; 219} 220 221 222static void amd64_cleanup(void) 223{ 224 u32 tmp; 225 int i; 226 for (i = 0; i < num_k8_northbridges; i++) { 227 struct pci_dev *dev = k8_northbridges[i]; 228 /* disable gart translation */ 229 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); 230 tmp &= ~AMD64_GARTEN; 231 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); 232 } 233} 234 235 236static const struct agp_bridge_driver amd_8151_driver = { 237 .owner = THIS_MODULE, 238 .aperture_sizes = amd_8151_sizes, 239 .size_type = U32_APER_SIZE, 240 .num_aperture_sizes = 7, 241 .configure = amd_8151_configure, 242 .fetch_size = amd64_fetch_size, 243 .cleanup = amd64_cleanup, 244 .tlb_flush = amd64_tlbflush, 245 .mask_memory = agp_generic_mask_memory, 246 .masks = NULL, 247 .agp_enable = agp_generic_enable, 248 .cache_flush = global_cache_flush, 249 .create_gatt_table = agp_generic_create_gatt_table, 250 .free_gatt_table = agp_generic_free_gatt_table, 251 .insert_memory = amd64_insert_memory, 252 .remove_memory = agp_generic_remove_memory, 253 .alloc_by_type = agp_generic_alloc_by_type, 254 .free_by_type = agp_generic_free_by_type, 255 .agp_alloc_page = agp_generic_alloc_page, 256 .agp_destroy_page = agp_generic_destroy_page, 257 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 258}; 259 260/* Some basic sanity checks for the aperture. */ 261static int __devinit aperture_valid(u64 aper, u32 size) 262{ 263 if (aper == 0) { 264 printk(KERN_ERR PFX "No aperture\n"); 265 return 0; 266 } 267 if (size < 32*1024*1024) { 268 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); 269 return 0; 270 } 271 if (aper + size > 0xffffffff) { 272 printk(KERN_ERR PFX "Aperture out of bounds\n"); 273 return 0; 274 } 275 if (e820_any_mapped(aper, aper + size, E820_RAM)) { 276 printk(KERN_ERR PFX "Aperture pointing to RAM\n"); 277 return 0; 278 } 279 280 /* Request the Aperture. This catches cases when someone else 281 already put a mapping in there - happens with some very broken BIOS 282 283 Maybe better to use pci_assign_resource/pci_enable_device instead 284 trusting the bridges? */ 285 if (!aperture_resource && 286 !(aperture_resource = request_mem_region(aper, size, "aperture"))) { 287 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); 288 return 0; 289 } 290 return 1; 291} 292 293/* 294 * W*s centric BIOS sometimes only set up the aperture in the AGP 295 * bridge, not the northbridge. On AMD64 this is handled early 296 * in aperture.c, but when IOMMU is not enabled or we run 297 * on a 32bit kernel this needs to be redone. 298 * Unfortunately it is impossible to fix the aperture here because it's too late 299 * to allocate that much memory. But at least error out cleanly instead of 300 * crashing. 301 */ 302static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, 303 u16 cap) 304{ 305 u32 aper_low, aper_hi; 306 u64 aper, nb_aper; 307 int order = 0; 308 u32 nb_order, nb_base; 309 u16 apsize; 310 311 pci_read_config_dword(nb, 0x90, &nb_order); 312 nb_order = (nb_order >> 1) & 7; 313 pci_read_config_dword(nb, 0x94, &nb_base); 314 nb_aper = nb_base << 25; 315 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { 316 return 0; 317 } 318 319 /* Northbridge seems to contain crap. Try the AGP bridge. */ 320 321 pci_read_config_word(agp, cap+0x14, &apsize); 322 if (apsize == 0xffff) 323 return -1; 324 325 apsize &= 0xfff; 326 /* Some BIOS use weird encodings not in the AGPv3 table. */ 327 if (apsize & 0xff) 328 apsize |= 0xf00; 329 order = 7 - hweight16(apsize); 330 331 pci_read_config_dword(agp, 0x10, &aper_low); 332 pci_read_config_dword(agp, 0x14, &aper_hi); 333 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 334 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); 335 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) 336 return -1; 337 338 pci_write_config_dword(nb, 0x90, order << 1); 339 pci_write_config_dword(nb, 0x94, aper >> 25); 340 341 return 0; 342} 343 344static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 345{ 346 int i; 347 348 if (cache_k8_northbridges() < 0) 349 return -ENODEV; 350 351 i = 0; 352 for (i = 0; i < num_k8_northbridges; i++) { 353 struct pci_dev *dev = k8_northbridges[i]; 354 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 355 printk(KERN_ERR PFX "No usable aperture found.\n"); 356#ifdef __x86_64__ 357 /* should port this to i386 */ 358 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); 359#endif 360 return -1; 361 } 362 } 363 return 0; 364} 365 366/* Handle AMD 8151 quirks */ 367static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) 368{ 369 char *revstring; 370 u8 rev_id; 371 372 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 373 switch (rev_id) { 374 case 0x01: revstring="A0"; break; 375 case 0x02: revstring="A1"; break; 376 case 0x11: revstring="B0"; break; 377 case 0x12: revstring="B1"; break; 378 case 0x13: revstring="B2"; break; 379 case 0x14: revstring="B3"; break; 380 default: revstring="??"; break; 381 } 382 383 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); 384 385 /* 386 * Work around errata. 387 * Chips before B2 stepping incorrectly reporting v3.5 388 */ 389 if (rev_id < 0x13) { 390 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); 391 bridge->major_version = 3; 392 bridge->minor_version = 0; 393 } 394} 395 396 397static const struct aper_size_info_32 uli_sizes[7] = 398{ 399 {256, 65536, 6, 10}, 400 {128, 32768, 5, 9}, 401 {64, 16384, 4, 8}, 402 {32, 8192, 3, 7}, 403 {16, 4096, 2, 6}, 404 {8, 2048, 1, 4}, 405 {4, 1024, 0, 3} 406}; 407static int __devinit uli_agp_init(struct pci_dev *pdev) 408{ 409 u32 httfea,baseaddr,enuscr; 410 struct pci_dev *dev1; 411 int i; 412 unsigned size = amd64_fetch_size(); 413 printk(KERN_INFO "Setting up ULi AGP.\n"); 414 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); 415 if (dev1 == NULL) { 416 printk(KERN_INFO PFX "Detected a ULi chipset, " 417 "but could not fine the secondary device.\n"); 418 return -ENODEV; 419 } 420 421 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) 422 if (uli_sizes[i].size == size) 423 break; 424 425 if (i == ARRAY_SIZE(uli_sizes)) { 426 printk(KERN_INFO PFX "No ULi size found for %d\n", size); 427 return -ENODEV; 428 } 429 430 /* shadow x86-64 registers into ULi registers */ 431 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 432 433 /* if x86-64 aperture base is beyond 4G, exit here */ 434 if ((httfea & 0x7fff) >> (32 - 25)) 435 return -ENODEV; 436 437 httfea = (httfea& 0x7fff) << 25; 438 439 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); 440 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; 441 baseaddr|= httfea; 442 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); 443 444 enuscr= httfea+ (size * 1024 * 1024) - 1; 445 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); 446 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); 447 448 pci_dev_put(dev1); 449 return 0; 450} 451 452 453static const struct aper_size_info_32 nforce3_sizes[5] = 454{ 455 {512, 131072, 7, 0x00000000 }, 456 {256, 65536, 6, 0x00000008 }, 457 {128, 32768, 5, 0x0000000C }, 458 {64, 16384, 4, 0x0000000E }, 459 {32, 8192, 3, 0x0000000F } 460}; 461 462/* Handle shadow device of the Nvidia NForce3 */ 463/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ 464static int nforce3_agp_init(struct pci_dev *pdev) 465{ 466 u32 tmp, apbase, apbar, aplimit; 467 struct pci_dev *dev1; 468 int i; 469 unsigned size = amd64_fetch_size(); 470 471 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); 472 473 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); 474 if (dev1 == NULL) { 475 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " 476 "nForce3 chipset, but could not find " 477 "the secondary device.\n"); 478 return -ENODEV; 479 } 480 481 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) 482 if (nforce3_sizes[i].size == size) 483 break; 484 485 if (i == ARRAY_SIZE(nforce3_sizes)) { 486 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); 487 return -ENODEV; 488 } 489 490 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); 491 tmp &= ~(0xf); 492 tmp |= nforce3_sizes[i].size_value; 493 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 494 495 /* shadow x86-64 registers into NVIDIA registers */ 496 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 497 498 /* if x86-64 aperture base is beyond 4G, exit here */ 499 if ( (apbase & 0x7fff) >> (32 - 25) ) { 500 printk(KERN_INFO PFX "aperture base > 4G\n"); 501 return -ENODEV; 502 } 503 504 apbase = (apbase & 0x7fff) << 25; 505 506 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); 507 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; 508 apbar |= apbase; 509 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); 510 511 aplimit = apbase + (size * 1024 * 1024) - 1; 512 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); 513 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); 514 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); 515 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); 516 517 pci_dev_put(dev1); 518 519 return 0; 520} 521 522static int __devinit agp_amd64_probe(struct pci_dev *pdev, 523 const struct pci_device_id *ent) 524{ 525 struct agp_bridge_data *bridge; 526 u8 cap_ptr; 527 528 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 529 if (!cap_ptr) 530 return -ENODEV; 531 532 /* Could check for AGPv3 here */ 533 534 bridge = agp_alloc_bridge(); 535 if (!bridge) 536 return -ENOMEM; 537 538 if (pdev->vendor == PCI_VENDOR_ID_AMD && 539 pdev->device == PCI_DEVICE_ID_AMD_8151_0) { 540 amd8151_init(pdev, bridge); 541 } else { 542 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); 543 } 544 545 bridge->driver = &amd_8151_driver; 546 bridge->dev = pdev; 547 bridge->capndx = cap_ptr; 548 549 /* Fill in the mode register */ 550 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 551 552 if (cache_nbs(pdev, cap_ptr) == -1) { 553 agp_put_bridge(bridge); 554 return -ENODEV; 555 } 556 557 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { 558 int ret = nforce3_agp_init(pdev); 559 if (ret) { 560 agp_put_bridge(bridge); 561 return ret; 562 } 563 } 564 565 if (pdev->vendor == PCI_VENDOR_ID_AL) { 566 int ret = uli_agp_init(pdev); 567 if (ret) { 568 agp_put_bridge(bridge); 569 return ret; 570 } 571 } 572 573 pci_set_drvdata(pdev, bridge); 574 return agp_add_bridge(bridge); 575} 576 577static void __devexit agp_amd64_remove(struct pci_dev *pdev) 578{ 579 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 580 581 release_mem_region(virt_to_gart(bridge->gatt_table_real), 582 amd64_aperture_sizes[bridge->aperture_size_idx].size); 583 agp_remove_bridge(bridge); 584 agp_put_bridge(bridge); 585} 586 587#ifdef CONFIG_PM 588 589static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) 590{ 591 pci_save_state(pdev); 592 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 593 594 return 0; 595} 596 597static int agp_amd64_resume(struct pci_dev *pdev) 598{ 599 pci_set_power_state(pdev, PCI_D0); 600 pci_restore_state(pdev); 601 602 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) 603 nforce3_agp_init(pdev); 604 605 return amd_8151_configure(); 606} 607 608#endif /* CONFIG_PM */ 609 610static struct pci_device_id agp_amd64_pci_table[] = { 611 { 612 .class = (PCI_CLASS_BRIDGE_HOST << 8), 613 .class_mask = ~0, 614 .vendor = PCI_VENDOR_ID_AMD, 615 .device = PCI_DEVICE_ID_AMD_8151_0, 616 .subvendor = PCI_ANY_ID, 617 .subdevice = PCI_ANY_ID, 618 }, 619 /* ULi M1689 */ 620 { 621 .class = (PCI_CLASS_BRIDGE_HOST << 8), 622 .class_mask = ~0, 623 .vendor = PCI_VENDOR_ID_AL, 624 .device = PCI_DEVICE_ID_AL_M1689, 625 .subvendor = PCI_ANY_ID, 626 .subdevice = PCI_ANY_ID, 627 }, 628 /* VIA K8T800Pro */ 629 { 630 .class = (PCI_CLASS_BRIDGE_HOST << 8), 631 .class_mask = ~0, 632 .vendor = PCI_VENDOR_ID_VIA, 633 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, 634 .subvendor = PCI_ANY_ID, 635 .subdevice = PCI_ANY_ID, 636 }, 637 /* VIA K8T800 */ 638 { 639 .class = (PCI_CLASS_BRIDGE_HOST << 8), 640 .class_mask = ~0, 641 .vendor = PCI_VENDOR_ID_VIA, 642 .device = PCI_DEVICE_ID_VIA_8385_0, 643 .subvendor = PCI_ANY_ID, 644 .subdevice = PCI_ANY_ID, 645 }, 646 /* VIA K8M800 / K8N800 */ 647 { 648 .class = (PCI_CLASS_BRIDGE_HOST << 8), 649 .class_mask = ~0, 650 .vendor = PCI_VENDOR_ID_VIA, 651 .device = PCI_DEVICE_ID_VIA_8380_0, 652 .subvendor = PCI_ANY_ID, 653 .subdevice = PCI_ANY_ID, 654 }, 655 /* VIA K8M890 / K8N890 */ 656 { 657 .class = (PCI_CLASS_BRIDGE_HOST << 8), 658 .class_mask = ~0, 659 .vendor = PCI_VENDOR_ID_VIA, 660 .device = PCI_DEVICE_ID_VIA_VT3336, 661 .subvendor = PCI_ANY_ID, 662 .subdevice = PCI_ANY_ID, 663 }, 664 /* VIA K8T890 */ 665 { 666 .class = (PCI_CLASS_BRIDGE_HOST << 8), 667 .class_mask = ~0, 668 .vendor = PCI_VENDOR_ID_VIA, 669 .device = PCI_DEVICE_ID_VIA_3238_0, 670 .subvendor = PCI_ANY_ID, 671 .subdevice = PCI_ANY_ID, 672 }, 673 /* VIA K8T800/K8M800/K8N800 */ 674 { 675 .class = (PCI_CLASS_BRIDGE_HOST << 8), 676 .class_mask = ~0, 677 .vendor = PCI_VENDOR_ID_VIA, 678 .device = PCI_DEVICE_ID_VIA_838X_1, 679 .subvendor = PCI_ANY_ID, 680 .subdevice = PCI_ANY_ID, 681 }, 682 /* NForce3 */ 683 { 684 .class = (PCI_CLASS_BRIDGE_HOST << 8), 685 .class_mask = ~0, 686 .vendor = PCI_VENDOR_ID_NVIDIA, 687 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, 688 .subvendor = PCI_ANY_ID, 689 .subdevice = PCI_ANY_ID, 690 }, 691 { 692 .class = (PCI_CLASS_BRIDGE_HOST << 8), 693 .class_mask = ~0, 694 .vendor = PCI_VENDOR_ID_NVIDIA, 695 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, 696 .subvendor = PCI_ANY_ID, 697 .subdevice = PCI_ANY_ID, 698 }, 699 /* SIS 755 */ 700 { 701 .class = (PCI_CLASS_BRIDGE_HOST << 8), 702 .class_mask = ~0, 703 .vendor = PCI_VENDOR_ID_SI, 704 .device = PCI_DEVICE_ID_SI_755, 705 .subvendor = PCI_ANY_ID, 706 .subdevice = PCI_ANY_ID, 707 }, 708 /* SIS 760 */ 709 { 710 .class = (PCI_CLASS_BRIDGE_HOST << 8), 711 .class_mask = ~0, 712 .vendor = PCI_VENDOR_ID_SI, 713 .device = PCI_DEVICE_ID_SI_760, 714 .subvendor = PCI_ANY_ID, 715 .subdevice = PCI_ANY_ID, 716 }, 717 /* ALI/ULI M1695 */ 718 { 719 .class = (PCI_CLASS_BRIDGE_HOST << 8), 720 .class_mask = ~0, 721 .vendor = PCI_VENDOR_ID_AL, 722 .device = 0x1695, 723 .subvendor = PCI_ANY_ID, 724 .subdevice = PCI_ANY_ID, 725 }, 726 727 { } 728}; 729 730MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); 731 732static struct pci_driver agp_amd64_pci_driver = { 733 .name = "agpgart-amd64", 734 .id_table = agp_amd64_pci_table, 735 .probe = agp_amd64_probe, 736 .remove = agp_amd64_remove, 737#ifdef CONFIG_PM 738 .suspend = agp_amd64_suspend, 739 .resume = agp_amd64_resume, 740#endif 741}; 742 743 744/* Not static due to IOMMU code calling it early. */ 745int __init agp_amd64_init(void) 746{ 747 int err = 0; 748 749 if (agp_off) 750 return -EINVAL; 751 if (pci_register_driver(&agp_amd64_pci_driver) < 0) { 752 struct pci_dev *dev; 753 if (!agp_try_unsupported && !agp_try_unsupported_boot) { 754 printk(KERN_INFO PFX "No supported AGP bridge found.\n"); 755#ifdef MODULE 756 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); 757#else 758 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 759#endif 760 return -ENODEV; 761 } 762 763 /* First check that we have at least one AMD64 NB */ 764 if (!pci_dev_present(k8_nb_ids)) 765 return -ENODEV; 766 767 /* Look for any AGP bridge */ 768 dev = NULL; 769 err = -ENODEV; 770 for_each_pci_dev(dev) { 771 if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) 772 continue; 773 /* Only one bridge supported right now */ 774 if (agp_amd64_probe(dev, NULL) == 0) { 775 err = 0; 776 break; 777 } 778 } 779 } 780 return err; 781} 782 783static void __exit agp_amd64_cleanup(void) 784{ 785 if (aperture_resource) 786 release_resource(aperture_resource); 787 pci_unregister_driver(&agp_amd64_pci_driver); 788} 789 790/* On AMD64 the PCI driver needs to initialize this driver early 791 for the IOMMU, so it has to be called via a backdoor. */ 792#ifndef CONFIG_IOMMU 793module_init(agp_amd64_init); 794module_exit(agp_amd64_cleanup); 795#endif 796 797MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen"); 798module_param(agp_try_unsupported, bool, 0); 799MODULE_LICENSE("GPL"); 800