intel-agp.c revision 1089e3009572e07a1fe12c3408828f27c96453be
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include "agp.h" 12 13/* 14 * If we have Intel graphics, we're not going to have anything other than 15 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 16 * on the Intel IOMMU support (CONFIG_DMAR). 17 * Only newer chipsets need to bother with this, of course. 18 */ 19#ifdef CONFIG_DMAR 20#define USE_PCI_DMA_API 1 21#endif 22 23#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 24#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 25#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 26#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 27#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 28#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 29#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 30#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 31#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 32#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 33#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 34#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 35#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 36#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 37#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 38#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 39#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 40#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 41#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 42#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 43#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 44#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 45#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 46#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 47#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 48#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 49#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 50#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 51#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 52#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 53#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 54#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 55#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 56#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 57#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 58#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 59#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 60#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 61#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 62#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 63#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 64#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 65#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a 66#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 67#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 68#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 69 70/* cover 915 and 945 variants */ 71#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 77 78#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 84 85#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ 88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 90 91#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 93 94#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ 95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ 100 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ 101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ 102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ 103 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ 104 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) 105 106extern int agp_memory_reserved; 107 108 109/* Intel 815 register */ 110#define INTEL_815_APCONT 0x51 111#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 112 113/* Intel i820 registers */ 114#define INTEL_I820_RDCR 0x51 115#define INTEL_I820_ERRSTS 0xc8 116 117/* Intel i840 registers */ 118#define INTEL_I840_MCHCFG 0x50 119#define INTEL_I840_ERRSTS 0xc8 120 121/* Intel i850 registers */ 122#define INTEL_I850_MCHCFG 0x50 123#define INTEL_I850_ERRSTS 0xc8 124 125/* intel 915G registers */ 126#define I915_GMADDR 0x18 127#define I915_MMADDR 0x10 128#define I915_PTEADDR 0x1C 129#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 130#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 131#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 132#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 133#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 134#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 135#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 136#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 137 138#define I915_IFPADDR 0x60 139 140/* Intel 965G registers */ 141#define I965_MSAC 0x62 142#define I965_IFPADDR 0x70 143 144/* Intel 7505 registers */ 145#define INTEL_I7505_APSIZE 0x74 146#define INTEL_I7505_NCAPID 0x60 147#define INTEL_I7505_NISTAT 0x6c 148#define INTEL_I7505_ATTBASE 0x78 149#define INTEL_I7505_ERRSTS 0x42 150#define INTEL_I7505_AGPCTRL 0x70 151#define INTEL_I7505_MCHCFG 0x50 152 153static const struct aper_size_info_fixed intel_i810_sizes[] = 154{ 155 {64, 16384, 4}, 156 /* The 32M mode still requires a 64k gatt */ 157 {32, 8192, 4} 158}; 159 160#define AGP_DCACHE_MEMORY 1 161#define AGP_PHYS_MEMORY 2 162#define INTEL_AGP_CACHED_MEMORY 3 163 164static struct gatt_mask intel_i810_masks[] = 165{ 166 {.mask = I810_PTE_VALID, .type = 0}, 167 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 168 {.mask = I810_PTE_VALID, .type = 0}, 169 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 170 .type = INTEL_AGP_CACHED_MEMORY} 171}; 172 173static struct _intel_private { 174 struct pci_dev *pcidev; /* device one */ 175 u8 __iomem *registers; 176 u32 __iomem *gtt; /* I915G */ 177 int num_dcache_entries; 178 /* gtt_entries is the number of gtt entries that are already mapped 179 * to stolen memory. Stolen memory is larger than the memory mapped 180 * through gtt_entries, as it includes some reserved space for the BIOS 181 * popup and for the GTT. 182 */ 183 int gtt_entries; /* i830+ */ 184 int gtt_total_size; 185 union { 186 void __iomem *i9xx_flush_page; 187 void *i8xx_flush_page; 188 }; 189 struct page *i8xx_page; 190 struct resource ifp_resource; 191 int resource_valid; 192} intel_private; 193 194#ifdef USE_PCI_DMA_API 195static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 196{ 197 *ret = pci_map_page(intel_private.pcidev, page, 0, 198 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 199 if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 200 return -EINVAL; 201 return 0; 202} 203 204static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 205{ 206 pci_unmap_page(intel_private.pcidev, dma, 207 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 208} 209 210static void intel_agp_free_sglist(struct agp_memory *mem) 211{ 212 struct sg_table st; 213 214 st.sgl = mem->sg_list; 215 st.orig_nents = st.nents = mem->page_count; 216 217 sg_free_table(&st); 218 219 mem->sg_list = NULL; 220 mem->num_sg = 0; 221} 222 223static int intel_agp_map_memory(struct agp_memory *mem) 224{ 225 struct sg_table st; 226 struct scatterlist *sg; 227 int i; 228 229 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 230 231 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 232 return -ENOMEM; 233 234 mem->sg_list = sg = st.sgl; 235 236 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 237 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 238 239 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 240 mem->page_count, PCI_DMA_BIDIRECTIONAL); 241 if (unlikely(!mem->num_sg)) { 242 intel_agp_free_sglist(mem); 243 return -ENOMEM; 244 } 245 return 0; 246} 247 248static void intel_agp_unmap_memory(struct agp_memory *mem) 249{ 250 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 251 252 pci_unmap_sg(intel_private.pcidev, mem->sg_list, 253 mem->page_count, PCI_DMA_BIDIRECTIONAL); 254 intel_agp_free_sglist(mem); 255} 256 257static void intel_agp_insert_sg_entries(struct agp_memory *mem, 258 off_t pg_start, int mask_type) 259{ 260 struct scatterlist *sg; 261 int i, j; 262 263 j = pg_start; 264 265 WARN_ON(!mem->num_sg); 266 267 if (mem->num_sg == mem->page_count) { 268 for_each_sg(mem->sg_list, sg, mem->page_count, i) { 269 writel(agp_bridge->driver->mask_memory(agp_bridge, 270 sg_dma_address(sg), mask_type), 271 intel_private.gtt+j); 272 j++; 273 } 274 } else { 275 /* sg may merge pages, but we have to seperate 276 * per-page addr for GTT */ 277 unsigned int len, m; 278 279 for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 280 len = sg_dma_len(sg) / PAGE_SIZE; 281 for (m = 0; m < len; m++) { 282 writel(agp_bridge->driver->mask_memory(agp_bridge, 283 sg_dma_address(sg) + m * PAGE_SIZE, 284 mask_type), 285 intel_private.gtt+j); 286 j++; 287 } 288 } 289 } 290 readl(intel_private.gtt+j-1); 291} 292 293#else 294 295static void intel_agp_insert_sg_entries(struct agp_memory *mem, 296 off_t pg_start, int mask_type) 297{ 298 int i, j; 299 300 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 301 writel(agp_bridge->driver->mask_memory(agp_bridge, 302 page_to_phys(mem->pages[i]), mask_type), 303 intel_private.gtt+j); 304 } 305 306 readl(intel_private.gtt+j-1); 307} 308 309#endif 310 311static int intel_i810_fetch_size(void) 312{ 313 u32 smram_miscc; 314 struct aper_size_info_fixed *values; 315 316 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 317 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 318 319 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 320 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 321 return 0; 322 } 323 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 324 agp_bridge->previous_size = 325 agp_bridge->current_size = (void *) (values + 1); 326 agp_bridge->aperture_size_idx = 1; 327 return values[1].size; 328 } else { 329 agp_bridge->previous_size = 330 agp_bridge->current_size = (void *) (values); 331 agp_bridge->aperture_size_idx = 0; 332 return values[0].size; 333 } 334 335 return 0; 336} 337 338static int intel_i810_configure(void) 339{ 340 struct aper_size_info_fixed *current_size; 341 u32 temp; 342 int i; 343 344 current_size = A_SIZE_FIX(agp_bridge->current_size); 345 346 if (!intel_private.registers) { 347 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 348 temp &= 0xfff80000; 349 350 intel_private.registers = ioremap(temp, 128 * 4096); 351 if (!intel_private.registers) { 352 dev_err(&intel_private.pcidev->dev, 353 "can't remap memory\n"); 354 return -ENOMEM; 355 } 356 } 357 358 if ((readl(intel_private.registers+I810_DRAM_CTL) 359 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 360 /* This will need to be dynamically assigned */ 361 dev_info(&intel_private.pcidev->dev, 362 "detected 4MB dedicated video ram\n"); 363 intel_private.num_dcache_entries = 1024; 364 } 365 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 366 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 367 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 368 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 369 370 if (agp_bridge->driver->needs_scratch_page) { 371 for (i = 0; i < current_size->num_entries; i++) { 372 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 373 } 374 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 375 } 376 global_cache_flush(); 377 return 0; 378} 379 380static void intel_i810_cleanup(void) 381{ 382 writel(0, intel_private.registers+I810_PGETBL_CTL); 383 readl(intel_private.registers); /* PCI Posting. */ 384 iounmap(intel_private.registers); 385} 386 387static void intel_i810_tlbflush(struct agp_memory *mem) 388{ 389 return; 390} 391 392static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 393{ 394 return; 395} 396 397/* Exists to support ARGB cursors */ 398static struct page *i8xx_alloc_pages(void) 399{ 400 struct page *page; 401 402 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 403 if (page == NULL) 404 return NULL; 405 406 if (set_pages_uc(page, 4) < 0) { 407 set_pages_wb(page, 4); 408 __free_pages(page, 2); 409 return NULL; 410 } 411 get_page(page); 412 atomic_inc(&agp_bridge->current_memory_agp); 413 return page; 414} 415 416static void i8xx_destroy_pages(struct page *page) 417{ 418 if (page == NULL) 419 return; 420 421 set_pages_wb(page, 4); 422 put_page(page); 423 __free_pages(page, 2); 424 atomic_dec(&agp_bridge->current_memory_agp); 425} 426 427static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 428 int type) 429{ 430 if (type < AGP_USER_TYPES) 431 return type; 432 else if (type == AGP_USER_CACHED_MEMORY) 433 return INTEL_AGP_CACHED_MEMORY; 434 else 435 return 0; 436} 437 438static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 439 int type) 440{ 441 int i, j, num_entries; 442 void *temp; 443 int ret = -EINVAL; 444 int mask_type; 445 446 if (mem->page_count == 0) 447 goto out; 448 449 temp = agp_bridge->current_size; 450 num_entries = A_SIZE_FIX(temp)->num_entries; 451 452 if ((pg_start + mem->page_count) > num_entries) 453 goto out_err; 454 455 456 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 457 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 458 ret = -EBUSY; 459 goto out_err; 460 } 461 } 462 463 if (type != mem->type) 464 goto out_err; 465 466 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 467 468 switch (mask_type) { 469 case AGP_DCACHE_MEMORY: 470 if (!mem->is_flushed) 471 global_cache_flush(); 472 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 473 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 474 intel_private.registers+I810_PTE_BASE+(i*4)); 475 } 476 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 477 break; 478 case AGP_PHYS_MEMORY: 479 case AGP_NORMAL_MEMORY: 480 if (!mem->is_flushed) 481 global_cache_flush(); 482 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 483 writel(agp_bridge->driver->mask_memory(agp_bridge, 484 page_to_phys(mem->pages[i]), mask_type), 485 intel_private.registers+I810_PTE_BASE+(j*4)); 486 } 487 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 488 break; 489 default: 490 goto out_err; 491 } 492 493 agp_bridge->driver->tlb_flush(mem); 494out: 495 ret = 0; 496out_err: 497 mem->is_flushed = true; 498 return ret; 499} 500 501static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 502 int type) 503{ 504 int i; 505 506 if (mem->page_count == 0) 507 return 0; 508 509 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 510 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 511 } 512 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 513 514 agp_bridge->driver->tlb_flush(mem); 515 return 0; 516} 517 518/* 519 * The i810/i830 requires a physical address to program its mouse 520 * pointer into hardware. 521 * However the Xserver still writes to it through the agp aperture. 522 */ 523static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 524{ 525 struct agp_memory *new; 526 struct page *page; 527 528 switch (pg_count) { 529 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 530 break; 531 case 4: 532 /* kludge to get 4 physical pages for ARGB cursor */ 533 page = i8xx_alloc_pages(); 534 break; 535 default: 536 return NULL; 537 } 538 539 if (page == NULL) 540 return NULL; 541 542 new = agp_create_memory(pg_count); 543 if (new == NULL) 544 return NULL; 545 546 new->pages[0] = page; 547 if (pg_count == 4) { 548 /* kludge to get 4 physical pages for ARGB cursor */ 549 new->pages[1] = new->pages[0] + 1; 550 new->pages[2] = new->pages[1] + 1; 551 new->pages[3] = new->pages[2] + 1; 552 } 553 new->page_count = pg_count; 554 new->num_scratch_pages = pg_count; 555 new->type = AGP_PHYS_MEMORY; 556 new->physical = page_to_phys(new->pages[0]); 557 return new; 558} 559 560static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 561{ 562 struct agp_memory *new; 563 564 if (type == AGP_DCACHE_MEMORY) { 565 if (pg_count != intel_private.num_dcache_entries) 566 return NULL; 567 568 new = agp_create_memory(1); 569 if (new == NULL) 570 return NULL; 571 572 new->type = AGP_DCACHE_MEMORY; 573 new->page_count = pg_count; 574 new->num_scratch_pages = 0; 575 agp_free_page_array(new); 576 return new; 577 } 578 if (type == AGP_PHYS_MEMORY) 579 return alloc_agpphysmem_i8xx(pg_count, type); 580 return NULL; 581} 582 583static void intel_i810_free_by_type(struct agp_memory *curr) 584{ 585 agp_free_key(curr->key); 586 if (curr->type == AGP_PHYS_MEMORY) { 587 if (curr->page_count == 4) 588 i8xx_destroy_pages(curr->pages[0]); 589 else { 590 agp_bridge->driver->agp_destroy_page(curr->pages[0], 591 AGP_PAGE_DESTROY_UNMAP); 592 agp_bridge->driver->agp_destroy_page(curr->pages[0], 593 AGP_PAGE_DESTROY_FREE); 594 } 595 agp_free_page_array(curr); 596 } 597 kfree(curr); 598} 599 600static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 601 dma_addr_t addr, int type) 602{ 603 /* Type checking must be done elsewhere */ 604 return addr | bridge->driver->masks[type].mask; 605} 606 607static struct aper_size_info_fixed intel_i830_sizes[] = 608{ 609 {128, 32768, 5}, 610 /* The 64M mode still requires a 128k gatt */ 611 {64, 16384, 5}, 612 {256, 65536, 6}, 613 {512, 131072, 7}, 614}; 615 616static void intel_i830_init_gtt_entries(void) 617{ 618 u16 gmch_ctrl; 619 int gtt_entries; 620 u8 rdct; 621 int local = 0; 622 static const int ddt[4] = { 0, 16, 32, 64 }; 623 int size; /* reserved space (in kb) at the top of stolen memory */ 624 625 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 626 627 if (IS_I965) { 628 u32 pgetbl_ctl; 629 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 630 631 /* The 965 has a field telling us the size of the GTT, 632 * which may be larger than what is necessary to map the 633 * aperture. 634 */ 635 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 636 case I965_PGETBL_SIZE_128KB: 637 size = 128; 638 break; 639 case I965_PGETBL_SIZE_256KB: 640 size = 256; 641 break; 642 case I965_PGETBL_SIZE_512KB: 643 size = 512; 644 break; 645 case I965_PGETBL_SIZE_1MB: 646 size = 1024; 647 break; 648 case I965_PGETBL_SIZE_2MB: 649 size = 2048; 650 break; 651 case I965_PGETBL_SIZE_1_5MB: 652 size = 1024 + 512; 653 break; 654 default: 655 dev_info(&intel_private.pcidev->dev, 656 "unknown page table size, assuming 512KB\n"); 657 size = 512; 658 } 659 size += 4; /* add in BIOS popup space */ 660 } else if (IS_G33 && !IS_PINEVIEW) { 661 /* G33's GTT size defined in gmch_ctrl */ 662 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 663 case G33_PGETBL_SIZE_1M: 664 size = 1024; 665 break; 666 case G33_PGETBL_SIZE_2M: 667 size = 2048; 668 break; 669 default: 670 dev_info(&agp_bridge->dev->dev, 671 "unknown page table size 0x%x, assuming 512KB\n", 672 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 673 size = 512; 674 } 675 size += 4; 676 } else if (IS_G4X || IS_PINEVIEW) { 677 /* On 4 series hardware, GTT stolen is separate from graphics 678 * stolen, ignore it in stolen gtt entries counting. However, 679 * 4KB of the stolen memory doesn't get mapped to the GTT. 680 */ 681 size = 4; 682 } else { 683 /* On previous hardware, the GTT size was just what was 684 * required to map the aperture. 685 */ 686 size = agp_bridge->driver->fetch_size() + 4; 687 } 688 689 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 690 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 691 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 692 case I830_GMCH_GMS_STOLEN_512: 693 gtt_entries = KB(512) - KB(size); 694 break; 695 case I830_GMCH_GMS_STOLEN_1024: 696 gtt_entries = MB(1) - KB(size); 697 break; 698 case I830_GMCH_GMS_STOLEN_8192: 699 gtt_entries = MB(8) - KB(size); 700 break; 701 case I830_GMCH_GMS_LOCAL: 702 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 703 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 704 MB(ddt[I830_RDRAM_DDT(rdct)]); 705 local = 1; 706 break; 707 default: 708 gtt_entries = 0; 709 break; 710 } 711 } else if (agp_bridge->dev->device == 712 PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { 713 /* XXX: This is what my A1 silicon has. What's the right 714 * answer? 715 */ 716 gtt_entries = MB(64) - KB(size); 717 } else { 718 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 719 case I855_GMCH_GMS_STOLEN_1M: 720 gtt_entries = MB(1) - KB(size); 721 break; 722 case I855_GMCH_GMS_STOLEN_4M: 723 gtt_entries = MB(4) - KB(size); 724 break; 725 case I855_GMCH_GMS_STOLEN_8M: 726 gtt_entries = MB(8) - KB(size); 727 break; 728 case I855_GMCH_GMS_STOLEN_16M: 729 gtt_entries = MB(16) - KB(size); 730 break; 731 case I855_GMCH_GMS_STOLEN_32M: 732 gtt_entries = MB(32) - KB(size); 733 break; 734 case I915_GMCH_GMS_STOLEN_48M: 735 /* Check it's really I915G */ 736 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 737 gtt_entries = MB(48) - KB(size); 738 else 739 gtt_entries = 0; 740 break; 741 case I915_GMCH_GMS_STOLEN_64M: 742 /* Check it's really I915G */ 743 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 744 gtt_entries = MB(64) - KB(size); 745 else 746 gtt_entries = 0; 747 break; 748 case G33_GMCH_GMS_STOLEN_128M: 749 if (IS_G33 || IS_I965 || IS_G4X) 750 gtt_entries = MB(128) - KB(size); 751 else 752 gtt_entries = 0; 753 break; 754 case G33_GMCH_GMS_STOLEN_256M: 755 if (IS_G33 || IS_I965 || IS_G4X) 756 gtt_entries = MB(256) - KB(size); 757 else 758 gtt_entries = 0; 759 break; 760 case INTEL_GMCH_GMS_STOLEN_96M: 761 if (IS_I965 || IS_G4X) 762 gtt_entries = MB(96) - KB(size); 763 else 764 gtt_entries = 0; 765 break; 766 case INTEL_GMCH_GMS_STOLEN_160M: 767 if (IS_I965 || IS_G4X) 768 gtt_entries = MB(160) - KB(size); 769 else 770 gtt_entries = 0; 771 break; 772 case INTEL_GMCH_GMS_STOLEN_224M: 773 if (IS_I965 || IS_G4X) 774 gtt_entries = MB(224) - KB(size); 775 else 776 gtt_entries = 0; 777 break; 778 case INTEL_GMCH_GMS_STOLEN_352M: 779 if (IS_I965 || IS_G4X) 780 gtt_entries = MB(352) - KB(size); 781 else 782 gtt_entries = 0; 783 break; 784 default: 785 gtt_entries = 0; 786 break; 787 } 788 } 789 if (gtt_entries > 0) { 790 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 791 gtt_entries / KB(1), local ? "local" : "stolen"); 792 gtt_entries /= KB(4); 793 } else { 794 dev_info(&agp_bridge->dev->dev, 795 "no pre-allocated video memory detected\n"); 796 gtt_entries = 0; 797 } 798 799 intel_private.gtt_entries = gtt_entries; 800} 801 802static void intel_i830_fini_flush(void) 803{ 804 kunmap(intel_private.i8xx_page); 805 intel_private.i8xx_flush_page = NULL; 806 unmap_page_from_agp(intel_private.i8xx_page); 807 808 __free_page(intel_private.i8xx_page); 809 intel_private.i8xx_page = NULL; 810} 811 812static void intel_i830_setup_flush(void) 813{ 814 /* return if we've already set the flush mechanism up */ 815 if (intel_private.i8xx_page) 816 return; 817 818 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 819 if (!intel_private.i8xx_page) 820 return; 821 822 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 823 if (!intel_private.i8xx_flush_page) 824 intel_i830_fini_flush(); 825} 826 827static void 828do_wbinvd(void *null) 829{ 830 wbinvd(); 831} 832 833/* The chipset_flush interface needs to get data that has already been 834 * flushed out of the CPU all the way out to main memory, because the GPU 835 * doesn't snoop those buffers. 836 * 837 * The 8xx series doesn't have the same lovely interface for flushing the 838 * chipset write buffers that the later chips do. According to the 865 839 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 840 * that buffer out, we just fill 1KB and clflush it out, on the assumption 841 * that it'll push whatever was in there out. It appears to work. 842 */ 843static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 844{ 845 unsigned int *pg = intel_private.i8xx_flush_page; 846 847 memset(pg, 0, 1024); 848 849 if (cpu_has_clflush) { 850 clflush_cache_range(pg, 1024); 851 } else { 852 if (on_each_cpu(do_wbinvd, NULL, 1) != 0) 853 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 854 } 855} 856 857/* The intel i830 automatically initializes the agp aperture during POST. 858 * Use the memory already set aside for in the GTT. 859 */ 860static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 861{ 862 int page_order; 863 struct aper_size_info_fixed *size; 864 int num_entries; 865 u32 temp; 866 867 size = agp_bridge->current_size; 868 page_order = size->page_order; 869 num_entries = size->num_entries; 870 agp_bridge->gatt_table_real = NULL; 871 872 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 873 temp &= 0xfff80000; 874 875 intel_private.registers = ioremap(temp, 128 * 4096); 876 if (!intel_private.registers) 877 return -ENOMEM; 878 879 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 880 global_cache_flush(); /* FIXME: ?? */ 881 882 /* we have to call this as early as possible after the MMIO base address is known */ 883 intel_i830_init_gtt_entries(); 884 885 agp_bridge->gatt_table = NULL; 886 887 agp_bridge->gatt_bus_addr = temp; 888 889 return 0; 890} 891 892/* Return the gatt table to a sane state. Use the top of stolen 893 * memory for the GTT. 894 */ 895static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 896{ 897 return 0; 898} 899 900static int intel_i830_fetch_size(void) 901{ 902 u16 gmch_ctrl; 903 struct aper_size_info_fixed *values; 904 905 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 906 907 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 908 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 909 /* 855GM/852GM/865G has 128MB aperture size */ 910 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 911 agp_bridge->aperture_size_idx = 0; 912 return values[0].size; 913 } 914 915 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 916 917 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 918 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 919 agp_bridge->aperture_size_idx = 0; 920 return values[0].size; 921 } else { 922 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 923 agp_bridge->aperture_size_idx = 1; 924 return values[1].size; 925 } 926 927 return 0; 928} 929 930static int intel_i830_configure(void) 931{ 932 struct aper_size_info_fixed *current_size; 933 u32 temp; 934 u16 gmch_ctrl; 935 int i; 936 937 current_size = A_SIZE_FIX(agp_bridge->current_size); 938 939 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 940 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 941 942 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 943 gmch_ctrl |= I830_GMCH_ENABLED; 944 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 945 946 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 947 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 948 949 if (agp_bridge->driver->needs_scratch_page) { 950 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 951 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 952 } 953 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 954 } 955 956 global_cache_flush(); 957 958 intel_i830_setup_flush(); 959 return 0; 960} 961 962static void intel_i830_cleanup(void) 963{ 964 iounmap(intel_private.registers); 965} 966 967static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 968 int type) 969{ 970 int i, j, num_entries; 971 void *temp; 972 int ret = -EINVAL; 973 int mask_type; 974 975 if (mem->page_count == 0) 976 goto out; 977 978 temp = agp_bridge->current_size; 979 num_entries = A_SIZE_FIX(temp)->num_entries; 980 981 if (pg_start < intel_private.gtt_entries) { 982 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 983 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 984 pg_start, intel_private.gtt_entries); 985 986 dev_info(&intel_private.pcidev->dev, 987 "trying to insert into local/stolen memory\n"); 988 goto out_err; 989 } 990 991 if ((pg_start + mem->page_count) > num_entries) 992 goto out_err; 993 994 /* The i830 can't check the GTT for entries since its read only, 995 * depend on the caller to make the correct offset decisions. 996 */ 997 998 if (type != mem->type) 999 goto out_err; 1000 1001 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1002 1003 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1004 mask_type != INTEL_AGP_CACHED_MEMORY) 1005 goto out_err; 1006 1007 if (!mem->is_flushed) 1008 global_cache_flush(); 1009 1010 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1011 writel(agp_bridge->driver->mask_memory(agp_bridge, 1012 page_to_phys(mem->pages[i]), mask_type), 1013 intel_private.registers+I810_PTE_BASE+(j*4)); 1014 } 1015 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 1016 agp_bridge->driver->tlb_flush(mem); 1017 1018out: 1019 ret = 0; 1020out_err: 1021 mem->is_flushed = true; 1022 return ret; 1023} 1024 1025static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1026 int type) 1027{ 1028 int i; 1029 1030 if (mem->page_count == 0) 1031 return 0; 1032 1033 if (pg_start < intel_private.gtt_entries) { 1034 dev_info(&intel_private.pcidev->dev, 1035 "trying to disable local/stolen memory\n"); 1036 return -EINVAL; 1037 } 1038 1039 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1040 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 1041 } 1042 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 1043 1044 agp_bridge->driver->tlb_flush(mem); 1045 return 0; 1046} 1047 1048static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 1049{ 1050 if (type == AGP_PHYS_MEMORY) 1051 return alloc_agpphysmem_i8xx(pg_count, type); 1052 /* always return NULL for other allocation types for now */ 1053 return NULL; 1054} 1055 1056static int intel_alloc_chipset_flush_resource(void) 1057{ 1058 int ret; 1059 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1060 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1061 pcibios_align_resource, agp_bridge->dev); 1062 1063 return ret; 1064} 1065 1066static void intel_i915_setup_chipset_flush(void) 1067{ 1068 int ret; 1069 u32 temp; 1070 1071 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 1072 if (!(temp & 0x1)) { 1073 intel_alloc_chipset_flush_resource(); 1074 intel_private.resource_valid = 1; 1075 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1076 } else { 1077 temp &= ~1; 1078 1079 intel_private.resource_valid = 1; 1080 intel_private.ifp_resource.start = temp; 1081 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1082 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1083 /* some BIOSes reserve this area in a pnp some don't */ 1084 if (ret) 1085 intel_private.resource_valid = 0; 1086 } 1087} 1088 1089static void intel_i965_g33_setup_chipset_flush(void) 1090{ 1091 u32 temp_hi, temp_lo; 1092 int ret; 1093 1094 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1095 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1096 1097 if (!(temp_lo & 0x1)) { 1098 1099 intel_alloc_chipset_flush_resource(); 1100 1101 intel_private.resource_valid = 1; 1102 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1103 upper_32_bits(intel_private.ifp_resource.start)); 1104 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1105 } else { 1106 u64 l64; 1107 1108 temp_lo &= ~0x1; 1109 l64 = ((u64)temp_hi << 32) | temp_lo; 1110 1111 intel_private.resource_valid = 1; 1112 intel_private.ifp_resource.start = l64; 1113 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1114 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1115 /* some BIOSes reserve this area in a pnp some don't */ 1116 if (ret) 1117 intel_private.resource_valid = 0; 1118 } 1119} 1120 1121static void intel_i9xx_setup_flush(void) 1122{ 1123 /* return if already configured */ 1124 if (intel_private.ifp_resource.start) 1125 return; 1126 1127 /* setup a resource for this object */ 1128 intel_private.ifp_resource.name = "Intel Flush Page"; 1129 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1130 1131 /* Setup chipset flush for 915 */ 1132 if (IS_I965 || IS_G33 || IS_G4X) { 1133 intel_i965_g33_setup_chipset_flush(); 1134 } else { 1135 intel_i915_setup_chipset_flush(); 1136 } 1137 1138 if (intel_private.ifp_resource.start) { 1139 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1140 if (!intel_private.i9xx_flush_page) 1141 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 1142 } 1143} 1144 1145static int intel_i915_configure(void) 1146{ 1147 struct aper_size_info_fixed *current_size; 1148 u32 temp; 1149 u16 gmch_ctrl; 1150 int i; 1151 1152 current_size = A_SIZE_FIX(agp_bridge->current_size); 1153 1154 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1155 1156 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1157 1158 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1159 gmch_ctrl |= I830_GMCH_ENABLED; 1160 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1161 1162 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1163 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1164 1165 if (agp_bridge->driver->needs_scratch_page) { 1166 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { 1167 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1168 } 1169 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1170 } 1171 1172 global_cache_flush(); 1173 1174 intel_i9xx_setup_flush(); 1175 1176 return 0; 1177} 1178 1179static void intel_i915_cleanup(void) 1180{ 1181 if (intel_private.i9xx_flush_page) 1182 iounmap(intel_private.i9xx_flush_page); 1183 if (intel_private.resource_valid) 1184 release_resource(&intel_private.ifp_resource); 1185 intel_private.ifp_resource.start = 0; 1186 intel_private.resource_valid = 0; 1187 iounmap(intel_private.gtt); 1188 iounmap(intel_private.registers); 1189} 1190 1191static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1192{ 1193 if (intel_private.i9xx_flush_page) 1194 writel(1, intel_private.i9xx_flush_page); 1195} 1196 1197static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1198 int type) 1199{ 1200 int num_entries; 1201 void *temp; 1202 int ret = -EINVAL; 1203 int mask_type; 1204 1205 if (mem->page_count == 0) 1206 goto out; 1207 1208 temp = agp_bridge->current_size; 1209 num_entries = A_SIZE_FIX(temp)->num_entries; 1210 1211 if (pg_start < intel_private.gtt_entries) { 1212 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1213 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1214 pg_start, intel_private.gtt_entries); 1215 1216 dev_info(&intel_private.pcidev->dev, 1217 "trying to insert into local/stolen memory\n"); 1218 goto out_err; 1219 } 1220 1221 if ((pg_start + mem->page_count) > num_entries) 1222 goto out_err; 1223 1224 /* The i915 can't check the GTT for entries since it's read only; 1225 * depend on the caller to make the correct offset decisions. 1226 */ 1227 1228 if (type != mem->type) 1229 goto out_err; 1230 1231 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1232 1233 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1234 mask_type != INTEL_AGP_CACHED_MEMORY) 1235 goto out_err; 1236 1237 if (!mem->is_flushed) 1238 global_cache_flush(); 1239 1240 intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1241 agp_bridge->driver->tlb_flush(mem); 1242 1243 out: 1244 ret = 0; 1245 out_err: 1246 mem->is_flushed = true; 1247 return ret; 1248} 1249 1250static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1251 int type) 1252{ 1253 int i; 1254 1255 if (mem->page_count == 0) 1256 return 0; 1257 1258 if (pg_start < intel_private.gtt_entries) { 1259 dev_info(&intel_private.pcidev->dev, 1260 "trying to disable local/stolen memory\n"); 1261 return -EINVAL; 1262 } 1263 1264 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1265 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1266 1267 readl(intel_private.gtt+i-1); 1268 1269 agp_bridge->driver->tlb_flush(mem); 1270 return 0; 1271} 1272 1273/* Return the aperture size by just checking the resource length. The effect 1274 * described in the spec of the MSAC registers is just changing of the 1275 * resource size. 1276 */ 1277static int intel_i9xx_fetch_size(void) 1278{ 1279 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1280 int aper_size; /* size in megabytes */ 1281 int i; 1282 1283 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1284 1285 for (i = 0; i < num_sizes; i++) { 1286 if (aper_size == intel_i830_sizes[i].size) { 1287 agp_bridge->current_size = intel_i830_sizes + i; 1288 agp_bridge->previous_size = agp_bridge->current_size; 1289 return aper_size; 1290 } 1291 } 1292 1293 return 0; 1294} 1295 1296/* The intel i915 automatically initializes the agp aperture during POST. 1297 * Use the memory already set aside for in the GTT. 1298 */ 1299static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1300{ 1301 int page_order; 1302 struct aper_size_info_fixed *size; 1303 int num_entries; 1304 u32 temp, temp2; 1305 int gtt_map_size = 256 * 1024; 1306 1307 size = agp_bridge->current_size; 1308 page_order = size->page_order; 1309 num_entries = size->num_entries; 1310 agp_bridge->gatt_table_real = NULL; 1311 1312 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1313 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1314 1315 if (IS_G33) 1316 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1317 intel_private.gtt = ioremap(temp2, gtt_map_size); 1318 if (!intel_private.gtt) 1319 return -ENOMEM; 1320 1321 intel_private.gtt_total_size = gtt_map_size / 4; 1322 1323 temp &= 0xfff80000; 1324 1325 intel_private.registers = ioremap(temp, 128 * 4096); 1326 if (!intel_private.registers) { 1327 iounmap(intel_private.gtt); 1328 return -ENOMEM; 1329 } 1330 1331 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1332 global_cache_flush(); /* FIXME: ? */ 1333 1334 /* we have to call this as early as possible after the MMIO base address is known */ 1335 intel_i830_init_gtt_entries(); 1336 1337 agp_bridge->gatt_table = NULL; 1338 1339 agp_bridge->gatt_bus_addr = temp; 1340 1341 return 0; 1342} 1343 1344/* 1345 * The i965 supports 36-bit physical addresses, but to keep 1346 * the format of the GTT the same, the bits that don't fit 1347 * in a 32-bit word are shifted down to bits 4..7. 1348 * 1349 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1350 * is always zero on 32-bit architectures, so no need to make 1351 * this conditional. 1352 */ 1353static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1354 dma_addr_t addr, int type) 1355{ 1356 /* Shift high bits down */ 1357 addr |= (addr >> 28) & 0xf0; 1358 1359 /* Type checking must be done elsewhere */ 1360 return addr | bridge->driver->masks[type].mask; 1361} 1362 1363static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1364{ 1365 switch (agp_bridge->dev->device) { 1366 case PCI_DEVICE_ID_INTEL_GM45_HB: 1367 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: 1368 case PCI_DEVICE_ID_INTEL_Q45_HB: 1369 case PCI_DEVICE_ID_INTEL_G45_HB: 1370 case PCI_DEVICE_ID_INTEL_G41_HB: 1371 case PCI_DEVICE_ID_INTEL_B43_HB: 1372 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB: 1373 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: 1374 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: 1375 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: 1376 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: 1377 *gtt_offset = *gtt_size = MB(2); 1378 break; 1379 default: 1380 *gtt_offset = *gtt_size = KB(512); 1381 } 1382} 1383 1384/* The intel i965 automatically initializes the agp aperture during POST. 1385 * Use the memory already set aside for in the GTT. 1386 */ 1387static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1388{ 1389 int page_order; 1390 struct aper_size_info_fixed *size; 1391 int num_entries; 1392 u32 temp; 1393 int gtt_offset, gtt_size; 1394 1395 size = agp_bridge->current_size; 1396 page_order = size->page_order; 1397 num_entries = size->num_entries; 1398 agp_bridge->gatt_table_real = NULL; 1399 1400 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1401 1402 temp &= 0xfff00000; 1403 1404 intel_i965_get_gtt_range(>t_offset, >t_size); 1405 1406 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1407 1408 if (!intel_private.gtt) 1409 return -ENOMEM; 1410 1411 intel_private.gtt_total_size = gtt_size / 4; 1412 1413 intel_private.registers = ioremap(temp, 128 * 4096); 1414 if (!intel_private.registers) { 1415 iounmap(intel_private.gtt); 1416 return -ENOMEM; 1417 } 1418 1419 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1420 global_cache_flush(); /* FIXME: ? */ 1421 1422 /* we have to call this as early as possible after the MMIO base address is known */ 1423 intel_i830_init_gtt_entries(); 1424 1425 agp_bridge->gatt_table = NULL; 1426 1427 agp_bridge->gatt_bus_addr = temp; 1428 1429 return 0; 1430} 1431 1432 1433static int intel_fetch_size(void) 1434{ 1435 int i; 1436 u16 temp; 1437 struct aper_size_info_16 *values; 1438 1439 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1440 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1441 1442 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1443 if (temp == values[i].size_value) { 1444 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1445 agp_bridge->aperture_size_idx = i; 1446 return values[i].size; 1447 } 1448 } 1449 1450 return 0; 1451} 1452 1453static int __intel_8xx_fetch_size(u8 temp) 1454{ 1455 int i; 1456 struct aper_size_info_8 *values; 1457 1458 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1459 1460 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1461 if (temp == values[i].size_value) { 1462 agp_bridge->previous_size = 1463 agp_bridge->current_size = (void *) (values + i); 1464 agp_bridge->aperture_size_idx = i; 1465 return values[i].size; 1466 } 1467 } 1468 return 0; 1469} 1470 1471static int intel_8xx_fetch_size(void) 1472{ 1473 u8 temp; 1474 1475 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1476 return __intel_8xx_fetch_size(temp); 1477} 1478 1479static int intel_815_fetch_size(void) 1480{ 1481 u8 temp; 1482 1483 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1484 * one non-reserved bit, so mask the others out ... */ 1485 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1486 temp &= (1 << 3); 1487 1488 return __intel_8xx_fetch_size(temp); 1489} 1490 1491static void intel_tlbflush(struct agp_memory *mem) 1492{ 1493 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1494 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1495} 1496 1497 1498static void intel_8xx_tlbflush(struct agp_memory *mem) 1499{ 1500 u32 temp; 1501 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1502 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1503 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1504 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1505} 1506 1507 1508static void intel_cleanup(void) 1509{ 1510 u16 temp; 1511 struct aper_size_info_16 *previous_size; 1512 1513 previous_size = A_SIZE_16(agp_bridge->previous_size); 1514 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1515 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1516 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1517} 1518 1519 1520static void intel_8xx_cleanup(void) 1521{ 1522 u16 temp; 1523 struct aper_size_info_8 *previous_size; 1524 1525 previous_size = A_SIZE_8(agp_bridge->previous_size); 1526 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1527 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1528 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1529} 1530 1531 1532static int intel_configure(void) 1533{ 1534 u32 temp; 1535 u16 temp2; 1536 struct aper_size_info_16 *current_size; 1537 1538 current_size = A_SIZE_16(agp_bridge->current_size); 1539 1540 /* aperture size */ 1541 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1542 1543 /* address to map to */ 1544 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1545 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1546 1547 /* attbase - aperture base */ 1548 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1549 1550 /* agpctrl */ 1551 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1552 1553 /* paccfg/nbxcfg */ 1554 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1555 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1556 (temp2 & ~(1 << 10)) | (1 << 9)); 1557 /* clear any possible error conditions */ 1558 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1559 return 0; 1560} 1561 1562static int intel_815_configure(void) 1563{ 1564 u32 temp, addr; 1565 u8 temp2; 1566 struct aper_size_info_8 *current_size; 1567 1568 /* attbase - aperture base */ 1569 /* the Intel 815 chipset spec. says that bits 29-31 in the 1570 * ATTBASE register are reserved -> try not to write them */ 1571 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1572 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1573 return -EINVAL; 1574 } 1575 1576 current_size = A_SIZE_8(agp_bridge->current_size); 1577 1578 /* aperture size */ 1579 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1580 current_size->size_value); 1581 1582 /* address to map to */ 1583 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1584 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1585 1586 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1587 addr &= INTEL_815_ATTBASE_MASK; 1588 addr |= agp_bridge->gatt_bus_addr; 1589 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1590 1591 /* agpctrl */ 1592 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1593 1594 /* apcont */ 1595 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1596 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1597 1598 /* clear any possible error conditions */ 1599 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1600 return 0; 1601} 1602 1603static void intel_820_tlbflush(struct agp_memory *mem) 1604{ 1605 return; 1606} 1607 1608static void intel_820_cleanup(void) 1609{ 1610 u8 temp; 1611 struct aper_size_info_8 *previous_size; 1612 1613 previous_size = A_SIZE_8(agp_bridge->previous_size); 1614 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1615 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1616 temp & ~(1 << 1)); 1617 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1618 previous_size->size_value); 1619} 1620 1621 1622static int intel_820_configure(void) 1623{ 1624 u32 temp; 1625 u8 temp2; 1626 struct aper_size_info_8 *current_size; 1627 1628 current_size = A_SIZE_8(agp_bridge->current_size); 1629 1630 /* aperture size */ 1631 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1632 1633 /* address to map to */ 1634 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1635 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1636 1637 /* attbase - aperture base */ 1638 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1639 1640 /* agpctrl */ 1641 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1642 1643 /* global enable aperture access */ 1644 /* This flag is not accessed through MCHCFG register as in */ 1645 /* i850 chipset. */ 1646 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1647 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1648 /* clear any possible AGP-related error conditions */ 1649 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1650 return 0; 1651} 1652 1653static int intel_840_configure(void) 1654{ 1655 u32 temp; 1656 u16 temp2; 1657 struct aper_size_info_8 *current_size; 1658 1659 current_size = A_SIZE_8(agp_bridge->current_size); 1660 1661 /* aperture size */ 1662 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1663 1664 /* address to map to */ 1665 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1666 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1667 1668 /* attbase - aperture base */ 1669 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1670 1671 /* agpctrl */ 1672 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1673 1674 /* mcgcfg */ 1675 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1676 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1677 /* clear any possible error conditions */ 1678 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1679 return 0; 1680} 1681 1682static int intel_845_configure(void) 1683{ 1684 u32 temp; 1685 u8 temp2; 1686 struct aper_size_info_8 *current_size; 1687 1688 current_size = A_SIZE_8(agp_bridge->current_size); 1689 1690 /* aperture size */ 1691 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1692 1693 if (agp_bridge->apbase_config != 0) { 1694 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1695 agp_bridge->apbase_config); 1696 } else { 1697 /* address to map to */ 1698 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1699 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1700 agp_bridge->apbase_config = temp; 1701 } 1702 1703 /* attbase - aperture base */ 1704 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1705 1706 /* agpctrl */ 1707 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1708 1709 /* agpm */ 1710 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1711 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1712 /* clear any possible error conditions */ 1713 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1714 1715 intel_i830_setup_flush(); 1716 return 0; 1717} 1718 1719static int intel_850_configure(void) 1720{ 1721 u32 temp; 1722 u16 temp2; 1723 struct aper_size_info_8 *current_size; 1724 1725 current_size = A_SIZE_8(agp_bridge->current_size); 1726 1727 /* aperture size */ 1728 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1729 1730 /* address to map to */ 1731 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1732 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1733 1734 /* attbase - aperture base */ 1735 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1736 1737 /* agpctrl */ 1738 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1739 1740 /* mcgcfg */ 1741 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1742 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1743 /* clear any possible AGP-related error conditions */ 1744 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1745 return 0; 1746} 1747 1748static int intel_860_configure(void) 1749{ 1750 u32 temp; 1751 u16 temp2; 1752 struct aper_size_info_8 *current_size; 1753 1754 current_size = A_SIZE_8(agp_bridge->current_size); 1755 1756 /* aperture size */ 1757 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1758 1759 /* address to map to */ 1760 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1761 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1762 1763 /* attbase - aperture base */ 1764 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1765 1766 /* agpctrl */ 1767 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1768 1769 /* mcgcfg */ 1770 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1771 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1772 /* clear any possible AGP-related error conditions */ 1773 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1774 return 0; 1775} 1776 1777static int intel_830mp_configure(void) 1778{ 1779 u32 temp; 1780 u16 temp2; 1781 struct aper_size_info_8 *current_size; 1782 1783 current_size = A_SIZE_8(agp_bridge->current_size); 1784 1785 /* aperture size */ 1786 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1787 1788 /* address to map to */ 1789 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1790 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1791 1792 /* attbase - aperture base */ 1793 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1794 1795 /* agpctrl */ 1796 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1797 1798 /* gmch */ 1799 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1800 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1801 /* clear any possible AGP-related error conditions */ 1802 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1803 return 0; 1804} 1805 1806static int intel_7505_configure(void) 1807{ 1808 u32 temp; 1809 u16 temp2; 1810 struct aper_size_info_8 *current_size; 1811 1812 current_size = A_SIZE_8(agp_bridge->current_size); 1813 1814 /* aperture size */ 1815 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1816 1817 /* address to map to */ 1818 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1819 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1820 1821 /* attbase - aperture base */ 1822 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1823 1824 /* agpctrl */ 1825 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1826 1827 /* mchcfg */ 1828 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1829 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1830 1831 return 0; 1832} 1833 1834/* Setup function */ 1835static const struct gatt_mask intel_generic_masks[] = 1836{ 1837 {.mask = 0x00000017, .type = 0} 1838}; 1839 1840static const struct aper_size_info_8 intel_815_sizes[2] = 1841{ 1842 {64, 16384, 4, 0}, 1843 {32, 8192, 3, 8}, 1844}; 1845 1846static const struct aper_size_info_8 intel_8xx_sizes[7] = 1847{ 1848 {256, 65536, 6, 0}, 1849 {128, 32768, 5, 32}, 1850 {64, 16384, 4, 48}, 1851 {32, 8192, 3, 56}, 1852 {16, 4096, 2, 60}, 1853 {8, 2048, 1, 62}, 1854 {4, 1024, 0, 63} 1855}; 1856 1857static const struct aper_size_info_16 intel_generic_sizes[7] = 1858{ 1859 {256, 65536, 6, 0}, 1860 {128, 32768, 5, 32}, 1861 {64, 16384, 4, 48}, 1862 {32, 8192, 3, 56}, 1863 {16, 4096, 2, 60}, 1864 {8, 2048, 1, 62}, 1865 {4, 1024, 0, 63} 1866}; 1867 1868static const struct aper_size_info_8 intel_830mp_sizes[4] = 1869{ 1870 {256, 65536, 6, 0}, 1871 {128, 32768, 5, 32}, 1872 {64, 16384, 4, 48}, 1873 {32, 8192, 3, 56} 1874}; 1875 1876static const struct agp_bridge_driver intel_generic_driver = { 1877 .owner = THIS_MODULE, 1878 .aperture_sizes = intel_generic_sizes, 1879 .size_type = U16_APER_SIZE, 1880 .num_aperture_sizes = 7, 1881 .configure = intel_configure, 1882 .fetch_size = intel_fetch_size, 1883 .cleanup = intel_cleanup, 1884 .tlb_flush = intel_tlbflush, 1885 .mask_memory = agp_generic_mask_memory, 1886 .masks = intel_generic_masks, 1887 .agp_enable = agp_generic_enable, 1888 .cache_flush = global_cache_flush, 1889 .create_gatt_table = agp_generic_create_gatt_table, 1890 .free_gatt_table = agp_generic_free_gatt_table, 1891 .insert_memory = agp_generic_insert_memory, 1892 .remove_memory = agp_generic_remove_memory, 1893 .alloc_by_type = agp_generic_alloc_by_type, 1894 .free_by_type = agp_generic_free_by_type, 1895 .agp_alloc_page = agp_generic_alloc_page, 1896 .agp_alloc_pages = agp_generic_alloc_pages, 1897 .agp_destroy_page = agp_generic_destroy_page, 1898 .agp_destroy_pages = agp_generic_destroy_pages, 1899 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1900}; 1901 1902static const struct agp_bridge_driver intel_810_driver = { 1903 .owner = THIS_MODULE, 1904 .aperture_sizes = intel_i810_sizes, 1905 .size_type = FIXED_APER_SIZE, 1906 .num_aperture_sizes = 2, 1907 .needs_scratch_page = true, 1908 .configure = intel_i810_configure, 1909 .fetch_size = intel_i810_fetch_size, 1910 .cleanup = intel_i810_cleanup, 1911 .tlb_flush = intel_i810_tlbflush, 1912 .mask_memory = intel_i810_mask_memory, 1913 .masks = intel_i810_masks, 1914 .agp_enable = intel_i810_agp_enable, 1915 .cache_flush = global_cache_flush, 1916 .create_gatt_table = agp_generic_create_gatt_table, 1917 .free_gatt_table = agp_generic_free_gatt_table, 1918 .insert_memory = intel_i810_insert_entries, 1919 .remove_memory = intel_i810_remove_entries, 1920 .alloc_by_type = intel_i810_alloc_by_type, 1921 .free_by_type = intel_i810_free_by_type, 1922 .agp_alloc_page = agp_generic_alloc_page, 1923 .agp_alloc_pages = agp_generic_alloc_pages, 1924 .agp_destroy_page = agp_generic_destroy_page, 1925 .agp_destroy_pages = agp_generic_destroy_pages, 1926 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1927}; 1928 1929static const struct agp_bridge_driver intel_815_driver = { 1930 .owner = THIS_MODULE, 1931 .aperture_sizes = intel_815_sizes, 1932 .size_type = U8_APER_SIZE, 1933 .num_aperture_sizes = 2, 1934 .configure = intel_815_configure, 1935 .fetch_size = intel_815_fetch_size, 1936 .cleanup = intel_8xx_cleanup, 1937 .tlb_flush = intel_8xx_tlbflush, 1938 .mask_memory = agp_generic_mask_memory, 1939 .masks = intel_generic_masks, 1940 .agp_enable = agp_generic_enable, 1941 .cache_flush = global_cache_flush, 1942 .create_gatt_table = agp_generic_create_gatt_table, 1943 .free_gatt_table = agp_generic_free_gatt_table, 1944 .insert_memory = agp_generic_insert_memory, 1945 .remove_memory = agp_generic_remove_memory, 1946 .alloc_by_type = agp_generic_alloc_by_type, 1947 .free_by_type = agp_generic_free_by_type, 1948 .agp_alloc_page = agp_generic_alloc_page, 1949 .agp_alloc_pages = agp_generic_alloc_pages, 1950 .agp_destroy_page = agp_generic_destroy_page, 1951 .agp_destroy_pages = agp_generic_destroy_pages, 1952 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1953}; 1954 1955static const struct agp_bridge_driver intel_830_driver = { 1956 .owner = THIS_MODULE, 1957 .aperture_sizes = intel_i830_sizes, 1958 .size_type = FIXED_APER_SIZE, 1959 .num_aperture_sizes = 4, 1960 .needs_scratch_page = true, 1961 .configure = intel_i830_configure, 1962 .fetch_size = intel_i830_fetch_size, 1963 .cleanup = intel_i830_cleanup, 1964 .tlb_flush = intel_i810_tlbflush, 1965 .mask_memory = intel_i810_mask_memory, 1966 .masks = intel_i810_masks, 1967 .agp_enable = intel_i810_agp_enable, 1968 .cache_flush = global_cache_flush, 1969 .create_gatt_table = intel_i830_create_gatt_table, 1970 .free_gatt_table = intel_i830_free_gatt_table, 1971 .insert_memory = intel_i830_insert_entries, 1972 .remove_memory = intel_i830_remove_entries, 1973 .alloc_by_type = intel_i830_alloc_by_type, 1974 .free_by_type = intel_i810_free_by_type, 1975 .agp_alloc_page = agp_generic_alloc_page, 1976 .agp_alloc_pages = agp_generic_alloc_pages, 1977 .agp_destroy_page = agp_generic_destroy_page, 1978 .agp_destroy_pages = agp_generic_destroy_pages, 1979 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1980 .chipset_flush = intel_i830_chipset_flush, 1981}; 1982 1983static const struct agp_bridge_driver intel_820_driver = { 1984 .owner = THIS_MODULE, 1985 .aperture_sizes = intel_8xx_sizes, 1986 .size_type = U8_APER_SIZE, 1987 .num_aperture_sizes = 7, 1988 .configure = intel_820_configure, 1989 .fetch_size = intel_8xx_fetch_size, 1990 .cleanup = intel_820_cleanup, 1991 .tlb_flush = intel_820_tlbflush, 1992 .mask_memory = agp_generic_mask_memory, 1993 .masks = intel_generic_masks, 1994 .agp_enable = agp_generic_enable, 1995 .cache_flush = global_cache_flush, 1996 .create_gatt_table = agp_generic_create_gatt_table, 1997 .free_gatt_table = agp_generic_free_gatt_table, 1998 .insert_memory = agp_generic_insert_memory, 1999 .remove_memory = agp_generic_remove_memory, 2000 .alloc_by_type = agp_generic_alloc_by_type, 2001 .free_by_type = agp_generic_free_by_type, 2002 .agp_alloc_page = agp_generic_alloc_page, 2003 .agp_alloc_pages = agp_generic_alloc_pages, 2004 .agp_destroy_page = agp_generic_destroy_page, 2005 .agp_destroy_pages = agp_generic_destroy_pages, 2006 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2007}; 2008 2009static const struct agp_bridge_driver intel_830mp_driver = { 2010 .owner = THIS_MODULE, 2011 .aperture_sizes = intel_830mp_sizes, 2012 .size_type = U8_APER_SIZE, 2013 .num_aperture_sizes = 4, 2014 .configure = intel_830mp_configure, 2015 .fetch_size = intel_8xx_fetch_size, 2016 .cleanup = intel_8xx_cleanup, 2017 .tlb_flush = intel_8xx_tlbflush, 2018 .mask_memory = agp_generic_mask_memory, 2019 .masks = intel_generic_masks, 2020 .agp_enable = agp_generic_enable, 2021 .cache_flush = global_cache_flush, 2022 .create_gatt_table = agp_generic_create_gatt_table, 2023 .free_gatt_table = agp_generic_free_gatt_table, 2024 .insert_memory = agp_generic_insert_memory, 2025 .remove_memory = agp_generic_remove_memory, 2026 .alloc_by_type = agp_generic_alloc_by_type, 2027 .free_by_type = agp_generic_free_by_type, 2028 .agp_alloc_page = agp_generic_alloc_page, 2029 .agp_alloc_pages = agp_generic_alloc_pages, 2030 .agp_destroy_page = agp_generic_destroy_page, 2031 .agp_destroy_pages = agp_generic_destroy_pages, 2032 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2033}; 2034 2035static const struct agp_bridge_driver intel_840_driver = { 2036 .owner = THIS_MODULE, 2037 .aperture_sizes = intel_8xx_sizes, 2038 .size_type = U8_APER_SIZE, 2039 .num_aperture_sizes = 7, 2040 .configure = intel_840_configure, 2041 .fetch_size = intel_8xx_fetch_size, 2042 .cleanup = intel_8xx_cleanup, 2043 .tlb_flush = intel_8xx_tlbflush, 2044 .mask_memory = agp_generic_mask_memory, 2045 .masks = intel_generic_masks, 2046 .agp_enable = agp_generic_enable, 2047 .cache_flush = global_cache_flush, 2048 .create_gatt_table = agp_generic_create_gatt_table, 2049 .free_gatt_table = agp_generic_free_gatt_table, 2050 .insert_memory = agp_generic_insert_memory, 2051 .remove_memory = agp_generic_remove_memory, 2052 .alloc_by_type = agp_generic_alloc_by_type, 2053 .free_by_type = agp_generic_free_by_type, 2054 .agp_alloc_page = agp_generic_alloc_page, 2055 .agp_alloc_pages = agp_generic_alloc_pages, 2056 .agp_destroy_page = agp_generic_destroy_page, 2057 .agp_destroy_pages = agp_generic_destroy_pages, 2058 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2059}; 2060 2061static const struct agp_bridge_driver intel_845_driver = { 2062 .owner = THIS_MODULE, 2063 .aperture_sizes = intel_8xx_sizes, 2064 .size_type = U8_APER_SIZE, 2065 .num_aperture_sizes = 7, 2066 .configure = intel_845_configure, 2067 .fetch_size = intel_8xx_fetch_size, 2068 .cleanup = intel_8xx_cleanup, 2069 .tlb_flush = intel_8xx_tlbflush, 2070 .mask_memory = agp_generic_mask_memory, 2071 .masks = intel_generic_masks, 2072 .agp_enable = agp_generic_enable, 2073 .cache_flush = global_cache_flush, 2074 .create_gatt_table = agp_generic_create_gatt_table, 2075 .free_gatt_table = agp_generic_free_gatt_table, 2076 .insert_memory = agp_generic_insert_memory, 2077 .remove_memory = agp_generic_remove_memory, 2078 .alloc_by_type = agp_generic_alloc_by_type, 2079 .free_by_type = agp_generic_free_by_type, 2080 .agp_alloc_page = agp_generic_alloc_page, 2081 .agp_alloc_pages = agp_generic_alloc_pages, 2082 .agp_destroy_page = agp_generic_destroy_page, 2083 .agp_destroy_pages = agp_generic_destroy_pages, 2084 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2085 .chipset_flush = intel_i830_chipset_flush, 2086}; 2087 2088static const struct agp_bridge_driver intel_850_driver = { 2089 .owner = THIS_MODULE, 2090 .aperture_sizes = intel_8xx_sizes, 2091 .size_type = U8_APER_SIZE, 2092 .num_aperture_sizes = 7, 2093 .configure = intel_850_configure, 2094 .fetch_size = intel_8xx_fetch_size, 2095 .cleanup = intel_8xx_cleanup, 2096 .tlb_flush = intel_8xx_tlbflush, 2097 .mask_memory = agp_generic_mask_memory, 2098 .masks = intel_generic_masks, 2099 .agp_enable = agp_generic_enable, 2100 .cache_flush = global_cache_flush, 2101 .create_gatt_table = agp_generic_create_gatt_table, 2102 .free_gatt_table = agp_generic_free_gatt_table, 2103 .insert_memory = agp_generic_insert_memory, 2104 .remove_memory = agp_generic_remove_memory, 2105 .alloc_by_type = agp_generic_alloc_by_type, 2106 .free_by_type = agp_generic_free_by_type, 2107 .agp_alloc_page = agp_generic_alloc_page, 2108 .agp_alloc_pages = agp_generic_alloc_pages, 2109 .agp_destroy_page = agp_generic_destroy_page, 2110 .agp_destroy_pages = agp_generic_destroy_pages, 2111 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2112}; 2113 2114static const struct agp_bridge_driver intel_860_driver = { 2115 .owner = THIS_MODULE, 2116 .aperture_sizes = intel_8xx_sizes, 2117 .size_type = U8_APER_SIZE, 2118 .num_aperture_sizes = 7, 2119 .configure = intel_860_configure, 2120 .fetch_size = intel_8xx_fetch_size, 2121 .cleanup = intel_8xx_cleanup, 2122 .tlb_flush = intel_8xx_tlbflush, 2123 .mask_memory = agp_generic_mask_memory, 2124 .masks = intel_generic_masks, 2125 .agp_enable = agp_generic_enable, 2126 .cache_flush = global_cache_flush, 2127 .create_gatt_table = agp_generic_create_gatt_table, 2128 .free_gatt_table = agp_generic_free_gatt_table, 2129 .insert_memory = agp_generic_insert_memory, 2130 .remove_memory = agp_generic_remove_memory, 2131 .alloc_by_type = agp_generic_alloc_by_type, 2132 .free_by_type = agp_generic_free_by_type, 2133 .agp_alloc_page = agp_generic_alloc_page, 2134 .agp_alloc_pages = agp_generic_alloc_pages, 2135 .agp_destroy_page = agp_generic_destroy_page, 2136 .agp_destroy_pages = agp_generic_destroy_pages, 2137 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2138}; 2139 2140static const struct agp_bridge_driver intel_915_driver = { 2141 .owner = THIS_MODULE, 2142 .aperture_sizes = intel_i830_sizes, 2143 .size_type = FIXED_APER_SIZE, 2144 .num_aperture_sizes = 4, 2145 .needs_scratch_page = true, 2146 .configure = intel_i915_configure, 2147 .fetch_size = intel_i9xx_fetch_size, 2148 .cleanup = intel_i915_cleanup, 2149 .tlb_flush = intel_i810_tlbflush, 2150 .mask_memory = intel_i810_mask_memory, 2151 .masks = intel_i810_masks, 2152 .agp_enable = intel_i810_agp_enable, 2153 .cache_flush = global_cache_flush, 2154 .create_gatt_table = intel_i915_create_gatt_table, 2155 .free_gatt_table = intel_i830_free_gatt_table, 2156 .insert_memory = intel_i915_insert_entries, 2157 .remove_memory = intel_i915_remove_entries, 2158 .alloc_by_type = intel_i830_alloc_by_type, 2159 .free_by_type = intel_i810_free_by_type, 2160 .agp_alloc_page = agp_generic_alloc_page, 2161 .agp_alloc_pages = agp_generic_alloc_pages, 2162 .agp_destroy_page = agp_generic_destroy_page, 2163 .agp_destroy_pages = agp_generic_destroy_pages, 2164 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2165 .chipset_flush = intel_i915_chipset_flush, 2166#ifdef USE_PCI_DMA_API 2167 .agp_map_page = intel_agp_map_page, 2168 .agp_unmap_page = intel_agp_unmap_page, 2169 .agp_map_memory = intel_agp_map_memory, 2170 .agp_unmap_memory = intel_agp_unmap_memory, 2171#endif 2172}; 2173 2174static const struct agp_bridge_driver intel_i965_driver = { 2175 .owner = THIS_MODULE, 2176 .aperture_sizes = intel_i830_sizes, 2177 .size_type = FIXED_APER_SIZE, 2178 .num_aperture_sizes = 4, 2179 .needs_scratch_page = true, 2180 .configure = intel_i915_configure, 2181 .fetch_size = intel_i9xx_fetch_size, 2182 .cleanup = intel_i915_cleanup, 2183 .tlb_flush = intel_i810_tlbflush, 2184 .mask_memory = intel_i965_mask_memory, 2185 .masks = intel_i810_masks, 2186 .agp_enable = intel_i810_agp_enable, 2187 .cache_flush = global_cache_flush, 2188 .create_gatt_table = intel_i965_create_gatt_table, 2189 .free_gatt_table = intel_i830_free_gatt_table, 2190 .insert_memory = intel_i915_insert_entries, 2191 .remove_memory = intel_i915_remove_entries, 2192 .alloc_by_type = intel_i830_alloc_by_type, 2193 .free_by_type = intel_i810_free_by_type, 2194 .agp_alloc_page = agp_generic_alloc_page, 2195 .agp_alloc_pages = agp_generic_alloc_pages, 2196 .agp_destroy_page = agp_generic_destroy_page, 2197 .agp_destroy_pages = agp_generic_destroy_pages, 2198 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2199 .chipset_flush = intel_i915_chipset_flush, 2200#ifdef USE_PCI_DMA_API 2201 .agp_map_page = intel_agp_map_page, 2202 .agp_unmap_page = intel_agp_unmap_page, 2203 .agp_map_memory = intel_agp_map_memory, 2204 .agp_unmap_memory = intel_agp_unmap_memory, 2205#endif 2206}; 2207 2208static const struct agp_bridge_driver intel_7505_driver = { 2209 .owner = THIS_MODULE, 2210 .aperture_sizes = intel_8xx_sizes, 2211 .size_type = U8_APER_SIZE, 2212 .num_aperture_sizes = 7, 2213 .configure = intel_7505_configure, 2214 .fetch_size = intel_8xx_fetch_size, 2215 .cleanup = intel_8xx_cleanup, 2216 .tlb_flush = intel_8xx_tlbflush, 2217 .mask_memory = agp_generic_mask_memory, 2218 .masks = intel_generic_masks, 2219 .agp_enable = agp_generic_enable, 2220 .cache_flush = global_cache_flush, 2221 .create_gatt_table = agp_generic_create_gatt_table, 2222 .free_gatt_table = agp_generic_free_gatt_table, 2223 .insert_memory = agp_generic_insert_memory, 2224 .remove_memory = agp_generic_remove_memory, 2225 .alloc_by_type = agp_generic_alloc_by_type, 2226 .free_by_type = agp_generic_free_by_type, 2227 .agp_alloc_page = agp_generic_alloc_page, 2228 .agp_alloc_pages = agp_generic_alloc_pages, 2229 .agp_destroy_page = agp_generic_destroy_page, 2230 .agp_destroy_pages = agp_generic_destroy_pages, 2231 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2232}; 2233 2234static const struct agp_bridge_driver intel_g33_driver = { 2235 .owner = THIS_MODULE, 2236 .aperture_sizes = intel_i830_sizes, 2237 .size_type = FIXED_APER_SIZE, 2238 .num_aperture_sizes = 4, 2239 .needs_scratch_page = true, 2240 .configure = intel_i915_configure, 2241 .fetch_size = intel_i9xx_fetch_size, 2242 .cleanup = intel_i915_cleanup, 2243 .tlb_flush = intel_i810_tlbflush, 2244 .mask_memory = intel_i965_mask_memory, 2245 .masks = intel_i810_masks, 2246 .agp_enable = intel_i810_agp_enable, 2247 .cache_flush = global_cache_flush, 2248 .create_gatt_table = intel_i915_create_gatt_table, 2249 .free_gatt_table = intel_i830_free_gatt_table, 2250 .insert_memory = intel_i915_insert_entries, 2251 .remove_memory = intel_i915_remove_entries, 2252 .alloc_by_type = intel_i830_alloc_by_type, 2253 .free_by_type = intel_i810_free_by_type, 2254 .agp_alloc_page = agp_generic_alloc_page, 2255 .agp_alloc_pages = agp_generic_alloc_pages, 2256 .agp_destroy_page = agp_generic_destroy_page, 2257 .agp_destroy_pages = agp_generic_destroy_pages, 2258 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2259 .chipset_flush = intel_i915_chipset_flush, 2260#ifdef USE_PCI_DMA_API 2261 .agp_map_page = intel_agp_map_page, 2262 .agp_unmap_page = intel_agp_unmap_page, 2263 .agp_map_memory = intel_agp_map_memory, 2264 .agp_unmap_memory = intel_agp_unmap_memory, 2265#endif 2266}; 2267 2268static int find_gmch(u16 device) 2269{ 2270 struct pci_dev *gmch_device; 2271 2272 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2273 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2274 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2275 device, gmch_device); 2276 } 2277 2278 if (!gmch_device) 2279 return 0; 2280 2281 intel_private.pcidev = gmch_device; 2282 return 1; 2283} 2284 2285/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2286 * driver and gmch_driver must be non-null, and find_gmch will determine 2287 * which one should be used if a gmch_chip_id is present. 2288 */ 2289static const struct intel_driver_description { 2290 unsigned int chip_id; 2291 unsigned int gmch_chip_id; 2292 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2293 char *name; 2294 const struct agp_bridge_driver *driver; 2295 const struct agp_bridge_driver *gmch_driver; 2296} intel_agp_chipsets[] = { 2297 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2298 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2299 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2300 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2301 NULL, &intel_810_driver }, 2302 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2303 NULL, &intel_810_driver }, 2304 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2305 NULL, &intel_810_driver }, 2306 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2307 &intel_815_driver, &intel_810_driver }, 2308 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2309 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2310 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2311 &intel_830mp_driver, &intel_830_driver }, 2312 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2313 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2314 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2315 &intel_845_driver, &intel_830_driver }, 2316 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2317 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", 2318 &intel_845_driver, &intel_830_driver }, 2319 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2320 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2321 &intel_845_driver, &intel_830_driver }, 2322 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2323 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2324 &intel_845_driver, &intel_830_driver }, 2325 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2326 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2327 NULL, &intel_915_driver }, 2328 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2329 NULL, &intel_915_driver }, 2330 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2331 NULL, &intel_915_driver }, 2332 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2333 NULL, &intel_915_driver }, 2334 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2335 NULL, &intel_915_driver }, 2336 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2337 NULL, &intel_915_driver }, 2338 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2339 NULL, &intel_i965_driver }, 2340 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2341 NULL, &intel_i965_driver }, 2342 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2343 NULL, &intel_i965_driver }, 2344 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2345 NULL, &intel_i965_driver }, 2346 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2347 NULL, &intel_i965_driver }, 2348 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2349 NULL, &intel_i965_driver }, 2350 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2351 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2352 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2353 NULL, &intel_g33_driver }, 2354 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2355 NULL, &intel_g33_driver }, 2356 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2357 NULL, &intel_g33_driver }, 2358 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150", 2359 NULL, &intel_g33_driver }, 2360 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150", 2361 NULL, &intel_g33_driver }, 2362 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2363 "GM45", NULL, &intel_i965_driver }, 2364 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0, 2365 "Eaglelake", NULL, &intel_i965_driver }, 2366 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2367 "Q45/Q43", NULL, &intel_i965_driver }, 2368 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2369 "G45/G43", NULL, &intel_i965_driver }, 2370 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, 2371 "B43", NULL, &intel_i965_driver }, 2372 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2373 "G41", NULL, &intel_i965_driver }, 2374 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0, 2375 "HD Graphics", NULL, &intel_i965_driver }, 2376 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2377 "HD Graphics", NULL, &intel_i965_driver }, 2378 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2379 "HD Graphics", NULL, &intel_i965_driver }, 2380 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2381 "HD Graphics", NULL, &intel_i965_driver }, 2382 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, 2383 "Sandybridge", NULL, &intel_i965_driver }, 2384 { 0, 0, 0, NULL, NULL, NULL } 2385}; 2386 2387static int __devinit agp_intel_probe(struct pci_dev *pdev, 2388 const struct pci_device_id *ent) 2389{ 2390 struct agp_bridge_data *bridge; 2391 u8 cap_ptr = 0; 2392 struct resource *r; 2393 int i; 2394 2395 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2396 2397 bridge = agp_alloc_bridge(); 2398 if (!bridge) 2399 return -ENOMEM; 2400 2401 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2402 /* In case that multiple models of gfx chip may 2403 stand on same host bridge type, this can be 2404 sure we detect the right IGD. */ 2405 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2406 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2407 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2408 bridge->driver = 2409 intel_agp_chipsets[i].gmch_driver; 2410 break; 2411 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2412 continue; 2413 } else { 2414 bridge->driver = intel_agp_chipsets[i].driver; 2415 break; 2416 } 2417 } 2418 } 2419 2420 if (intel_agp_chipsets[i].name == NULL) { 2421 if (cap_ptr) 2422 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2423 pdev->vendor, pdev->device); 2424 agp_put_bridge(bridge); 2425 return -ENODEV; 2426 } 2427 2428 if (bridge->driver == NULL) { 2429 /* bridge has no AGP and no IGD detected */ 2430 if (cap_ptr) 2431 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2432 intel_agp_chipsets[i].gmch_chip_id); 2433 agp_put_bridge(bridge); 2434 return -ENODEV; 2435 } 2436 2437 bridge->dev = pdev; 2438 bridge->capndx = cap_ptr; 2439 bridge->dev_private_data = &intel_private; 2440 2441 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2442 2443 /* 2444 * The following fixes the case where the BIOS has "forgotten" to 2445 * provide an address range for the GART. 2446 * 20030610 - hamish@zot.org 2447 */ 2448 r = &pdev->resource[0]; 2449 if (!r->start && r->end) { 2450 if (pci_assign_resource(pdev, 0)) { 2451 dev_err(&pdev->dev, "can't assign resource 0\n"); 2452 agp_put_bridge(bridge); 2453 return -ENODEV; 2454 } 2455 } 2456 2457 /* 2458 * If the device has not been properly setup, the following will catch 2459 * the problem and should stop the system from crashing. 2460 * 20030610 - hamish@zot.org 2461 */ 2462 if (pci_enable_device(pdev)) { 2463 dev_err(&pdev->dev, "can't enable PCI device\n"); 2464 agp_put_bridge(bridge); 2465 return -ENODEV; 2466 } 2467 2468 /* Fill in the mode register */ 2469 if (cap_ptr) { 2470 pci_read_config_dword(pdev, 2471 bridge->capndx+PCI_AGP_STATUS, 2472 &bridge->mode); 2473 } 2474 2475 if (bridge->driver->mask_memory == intel_i965_mask_memory) { 2476 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) 2477 dev_err(&intel_private.pcidev->dev, 2478 "set gfx device dma mask 36bit failed!\n"); 2479 else 2480 pci_set_consistent_dma_mask(intel_private.pcidev, 2481 DMA_BIT_MASK(36)); 2482 } 2483 2484 pci_set_drvdata(pdev, bridge); 2485 return agp_add_bridge(bridge); 2486} 2487 2488static void __devexit agp_intel_remove(struct pci_dev *pdev) 2489{ 2490 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2491 2492 agp_remove_bridge(bridge); 2493 2494 if (intel_private.pcidev) 2495 pci_dev_put(intel_private.pcidev); 2496 2497 agp_put_bridge(bridge); 2498} 2499 2500#ifdef CONFIG_PM 2501static int agp_intel_resume(struct pci_dev *pdev) 2502{ 2503 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2504 int ret_val; 2505 2506 if (bridge->driver == &intel_generic_driver) 2507 intel_configure(); 2508 else if (bridge->driver == &intel_850_driver) 2509 intel_850_configure(); 2510 else if (bridge->driver == &intel_845_driver) 2511 intel_845_configure(); 2512 else if (bridge->driver == &intel_830mp_driver) 2513 intel_830mp_configure(); 2514 else if (bridge->driver == &intel_915_driver) 2515 intel_i915_configure(); 2516 else if (bridge->driver == &intel_830_driver) 2517 intel_i830_configure(); 2518 else if (bridge->driver == &intel_810_driver) 2519 intel_i810_configure(); 2520 else if (bridge->driver == &intel_i965_driver) 2521 intel_i915_configure(); 2522 2523 ret_val = agp_rebind_memory(); 2524 if (ret_val != 0) 2525 return ret_val; 2526 2527 return 0; 2528} 2529#endif 2530 2531static struct pci_device_id agp_intel_pci_table[] = { 2532#define ID(x) \ 2533 { \ 2534 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2535 .class_mask = ~0, \ 2536 .vendor = PCI_VENDOR_ID_INTEL, \ 2537 .device = x, \ 2538 .subvendor = PCI_ANY_ID, \ 2539 .subdevice = PCI_ANY_ID, \ 2540 } 2541 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2542 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2543 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2544 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2545 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2546 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2547 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2548 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2549 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2550 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2551 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2552 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2553 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2554 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2555 ID(PCI_DEVICE_ID_INTEL_82854_HB), 2556 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2557 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2558 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2559 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2560 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2561 ID(PCI_DEVICE_ID_INTEL_7505_0), 2562 ID(PCI_DEVICE_ID_INTEL_7205_0), 2563 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2564 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2565 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2566 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2567 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2568 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2569 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB), 2570 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB), 2571 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2572 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2573 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2574 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2575 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2576 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2577 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2578 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2579 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2580 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2581 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB), 2582 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2583 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2584 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2585 ID(PCI_DEVICE_ID_INTEL_B43_HB), 2586 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), 2587 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), 2588 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), 2589 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), 2590 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), 2591 { } 2592}; 2593 2594MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2595 2596static struct pci_driver agp_intel_pci_driver = { 2597 .name = "agpgart-intel", 2598 .id_table = agp_intel_pci_table, 2599 .probe = agp_intel_probe, 2600 .remove = __devexit_p(agp_intel_remove), 2601#ifdef CONFIG_PM 2602 .resume = agp_intel_resume, 2603#endif 2604}; 2605 2606static int __init agp_intel_init(void) 2607{ 2608 if (agp_off) 2609 return -EINVAL; 2610 return pci_register_driver(&agp_intel_pci_driver); 2611} 2612 2613static void __exit agp_intel_cleanup(void) 2614{ 2615 pci_unregister_driver(&agp_intel_pci_driver); 2616} 2617 2618module_init(agp_intel_init); 2619module_exit(agp_intel_cleanup); 2620 2621MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 2622MODULE_LICENSE("GPL and additional rights"); 2623