intel-agp.c revision 22dd82a3f5ceef72be19e502418823a2f8801ed0
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include <asm/smp.h> 12#include "agp.h" 13#include "intel-agp.h" 14 15#include "intel-gtt.c" 16 17int intel_agp_enabled; 18EXPORT_SYMBOL(intel_agp_enabled); 19 20static int intel_fetch_size(void) 21{ 22 int i; 23 u16 temp; 24 struct aper_size_info_16 *values; 25 26 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 27 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 28 29 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 30 if (temp == values[i].size_value) { 31 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 32 agp_bridge->aperture_size_idx = i; 33 return values[i].size; 34 } 35 } 36 37 return 0; 38} 39 40static int __intel_8xx_fetch_size(u8 temp) 41{ 42 int i; 43 struct aper_size_info_8 *values; 44 45 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 46 47 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 48 if (temp == values[i].size_value) { 49 agp_bridge->previous_size = 50 agp_bridge->current_size = (void *) (values + i); 51 agp_bridge->aperture_size_idx = i; 52 return values[i].size; 53 } 54 } 55 return 0; 56} 57 58static int intel_8xx_fetch_size(void) 59{ 60 u8 temp; 61 62 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 63 return __intel_8xx_fetch_size(temp); 64} 65 66static int intel_815_fetch_size(void) 67{ 68 u8 temp; 69 70 /* Intel 815 chipsets have a _weird_ APSIZE register with only 71 * one non-reserved bit, so mask the others out ... */ 72 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 73 temp &= (1 << 3); 74 75 return __intel_8xx_fetch_size(temp); 76} 77 78static void intel_tlbflush(struct agp_memory *mem) 79{ 80 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 81 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 82} 83 84 85static void intel_8xx_tlbflush(struct agp_memory *mem) 86{ 87 u32 temp; 88 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 89 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 90 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 91 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 92} 93 94 95static void intel_cleanup(void) 96{ 97 u16 temp; 98 struct aper_size_info_16 *previous_size; 99 100 previous_size = A_SIZE_16(agp_bridge->previous_size); 101 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 102 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 103 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 104} 105 106 107static void intel_8xx_cleanup(void) 108{ 109 u16 temp; 110 struct aper_size_info_8 *previous_size; 111 112 previous_size = A_SIZE_8(agp_bridge->previous_size); 113 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 114 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 115 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 116} 117 118 119static int intel_configure(void) 120{ 121 u32 temp; 122 u16 temp2; 123 struct aper_size_info_16 *current_size; 124 125 current_size = A_SIZE_16(agp_bridge->current_size); 126 127 /* aperture size */ 128 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 129 130 /* address to map to */ 131 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 132 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 133 134 /* attbase - aperture base */ 135 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 136 137 /* agpctrl */ 138 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 139 140 /* paccfg/nbxcfg */ 141 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 142 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 143 (temp2 & ~(1 << 10)) | (1 << 9)); 144 /* clear any possible error conditions */ 145 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 146 return 0; 147} 148 149static int intel_815_configure(void) 150{ 151 u32 temp, addr; 152 u8 temp2; 153 struct aper_size_info_8 *current_size; 154 155 /* attbase - aperture base */ 156 /* the Intel 815 chipset spec. says that bits 29-31 in the 157 * ATTBASE register are reserved -> try not to write them */ 158 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 159 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 160 return -EINVAL; 161 } 162 163 current_size = A_SIZE_8(agp_bridge->current_size); 164 165 /* aperture size */ 166 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 167 current_size->size_value); 168 169 /* address to map to */ 170 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 171 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 172 173 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 174 addr &= INTEL_815_ATTBASE_MASK; 175 addr |= agp_bridge->gatt_bus_addr; 176 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 177 178 /* agpctrl */ 179 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 180 181 /* apcont */ 182 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 183 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 184 185 /* clear any possible error conditions */ 186 /* Oddness : this chipset seems to have no ERRSTS register ! */ 187 return 0; 188} 189 190static void intel_820_tlbflush(struct agp_memory *mem) 191{ 192 return; 193} 194 195static void intel_820_cleanup(void) 196{ 197 u8 temp; 198 struct aper_size_info_8 *previous_size; 199 200 previous_size = A_SIZE_8(agp_bridge->previous_size); 201 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 202 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 203 temp & ~(1 << 1)); 204 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 205 previous_size->size_value); 206} 207 208 209static int intel_820_configure(void) 210{ 211 u32 temp; 212 u8 temp2; 213 struct aper_size_info_8 *current_size; 214 215 current_size = A_SIZE_8(agp_bridge->current_size); 216 217 /* aperture size */ 218 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 219 220 /* address to map to */ 221 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 222 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 223 224 /* attbase - aperture base */ 225 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 226 227 /* agpctrl */ 228 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 229 230 /* global enable aperture access */ 231 /* This flag is not accessed through MCHCFG register as in */ 232 /* i850 chipset. */ 233 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 234 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 235 /* clear any possible AGP-related error conditions */ 236 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 237 return 0; 238} 239 240static int intel_840_configure(void) 241{ 242 u32 temp; 243 u16 temp2; 244 struct aper_size_info_8 *current_size; 245 246 current_size = A_SIZE_8(agp_bridge->current_size); 247 248 /* aperture size */ 249 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 250 251 /* address to map to */ 252 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 253 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 254 255 /* attbase - aperture base */ 256 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 257 258 /* agpctrl */ 259 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 260 261 /* mcgcfg */ 262 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 263 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 264 /* clear any possible error conditions */ 265 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 266 return 0; 267} 268 269static int intel_845_configure(void) 270{ 271 u32 temp; 272 u8 temp2; 273 struct aper_size_info_8 *current_size; 274 275 current_size = A_SIZE_8(agp_bridge->current_size); 276 277 /* aperture size */ 278 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 279 280 if (agp_bridge->apbase_config != 0) { 281 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 282 agp_bridge->apbase_config); 283 } else { 284 /* address to map to */ 285 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 286 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 287 agp_bridge->apbase_config = temp; 288 } 289 290 /* attbase - aperture base */ 291 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 292 293 /* agpctrl */ 294 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 295 296 /* agpm */ 297 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 298 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 299 /* clear any possible error conditions */ 300 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 301 return 0; 302} 303 304static int intel_850_configure(void) 305{ 306 u32 temp; 307 u16 temp2; 308 struct aper_size_info_8 *current_size; 309 310 current_size = A_SIZE_8(agp_bridge->current_size); 311 312 /* aperture size */ 313 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 314 315 /* address to map to */ 316 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 317 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 318 319 /* attbase - aperture base */ 320 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 321 322 /* agpctrl */ 323 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 324 325 /* mcgcfg */ 326 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 327 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 328 /* clear any possible AGP-related error conditions */ 329 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 330 return 0; 331} 332 333static int intel_860_configure(void) 334{ 335 u32 temp; 336 u16 temp2; 337 struct aper_size_info_8 *current_size; 338 339 current_size = A_SIZE_8(agp_bridge->current_size); 340 341 /* aperture size */ 342 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 343 344 /* address to map to */ 345 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 346 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 347 348 /* attbase - aperture base */ 349 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 350 351 /* agpctrl */ 352 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 353 354 /* mcgcfg */ 355 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 356 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 357 /* clear any possible AGP-related error conditions */ 358 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 359 return 0; 360} 361 362static int intel_830mp_configure(void) 363{ 364 u32 temp; 365 u16 temp2; 366 struct aper_size_info_8 *current_size; 367 368 current_size = A_SIZE_8(agp_bridge->current_size); 369 370 /* aperture size */ 371 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 372 373 /* address to map to */ 374 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 375 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 376 377 /* attbase - aperture base */ 378 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 379 380 /* agpctrl */ 381 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 382 383 /* gmch */ 384 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 385 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 386 /* clear any possible AGP-related error conditions */ 387 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 388 return 0; 389} 390 391static int intel_7505_configure(void) 392{ 393 u32 temp; 394 u16 temp2; 395 struct aper_size_info_8 *current_size; 396 397 current_size = A_SIZE_8(agp_bridge->current_size); 398 399 /* aperture size */ 400 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 401 402 /* address to map to */ 403 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 404 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 405 406 /* attbase - aperture base */ 407 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 408 409 /* agpctrl */ 410 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 411 412 /* mchcfg */ 413 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 414 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 415 416 return 0; 417} 418 419/* Setup function */ 420static const struct gatt_mask intel_generic_masks[] = 421{ 422 {.mask = 0x00000017, .type = 0} 423}; 424 425static const struct aper_size_info_8 intel_815_sizes[2] = 426{ 427 {64, 16384, 4, 0}, 428 {32, 8192, 3, 8}, 429}; 430 431static const struct aper_size_info_8 intel_8xx_sizes[7] = 432{ 433 {256, 65536, 6, 0}, 434 {128, 32768, 5, 32}, 435 {64, 16384, 4, 48}, 436 {32, 8192, 3, 56}, 437 {16, 4096, 2, 60}, 438 {8, 2048, 1, 62}, 439 {4, 1024, 0, 63} 440}; 441 442static const struct aper_size_info_16 intel_generic_sizes[7] = 443{ 444 {256, 65536, 6, 0}, 445 {128, 32768, 5, 32}, 446 {64, 16384, 4, 48}, 447 {32, 8192, 3, 56}, 448 {16, 4096, 2, 60}, 449 {8, 2048, 1, 62}, 450 {4, 1024, 0, 63} 451}; 452 453static const struct aper_size_info_8 intel_830mp_sizes[4] = 454{ 455 {256, 65536, 6, 0}, 456 {128, 32768, 5, 32}, 457 {64, 16384, 4, 48}, 458 {32, 8192, 3, 56} 459}; 460 461static const struct agp_bridge_driver intel_generic_driver = { 462 .owner = THIS_MODULE, 463 .aperture_sizes = intel_generic_sizes, 464 .size_type = U16_APER_SIZE, 465 .num_aperture_sizes = 7, 466 .configure = intel_configure, 467 .fetch_size = intel_fetch_size, 468 .cleanup = intel_cleanup, 469 .tlb_flush = intel_tlbflush, 470 .mask_memory = agp_generic_mask_memory, 471 .masks = intel_generic_masks, 472 .agp_enable = agp_generic_enable, 473 .cache_flush = global_cache_flush, 474 .create_gatt_table = agp_generic_create_gatt_table, 475 .free_gatt_table = agp_generic_free_gatt_table, 476 .insert_memory = agp_generic_insert_memory, 477 .remove_memory = agp_generic_remove_memory, 478 .alloc_by_type = agp_generic_alloc_by_type, 479 .free_by_type = agp_generic_free_by_type, 480 .agp_alloc_page = agp_generic_alloc_page, 481 .agp_alloc_pages = agp_generic_alloc_pages, 482 .agp_destroy_page = agp_generic_destroy_page, 483 .agp_destroy_pages = agp_generic_destroy_pages, 484 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 485}; 486 487static const struct agp_bridge_driver intel_815_driver = { 488 .owner = THIS_MODULE, 489 .aperture_sizes = intel_815_sizes, 490 .size_type = U8_APER_SIZE, 491 .num_aperture_sizes = 2, 492 .configure = intel_815_configure, 493 .fetch_size = intel_815_fetch_size, 494 .cleanup = intel_8xx_cleanup, 495 .tlb_flush = intel_8xx_tlbflush, 496 .mask_memory = agp_generic_mask_memory, 497 .masks = intel_generic_masks, 498 .agp_enable = agp_generic_enable, 499 .cache_flush = global_cache_flush, 500 .create_gatt_table = agp_generic_create_gatt_table, 501 .free_gatt_table = agp_generic_free_gatt_table, 502 .insert_memory = agp_generic_insert_memory, 503 .remove_memory = agp_generic_remove_memory, 504 .alloc_by_type = agp_generic_alloc_by_type, 505 .free_by_type = agp_generic_free_by_type, 506 .agp_alloc_page = agp_generic_alloc_page, 507 .agp_alloc_pages = agp_generic_alloc_pages, 508 .agp_destroy_page = agp_generic_destroy_page, 509 .agp_destroy_pages = agp_generic_destroy_pages, 510 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 511}; 512 513static const struct agp_bridge_driver intel_820_driver = { 514 .owner = THIS_MODULE, 515 .aperture_sizes = intel_8xx_sizes, 516 .size_type = U8_APER_SIZE, 517 .num_aperture_sizes = 7, 518 .configure = intel_820_configure, 519 .fetch_size = intel_8xx_fetch_size, 520 .cleanup = intel_820_cleanup, 521 .tlb_flush = intel_820_tlbflush, 522 .mask_memory = agp_generic_mask_memory, 523 .masks = intel_generic_masks, 524 .agp_enable = agp_generic_enable, 525 .cache_flush = global_cache_flush, 526 .create_gatt_table = agp_generic_create_gatt_table, 527 .free_gatt_table = agp_generic_free_gatt_table, 528 .insert_memory = agp_generic_insert_memory, 529 .remove_memory = agp_generic_remove_memory, 530 .alloc_by_type = agp_generic_alloc_by_type, 531 .free_by_type = agp_generic_free_by_type, 532 .agp_alloc_page = agp_generic_alloc_page, 533 .agp_alloc_pages = agp_generic_alloc_pages, 534 .agp_destroy_page = agp_generic_destroy_page, 535 .agp_destroy_pages = agp_generic_destroy_pages, 536 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 537}; 538 539static const struct agp_bridge_driver intel_830mp_driver = { 540 .owner = THIS_MODULE, 541 .aperture_sizes = intel_830mp_sizes, 542 .size_type = U8_APER_SIZE, 543 .num_aperture_sizes = 4, 544 .configure = intel_830mp_configure, 545 .fetch_size = intel_8xx_fetch_size, 546 .cleanup = intel_8xx_cleanup, 547 .tlb_flush = intel_8xx_tlbflush, 548 .mask_memory = agp_generic_mask_memory, 549 .masks = intel_generic_masks, 550 .agp_enable = agp_generic_enable, 551 .cache_flush = global_cache_flush, 552 .create_gatt_table = agp_generic_create_gatt_table, 553 .free_gatt_table = agp_generic_free_gatt_table, 554 .insert_memory = agp_generic_insert_memory, 555 .remove_memory = agp_generic_remove_memory, 556 .alloc_by_type = agp_generic_alloc_by_type, 557 .free_by_type = agp_generic_free_by_type, 558 .agp_alloc_page = agp_generic_alloc_page, 559 .agp_alloc_pages = agp_generic_alloc_pages, 560 .agp_destroy_page = agp_generic_destroy_page, 561 .agp_destroy_pages = agp_generic_destroy_pages, 562 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 563}; 564 565static const struct agp_bridge_driver intel_840_driver = { 566 .owner = THIS_MODULE, 567 .aperture_sizes = intel_8xx_sizes, 568 .size_type = U8_APER_SIZE, 569 .num_aperture_sizes = 7, 570 .configure = intel_840_configure, 571 .fetch_size = intel_8xx_fetch_size, 572 .cleanup = intel_8xx_cleanup, 573 .tlb_flush = intel_8xx_tlbflush, 574 .mask_memory = agp_generic_mask_memory, 575 .masks = intel_generic_masks, 576 .agp_enable = agp_generic_enable, 577 .cache_flush = global_cache_flush, 578 .create_gatt_table = agp_generic_create_gatt_table, 579 .free_gatt_table = agp_generic_free_gatt_table, 580 .insert_memory = agp_generic_insert_memory, 581 .remove_memory = agp_generic_remove_memory, 582 .alloc_by_type = agp_generic_alloc_by_type, 583 .free_by_type = agp_generic_free_by_type, 584 .agp_alloc_page = agp_generic_alloc_page, 585 .agp_alloc_pages = agp_generic_alloc_pages, 586 .agp_destroy_page = agp_generic_destroy_page, 587 .agp_destroy_pages = agp_generic_destroy_pages, 588 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 589}; 590 591static const struct agp_bridge_driver intel_845_driver = { 592 .owner = THIS_MODULE, 593 .aperture_sizes = intel_8xx_sizes, 594 .size_type = U8_APER_SIZE, 595 .num_aperture_sizes = 7, 596 .configure = intel_845_configure, 597 .fetch_size = intel_8xx_fetch_size, 598 .cleanup = intel_8xx_cleanup, 599 .tlb_flush = intel_8xx_tlbflush, 600 .mask_memory = agp_generic_mask_memory, 601 .masks = intel_generic_masks, 602 .agp_enable = agp_generic_enable, 603 .cache_flush = global_cache_flush, 604 .create_gatt_table = agp_generic_create_gatt_table, 605 .free_gatt_table = agp_generic_free_gatt_table, 606 .insert_memory = agp_generic_insert_memory, 607 .remove_memory = agp_generic_remove_memory, 608 .alloc_by_type = agp_generic_alloc_by_type, 609 .free_by_type = agp_generic_free_by_type, 610 .agp_alloc_page = agp_generic_alloc_page, 611 .agp_alloc_pages = agp_generic_alloc_pages, 612 .agp_destroy_page = agp_generic_destroy_page, 613 .agp_destroy_pages = agp_generic_destroy_pages, 614 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 615}; 616 617static const struct agp_bridge_driver intel_850_driver = { 618 .owner = THIS_MODULE, 619 .aperture_sizes = intel_8xx_sizes, 620 .size_type = U8_APER_SIZE, 621 .num_aperture_sizes = 7, 622 .configure = intel_850_configure, 623 .fetch_size = intel_8xx_fetch_size, 624 .cleanup = intel_8xx_cleanup, 625 .tlb_flush = intel_8xx_tlbflush, 626 .mask_memory = agp_generic_mask_memory, 627 .masks = intel_generic_masks, 628 .agp_enable = agp_generic_enable, 629 .cache_flush = global_cache_flush, 630 .create_gatt_table = agp_generic_create_gatt_table, 631 .free_gatt_table = agp_generic_free_gatt_table, 632 .insert_memory = agp_generic_insert_memory, 633 .remove_memory = agp_generic_remove_memory, 634 .alloc_by_type = agp_generic_alloc_by_type, 635 .free_by_type = agp_generic_free_by_type, 636 .agp_alloc_page = agp_generic_alloc_page, 637 .agp_alloc_pages = agp_generic_alloc_pages, 638 .agp_destroy_page = agp_generic_destroy_page, 639 .agp_destroy_pages = agp_generic_destroy_pages, 640 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 641}; 642 643static const struct agp_bridge_driver intel_860_driver = { 644 .owner = THIS_MODULE, 645 .aperture_sizes = intel_8xx_sizes, 646 .size_type = U8_APER_SIZE, 647 .num_aperture_sizes = 7, 648 .configure = intel_860_configure, 649 .fetch_size = intel_8xx_fetch_size, 650 .cleanup = intel_8xx_cleanup, 651 .tlb_flush = intel_8xx_tlbflush, 652 .mask_memory = agp_generic_mask_memory, 653 .masks = intel_generic_masks, 654 .agp_enable = agp_generic_enable, 655 .cache_flush = global_cache_flush, 656 .create_gatt_table = agp_generic_create_gatt_table, 657 .free_gatt_table = agp_generic_free_gatt_table, 658 .insert_memory = agp_generic_insert_memory, 659 .remove_memory = agp_generic_remove_memory, 660 .alloc_by_type = agp_generic_alloc_by_type, 661 .free_by_type = agp_generic_free_by_type, 662 .agp_alloc_page = agp_generic_alloc_page, 663 .agp_alloc_pages = agp_generic_alloc_pages, 664 .agp_destroy_page = agp_generic_destroy_page, 665 .agp_destroy_pages = agp_generic_destroy_pages, 666 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 667}; 668 669static const struct agp_bridge_driver intel_7505_driver = { 670 .owner = THIS_MODULE, 671 .aperture_sizes = intel_8xx_sizes, 672 .size_type = U8_APER_SIZE, 673 .num_aperture_sizes = 7, 674 .configure = intel_7505_configure, 675 .fetch_size = intel_8xx_fetch_size, 676 .cleanup = intel_8xx_cleanup, 677 .tlb_flush = intel_8xx_tlbflush, 678 .mask_memory = agp_generic_mask_memory, 679 .masks = intel_generic_masks, 680 .agp_enable = agp_generic_enable, 681 .cache_flush = global_cache_flush, 682 .create_gatt_table = agp_generic_create_gatt_table, 683 .free_gatt_table = agp_generic_free_gatt_table, 684 .insert_memory = agp_generic_insert_memory, 685 .remove_memory = agp_generic_remove_memory, 686 .alloc_by_type = agp_generic_alloc_by_type, 687 .free_by_type = agp_generic_free_by_type, 688 .agp_alloc_page = agp_generic_alloc_page, 689 .agp_alloc_pages = agp_generic_alloc_pages, 690 .agp_destroy_page = agp_generic_destroy_page, 691 .agp_destroy_pages = agp_generic_destroy_pages, 692 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 693}; 694 695static int find_gmch(u16 device) 696{ 697 struct pci_dev *gmch_device; 698 699 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 700 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 701 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 702 device, gmch_device); 703 } 704 705 if (!gmch_device) 706 return 0; 707 708 intel_private.pcidev = gmch_device; 709 return 1; 710} 711 712/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 713 * driver and gmch_driver must be non-null, and find_gmch will determine 714 * which one should be used if a gmch_chip_id is present. 715 */ 716static const struct intel_driver_description { 717 unsigned int chip_id; 718 unsigned int gmch_chip_id; 719 char *name; 720 const struct agp_bridge_driver *driver; 721 const struct agp_bridge_driver *gmch_driver; 722} intel_agp_chipsets[] = { 723 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL }, 724 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL }, 725 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL }, 726 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 727 NULL, &intel_810_driver }, 728 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 729 NULL, &intel_810_driver }, 730 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 731 NULL, &intel_810_driver }, 732 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 733 &intel_815_driver, &intel_810_driver }, 734 { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL }, 735 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL }, 736 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 737 &intel_830mp_driver, &intel_830_driver }, 738 { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL }, 739 { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL }, 740 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 741 &intel_845_driver, &intel_830_driver }, 742 { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL }, 743 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854", 744 &intel_845_driver, &intel_830_driver }, 745 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL }, 746 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 747 &intel_845_driver, &intel_830_driver }, 748 { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL }, 749 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865", 750 &intel_845_driver, &intel_830_driver }, 751 { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL }, 752 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 753 NULL, &intel_915_driver }, 754 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 755 NULL, &intel_915_driver }, 756 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 757 NULL, &intel_915_driver }, 758 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 759 NULL, &intel_915_driver }, 760 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 761 NULL, &intel_915_driver }, 762 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 763 NULL, &intel_915_driver }, 764 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 765 NULL, &intel_i965_driver }, 766 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 767 NULL, &intel_i965_driver }, 768 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 769 NULL, &intel_i965_driver }, 770 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 771 NULL, &intel_i965_driver }, 772 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 773 NULL, &intel_i965_driver }, 774 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 775 NULL, &intel_i965_driver }, 776 { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL }, 777 { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL }, 778 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33", 779 NULL, &intel_g33_driver }, 780 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 781 NULL, &intel_g33_driver }, 782 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 783 NULL, &intel_g33_driver }, 784 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 785 NULL, &intel_g33_driver }, 786 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 787 NULL, &intel_g33_driver }, 788 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 789 "GM45", NULL, &intel_i965_driver }, 790 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 791 "Eaglelake", NULL, &intel_i965_driver }, 792 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 793 "Q45/Q43", NULL, &intel_i965_driver }, 794 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 795 "G45/G43", NULL, &intel_i965_driver }, 796 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 797 "B43", NULL, &intel_i965_driver }, 798 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 799 "G41", NULL, &intel_i965_driver }, 800 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 801 "HD Graphics", NULL, &intel_i965_driver }, 802 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 803 "HD Graphics", NULL, &intel_i965_driver }, 804 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 805 "HD Graphics", NULL, &intel_i965_driver }, 806 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 807 "HD Graphics", NULL, &intel_i965_driver }, 808 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 809 "Sandybridge", NULL, &intel_i965_driver }, 810 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 811 "Sandybridge", NULL, &intel_i965_driver }, 812 { 0, 0, NULL, NULL, NULL } 813}; 814 815static int __devinit intel_gmch_probe(struct pci_dev *pdev, 816 struct agp_bridge_data *bridge) 817{ 818 int i; 819 bridge->driver = NULL; 820 821 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 822 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 823 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 824 bridge->driver = 825 intel_agp_chipsets[i].gmch_driver; 826 break; 827 } 828 } 829 830 if (!bridge->driver) 831 return 0; 832 833 bridge->dev_private_data = &intel_private; 834 bridge->dev = pdev; 835 836 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 837 838 if (bridge->driver->mask_memory == intel_i965_mask_memory) { 839 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) 840 dev_err(&intel_private.pcidev->dev, 841 "set gfx device dma mask 36bit failed!\n"); 842 else 843 pci_set_consistent_dma_mask(intel_private.pcidev, 844 DMA_BIT_MASK(36)); 845 } 846 847 return 1; 848} 849 850static int __devinit agp_intel_probe(struct pci_dev *pdev, 851 const struct pci_device_id *ent) 852{ 853 struct agp_bridge_data *bridge; 854 u8 cap_ptr = 0; 855 struct resource *r; 856 int i, err; 857 858 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 859 860 bridge = agp_alloc_bridge(); 861 if (!bridge) 862 return -ENOMEM; 863 864 bridge->capndx = cap_ptr; 865 866 if (intel_gmch_probe(pdev, bridge)) 867 goto found_gmch; 868 869 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 870 /* In case that multiple models of gfx chip may 871 stand on same host bridge type, this can be 872 sure we detect the right IGD. */ 873 if (pdev->device == intel_agp_chipsets[i].chip_id) { 874 bridge->driver = intel_agp_chipsets[i].driver; 875 break; 876 } 877 } 878 879 if (intel_agp_chipsets[i].name == NULL) { 880 if (cap_ptr) 881 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 882 pdev->vendor, pdev->device); 883 agp_put_bridge(bridge); 884 return -ENODEV; 885 } 886 887 bridge->dev = pdev; 888 bridge->dev_private_data = NULL; 889 890 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 891 892 /* 893 * The following fixes the case where the BIOS has "forgotten" to 894 * provide an address range for the GART. 895 * 20030610 - hamish@zot.org 896 */ 897 r = &pdev->resource[0]; 898 if (!r->start && r->end) { 899 if (pci_assign_resource(pdev, 0)) { 900 dev_err(&pdev->dev, "can't assign resource 0\n"); 901 agp_put_bridge(bridge); 902 return -ENODEV; 903 } 904 } 905 906 /* 907 * If the device has not been properly setup, the following will catch 908 * the problem and should stop the system from crashing. 909 * 20030610 - hamish@zot.org 910 */ 911 if (pci_enable_device(pdev)) { 912 dev_err(&pdev->dev, "can't enable PCI device\n"); 913 agp_put_bridge(bridge); 914 return -ENODEV; 915 } 916 917 /* Fill in the mode register */ 918 if (cap_ptr) { 919 pci_read_config_dword(pdev, 920 bridge->capndx+PCI_AGP_STATUS, 921 &bridge->mode); 922 } 923 924found_gmch: 925 pci_set_drvdata(pdev, bridge); 926 err = agp_add_bridge(bridge); 927 if (!err) 928 intel_agp_enabled = 1; 929 return err; 930} 931 932static void __devexit agp_intel_remove(struct pci_dev *pdev) 933{ 934 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 935 936 agp_remove_bridge(bridge); 937 938 if (intel_private.pcidev) 939 pci_dev_put(intel_private.pcidev); 940 941 agp_put_bridge(bridge); 942} 943 944#ifdef CONFIG_PM 945static int agp_intel_resume(struct pci_dev *pdev) 946{ 947 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 948 int ret_val; 949 950 bridge->driver->configure(); 951 952 ret_val = agp_rebind_memory(); 953 if (ret_val != 0) 954 return ret_val; 955 956 return 0; 957} 958#endif 959 960static struct pci_device_id agp_intel_pci_table[] = { 961#define ID(x) \ 962 { \ 963 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 964 .class_mask = ~0, \ 965 .vendor = PCI_VENDOR_ID_INTEL, \ 966 .device = x, \ 967 .subvendor = PCI_ANY_ID, \ 968 .subdevice = PCI_ANY_ID, \ 969 } 970 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 971 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 972 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 973 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 974 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 975 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 976 ID(PCI_DEVICE_ID_INTEL_82815_MC), 977 ID(PCI_DEVICE_ID_INTEL_82820_HB), 978 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 979 ID(PCI_DEVICE_ID_INTEL_82830_HB), 980 ID(PCI_DEVICE_ID_INTEL_82840_HB), 981 ID(PCI_DEVICE_ID_INTEL_82845_HB), 982 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 983 ID(PCI_DEVICE_ID_INTEL_82850_HB), 984 ID(PCI_DEVICE_ID_INTEL_82854_HB), 985 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 986 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 987 ID(PCI_DEVICE_ID_INTEL_82860_HB), 988 ID(PCI_DEVICE_ID_INTEL_82865_HB), 989 ID(PCI_DEVICE_ID_INTEL_82875_HB), 990 ID(PCI_DEVICE_ID_INTEL_7505_0), 991 ID(PCI_DEVICE_ID_INTEL_7205_0), 992 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 993 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 994 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 995 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 996 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 997 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 998 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB), 999 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB), 1000 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 1001 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 1002 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 1003 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 1004 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 1005 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 1006 ID(PCI_DEVICE_ID_INTEL_G33_HB), 1007 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 1008 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 1009 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 1010 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB), 1011 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 1012 ID(PCI_DEVICE_ID_INTEL_G45_HB), 1013 ID(PCI_DEVICE_ID_INTEL_G41_HB), 1014 ID(PCI_DEVICE_ID_INTEL_B43_HB), 1015 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), 1016 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), 1017 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), 1018 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), 1019 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), 1020 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), 1021 { } 1022}; 1023 1024MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 1025 1026static struct pci_driver agp_intel_pci_driver = { 1027 .name = "agpgart-intel", 1028 .id_table = agp_intel_pci_table, 1029 .probe = agp_intel_probe, 1030 .remove = __devexit_p(agp_intel_remove), 1031#ifdef CONFIG_PM 1032 .resume = agp_intel_resume, 1033#endif 1034}; 1035 1036static int __init agp_intel_init(void) 1037{ 1038 if (agp_off) 1039 return -EINVAL; 1040 return pci_register_driver(&agp_intel_pci_driver); 1041} 1042 1043static void __exit agp_intel_cleanup(void) 1044{ 1045 pci_unregister_driver(&agp_intel_pci_driver); 1046} 1047 1048module_init(agp_intel_init); 1049module_exit(agp_intel_cleanup); 1050 1051MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1052MODULE_LICENSE("GPL and additional rights"); 1053