intel-agp.c revision 38d8a95621b20ed7868e232a35a26ee61bdcae6f
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include "agp.h" 12 13#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 15#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 17#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 19#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 23#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 25#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 26#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 27#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 28#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 29#define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 30#define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 31#define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 32#define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 33#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 34#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 35#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 36#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 37#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 38#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 39#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 40#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 41#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 42#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 43#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 44#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 45#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 46#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 47#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 48#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 49#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 50#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 51#define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 52#define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 53#define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 54#define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062 55#define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 56 57/* cover 915 and 945 variants */ 58#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 59 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 63 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 64 65#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 67 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 70 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 71 72#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ 75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 77 78#define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ 79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) 80 81#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ 82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ 87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ 88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \ 89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB) 90 91extern int agp_memory_reserved; 92 93 94/* Intel 815 register */ 95#define INTEL_815_APCONT 0x51 96#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 97 98/* Intel i820 registers */ 99#define INTEL_I820_RDCR 0x51 100#define INTEL_I820_ERRSTS 0xc8 101 102/* Intel i840 registers */ 103#define INTEL_I840_MCHCFG 0x50 104#define INTEL_I840_ERRSTS 0xc8 105 106/* Intel i850 registers */ 107#define INTEL_I850_MCHCFG 0x50 108#define INTEL_I850_ERRSTS 0xc8 109 110/* intel 915G registers */ 111#define I915_GMADDR 0x18 112#define I915_MMADDR 0x10 113#define I915_PTEADDR 0x1C 114#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 115#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 116#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 117#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 118#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 119#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 120#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 121#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 122 123#define I915_IFPADDR 0x60 124 125/* Intel 965G registers */ 126#define I965_MSAC 0x62 127#define I965_IFPADDR 0x70 128 129/* Intel 7505 registers */ 130#define INTEL_I7505_APSIZE 0x74 131#define INTEL_I7505_NCAPID 0x60 132#define INTEL_I7505_NISTAT 0x6c 133#define INTEL_I7505_ATTBASE 0x78 134#define INTEL_I7505_ERRSTS 0x42 135#define INTEL_I7505_AGPCTRL 0x70 136#define INTEL_I7505_MCHCFG 0x50 137 138static const struct aper_size_info_fixed intel_i810_sizes[] = 139{ 140 {64, 16384, 4}, 141 /* The 32M mode still requires a 64k gatt */ 142 {32, 8192, 4} 143}; 144 145#define AGP_DCACHE_MEMORY 1 146#define AGP_PHYS_MEMORY 2 147#define INTEL_AGP_CACHED_MEMORY 3 148 149static struct gatt_mask intel_i810_masks[] = 150{ 151 {.mask = I810_PTE_VALID, .type = 0}, 152 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 153 {.mask = I810_PTE_VALID, .type = 0}, 154 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 155 .type = INTEL_AGP_CACHED_MEMORY} 156}; 157 158static struct _intel_private { 159 struct pci_dev *pcidev; /* device one */ 160 u8 __iomem *registers; 161 u32 __iomem *gtt; /* I915G */ 162 int num_dcache_entries; 163 /* gtt_entries is the number of gtt entries that are already mapped 164 * to stolen memory. Stolen memory is larger than the memory mapped 165 * through gtt_entries, as it includes some reserved space for the BIOS 166 * popup and for the GTT. 167 */ 168 int gtt_entries; /* i830+ */ 169 union { 170 void __iomem *i9xx_flush_page; 171 void *i8xx_flush_page; 172 }; 173 struct page *i8xx_page; 174 struct resource ifp_resource; 175 int resource_valid; 176} intel_private; 177 178static int intel_i810_fetch_size(void) 179{ 180 u32 smram_miscc; 181 struct aper_size_info_fixed *values; 182 183 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 184 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 185 186 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 187 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 188 return 0; 189 } 190 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 191 agp_bridge->previous_size = 192 agp_bridge->current_size = (void *) (values + 1); 193 agp_bridge->aperture_size_idx = 1; 194 return values[1].size; 195 } else { 196 agp_bridge->previous_size = 197 agp_bridge->current_size = (void *) (values); 198 agp_bridge->aperture_size_idx = 0; 199 return values[0].size; 200 } 201 202 return 0; 203} 204 205static int intel_i810_configure(void) 206{ 207 struct aper_size_info_fixed *current_size; 208 u32 temp; 209 int i; 210 211 current_size = A_SIZE_FIX(agp_bridge->current_size); 212 213 if (!intel_private.registers) { 214 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 215 temp &= 0xfff80000; 216 217 intel_private.registers = ioremap(temp, 128 * 4096); 218 if (!intel_private.registers) { 219 dev_err(&intel_private.pcidev->dev, 220 "can't remap memory\n"); 221 return -ENOMEM; 222 } 223 } 224 225 if ((readl(intel_private.registers+I810_DRAM_CTL) 226 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 227 /* This will need to be dynamically assigned */ 228 dev_info(&intel_private.pcidev->dev, 229 "detected 4MB dedicated video ram\n"); 230 intel_private.num_dcache_entries = 1024; 231 } 232 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 233 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 234 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 235 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 236 237 if (agp_bridge->driver->needs_scratch_page) { 238 for (i = 0; i < current_size->num_entries; i++) { 239 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 240 } 241 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 242 } 243 global_cache_flush(); 244 return 0; 245} 246 247static void intel_i810_cleanup(void) 248{ 249 writel(0, intel_private.registers+I810_PGETBL_CTL); 250 readl(intel_private.registers); /* PCI Posting. */ 251 iounmap(intel_private.registers); 252} 253 254static void intel_i810_tlbflush(struct agp_memory *mem) 255{ 256 return; 257} 258 259static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 260{ 261 return; 262} 263 264/* Exists to support ARGB cursors */ 265static struct page *i8xx_alloc_pages(void) 266{ 267 struct page *page; 268 269 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 270 if (page == NULL) 271 return NULL; 272 273 if (set_pages_uc(page, 4) < 0) { 274 set_pages_wb(page, 4); 275 __free_pages(page, 2); 276 return NULL; 277 } 278 get_page(page); 279 atomic_inc(&agp_bridge->current_memory_agp); 280 return page; 281} 282 283static void i8xx_destroy_pages(struct page *page) 284{ 285 if (page == NULL) 286 return; 287 288 set_pages_wb(page, 4); 289 put_page(page); 290 __free_pages(page, 2); 291 atomic_dec(&agp_bridge->current_memory_agp); 292} 293 294static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 295 int type) 296{ 297 if (type < AGP_USER_TYPES) 298 return type; 299 else if (type == AGP_USER_CACHED_MEMORY) 300 return INTEL_AGP_CACHED_MEMORY; 301 else 302 return 0; 303} 304 305static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 306 int type) 307{ 308 int i, j, num_entries; 309 void *temp; 310 int ret = -EINVAL; 311 int mask_type; 312 313 if (mem->page_count == 0) 314 goto out; 315 316 temp = agp_bridge->current_size; 317 num_entries = A_SIZE_FIX(temp)->num_entries; 318 319 if ((pg_start + mem->page_count) > num_entries) 320 goto out_err; 321 322 323 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 324 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 325 ret = -EBUSY; 326 goto out_err; 327 } 328 } 329 330 if (type != mem->type) 331 goto out_err; 332 333 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 334 335 switch (mask_type) { 336 case AGP_DCACHE_MEMORY: 337 if (!mem->is_flushed) 338 global_cache_flush(); 339 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 340 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 341 intel_private.registers+I810_PTE_BASE+(i*4)); 342 } 343 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 344 break; 345 case AGP_PHYS_MEMORY: 346 case AGP_NORMAL_MEMORY: 347 if (!mem->is_flushed) 348 global_cache_flush(); 349 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 350 writel(agp_bridge->driver->mask_memory(agp_bridge, 351 mem->pages[i], 352 mask_type), 353 intel_private.registers+I810_PTE_BASE+(j*4)); 354 } 355 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 356 break; 357 default: 358 goto out_err; 359 } 360 361 agp_bridge->driver->tlb_flush(mem); 362out: 363 ret = 0; 364out_err: 365 mem->is_flushed = true; 366 return ret; 367} 368 369static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 370 int type) 371{ 372 int i; 373 374 if (mem->page_count == 0) 375 return 0; 376 377 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 378 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 379 } 380 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 381 382 agp_bridge->driver->tlb_flush(mem); 383 return 0; 384} 385 386/* 387 * The i810/i830 requires a physical address to program its mouse 388 * pointer into hardware. 389 * However the Xserver still writes to it through the agp aperture. 390 */ 391static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 392{ 393 struct agp_memory *new; 394 struct page *page; 395 396 switch (pg_count) { 397 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 398 break; 399 case 4: 400 /* kludge to get 4 physical pages for ARGB cursor */ 401 page = i8xx_alloc_pages(); 402 break; 403 default: 404 return NULL; 405 } 406 407 if (page == NULL) 408 return NULL; 409 410 new = agp_create_memory(pg_count); 411 if (new == NULL) 412 return NULL; 413 414 new->pages[0] = page; 415 if (pg_count == 4) { 416 /* kludge to get 4 physical pages for ARGB cursor */ 417 new->pages[1] = new->pages[0] + 1; 418 new->pages[2] = new->pages[1] + 1; 419 new->pages[3] = new->pages[2] + 1; 420 } 421 new->page_count = pg_count; 422 new->num_scratch_pages = pg_count; 423 new->type = AGP_PHYS_MEMORY; 424 new->physical = page_to_phys(new->pages[0]); 425 return new; 426} 427 428static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 429{ 430 struct agp_memory *new; 431 432 if (type == AGP_DCACHE_MEMORY) { 433 if (pg_count != intel_private.num_dcache_entries) 434 return NULL; 435 436 new = agp_create_memory(1); 437 if (new == NULL) 438 return NULL; 439 440 new->type = AGP_DCACHE_MEMORY; 441 new->page_count = pg_count; 442 new->num_scratch_pages = 0; 443 agp_free_page_array(new); 444 return new; 445 } 446 if (type == AGP_PHYS_MEMORY) 447 return alloc_agpphysmem_i8xx(pg_count, type); 448 return NULL; 449} 450 451static void intel_i810_free_by_type(struct agp_memory *curr) 452{ 453 agp_free_key(curr->key); 454 if (curr->type == AGP_PHYS_MEMORY) { 455 if (curr->page_count == 4) 456 i8xx_destroy_pages(curr->pages[0]); 457 else { 458 agp_bridge->driver->agp_destroy_page(curr->pages[0], 459 AGP_PAGE_DESTROY_UNMAP); 460 agp_bridge->driver->agp_destroy_page(curr->pages[0], 461 AGP_PAGE_DESTROY_FREE); 462 } 463 agp_free_page_array(curr); 464 } 465 kfree(curr); 466} 467 468static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 469 struct page *page, int type) 470{ 471 unsigned long addr = phys_to_gart(page_to_phys(page)); 472 /* Type checking must be done elsewhere */ 473 return addr | bridge->driver->masks[type].mask; 474} 475 476static struct aper_size_info_fixed intel_i830_sizes[] = 477{ 478 {128, 32768, 5}, 479 /* The 64M mode still requires a 128k gatt */ 480 {64, 16384, 5}, 481 {256, 65536, 6}, 482 {512, 131072, 7}, 483}; 484 485static void intel_i830_init_gtt_entries(void) 486{ 487 u16 gmch_ctrl; 488 int gtt_entries; 489 u8 rdct; 490 int local = 0; 491 static const int ddt[4] = { 0, 16, 32, 64 }; 492 int size; /* reserved space (in kb) at the top of stolen memory */ 493 494 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 495 496 if (IS_I965) { 497 u32 pgetbl_ctl; 498 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 499 500 /* The 965 has a field telling us the size of the GTT, 501 * which may be larger than what is necessary to map the 502 * aperture. 503 */ 504 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 505 case I965_PGETBL_SIZE_128KB: 506 size = 128; 507 break; 508 case I965_PGETBL_SIZE_256KB: 509 size = 256; 510 break; 511 case I965_PGETBL_SIZE_512KB: 512 size = 512; 513 break; 514 case I965_PGETBL_SIZE_1MB: 515 size = 1024; 516 break; 517 case I965_PGETBL_SIZE_2MB: 518 size = 2048; 519 break; 520 case I965_PGETBL_SIZE_1_5MB: 521 size = 1024 + 512; 522 break; 523 default: 524 dev_info(&intel_private.pcidev->dev, 525 "unknown page table size, assuming 512KB\n"); 526 size = 512; 527 } 528 size += 4; /* add in BIOS popup space */ 529 } else if (IS_G33 && !IS_IGD) { 530 /* G33's GTT size defined in gmch_ctrl */ 531 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 532 case G33_PGETBL_SIZE_1M: 533 size = 1024; 534 break; 535 case G33_PGETBL_SIZE_2M: 536 size = 2048; 537 break; 538 default: 539 dev_info(&agp_bridge->dev->dev, 540 "unknown page table size 0x%x, assuming 512KB\n", 541 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 542 size = 512; 543 } 544 size += 4; 545 } else if (IS_G4X || IS_IGD) { 546 /* On 4 series hardware, GTT stolen is separate from graphics 547 * stolen, ignore it in stolen gtt entries counting. However, 548 * 4KB of the stolen memory doesn't get mapped to the GTT. 549 */ 550 size = 4; 551 } else { 552 /* On previous hardware, the GTT size was just what was 553 * required to map the aperture. 554 */ 555 size = agp_bridge->driver->fetch_size() + 4; 556 } 557 558 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 559 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 560 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 561 case I830_GMCH_GMS_STOLEN_512: 562 gtt_entries = KB(512) - KB(size); 563 break; 564 case I830_GMCH_GMS_STOLEN_1024: 565 gtt_entries = MB(1) - KB(size); 566 break; 567 case I830_GMCH_GMS_STOLEN_8192: 568 gtt_entries = MB(8) - KB(size); 569 break; 570 case I830_GMCH_GMS_LOCAL: 571 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 572 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 573 MB(ddt[I830_RDRAM_DDT(rdct)]); 574 local = 1; 575 break; 576 default: 577 gtt_entries = 0; 578 break; 579 } 580 } else { 581 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 582 case I855_GMCH_GMS_STOLEN_1M: 583 gtt_entries = MB(1) - KB(size); 584 break; 585 case I855_GMCH_GMS_STOLEN_4M: 586 gtt_entries = MB(4) - KB(size); 587 break; 588 case I855_GMCH_GMS_STOLEN_8M: 589 gtt_entries = MB(8) - KB(size); 590 break; 591 case I855_GMCH_GMS_STOLEN_16M: 592 gtt_entries = MB(16) - KB(size); 593 break; 594 case I855_GMCH_GMS_STOLEN_32M: 595 gtt_entries = MB(32) - KB(size); 596 break; 597 case I915_GMCH_GMS_STOLEN_48M: 598 /* Check it's really I915G */ 599 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 600 gtt_entries = MB(48) - KB(size); 601 else 602 gtt_entries = 0; 603 break; 604 case I915_GMCH_GMS_STOLEN_64M: 605 /* Check it's really I915G */ 606 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 607 gtt_entries = MB(64) - KB(size); 608 else 609 gtt_entries = 0; 610 break; 611 case G33_GMCH_GMS_STOLEN_128M: 612 if (IS_G33 || IS_I965 || IS_G4X) 613 gtt_entries = MB(128) - KB(size); 614 else 615 gtt_entries = 0; 616 break; 617 case G33_GMCH_GMS_STOLEN_256M: 618 if (IS_G33 || IS_I965 || IS_G4X) 619 gtt_entries = MB(256) - KB(size); 620 else 621 gtt_entries = 0; 622 break; 623 case INTEL_GMCH_GMS_STOLEN_96M: 624 if (IS_I965 || IS_G4X) 625 gtt_entries = MB(96) - KB(size); 626 else 627 gtt_entries = 0; 628 break; 629 case INTEL_GMCH_GMS_STOLEN_160M: 630 if (IS_I965 || IS_G4X) 631 gtt_entries = MB(160) - KB(size); 632 else 633 gtt_entries = 0; 634 break; 635 case INTEL_GMCH_GMS_STOLEN_224M: 636 if (IS_I965 || IS_G4X) 637 gtt_entries = MB(224) - KB(size); 638 else 639 gtt_entries = 0; 640 break; 641 case INTEL_GMCH_GMS_STOLEN_352M: 642 if (IS_I965 || IS_G4X) 643 gtt_entries = MB(352) - KB(size); 644 else 645 gtt_entries = 0; 646 break; 647 default: 648 gtt_entries = 0; 649 break; 650 } 651 } 652 if (gtt_entries > 0) { 653 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 654 gtt_entries / KB(1), local ? "local" : "stolen"); 655 gtt_entries /= KB(4); 656 } else { 657 dev_info(&agp_bridge->dev->dev, 658 "no pre-allocated video memory detected\n"); 659 gtt_entries = 0; 660 } 661 662 intel_private.gtt_entries = gtt_entries; 663} 664 665static void intel_i830_fini_flush(void) 666{ 667 kunmap(intel_private.i8xx_page); 668 intel_private.i8xx_flush_page = NULL; 669 unmap_page_from_agp(intel_private.i8xx_page); 670 671 __free_page(intel_private.i8xx_page); 672 intel_private.i8xx_page = NULL; 673} 674 675static void intel_i830_setup_flush(void) 676{ 677 /* return if we've already set the flush mechanism up */ 678 if (intel_private.i8xx_page) 679 return; 680 681 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 682 if (!intel_private.i8xx_page) 683 return; 684 685 /* make page uncached */ 686 map_page_into_agp(intel_private.i8xx_page); 687 688 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 689 if (!intel_private.i8xx_flush_page) 690 intel_i830_fini_flush(); 691} 692 693static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 694{ 695 unsigned int *pg = intel_private.i8xx_flush_page; 696 int i; 697 698 for (i = 0; i < 256; i += 2) 699 *(pg + i) = i; 700 701 wmb(); 702} 703 704/* The intel i830 automatically initializes the agp aperture during POST. 705 * Use the memory already set aside for in the GTT. 706 */ 707static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 708{ 709 int page_order; 710 struct aper_size_info_fixed *size; 711 int num_entries; 712 u32 temp; 713 714 size = agp_bridge->current_size; 715 page_order = size->page_order; 716 num_entries = size->num_entries; 717 agp_bridge->gatt_table_real = NULL; 718 719 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 720 temp &= 0xfff80000; 721 722 intel_private.registers = ioremap(temp, 128 * 4096); 723 if (!intel_private.registers) 724 return -ENOMEM; 725 726 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 727 global_cache_flush(); /* FIXME: ?? */ 728 729 /* we have to call this as early as possible after the MMIO base address is known */ 730 intel_i830_init_gtt_entries(); 731 732 agp_bridge->gatt_table = NULL; 733 734 agp_bridge->gatt_bus_addr = temp; 735 736 return 0; 737} 738 739/* Return the gatt table to a sane state. Use the top of stolen 740 * memory for the GTT. 741 */ 742static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 743{ 744 return 0; 745} 746 747static int intel_i830_fetch_size(void) 748{ 749 u16 gmch_ctrl; 750 struct aper_size_info_fixed *values; 751 752 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 753 754 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 755 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 756 /* 855GM/852GM/865G has 128MB aperture size */ 757 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 758 agp_bridge->aperture_size_idx = 0; 759 return values[0].size; 760 } 761 762 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 763 764 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 765 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 766 agp_bridge->aperture_size_idx = 0; 767 return values[0].size; 768 } else { 769 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 770 agp_bridge->aperture_size_idx = 1; 771 return values[1].size; 772 } 773 774 return 0; 775} 776 777static int intel_i830_configure(void) 778{ 779 struct aper_size_info_fixed *current_size; 780 u32 temp; 781 u16 gmch_ctrl; 782 int i; 783 784 current_size = A_SIZE_FIX(agp_bridge->current_size); 785 786 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 787 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 788 789 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 790 gmch_ctrl |= I830_GMCH_ENABLED; 791 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 792 793 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 794 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 795 796 if (agp_bridge->driver->needs_scratch_page) { 797 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 798 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 799 } 800 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 801 } 802 803 global_cache_flush(); 804 805 intel_i830_setup_flush(); 806 return 0; 807} 808 809static void intel_i830_cleanup(void) 810{ 811 iounmap(intel_private.registers); 812} 813 814static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 815 int type) 816{ 817 int i, j, num_entries; 818 void *temp; 819 int ret = -EINVAL; 820 int mask_type; 821 822 if (mem->page_count == 0) 823 goto out; 824 825 temp = agp_bridge->current_size; 826 num_entries = A_SIZE_FIX(temp)->num_entries; 827 828 if (pg_start < intel_private.gtt_entries) { 829 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 830 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 831 pg_start, intel_private.gtt_entries); 832 833 dev_info(&intel_private.pcidev->dev, 834 "trying to insert into local/stolen memory\n"); 835 goto out_err; 836 } 837 838 if ((pg_start + mem->page_count) > num_entries) 839 goto out_err; 840 841 /* The i830 can't check the GTT for entries since its read only, 842 * depend on the caller to make the correct offset decisions. 843 */ 844 845 if (type != mem->type) 846 goto out_err; 847 848 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 849 850 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 851 mask_type != INTEL_AGP_CACHED_MEMORY) 852 goto out_err; 853 854 if (!mem->is_flushed) 855 global_cache_flush(); 856 857 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 858 writel(agp_bridge->driver->mask_memory(agp_bridge, 859 mem->pages[i], mask_type), 860 intel_private.registers+I810_PTE_BASE+(j*4)); 861 } 862 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 863 agp_bridge->driver->tlb_flush(mem); 864 865out: 866 ret = 0; 867out_err: 868 mem->is_flushed = true; 869 return ret; 870} 871 872static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 873 int type) 874{ 875 int i; 876 877 if (mem->page_count == 0) 878 return 0; 879 880 if (pg_start < intel_private.gtt_entries) { 881 dev_info(&intel_private.pcidev->dev, 882 "trying to disable local/stolen memory\n"); 883 return -EINVAL; 884 } 885 886 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 887 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 888 } 889 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 890 891 agp_bridge->driver->tlb_flush(mem); 892 return 0; 893} 894 895static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 896{ 897 if (type == AGP_PHYS_MEMORY) 898 return alloc_agpphysmem_i8xx(pg_count, type); 899 /* always return NULL for other allocation types for now */ 900 return NULL; 901} 902 903static int intel_alloc_chipset_flush_resource(void) 904{ 905 int ret; 906 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 907 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 908 pcibios_align_resource, agp_bridge->dev); 909 910 return ret; 911} 912 913static void intel_i915_setup_chipset_flush(void) 914{ 915 int ret; 916 u32 temp; 917 918 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 919 if (!(temp & 0x1)) { 920 intel_alloc_chipset_flush_resource(); 921 intel_private.resource_valid = 1; 922 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 923 } else { 924 temp &= ~1; 925 926 intel_private.resource_valid = 1; 927 intel_private.ifp_resource.start = temp; 928 intel_private.ifp_resource.end = temp + PAGE_SIZE; 929 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 930 /* some BIOSes reserve this area in a pnp some don't */ 931 if (ret) 932 intel_private.resource_valid = 0; 933 } 934} 935 936static void intel_i965_g33_setup_chipset_flush(void) 937{ 938 u32 temp_hi, temp_lo; 939 int ret; 940 941 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 942 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 943 944 if (!(temp_lo & 0x1)) { 945 946 intel_alloc_chipset_flush_resource(); 947 948 intel_private.resource_valid = 1; 949 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 950 upper_32_bits(intel_private.ifp_resource.start)); 951 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 952 } else { 953 u64 l64; 954 955 temp_lo &= ~0x1; 956 l64 = ((u64)temp_hi << 32) | temp_lo; 957 958 intel_private.resource_valid = 1; 959 intel_private.ifp_resource.start = l64; 960 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 961 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 962 /* some BIOSes reserve this area in a pnp some don't */ 963 if (ret) 964 intel_private.resource_valid = 0; 965 } 966} 967 968static void intel_i9xx_setup_flush(void) 969{ 970 /* return if already configured */ 971 if (intel_private.ifp_resource.start) 972 return; 973 974 /* setup a resource for this object */ 975 intel_private.ifp_resource.name = "Intel Flush Page"; 976 intel_private.ifp_resource.flags = IORESOURCE_MEM; 977 978 /* Setup chipset flush for 915 */ 979 if (IS_I965 || IS_G33 || IS_G4X) { 980 intel_i965_g33_setup_chipset_flush(); 981 } else { 982 intel_i915_setup_chipset_flush(); 983 } 984 985 if (intel_private.ifp_resource.start) { 986 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 987 if (!intel_private.i9xx_flush_page) 988 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 989 } 990} 991 992static int intel_i915_configure(void) 993{ 994 struct aper_size_info_fixed *current_size; 995 u32 temp; 996 u16 gmch_ctrl; 997 int i; 998 999 current_size = A_SIZE_FIX(agp_bridge->current_size); 1000 1001 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1002 1003 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1004 1005 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1006 gmch_ctrl |= I830_GMCH_ENABLED; 1007 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1008 1009 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1010 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1011 1012 if (agp_bridge->driver->needs_scratch_page) { 1013 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 1014 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1015 } 1016 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1017 } 1018 1019 global_cache_flush(); 1020 1021 intel_i9xx_setup_flush(); 1022 1023 return 0; 1024} 1025 1026static void intel_i915_cleanup(void) 1027{ 1028 if (intel_private.i9xx_flush_page) 1029 iounmap(intel_private.i9xx_flush_page); 1030 if (intel_private.resource_valid) 1031 release_resource(&intel_private.ifp_resource); 1032 intel_private.ifp_resource.start = 0; 1033 intel_private.resource_valid = 0; 1034 iounmap(intel_private.gtt); 1035 iounmap(intel_private.registers); 1036} 1037 1038static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1039{ 1040 if (intel_private.i9xx_flush_page) 1041 writel(1, intel_private.i9xx_flush_page); 1042} 1043 1044static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1045 int type) 1046{ 1047 int i, j, num_entries; 1048 void *temp; 1049 int ret = -EINVAL; 1050 int mask_type; 1051 1052 if (mem->page_count == 0) 1053 goto out; 1054 1055 temp = agp_bridge->current_size; 1056 num_entries = A_SIZE_FIX(temp)->num_entries; 1057 1058 if (pg_start < intel_private.gtt_entries) { 1059 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1060 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1061 pg_start, intel_private.gtt_entries); 1062 1063 dev_info(&intel_private.pcidev->dev, 1064 "trying to insert into local/stolen memory\n"); 1065 goto out_err; 1066 } 1067 1068 if ((pg_start + mem->page_count) > num_entries) 1069 goto out_err; 1070 1071 /* The i915 can't check the GTT for entries since its read only, 1072 * depend on the caller to make the correct offset decisions. 1073 */ 1074 1075 if (type != mem->type) 1076 goto out_err; 1077 1078 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1079 1080 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1081 mask_type != INTEL_AGP_CACHED_MEMORY) 1082 goto out_err; 1083 1084 if (!mem->is_flushed) 1085 global_cache_flush(); 1086 1087 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1088 writel(agp_bridge->driver->mask_memory(agp_bridge, 1089 mem->pages[i], mask_type), intel_private.gtt+j); 1090 } 1091 1092 readl(intel_private.gtt+j-1); 1093 agp_bridge->driver->tlb_flush(mem); 1094 1095 out: 1096 ret = 0; 1097 out_err: 1098 mem->is_flushed = true; 1099 return ret; 1100} 1101 1102static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1103 int type) 1104{ 1105 int i; 1106 1107 if (mem->page_count == 0) 1108 return 0; 1109 1110 if (pg_start < intel_private.gtt_entries) { 1111 dev_info(&intel_private.pcidev->dev, 1112 "trying to disable local/stolen memory\n"); 1113 return -EINVAL; 1114 } 1115 1116 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1117 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1118 1119 readl(intel_private.gtt+i-1); 1120 1121 agp_bridge->driver->tlb_flush(mem); 1122 return 0; 1123} 1124 1125/* Return the aperture size by just checking the resource length. The effect 1126 * described in the spec of the MSAC registers is just changing of the 1127 * resource size. 1128 */ 1129static int intel_i9xx_fetch_size(void) 1130{ 1131 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1132 int aper_size; /* size in megabytes */ 1133 int i; 1134 1135 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1136 1137 for (i = 0; i < num_sizes; i++) { 1138 if (aper_size == intel_i830_sizes[i].size) { 1139 agp_bridge->current_size = intel_i830_sizes + i; 1140 agp_bridge->previous_size = agp_bridge->current_size; 1141 return aper_size; 1142 } 1143 } 1144 1145 return 0; 1146} 1147 1148/* The intel i915 automatically initializes the agp aperture during POST. 1149 * Use the memory already set aside for in the GTT. 1150 */ 1151static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1152{ 1153 int page_order; 1154 struct aper_size_info_fixed *size; 1155 int num_entries; 1156 u32 temp, temp2; 1157 int gtt_map_size = 256 * 1024; 1158 1159 size = agp_bridge->current_size; 1160 page_order = size->page_order; 1161 num_entries = size->num_entries; 1162 agp_bridge->gatt_table_real = NULL; 1163 1164 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1165 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1166 1167 if (IS_G33) 1168 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1169 intel_private.gtt = ioremap(temp2, gtt_map_size); 1170 if (!intel_private.gtt) 1171 return -ENOMEM; 1172 1173 temp &= 0xfff80000; 1174 1175 intel_private.registers = ioremap(temp, 128 * 4096); 1176 if (!intel_private.registers) { 1177 iounmap(intel_private.gtt); 1178 return -ENOMEM; 1179 } 1180 1181 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1182 global_cache_flush(); /* FIXME: ? */ 1183 1184 /* we have to call this as early as possible after the MMIO base address is known */ 1185 intel_i830_init_gtt_entries(); 1186 1187 agp_bridge->gatt_table = NULL; 1188 1189 agp_bridge->gatt_bus_addr = temp; 1190 1191 return 0; 1192} 1193 1194/* 1195 * The i965 supports 36-bit physical addresses, but to keep 1196 * the format of the GTT the same, the bits that don't fit 1197 * in a 32-bit word are shifted down to bits 4..7. 1198 * 1199 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1200 * is always zero on 32-bit architectures, so no need to make 1201 * this conditional. 1202 */ 1203static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1204 struct page *page, int type) 1205{ 1206 dma_addr_t addr = phys_to_gart(page_to_phys(page)); 1207 /* Shift high bits down */ 1208 addr |= (addr >> 28) & 0xf0; 1209 1210 /* Type checking must be done elsewhere */ 1211 return addr | bridge->driver->masks[type].mask; 1212} 1213 1214static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1215{ 1216 switch (agp_bridge->dev->device) { 1217 case PCI_DEVICE_ID_INTEL_GM45_HB: 1218 case PCI_DEVICE_ID_INTEL_IGD_E_HB: 1219 case PCI_DEVICE_ID_INTEL_Q45_HB: 1220 case PCI_DEVICE_ID_INTEL_G45_HB: 1221 case PCI_DEVICE_ID_INTEL_G41_HB: 1222 case PCI_DEVICE_ID_INTEL_B43_HB: 1223 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: 1224 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: 1225 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB: 1226 *gtt_offset = *gtt_size = MB(2); 1227 break; 1228 default: 1229 *gtt_offset = *gtt_size = KB(512); 1230 } 1231} 1232 1233/* The intel i965 automatically initializes the agp aperture during POST. 1234 * Use the memory already set aside for in the GTT. 1235 */ 1236static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1237{ 1238 int page_order; 1239 struct aper_size_info_fixed *size; 1240 int num_entries; 1241 u32 temp; 1242 int gtt_offset, gtt_size; 1243 1244 size = agp_bridge->current_size; 1245 page_order = size->page_order; 1246 num_entries = size->num_entries; 1247 agp_bridge->gatt_table_real = NULL; 1248 1249 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1250 1251 temp &= 0xfff00000; 1252 1253 intel_i965_get_gtt_range(>t_offset, >t_size); 1254 1255 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1256 1257 if (!intel_private.gtt) 1258 return -ENOMEM; 1259 1260 intel_private.registers = ioremap(temp, 128 * 4096); 1261 if (!intel_private.registers) { 1262 iounmap(intel_private.gtt); 1263 return -ENOMEM; 1264 } 1265 1266 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1267 global_cache_flush(); /* FIXME: ? */ 1268 1269 /* we have to call this as early as possible after the MMIO base address is known */ 1270 intel_i830_init_gtt_entries(); 1271 1272 agp_bridge->gatt_table = NULL; 1273 1274 agp_bridge->gatt_bus_addr = temp; 1275 1276 return 0; 1277} 1278 1279 1280static int intel_fetch_size(void) 1281{ 1282 int i; 1283 u16 temp; 1284 struct aper_size_info_16 *values; 1285 1286 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1287 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1288 1289 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1290 if (temp == values[i].size_value) { 1291 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1292 agp_bridge->aperture_size_idx = i; 1293 return values[i].size; 1294 } 1295 } 1296 1297 return 0; 1298} 1299 1300static int __intel_8xx_fetch_size(u8 temp) 1301{ 1302 int i; 1303 struct aper_size_info_8 *values; 1304 1305 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1306 1307 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1308 if (temp == values[i].size_value) { 1309 agp_bridge->previous_size = 1310 agp_bridge->current_size = (void *) (values + i); 1311 agp_bridge->aperture_size_idx = i; 1312 return values[i].size; 1313 } 1314 } 1315 return 0; 1316} 1317 1318static int intel_8xx_fetch_size(void) 1319{ 1320 u8 temp; 1321 1322 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1323 return __intel_8xx_fetch_size(temp); 1324} 1325 1326static int intel_815_fetch_size(void) 1327{ 1328 u8 temp; 1329 1330 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1331 * one non-reserved bit, so mask the others out ... */ 1332 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1333 temp &= (1 << 3); 1334 1335 return __intel_8xx_fetch_size(temp); 1336} 1337 1338static void intel_tlbflush(struct agp_memory *mem) 1339{ 1340 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1341 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1342} 1343 1344 1345static void intel_8xx_tlbflush(struct agp_memory *mem) 1346{ 1347 u32 temp; 1348 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1349 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1350 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1351 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1352} 1353 1354 1355static void intel_cleanup(void) 1356{ 1357 u16 temp; 1358 struct aper_size_info_16 *previous_size; 1359 1360 previous_size = A_SIZE_16(agp_bridge->previous_size); 1361 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1362 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1363 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1364} 1365 1366 1367static void intel_8xx_cleanup(void) 1368{ 1369 u16 temp; 1370 struct aper_size_info_8 *previous_size; 1371 1372 previous_size = A_SIZE_8(agp_bridge->previous_size); 1373 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1374 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1375 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1376} 1377 1378 1379static int intel_configure(void) 1380{ 1381 u32 temp; 1382 u16 temp2; 1383 struct aper_size_info_16 *current_size; 1384 1385 current_size = A_SIZE_16(agp_bridge->current_size); 1386 1387 /* aperture size */ 1388 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1389 1390 /* address to map to */ 1391 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1392 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1393 1394 /* attbase - aperture base */ 1395 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1396 1397 /* agpctrl */ 1398 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1399 1400 /* paccfg/nbxcfg */ 1401 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1402 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1403 (temp2 & ~(1 << 10)) | (1 << 9)); 1404 /* clear any possible error conditions */ 1405 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1406 return 0; 1407} 1408 1409static int intel_815_configure(void) 1410{ 1411 u32 temp, addr; 1412 u8 temp2; 1413 struct aper_size_info_8 *current_size; 1414 1415 /* attbase - aperture base */ 1416 /* the Intel 815 chipset spec. says that bits 29-31 in the 1417 * ATTBASE register are reserved -> try not to write them */ 1418 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1419 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1420 return -EINVAL; 1421 } 1422 1423 current_size = A_SIZE_8(agp_bridge->current_size); 1424 1425 /* aperture size */ 1426 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1427 current_size->size_value); 1428 1429 /* address to map to */ 1430 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1431 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1432 1433 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1434 addr &= INTEL_815_ATTBASE_MASK; 1435 addr |= agp_bridge->gatt_bus_addr; 1436 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1437 1438 /* agpctrl */ 1439 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1440 1441 /* apcont */ 1442 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1443 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1444 1445 /* clear any possible error conditions */ 1446 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1447 return 0; 1448} 1449 1450static void intel_820_tlbflush(struct agp_memory *mem) 1451{ 1452 return; 1453} 1454 1455static void intel_820_cleanup(void) 1456{ 1457 u8 temp; 1458 struct aper_size_info_8 *previous_size; 1459 1460 previous_size = A_SIZE_8(agp_bridge->previous_size); 1461 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1462 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1463 temp & ~(1 << 1)); 1464 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1465 previous_size->size_value); 1466} 1467 1468 1469static int intel_820_configure(void) 1470{ 1471 u32 temp; 1472 u8 temp2; 1473 struct aper_size_info_8 *current_size; 1474 1475 current_size = A_SIZE_8(agp_bridge->current_size); 1476 1477 /* aperture size */ 1478 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1479 1480 /* address to map to */ 1481 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1482 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1483 1484 /* attbase - aperture base */ 1485 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1486 1487 /* agpctrl */ 1488 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1489 1490 /* global enable aperture access */ 1491 /* This flag is not accessed through MCHCFG register as in */ 1492 /* i850 chipset. */ 1493 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1494 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1495 /* clear any possible AGP-related error conditions */ 1496 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1497 return 0; 1498} 1499 1500static int intel_840_configure(void) 1501{ 1502 u32 temp; 1503 u16 temp2; 1504 struct aper_size_info_8 *current_size; 1505 1506 current_size = A_SIZE_8(agp_bridge->current_size); 1507 1508 /* aperture size */ 1509 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1510 1511 /* address to map to */ 1512 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1513 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1514 1515 /* attbase - aperture base */ 1516 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1517 1518 /* agpctrl */ 1519 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1520 1521 /* mcgcfg */ 1522 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1523 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1524 /* clear any possible error conditions */ 1525 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1526 return 0; 1527} 1528 1529static int intel_845_configure(void) 1530{ 1531 u32 temp; 1532 u8 temp2; 1533 struct aper_size_info_8 *current_size; 1534 1535 current_size = A_SIZE_8(agp_bridge->current_size); 1536 1537 /* aperture size */ 1538 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1539 1540 if (agp_bridge->apbase_config != 0) { 1541 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1542 agp_bridge->apbase_config); 1543 } else { 1544 /* address to map to */ 1545 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1546 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1547 agp_bridge->apbase_config = temp; 1548 } 1549 1550 /* attbase - aperture base */ 1551 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1552 1553 /* agpctrl */ 1554 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1555 1556 /* agpm */ 1557 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1558 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1559 /* clear any possible error conditions */ 1560 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1561 1562 intel_i830_setup_flush(); 1563 return 0; 1564} 1565 1566static int intel_850_configure(void) 1567{ 1568 u32 temp; 1569 u16 temp2; 1570 struct aper_size_info_8 *current_size; 1571 1572 current_size = A_SIZE_8(agp_bridge->current_size); 1573 1574 /* aperture size */ 1575 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1576 1577 /* address to map to */ 1578 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1579 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1580 1581 /* attbase - aperture base */ 1582 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1583 1584 /* agpctrl */ 1585 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1586 1587 /* mcgcfg */ 1588 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1589 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1590 /* clear any possible AGP-related error conditions */ 1591 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1592 return 0; 1593} 1594 1595static int intel_860_configure(void) 1596{ 1597 u32 temp; 1598 u16 temp2; 1599 struct aper_size_info_8 *current_size; 1600 1601 current_size = A_SIZE_8(agp_bridge->current_size); 1602 1603 /* aperture size */ 1604 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1605 1606 /* address to map to */ 1607 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1608 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1609 1610 /* attbase - aperture base */ 1611 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1612 1613 /* agpctrl */ 1614 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1615 1616 /* mcgcfg */ 1617 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1618 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1619 /* clear any possible AGP-related error conditions */ 1620 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1621 return 0; 1622} 1623 1624static int intel_830mp_configure(void) 1625{ 1626 u32 temp; 1627 u16 temp2; 1628 struct aper_size_info_8 *current_size; 1629 1630 current_size = A_SIZE_8(agp_bridge->current_size); 1631 1632 /* aperture size */ 1633 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1634 1635 /* address to map to */ 1636 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1637 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1638 1639 /* attbase - aperture base */ 1640 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1641 1642 /* agpctrl */ 1643 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1644 1645 /* gmch */ 1646 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1647 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1648 /* clear any possible AGP-related error conditions */ 1649 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1650 return 0; 1651} 1652 1653static int intel_7505_configure(void) 1654{ 1655 u32 temp; 1656 u16 temp2; 1657 struct aper_size_info_8 *current_size; 1658 1659 current_size = A_SIZE_8(agp_bridge->current_size); 1660 1661 /* aperture size */ 1662 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1663 1664 /* address to map to */ 1665 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1666 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1667 1668 /* attbase - aperture base */ 1669 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1670 1671 /* agpctrl */ 1672 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1673 1674 /* mchcfg */ 1675 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1676 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1677 1678 return 0; 1679} 1680 1681/* Setup function */ 1682static const struct gatt_mask intel_generic_masks[] = 1683{ 1684 {.mask = 0x00000017, .type = 0} 1685}; 1686 1687static const struct aper_size_info_8 intel_815_sizes[2] = 1688{ 1689 {64, 16384, 4, 0}, 1690 {32, 8192, 3, 8}, 1691}; 1692 1693static const struct aper_size_info_8 intel_8xx_sizes[7] = 1694{ 1695 {256, 65536, 6, 0}, 1696 {128, 32768, 5, 32}, 1697 {64, 16384, 4, 48}, 1698 {32, 8192, 3, 56}, 1699 {16, 4096, 2, 60}, 1700 {8, 2048, 1, 62}, 1701 {4, 1024, 0, 63} 1702}; 1703 1704static const struct aper_size_info_16 intel_generic_sizes[7] = 1705{ 1706 {256, 65536, 6, 0}, 1707 {128, 32768, 5, 32}, 1708 {64, 16384, 4, 48}, 1709 {32, 8192, 3, 56}, 1710 {16, 4096, 2, 60}, 1711 {8, 2048, 1, 62}, 1712 {4, 1024, 0, 63} 1713}; 1714 1715static const struct aper_size_info_8 intel_830mp_sizes[4] = 1716{ 1717 {256, 65536, 6, 0}, 1718 {128, 32768, 5, 32}, 1719 {64, 16384, 4, 48}, 1720 {32, 8192, 3, 56} 1721}; 1722 1723static const struct agp_bridge_driver intel_generic_driver = { 1724 .owner = THIS_MODULE, 1725 .aperture_sizes = intel_generic_sizes, 1726 .size_type = U16_APER_SIZE, 1727 .num_aperture_sizes = 7, 1728 .configure = intel_configure, 1729 .fetch_size = intel_fetch_size, 1730 .cleanup = intel_cleanup, 1731 .tlb_flush = intel_tlbflush, 1732 .mask_memory = agp_generic_mask_memory, 1733 .masks = intel_generic_masks, 1734 .agp_enable = agp_generic_enable, 1735 .cache_flush = global_cache_flush, 1736 .create_gatt_table = agp_generic_create_gatt_table, 1737 .free_gatt_table = agp_generic_free_gatt_table, 1738 .insert_memory = agp_generic_insert_memory, 1739 .remove_memory = agp_generic_remove_memory, 1740 .alloc_by_type = agp_generic_alloc_by_type, 1741 .free_by_type = agp_generic_free_by_type, 1742 .agp_alloc_page = agp_generic_alloc_page, 1743 .agp_alloc_pages = agp_generic_alloc_pages, 1744 .agp_destroy_page = agp_generic_destroy_page, 1745 .agp_destroy_pages = agp_generic_destroy_pages, 1746 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1747}; 1748 1749static const struct agp_bridge_driver intel_810_driver = { 1750 .owner = THIS_MODULE, 1751 .aperture_sizes = intel_i810_sizes, 1752 .size_type = FIXED_APER_SIZE, 1753 .num_aperture_sizes = 2, 1754 .needs_scratch_page = true, 1755 .configure = intel_i810_configure, 1756 .fetch_size = intel_i810_fetch_size, 1757 .cleanup = intel_i810_cleanup, 1758 .tlb_flush = intel_i810_tlbflush, 1759 .mask_memory = intel_i810_mask_memory, 1760 .masks = intel_i810_masks, 1761 .agp_enable = intel_i810_agp_enable, 1762 .cache_flush = global_cache_flush, 1763 .create_gatt_table = agp_generic_create_gatt_table, 1764 .free_gatt_table = agp_generic_free_gatt_table, 1765 .insert_memory = intel_i810_insert_entries, 1766 .remove_memory = intel_i810_remove_entries, 1767 .alloc_by_type = intel_i810_alloc_by_type, 1768 .free_by_type = intel_i810_free_by_type, 1769 .agp_alloc_page = agp_generic_alloc_page, 1770 .agp_alloc_pages = agp_generic_alloc_pages, 1771 .agp_destroy_page = agp_generic_destroy_page, 1772 .agp_destroy_pages = agp_generic_destroy_pages, 1773 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1774}; 1775 1776static const struct agp_bridge_driver intel_815_driver = { 1777 .owner = THIS_MODULE, 1778 .aperture_sizes = intel_815_sizes, 1779 .size_type = U8_APER_SIZE, 1780 .num_aperture_sizes = 2, 1781 .configure = intel_815_configure, 1782 .fetch_size = intel_815_fetch_size, 1783 .cleanup = intel_8xx_cleanup, 1784 .tlb_flush = intel_8xx_tlbflush, 1785 .mask_memory = agp_generic_mask_memory, 1786 .masks = intel_generic_masks, 1787 .agp_enable = agp_generic_enable, 1788 .cache_flush = global_cache_flush, 1789 .create_gatt_table = agp_generic_create_gatt_table, 1790 .free_gatt_table = agp_generic_free_gatt_table, 1791 .insert_memory = agp_generic_insert_memory, 1792 .remove_memory = agp_generic_remove_memory, 1793 .alloc_by_type = agp_generic_alloc_by_type, 1794 .free_by_type = agp_generic_free_by_type, 1795 .agp_alloc_page = agp_generic_alloc_page, 1796 .agp_alloc_pages = agp_generic_alloc_pages, 1797 .agp_destroy_page = agp_generic_destroy_page, 1798 .agp_destroy_pages = agp_generic_destroy_pages, 1799 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1800}; 1801 1802static const struct agp_bridge_driver intel_830_driver = { 1803 .owner = THIS_MODULE, 1804 .aperture_sizes = intel_i830_sizes, 1805 .size_type = FIXED_APER_SIZE, 1806 .num_aperture_sizes = 4, 1807 .needs_scratch_page = true, 1808 .configure = intel_i830_configure, 1809 .fetch_size = intel_i830_fetch_size, 1810 .cleanup = intel_i830_cleanup, 1811 .tlb_flush = intel_i810_tlbflush, 1812 .mask_memory = intel_i810_mask_memory, 1813 .masks = intel_i810_masks, 1814 .agp_enable = intel_i810_agp_enable, 1815 .cache_flush = global_cache_flush, 1816 .create_gatt_table = intel_i830_create_gatt_table, 1817 .free_gatt_table = intel_i830_free_gatt_table, 1818 .insert_memory = intel_i830_insert_entries, 1819 .remove_memory = intel_i830_remove_entries, 1820 .alloc_by_type = intel_i830_alloc_by_type, 1821 .free_by_type = intel_i810_free_by_type, 1822 .agp_alloc_page = agp_generic_alloc_page, 1823 .agp_alloc_pages = agp_generic_alloc_pages, 1824 .agp_destroy_page = agp_generic_destroy_page, 1825 .agp_destroy_pages = agp_generic_destroy_pages, 1826 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1827 .chipset_flush = intel_i830_chipset_flush, 1828}; 1829 1830static const struct agp_bridge_driver intel_820_driver = { 1831 .owner = THIS_MODULE, 1832 .aperture_sizes = intel_8xx_sizes, 1833 .size_type = U8_APER_SIZE, 1834 .num_aperture_sizes = 7, 1835 .configure = intel_820_configure, 1836 .fetch_size = intel_8xx_fetch_size, 1837 .cleanup = intel_820_cleanup, 1838 .tlb_flush = intel_820_tlbflush, 1839 .mask_memory = agp_generic_mask_memory, 1840 .masks = intel_generic_masks, 1841 .agp_enable = agp_generic_enable, 1842 .cache_flush = global_cache_flush, 1843 .create_gatt_table = agp_generic_create_gatt_table, 1844 .free_gatt_table = agp_generic_free_gatt_table, 1845 .insert_memory = agp_generic_insert_memory, 1846 .remove_memory = agp_generic_remove_memory, 1847 .alloc_by_type = agp_generic_alloc_by_type, 1848 .free_by_type = agp_generic_free_by_type, 1849 .agp_alloc_page = agp_generic_alloc_page, 1850 .agp_alloc_pages = agp_generic_alloc_pages, 1851 .agp_destroy_page = agp_generic_destroy_page, 1852 .agp_destroy_pages = agp_generic_destroy_pages, 1853 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1854}; 1855 1856static const struct agp_bridge_driver intel_830mp_driver = { 1857 .owner = THIS_MODULE, 1858 .aperture_sizes = intel_830mp_sizes, 1859 .size_type = U8_APER_SIZE, 1860 .num_aperture_sizes = 4, 1861 .configure = intel_830mp_configure, 1862 .fetch_size = intel_8xx_fetch_size, 1863 .cleanup = intel_8xx_cleanup, 1864 .tlb_flush = intel_8xx_tlbflush, 1865 .mask_memory = agp_generic_mask_memory, 1866 .masks = intel_generic_masks, 1867 .agp_enable = agp_generic_enable, 1868 .cache_flush = global_cache_flush, 1869 .create_gatt_table = agp_generic_create_gatt_table, 1870 .free_gatt_table = agp_generic_free_gatt_table, 1871 .insert_memory = agp_generic_insert_memory, 1872 .remove_memory = agp_generic_remove_memory, 1873 .alloc_by_type = agp_generic_alloc_by_type, 1874 .free_by_type = agp_generic_free_by_type, 1875 .agp_alloc_page = agp_generic_alloc_page, 1876 .agp_alloc_pages = agp_generic_alloc_pages, 1877 .agp_destroy_page = agp_generic_destroy_page, 1878 .agp_destroy_pages = agp_generic_destroy_pages, 1879 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1880}; 1881 1882static const struct agp_bridge_driver intel_840_driver = { 1883 .owner = THIS_MODULE, 1884 .aperture_sizes = intel_8xx_sizes, 1885 .size_type = U8_APER_SIZE, 1886 .num_aperture_sizes = 7, 1887 .configure = intel_840_configure, 1888 .fetch_size = intel_8xx_fetch_size, 1889 .cleanup = intel_8xx_cleanup, 1890 .tlb_flush = intel_8xx_tlbflush, 1891 .mask_memory = agp_generic_mask_memory, 1892 .masks = intel_generic_masks, 1893 .agp_enable = agp_generic_enable, 1894 .cache_flush = global_cache_flush, 1895 .create_gatt_table = agp_generic_create_gatt_table, 1896 .free_gatt_table = agp_generic_free_gatt_table, 1897 .insert_memory = agp_generic_insert_memory, 1898 .remove_memory = agp_generic_remove_memory, 1899 .alloc_by_type = agp_generic_alloc_by_type, 1900 .free_by_type = agp_generic_free_by_type, 1901 .agp_alloc_page = agp_generic_alloc_page, 1902 .agp_alloc_pages = agp_generic_alloc_pages, 1903 .agp_destroy_page = agp_generic_destroy_page, 1904 .agp_destroy_pages = agp_generic_destroy_pages, 1905 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1906}; 1907 1908static const struct agp_bridge_driver intel_845_driver = { 1909 .owner = THIS_MODULE, 1910 .aperture_sizes = intel_8xx_sizes, 1911 .size_type = U8_APER_SIZE, 1912 .num_aperture_sizes = 7, 1913 .configure = intel_845_configure, 1914 .fetch_size = intel_8xx_fetch_size, 1915 .cleanup = intel_8xx_cleanup, 1916 .tlb_flush = intel_8xx_tlbflush, 1917 .mask_memory = agp_generic_mask_memory, 1918 .masks = intel_generic_masks, 1919 .agp_enable = agp_generic_enable, 1920 .cache_flush = global_cache_flush, 1921 .create_gatt_table = agp_generic_create_gatt_table, 1922 .free_gatt_table = agp_generic_free_gatt_table, 1923 .insert_memory = agp_generic_insert_memory, 1924 .remove_memory = agp_generic_remove_memory, 1925 .alloc_by_type = agp_generic_alloc_by_type, 1926 .free_by_type = agp_generic_free_by_type, 1927 .agp_alloc_page = agp_generic_alloc_page, 1928 .agp_alloc_pages = agp_generic_alloc_pages, 1929 .agp_destroy_page = agp_generic_destroy_page, 1930 .agp_destroy_pages = agp_generic_destroy_pages, 1931 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1932 .chipset_flush = intel_i830_chipset_flush, 1933}; 1934 1935static const struct agp_bridge_driver intel_850_driver = { 1936 .owner = THIS_MODULE, 1937 .aperture_sizes = intel_8xx_sizes, 1938 .size_type = U8_APER_SIZE, 1939 .num_aperture_sizes = 7, 1940 .configure = intel_850_configure, 1941 .fetch_size = intel_8xx_fetch_size, 1942 .cleanup = intel_8xx_cleanup, 1943 .tlb_flush = intel_8xx_tlbflush, 1944 .mask_memory = agp_generic_mask_memory, 1945 .masks = intel_generic_masks, 1946 .agp_enable = agp_generic_enable, 1947 .cache_flush = global_cache_flush, 1948 .create_gatt_table = agp_generic_create_gatt_table, 1949 .free_gatt_table = agp_generic_free_gatt_table, 1950 .insert_memory = agp_generic_insert_memory, 1951 .remove_memory = agp_generic_remove_memory, 1952 .alloc_by_type = agp_generic_alloc_by_type, 1953 .free_by_type = agp_generic_free_by_type, 1954 .agp_alloc_page = agp_generic_alloc_page, 1955 .agp_alloc_pages = agp_generic_alloc_pages, 1956 .agp_destroy_page = agp_generic_destroy_page, 1957 .agp_destroy_pages = agp_generic_destroy_pages, 1958 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1959}; 1960 1961static const struct agp_bridge_driver intel_860_driver = { 1962 .owner = THIS_MODULE, 1963 .aperture_sizes = intel_8xx_sizes, 1964 .size_type = U8_APER_SIZE, 1965 .num_aperture_sizes = 7, 1966 .configure = intel_860_configure, 1967 .fetch_size = intel_8xx_fetch_size, 1968 .cleanup = intel_8xx_cleanup, 1969 .tlb_flush = intel_8xx_tlbflush, 1970 .mask_memory = agp_generic_mask_memory, 1971 .masks = intel_generic_masks, 1972 .agp_enable = agp_generic_enable, 1973 .cache_flush = global_cache_flush, 1974 .create_gatt_table = agp_generic_create_gatt_table, 1975 .free_gatt_table = agp_generic_free_gatt_table, 1976 .insert_memory = agp_generic_insert_memory, 1977 .remove_memory = agp_generic_remove_memory, 1978 .alloc_by_type = agp_generic_alloc_by_type, 1979 .free_by_type = agp_generic_free_by_type, 1980 .agp_alloc_page = agp_generic_alloc_page, 1981 .agp_alloc_pages = agp_generic_alloc_pages, 1982 .agp_destroy_page = agp_generic_destroy_page, 1983 .agp_destroy_pages = agp_generic_destroy_pages, 1984 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1985}; 1986 1987static const struct agp_bridge_driver intel_915_driver = { 1988 .owner = THIS_MODULE, 1989 .aperture_sizes = intel_i830_sizes, 1990 .size_type = FIXED_APER_SIZE, 1991 .num_aperture_sizes = 4, 1992 .needs_scratch_page = true, 1993 .configure = intel_i915_configure, 1994 .fetch_size = intel_i9xx_fetch_size, 1995 .cleanup = intel_i915_cleanup, 1996 .tlb_flush = intel_i810_tlbflush, 1997 .mask_memory = intel_i810_mask_memory, 1998 .masks = intel_i810_masks, 1999 .agp_enable = intel_i810_agp_enable, 2000 .cache_flush = global_cache_flush, 2001 .create_gatt_table = intel_i915_create_gatt_table, 2002 .free_gatt_table = intel_i830_free_gatt_table, 2003 .insert_memory = intel_i915_insert_entries, 2004 .remove_memory = intel_i915_remove_entries, 2005 .alloc_by_type = intel_i830_alloc_by_type, 2006 .free_by_type = intel_i810_free_by_type, 2007 .agp_alloc_page = agp_generic_alloc_page, 2008 .agp_alloc_pages = agp_generic_alloc_pages, 2009 .agp_destroy_page = agp_generic_destroy_page, 2010 .agp_destroy_pages = agp_generic_destroy_pages, 2011 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2012 .chipset_flush = intel_i915_chipset_flush, 2013}; 2014 2015static const struct agp_bridge_driver intel_i965_driver = { 2016 .owner = THIS_MODULE, 2017 .aperture_sizes = intel_i830_sizes, 2018 .size_type = FIXED_APER_SIZE, 2019 .num_aperture_sizes = 4, 2020 .needs_scratch_page = true, 2021 .configure = intel_i915_configure, 2022 .fetch_size = intel_i9xx_fetch_size, 2023 .cleanup = intel_i915_cleanup, 2024 .tlb_flush = intel_i810_tlbflush, 2025 .mask_memory = intel_i965_mask_memory, 2026 .masks = intel_i810_masks, 2027 .agp_enable = intel_i810_agp_enable, 2028 .cache_flush = global_cache_flush, 2029 .create_gatt_table = intel_i965_create_gatt_table, 2030 .free_gatt_table = intel_i830_free_gatt_table, 2031 .insert_memory = intel_i915_insert_entries, 2032 .remove_memory = intel_i915_remove_entries, 2033 .alloc_by_type = intel_i830_alloc_by_type, 2034 .free_by_type = intel_i810_free_by_type, 2035 .agp_alloc_page = agp_generic_alloc_page, 2036 .agp_alloc_pages = agp_generic_alloc_pages, 2037 .agp_destroy_page = agp_generic_destroy_page, 2038 .agp_destroy_pages = agp_generic_destroy_pages, 2039 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2040 .chipset_flush = intel_i915_chipset_flush, 2041}; 2042 2043static const struct agp_bridge_driver intel_7505_driver = { 2044 .owner = THIS_MODULE, 2045 .aperture_sizes = intel_8xx_sizes, 2046 .size_type = U8_APER_SIZE, 2047 .num_aperture_sizes = 7, 2048 .configure = intel_7505_configure, 2049 .fetch_size = intel_8xx_fetch_size, 2050 .cleanup = intel_8xx_cleanup, 2051 .tlb_flush = intel_8xx_tlbflush, 2052 .mask_memory = agp_generic_mask_memory, 2053 .masks = intel_generic_masks, 2054 .agp_enable = agp_generic_enable, 2055 .cache_flush = global_cache_flush, 2056 .create_gatt_table = agp_generic_create_gatt_table, 2057 .free_gatt_table = agp_generic_free_gatt_table, 2058 .insert_memory = agp_generic_insert_memory, 2059 .remove_memory = agp_generic_remove_memory, 2060 .alloc_by_type = agp_generic_alloc_by_type, 2061 .free_by_type = agp_generic_free_by_type, 2062 .agp_alloc_page = agp_generic_alloc_page, 2063 .agp_alloc_pages = agp_generic_alloc_pages, 2064 .agp_destroy_page = agp_generic_destroy_page, 2065 .agp_destroy_pages = agp_generic_destroy_pages, 2066 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2067}; 2068 2069static const struct agp_bridge_driver intel_g33_driver = { 2070 .owner = THIS_MODULE, 2071 .aperture_sizes = intel_i830_sizes, 2072 .size_type = FIXED_APER_SIZE, 2073 .num_aperture_sizes = 4, 2074 .needs_scratch_page = true, 2075 .configure = intel_i915_configure, 2076 .fetch_size = intel_i9xx_fetch_size, 2077 .cleanup = intel_i915_cleanup, 2078 .tlb_flush = intel_i810_tlbflush, 2079 .mask_memory = intel_i965_mask_memory, 2080 .masks = intel_i810_masks, 2081 .agp_enable = intel_i810_agp_enable, 2082 .cache_flush = global_cache_flush, 2083 .create_gatt_table = intel_i915_create_gatt_table, 2084 .free_gatt_table = intel_i830_free_gatt_table, 2085 .insert_memory = intel_i915_insert_entries, 2086 .remove_memory = intel_i915_remove_entries, 2087 .alloc_by_type = intel_i830_alloc_by_type, 2088 .free_by_type = intel_i810_free_by_type, 2089 .agp_alloc_page = agp_generic_alloc_page, 2090 .agp_alloc_pages = agp_generic_alloc_pages, 2091 .agp_destroy_page = agp_generic_destroy_page, 2092 .agp_destroy_pages = agp_generic_destroy_pages, 2093 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2094 .chipset_flush = intel_i915_chipset_flush, 2095}; 2096 2097static int find_gmch(u16 device) 2098{ 2099 struct pci_dev *gmch_device; 2100 2101 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2102 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2103 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2104 device, gmch_device); 2105 } 2106 2107 if (!gmch_device) 2108 return 0; 2109 2110 intel_private.pcidev = gmch_device; 2111 return 1; 2112} 2113 2114/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2115 * driver and gmch_driver must be non-null, and find_gmch will determine 2116 * which one should be used if a gmch_chip_id is present. 2117 */ 2118static const struct intel_driver_description { 2119 unsigned int chip_id; 2120 unsigned int gmch_chip_id; 2121 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2122 char *name; 2123 const struct agp_bridge_driver *driver; 2124 const struct agp_bridge_driver *gmch_driver; 2125} intel_agp_chipsets[] = { 2126 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2127 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2128 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2129 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2130 NULL, &intel_810_driver }, 2131 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2132 NULL, &intel_810_driver }, 2133 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2134 NULL, &intel_810_driver }, 2135 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2136 &intel_815_driver, &intel_810_driver }, 2137 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2138 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2139 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2140 &intel_830mp_driver, &intel_830_driver }, 2141 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2142 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2143 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2144 &intel_845_driver, &intel_830_driver }, 2145 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2146 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", 2147 &intel_845_driver, &intel_830_driver }, 2148 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2149 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2150 &intel_845_driver, &intel_830_driver }, 2151 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2152 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2153 &intel_845_driver, &intel_830_driver }, 2154 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2155 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2156 NULL, &intel_915_driver }, 2157 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2158 NULL, &intel_915_driver }, 2159 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2160 NULL, &intel_915_driver }, 2161 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2162 NULL, &intel_915_driver }, 2163 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2164 NULL, &intel_915_driver }, 2165 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2166 NULL, &intel_915_driver }, 2167 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2168 NULL, &intel_i965_driver }, 2169 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2170 NULL, &intel_i965_driver }, 2171 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2172 NULL, &intel_i965_driver }, 2173 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2174 NULL, &intel_i965_driver }, 2175 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2176 NULL, &intel_i965_driver }, 2177 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2178 NULL, &intel_i965_driver }, 2179 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2180 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2181 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2182 NULL, &intel_g33_driver }, 2183 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2184 NULL, &intel_g33_driver }, 2185 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2186 NULL, &intel_g33_driver }, 2187 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", 2188 NULL, &intel_g33_driver }, 2189 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", 2190 NULL, &intel_g33_driver }, 2191 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2192 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, 2193 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, 2194 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2195 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2196 "Q45/Q43", NULL, &intel_i965_driver }, 2197 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2198 "G45/G43", NULL, &intel_i965_driver }, 2199 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, 2200 "B43", NULL, &intel_i965_driver }, 2201 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2202 "G41", NULL, &intel_i965_driver }, 2203 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, 2204 "IGDNG/D", NULL, &intel_i965_driver }, 2205 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2206 "IGDNG/M", NULL, &intel_i965_driver }, 2207 { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, 2208 "IGDNG/MA", NULL, &intel_i965_driver }, 2209 { 0, 0, 0, NULL, NULL, NULL } 2210}; 2211 2212static int __devinit agp_intel_probe(struct pci_dev *pdev, 2213 const struct pci_device_id *ent) 2214{ 2215 struct agp_bridge_data *bridge; 2216 u8 cap_ptr = 0; 2217 struct resource *r; 2218 int i; 2219 2220 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2221 2222 bridge = agp_alloc_bridge(); 2223 if (!bridge) 2224 return -ENOMEM; 2225 2226 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2227 /* In case that multiple models of gfx chip may 2228 stand on same host bridge type, this can be 2229 sure we detect the right IGD. */ 2230 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2231 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2232 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2233 bridge->driver = 2234 intel_agp_chipsets[i].gmch_driver; 2235 break; 2236 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2237 continue; 2238 } else { 2239 bridge->driver = intel_agp_chipsets[i].driver; 2240 break; 2241 } 2242 } 2243 } 2244 2245 if (intel_agp_chipsets[i].name == NULL) { 2246 if (cap_ptr) 2247 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2248 pdev->vendor, pdev->device); 2249 agp_put_bridge(bridge); 2250 return -ENODEV; 2251 } 2252 2253 if (bridge->driver == NULL) { 2254 /* bridge has no AGP and no IGD detected */ 2255 if (cap_ptr) 2256 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2257 intel_agp_chipsets[i].gmch_chip_id); 2258 agp_put_bridge(bridge); 2259 return -ENODEV; 2260 } 2261 2262 bridge->dev = pdev; 2263 bridge->capndx = cap_ptr; 2264 bridge->dev_private_data = &intel_private; 2265 2266 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2267 2268 /* 2269 * The following fixes the case where the BIOS has "forgotten" to 2270 * provide an address range for the GART. 2271 * 20030610 - hamish@zot.org 2272 */ 2273 r = &pdev->resource[0]; 2274 if (!r->start && r->end) { 2275 if (pci_assign_resource(pdev, 0)) { 2276 dev_err(&pdev->dev, "can't assign resource 0\n"); 2277 agp_put_bridge(bridge); 2278 return -ENODEV; 2279 } 2280 } 2281 2282 /* 2283 * If the device has not been properly setup, the following will catch 2284 * the problem and should stop the system from crashing. 2285 * 20030610 - hamish@zot.org 2286 */ 2287 if (pci_enable_device(pdev)) { 2288 dev_err(&pdev->dev, "can't enable PCI device\n"); 2289 agp_put_bridge(bridge); 2290 return -ENODEV; 2291 } 2292 2293 /* Fill in the mode register */ 2294 if (cap_ptr) { 2295 pci_read_config_dword(pdev, 2296 bridge->capndx+PCI_AGP_STATUS, 2297 &bridge->mode); 2298 } 2299 2300 pci_set_drvdata(pdev, bridge); 2301 return agp_add_bridge(bridge); 2302} 2303 2304static void __devexit agp_intel_remove(struct pci_dev *pdev) 2305{ 2306 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2307 2308 agp_remove_bridge(bridge); 2309 2310 if (intel_private.pcidev) 2311 pci_dev_put(intel_private.pcidev); 2312 2313 agp_put_bridge(bridge); 2314} 2315 2316#ifdef CONFIG_PM 2317static int agp_intel_resume(struct pci_dev *pdev) 2318{ 2319 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2320 int ret_val; 2321 2322 pci_restore_state(pdev); 2323 2324 /* We should restore our graphics device's config space, 2325 * as host bridge (00:00) resumes before graphics device (02:00), 2326 * then our access to its pci space can work right. 2327 */ 2328 if (intel_private.pcidev) 2329 pci_restore_state(intel_private.pcidev); 2330 2331 if (bridge->driver == &intel_generic_driver) 2332 intel_configure(); 2333 else if (bridge->driver == &intel_850_driver) 2334 intel_850_configure(); 2335 else if (bridge->driver == &intel_845_driver) 2336 intel_845_configure(); 2337 else if (bridge->driver == &intel_830mp_driver) 2338 intel_830mp_configure(); 2339 else if (bridge->driver == &intel_915_driver) 2340 intel_i915_configure(); 2341 else if (bridge->driver == &intel_830_driver) 2342 intel_i830_configure(); 2343 else if (bridge->driver == &intel_810_driver) 2344 intel_i810_configure(); 2345 else if (bridge->driver == &intel_i965_driver) 2346 intel_i915_configure(); 2347 2348 ret_val = agp_rebind_memory(); 2349 if (ret_val != 0) 2350 return ret_val; 2351 2352 return 0; 2353} 2354#endif 2355 2356static struct pci_device_id agp_intel_pci_table[] = { 2357#define ID(x) \ 2358 { \ 2359 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2360 .class_mask = ~0, \ 2361 .vendor = PCI_VENDOR_ID_INTEL, \ 2362 .device = x, \ 2363 .subvendor = PCI_ANY_ID, \ 2364 .subdevice = PCI_ANY_ID, \ 2365 } 2366 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2367 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2368 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2369 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2370 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2371 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2372 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2373 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2374 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2375 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2376 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2377 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2378 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2379 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2380 ID(PCI_DEVICE_ID_INTEL_82854_HB), 2381 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2382 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2383 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2384 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2385 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2386 ID(PCI_DEVICE_ID_INTEL_7505_0), 2387 ID(PCI_DEVICE_ID_INTEL_7205_0), 2388 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2389 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2390 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2391 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2392 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2393 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2394 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), 2395 ID(PCI_DEVICE_ID_INTEL_IGDG_HB), 2396 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2397 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2398 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2399 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2400 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2401 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2402 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2403 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2404 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2405 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2406 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), 2407 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2408 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2409 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2410 ID(PCI_DEVICE_ID_INTEL_B43_HB), 2411 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), 2412 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), 2413 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB), 2414 { } 2415}; 2416 2417MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2418 2419static struct pci_driver agp_intel_pci_driver = { 2420 .name = "agpgart-intel", 2421 .id_table = agp_intel_pci_table, 2422 .probe = agp_intel_probe, 2423 .remove = __devexit_p(agp_intel_remove), 2424#ifdef CONFIG_PM 2425 .resume = agp_intel_resume, 2426#endif 2427}; 2428 2429static int __init agp_intel_init(void) 2430{ 2431 if (agp_off) 2432 return -EINVAL; 2433 return pci_register_driver(&agp_intel_pci_driver); 2434} 2435 2436static void __exit agp_intel_cleanup(void) 2437{ 2438 pci_unregister_driver(&agp_intel_pci_driver); 2439} 2440 2441module_init(agp_intel_init); 2442module_exit(agp_intel_cleanup); 2443 2444MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 2445MODULE_LICENSE("GPL and additional rights"); 2446