intel-agp.c revision 5aa80c72263904f1e52eee8ed8cb75887b1d1dc3
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/pagemap.h> 9#include <linux/agp_backend.h> 10#include "agp.h" 11 12#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 13#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 14#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980 15#define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982 16#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 17#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 18#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 19#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 20 21#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 22 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \ 23 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 24 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB) 25 26 27/* Intel 815 register */ 28#define INTEL_815_APCONT 0x51 29#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 30 31/* Intel i820 registers */ 32#define INTEL_I820_RDCR 0x51 33#define INTEL_I820_ERRSTS 0xc8 34 35/* Intel i840 registers */ 36#define INTEL_I840_MCHCFG 0x50 37#define INTEL_I840_ERRSTS 0xc8 38 39/* Intel i850 registers */ 40#define INTEL_I850_MCHCFG 0x50 41#define INTEL_I850_ERRSTS 0xc8 42 43/* intel 915G registers */ 44#define I915_GMADDR 0x18 45#define I915_MMADDR 0x10 46#define I915_PTEADDR 0x1C 47#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 48#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 49 50/* Intel 965G registers */ 51#define I965_MSAC 0x62 52 53/* Intel 7505 registers */ 54#define INTEL_I7505_APSIZE 0x74 55#define INTEL_I7505_NCAPID 0x60 56#define INTEL_I7505_NISTAT 0x6c 57#define INTEL_I7505_ATTBASE 0x78 58#define INTEL_I7505_ERRSTS 0x42 59#define INTEL_I7505_AGPCTRL 0x70 60#define INTEL_I7505_MCHCFG 0x50 61 62static struct aper_size_info_fixed intel_i810_sizes[] = 63{ 64 {64, 16384, 4}, 65 /* The 32M mode still requires a 64k gatt */ 66 {32, 8192, 4} 67}; 68 69#define AGP_DCACHE_MEMORY 1 70#define AGP_PHYS_MEMORY 2 71 72static struct gatt_mask intel_i810_masks[] = 73{ 74 {.mask = I810_PTE_VALID, .type = 0}, 75 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 76 {.mask = I810_PTE_VALID, .type = 0} 77}; 78 79static struct _intel_i810_private { 80 struct pci_dev *i810_dev; /* device one */ 81 volatile u8 __iomem *registers; 82 int num_dcache_entries; 83} intel_i810_private; 84 85static int intel_i810_fetch_size(void) 86{ 87 u32 smram_miscc; 88 struct aper_size_info_fixed *values; 89 90 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 91 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 92 93 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 94 printk(KERN_WARNING PFX "i810 is disabled\n"); 95 return 0; 96 } 97 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 98 agp_bridge->previous_size = 99 agp_bridge->current_size = (void *) (values + 1); 100 agp_bridge->aperture_size_idx = 1; 101 return values[1].size; 102 } else { 103 agp_bridge->previous_size = 104 agp_bridge->current_size = (void *) (values); 105 agp_bridge->aperture_size_idx = 0; 106 return values[0].size; 107 } 108 109 return 0; 110} 111 112static int intel_i810_configure(void) 113{ 114 struct aper_size_info_fixed *current_size; 115 u32 temp; 116 int i; 117 118 current_size = A_SIZE_FIX(agp_bridge->current_size); 119 120 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); 121 temp &= 0xfff80000; 122 123 intel_i810_private.registers = ioremap(temp, 128 * 4096); 124 if (!intel_i810_private.registers) { 125 printk(KERN_ERR PFX "Unable to remap memory.\n"); 126 return -ENOMEM; 127 } 128 129 if ((readl(intel_i810_private.registers+I810_DRAM_CTL) 130 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 131 /* This will need to be dynamically assigned */ 132 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 133 intel_i810_private.num_dcache_entries = 1024; 134 } 135 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); 136 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 137 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); 138 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 139 140 if (agp_bridge->driver->needs_scratch_page) { 141 for (i = 0; i < current_size->num_entries; i++) { 142 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 143 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 144 } 145 } 146 global_cache_flush(); 147 return 0; 148} 149 150static void intel_i810_cleanup(void) 151{ 152 writel(0, intel_i810_private.registers+I810_PGETBL_CTL); 153 readl(intel_i810_private.registers); /* PCI Posting. */ 154 iounmap(intel_i810_private.registers); 155} 156 157static void intel_i810_tlbflush(struct agp_memory *mem) 158{ 159 return; 160} 161 162static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 163{ 164 return; 165} 166 167/* Exists to support ARGB cursors */ 168static void *i8xx_alloc_pages(void) 169{ 170 struct page * page; 171 172 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 173 if (page == NULL) 174 return NULL; 175 176 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 177 global_flush_tlb(); 178 __free_page(page); 179 return NULL; 180 } 181 global_flush_tlb(); 182 get_page(page); 183 SetPageLocked(page); 184 atomic_inc(&agp_bridge->current_memory_agp); 185 return page_address(page); 186} 187 188static void i8xx_destroy_pages(void *addr) 189{ 190 struct page *page; 191 192 if (addr == NULL) 193 return; 194 195 page = virt_to_page(addr); 196 change_page_attr(page, 4, PAGE_KERNEL); 197 global_flush_tlb(); 198 put_page(page); 199 unlock_page(page); 200 free_pages((unsigned long)addr, 2); 201 atomic_dec(&agp_bridge->current_memory_agp); 202} 203 204static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 205 int type) 206{ 207 int i, j, num_entries; 208 void *temp; 209 210 if (mem->page_count == 0) 211 return 0; 212 213 temp = agp_bridge->current_size; 214 num_entries = A_SIZE_FIX(temp)->num_entries; 215 216 if ((pg_start + mem->page_count) > num_entries) 217 return -EINVAL; 218 219 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 220 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 221 return -EBUSY; 222 } 223 224 if (type != 0 || mem->type != 0) { 225 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) { 226 /* special insert */ 227 if (!mem->is_flushed) { 228 global_cache_flush(); 229 mem->is_flushed = TRUE; 230 } 231 232 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 233 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 234 } 235 readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 236 237 agp_bridge->driver->tlb_flush(mem); 238 return 0; 239 } 240 if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY)) 241 goto insert; 242 return -EINVAL; 243 } 244 245insert: 246 if (!mem->is_flushed) { 247 global_cache_flush(); 248 mem->is_flushed = TRUE; 249 } 250 251 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 252 writel(agp_bridge->driver->mask_memory(agp_bridge, 253 mem->memory[i], mem->type), 254 intel_i810_private.registers+I810_PTE_BASE+(j*4)); 255 } 256 readl(intel_i810_private.registers+I810_PTE_BASE+(j-1*4)); /* PCI Posting. */ 257 258 agp_bridge->driver->tlb_flush(mem); 259 return 0; 260} 261 262static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 263 int type) 264{ 265 int i; 266 267 if (mem->page_count == 0) 268 return 0; 269 270 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 271 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 272 } 273 readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); 274 275 agp_bridge->driver->tlb_flush(mem); 276 return 0; 277} 278 279/* 280 * The i810/i830 requires a physical address to program its mouse 281 * pointer into hardware. 282 * However the Xserver still writes to it through the agp aperture. 283 */ 284static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 285{ 286 struct agp_memory *new; 287 void *addr; 288 289 if (pg_count != 1 && pg_count != 4) 290 return NULL; 291 292 switch (pg_count) { 293 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 294 global_flush_tlb(); 295 break; 296 case 4: 297 /* kludge to get 4 physical pages for ARGB cursor */ 298 addr = i8xx_alloc_pages(); 299 break; 300 default: 301 return NULL; 302 } 303 304 if (addr == NULL) 305 return NULL; 306 307 new = agp_create_memory(pg_count); 308 if (new == NULL) 309 return NULL; 310 311 new->memory[0] = virt_to_gart(addr); 312 if (pg_count == 4) { 313 /* kludge to get 4 physical pages for ARGB cursor */ 314 new->memory[1] = new->memory[0] + PAGE_SIZE; 315 new->memory[2] = new->memory[1] + PAGE_SIZE; 316 new->memory[3] = new->memory[2] + PAGE_SIZE; 317 } 318 new->page_count = pg_count; 319 new->num_scratch_pages = pg_count; 320 new->type = AGP_PHYS_MEMORY; 321 new->physical = new->memory[0]; 322 return new; 323} 324 325static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 326{ 327 struct agp_memory *new; 328 329 if (type == AGP_DCACHE_MEMORY) { 330 if (pg_count != intel_i810_private.num_dcache_entries) 331 return NULL; 332 333 new = agp_create_memory(1); 334 if (new == NULL) 335 return NULL; 336 337 new->type = AGP_DCACHE_MEMORY; 338 new->page_count = pg_count; 339 new->num_scratch_pages = 0; 340 vfree(new->memory); 341 return new; 342 } 343 if (type == AGP_PHYS_MEMORY) 344 return alloc_agpphysmem_i8xx(pg_count, type); 345 346 return NULL; 347} 348 349static void intel_i810_free_by_type(struct agp_memory *curr) 350{ 351 agp_free_key(curr->key); 352 if (curr->type == AGP_PHYS_MEMORY) { 353 if (curr->page_count == 4) 354 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 355 else { 356 agp_bridge->driver->agp_destroy_page( 357 gart_to_virt(curr->memory[0])); 358 global_flush_tlb(); 359 } 360 vfree(curr->memory); 361 } 362 kfree(curr); 363} 364 365static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 366 unsigned long addr, int type) 367{ 368 /* Type checking must be done elsewhere */ 369 return addr | bridge->driver->masks[type].mask; 370} 371 372static struct aper_size_info_fixed intel_i830_sizes[] = 373{ 374 {128, 32768, 5}, 375 /* The 64M mode still requires a 128k gatt */ 376 {64, 16384, 5}, 377 {256, 65536, 6}, 378 {512, 131072, 7}, 379}; 380 381static struct _intel_i830_private { 382 struct pci_dev *i830_dev; /* device one */ 383 volatile u8 __iomem *registers; 384 volatile u32 __iomem *gtt; /* I915G */ 385 int gtt_entries; 386} intel_i830_private; 387 388static void intel_i830_init_gtt_entries(void) 389{ 390 u16 gmch_ctrl; 391 int gtt_entries; 392 u8 rdct; 393 int local = 0; 394 static const int ddt[4] = { 0, 16, 32, 64 }; 395 int size; 396 397 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 398 399 /* We obtain the size of the GTT, which is also stored (for some 400 * reason) at the top of stolen memory. Then we add 4KB to that 401 * for the video BIOS popup, which is also stored in there. */ 402 size = agp_bridge->driver->fetch_size() + 4; 403 404 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 405 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 406 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 407 case I830_GMCH_GMS_STOLEN_512: 408 gtt_entries = KB(512) - KB(size); 409 break; 410 case I830_GMCH_GMS_STOLEN_1024: 411 gtt_entries = MB(1) - KB(size); 412 break; 413 case I830_GMCH_GMS_STOLEN_8192: 414 gtt_entries = MB(8) - KB(size); 415 break; 416 case I830_GMCH_GMS_LOCAL: 417 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); 418 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 419 MB(ddt[I830_RDRAM_DDT(rdct)]); 420 local = 1; 421 break; 422 default: 423 gtt_entries = 0; 424 break; 425 } 426 } else { 427 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 428 case I855_GMCH_GMS_STOLEN_1M: 429 gtt_entries = MB(1) - KB(size); 430 break; 431 case I855_GMCH_GMS_STOLEN_4M: 432 gtt_entries = MB(4) - KB(size); 433 break; 434 case I855_GMCH_GMS_STOLEN_8M: 435 gtt_entries = MB(8) - KB(size); 436 break; 437 case I855_GMCH_GMS_STOLEN_16M: 438 gtt_entries = MB(16) - KB(size); 439 break; 440 case I855_GMCH_GMS_STOLEN_32M: 441 gtt_entries = MB(32) - KB(size); 442 break; 443 case I915_GMCH_GMS_STOLEN_48M: 444 /* Check it's really I915G */ 445 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 446 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 447 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 448 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 ) 449 gtt_entries = MB(48) - KB(size); 450 else 451 gtt_entries = 0; 452 break; 453 case I915_GMCH_GMS_STOLEN_64M: 454 /* Check it's really I915G */ 455 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 456 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 457 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 458 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965) 459 gtt_entries = MB(64) - KB(size); 460 else 461 gtt_entries = 0; 462 default: 463 gtt_entries = 0; 464 break; 465 } 466 } 467 if (gtt_entries > 0) 468 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 469 gtt_entries / KB(1), local ? "local" : "stolen"); 470 else 471 printk(KERN_INFO PFX 472 "No pre-allocated video memory detected.\n"); 473 gtt_entries /= KB(4); 474 475 intel_i830_private.gtt_entries = gtt_entries; 476} 477 478/* The intel i830 automatically initializes the agp aperture during POST. 479 * Use the memory already set aside for in the GTT. 480 */ 481static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 482{ 483 int page_order; 484 struct aper_size_info_fixed *size; 485 int num_entries; 486 u32 temp; 487 488 size = agp_bridge->current_size; 489 page_order = size->page_order; 490 num_entries = size->num_entries; 491 agp_bridge->gatt_table_real = NULL; 492 493 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); 494 temp &= 0xfff80000; 495 496 intel_i830_private.registers = ioremap(temp,128 * 4096); 497 if (!intel_i830_private.registers) 498 return -ENOMEM; 499 500 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 501 global_cache_flush(); /* FIXME: ?? */ 502 503 /* we have to call this as early as possible after the MMIO base address is known */ 504 intel_i830_init_gtt_entries(); 505 506 agp_bridge->gatt_table = NULL; 507 508 agp_bridge->gatt_bus_addr = temp; 509 510 return 0; 511} 512 513/* Return the gatt table to a sane state. Use the top of stolen 514 * memory for the GTT. 515 */ 516static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 517{ 518 return 0; 519} 520 521static int intel_i830_fetch_size(void) 522{ 523 u16 gmch_ctrl; 524 struct aper_size_info_fixed *values; 525 526 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 527 528 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 529 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 530 /* 855GM/852GM/865G has 128MB aperture size */ 531 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 532 agp_bridge->aperture_size_idx = 0; 533 return values[0].size; 534 } 535 536 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 537 538 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 539 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 540 agp_bridge->aperture_size_idx = 0; 541 return values[0].size; 542 } else { 543 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 544 agp_bridge->aperture_size_idx = 1; 545 return values[1].size; 546 } 547 548 return 0; 549} 550 551static int intel_i830_configure(void) 552{ 553 struct aper_size_info_fixed *current_size; 554 u32 temp; 555 u16 gmch_ctrl; 556 int i; 557 558 current_size = A_SIZE_FIX(agp_bridge->current_size); 559 560 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); 561 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 562 563 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 564 gmch_ctrl |= I830_GMCH_ENABLED; 565 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 566 567 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 568 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 569 570 if (agp_bridge->driver->needs_scratch_page) { 571 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 572 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 573 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 574 } 575 } 576 577 global_cache_flush(); 578 return 0; 579} 580 581static void intel_i830_cleanup(void) 582{ 583 iounmap(intel_i830_private.registers); 584} 585 586static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 587{ 588 int i,j,num_entries; 589 void *temp; 590 591 if (mem->page_count == 0) 592 return 0; 593 594 temp = agp_bridge->current_size; 595 num_entries = A_SIZE_FIX(temp)->num_entries; 596 597 if (pg_start < intel_i830_private.gtt_entries) { 598 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 599 pg_start,intel_i830_private.gtt_entries); 600 601 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 602 return -EINVAL; 603 } 604 605 if ((pg_start + mem->page_count) > num_entries) 606 return -EINVAL; 607 608 /* The i830 can't check the GTT for entries since its read only, 609 * depend on the caller to make the correct offset decisions. 610 */ 611 612 if ((type != 0 && type != AGP_PHYS_MEMORY) || 613 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 614 return -EINVAL; 615 616 if (!mem->is_flushed) { 617 global_cache_flush(); 618 mem->is_flushed = TRUE; 619 } 620 621 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 622 writel(agp_bridge->driver->mask_memory(agp_bridge, 623 mem->memory[i], mem->type), 624 intel_i830_private.registers+I810_PTE_BASE+(j*4)); 625 } 626 readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4)); 627 628 agp_bridge->driver->tlb_flush(mem); 629 return 0; 630} 631 632static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 633 int type) 634{ 635 int i; 636 637 if (mem->page_count == 0) 638 return 0; 639 640 if (pg_start < intel_i830_private.gtt_entries) { 641 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 642 return -EINVAL; 643 } 644 645 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 646 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 647 } 648 readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4)); 649 650 agp_bridge->driver->tlb_flush(mem); 651 return 0; 652} 653 654static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 655{ 656 if (type == AGP_PHYS_MEMORY) 657 return alloc_agpphysmem_i8xx(pg_count, type); 658 659 /* always return NULL for other allocation types for now */ 660 return NULL; 661} 662 663static int intel_i915_configure(void) 664{ 665 struct aper_size_info_fixed *current_size; 666 u32 temp; 667 u16 gmch_ctrl; 668 int i; 669 670 current_size = A_SIZE_FIX(agp_bridge->current_size); 671 672 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 673 674 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 675 676 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 677 gmch_ctrl |= I830_GMCH_ENABLED; 678 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 679 680 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 681 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 682 683 if (agp_bridge->driver->needs_scratch_page) { 684 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 685 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 686 readl(intel_i830_private.gtt+i); /* PCI Posting. */ 687 } 688 } 689 690 global_cache_flush(); 691 return 0; 692} 693 694static void intel_i915_cleanup(void) 695{ 696 iounmap(intel_i830_private.gtt); 697 iounmap(intel_i830_private.registers); 698} 699 700static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 701 int type) 702{ 703 int i,j,num_entries; 704 void *temp; 705 706 if (mem->page_count == 0) 707 return 0; 708 709 temp = agp_bridge->current_size; 710 num_entries = A_SIZE_FIX(temp)->num_entries; 711 712 if (pg_start < intel_i830_private.gtt_entries) { 713 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 714 pg_start,intel_i830_private.gtt_entries); 715 716 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 717 return -EINVAL; 718 } 719 720 if ((pg_start + mem->page_count) > num_entries) 721 return -EINVAL; 722 723 /* The i830 can't check the GTT for entries since its read only, 724 * depend on the caller to make the correct offset decisions. 725 */ 726 727 if ((type != 0 && type != AGP_PHYS_MEMORY) || 728 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 729 return -EINVAL; 730 731 if (!mem->is_flushed) { 732 global_cache_flush(); 733 mem->is_flushed = TRUE; 734 } 735 736 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 737 writel(agp_bridge->driver->mask_memory(agp_bridge, 738 mem->memory[i], mem->type), intel_i830_private.gtt+j); 739 } 740 readl(intel_i830_private.gtt+j-1); 741 742 agp_bridge->driver->tlb_flush(mem); 743 return 0; 744} 745 746static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 747 int type) 748{ 749 int i; 750 751 if (mem->page_count == 0) 752 return 0; 753 754 if (pg_start < intel_i830_private.gtt_entries) { 755 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 756 return -EINVAL; 757 } 758 759 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 760 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 761 } 762 readl(intel_i830_private.gtt+i-1); 763 764 agp_bridge->driver->tlb_flush(mem); 765 return 0; 766} 767 768static int intel_i915_fetch_size(void) 769{ 770 struct aper_size_info_fixed *values; 771 u32 temp, offset; 772 773#define I915_256MB_ADDRESS_MASK (1<<27) 774 775 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 776 777 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 778 if (temp & I915_256MB_ADDRESS_MASK) 779 offset = 0; /* 128MB aperture */ 780 else 781 offset = 2; /* 256MB aperture */ 782 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); 783 return values[offset].size; 784} 785 786/* The intel i915 automatically initializes the agp aperture during POST. 787 * Use the memory already set aside for in the GTT. 788 */ 789static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 790{ 791 int page_order; 792 struct aper_size_info_fixed *size; 793 int num_entries; 794 u32 temp, temp2; 795 796 size = agp_bridge->current_size; 797 page_order = size->page_order; 798 num_entries = size->num_entries; 799 agp_bridge->gatt_table_real = NULL; 800 801 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 802 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); 803 804 intel_i830_private.gtt = ioremap(temp2, 256 * 1024); 805 if (!intel_i830_private.gtt) 806 return -ENOMEM; 807 808 temp &= 0xfff80000; 809 810 intel_i830_private.registers = ioremap(temp,128 * 4096); 811 if (!intel_i830_private.registers) 812 return -ENOMEM; 813 814 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 815 global_cache_flush(); /* FIXME: ? */ 816 817 /* we have to call this as early as possible after the MMIO base address is known */ 818 intel_i830_init_gtt_entries(); 819 820 agp_bridge->gatt_table = NULL; 821 822 agp_bridge->gatt_bus_addr = temp; 823 824 return 0; 825} 826 827/* 828 * The i965 supports 36-bit physical addresses, but to keep 829 * the format of the GTT the same, the bits that don't fit 830 * in a 32-bit word are shifted down to bits 4..7. 831 * 832 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 833 * is always zero on 32-bit architectures, so no need to make 834 * this conditional. 835 */ 836static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 837 unsigned long addr, int type) 838{ 839 /* Shift high bits down */ 840 addr |= (addr >> 28) & 0xf0; 841 842 /* Type checking must be done elsewhere */ 843 return addr | bridge->driver->masks[type].mask; 844} 845 846static int intel_i965_fetch_size(void) 847{ 848 struct aper_size_info_fixed *values; 849 u32 offset = 0; 850 u8 temp; 851 852#define I965_512MB_ADDRESS_MASK (3<<1) 853 854 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 855 856 pci_read_config_byte(intel_i830_private.i830_dev, I965_MSAC, &temp); 857 temp &= I965_512MB_ADDRESS_MASK; 858 switch (temp) { 859 case 0x00: 860 offset = 0; /* 128MB */ 861 break; 862 case 0x06: 863 offset = 3; /* 512MB */ 864 break; 865 default: 866 case 0x02: 867 offset = 2; /* 256MB */ 868 break; 869 } 870 871 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); 872 873 /* The i965 GTT is always sized as if it had a 512kB aperture size */ 874 return 512; 875} 876 877/* The intel i965 automatically initializes the agp aperture during POST. 878+ * Use the memory already set aside for in the GTT. 879+ */ 880static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 881{ 882 int page_order; 883 struct aper_size_info_fixed *size; 884 int num_entries; 885 u32 temp; 886 887 size = agp_bridge->current_size; 888 page_order = size->page_order; 889 num_entries = size->num_entries; 890 agp_bridge->gatt_table_real = NULL; 891 892 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 893 894 temp &= 0xfff00000; 895 intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); 896 897 if (!intel_i830_private.gtt) 898 return -ENOMEM; 899 900 901 intel_i830_private.registers = ioremap(temp,128 * 4096); 902 if (!intel_i830_private.registers) 903 return -ENOMEM; 904 905 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 906 global_cache_flush(); /* FIXME: ? */ 907 908 /* we have to call this as early as possible after the MMIO base address is known */ 909 intel_i830_init_gtt_entries(); 910 911 agp_bridge->gatt_table = NULL; 912 913 agp_bridge->gatt_bus_addr = temp; 914 915 return 0; 916} 917 918 919static int intel_fetch_size(void) 920{ 921 int i; 922 u16 temp; 923 struct aper_size_info_16 *values; 924 925 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 926 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 927 928 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 929 if (temp == values[i].size_value) { 930 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 931 agp_bridge->aperture_size_idx = i; 932 return values[i].size; 933 } 934 } 935 936 return 0; 937} 938 939static int __intel_8xx_fetch_size(u8 temp) 940{ 941 int i; 942 struct aper_size_info_8 *values; 943 944 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 945 946 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 947 if (temp == values[i].size_value) { 948 agp_bridge->previous_size = 949 agp_bridge->current_size = (void *) (values + i); 950 agp_bridge->aperture_size_idx = i; 951 return values[i].size; 952 } 953 } 954 return 0; 955} 956 957static int intel_8xx_fetch_size(void) 958{ 959 u8 temp; 960 961 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 962 return __intel_8xx_fetch_size(temp); 963} 964 965static int intel_815_fetch_size(void) 966{ 967 u8 temp; 968 969 /* Intel 815 chipsets have a _weird_ APSIZE register with only 970 * one non-reserved bit, so mask the others out ... */ 971 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 972 temp &= (1 << 3); 973 974 return __intel_8xx_fetch_size(temp); 975} 976 977static void intel_tlbflush(struct agp_memory *mem) 978{ 979 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 980 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 981} 982 983 984static void intel_8xx_tlbflush(struct agp_memory *mem) 985{ 986 u32 temp; 987 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 988 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 989 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 990 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 991} 992 993 994static void intel_cleanup(void) 995{ 996 u16 temp; 997 struct aper_size_info_16 *previous_size; 998 999 previous_size = A_SIZE_16(agp_bridge->previous_size); 1000 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1001 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1002 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1003} 1004 1005 1006static void intel_8xx_cleanup(void) 1007{ 1008 u16 temp; 1009 struct aper_size_info_8 *previous_size; 1010 1011 previous_size = A_SIZE_8(agp_bridge->previous_size); 1012 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1013 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1014 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1015} 1016 1017 1018static int intel_configure(void) 1019{ 1020 u32 temp; 1021 u16 temp2; 1022 struct aper_size_info_16 *current_size; 1023 1024 current_size = A_SIZE_16(agp_bridge->current_size); 1025 1026 /* aperture size */ 1027 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1028 1029 /* address to map to */ 1030 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1031 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1032 1033 /* attbase - aperture base */ 1034 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1035 1036 /* agpctrl */ 1037 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1038 1039 /* paccfg/nbxcfg */ 1040 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1041 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1042 (temp2 & ~(1 << 10)) | (1 << 9)); 1043 /* clear any possible error conditions */ 1044 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1045 return 0; 1046} 1047 1048static int intel_815_configure(void) 1049{ 1050 u32 temp, addr; 1051 u8 temp2; 1052 struct aper_size_info_8 *current_size; 1053 1054 /* attbase - aperture base */ 1055 /* the Intel 815 chipset spec. says that bits 29-31 in the 1056 * ATTBASE register are reserved -> try not to write them */ 1057 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1058 printk (KERN_EMERG PFX "gatt bus addr too high"); 1059 return -EINVAL; 1060 } 1061 1062 current_size = A_SIZE_8(agp_bridge->current_size); 1063 1064 /* aperture size */ 1065 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1066 current_size->size_value); 1067 1068 /* address to map to */ 1069 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1070 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1071 1072 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1073 addr &= INTEL_815_ATTBASE_MASK; 1074 addr |= agp_bridge->gatt_bus_addr; 1075 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1076 1077 /* agpctrl */ 1078 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1079 1080 /* apcont */ 1081 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1082 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1083 1084 /* clear any possible error conditions */ 1085 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1086 return 0; 1087} 1088 1089static void intel_820_tlbflush(struct agp_memory *mem) 1090{ 1091 return; 1092} 1093 1094static void intel_820_cleanup(void) 1095{ 1096 u8 temp; 1097 struct aper_size_info_8 *previous_size; 1098 1099 previous_size = A_SIZE_8(agp_bridge->previous_size); 1100 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1101 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1102 temp & ~(1 << 1)); 1103 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1104 previous_size->size_value); 1105} 1106 1107 1108static int intel_820_configure(void) 1109{ 1110 u32 temp; 1111 u8 temp2; 1112 struct aper_size_info_8 *current_size; 1113 1114 current_size = A_SIZE_8(agp_bridge->current_size); 1115 1116 /* aperture size */ 1117 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1118 1119 /* address to map to */ 1120 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1121 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1122 1123 /* attbase - aperture base */ 1124 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1125 1126 /* agpctrl */ 1127 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1128 1129 /* global enable aperture access */ 1130 /* This flag is not accessed through MCHCFG register as in */ 1131 /* i850 chipset. */ 1132 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1133 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1134 /* clear any possible AGP-related error conditions */ 1135 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1136 return 0; 1137} 1138 1139static int intel_840_configure(void) 1140{ 1141 u32 temp; 1142 u16 temp2; 1143 struct aper_size_info_8 *current_size; 1144 1145 current_size = A_SIZE_8(agp_bridge->current_size); 1146 1147 /* aperture size */ 1148 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1149 1150 /* address to map to */ 1151 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1152 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1153 1154 /* attbase - aperture base */ 1155 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1156 1157 /* agpctrl */ 1158 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1159 1160 /* mcgcfg */ 1161 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1162 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1163 /* clear any possible error conditions */ 1164 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1165 return 0; 1166} 1167 1168static int intel_845_configure(void) 1169{ 1170 u32 temp; 1171 u8 temp2; 1172 struct aper_size_info_8 *current_size; 1173 1174 current_size = A_SIZE_8(agp_bridge->current_size); 1175 1176 /* aperture size */ 1177 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1178 1179 if (agp_bridge->apbase_config != 0) { 1180 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1181 agp_bridge->apbase_config); 1182 } else { 1183 /* address to map to */ 1184 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1185 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1186 agp_bridge->apbase_config = temp; 1187 } 1188 1189 /* attbase - aperture base */ 1190 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1191 1192 /* agpctrl */ 1193 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1194 1195 /* agpm */ 1196 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1197 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1198 /* clear any possible error conditions */ 1199 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1200 return 0; 1201} 1202 1203static int intel_850_configure(void) 1204{ 1205 u32 temp; 1206 u16 temp2; 1207 struct aper_size_info_8 *current_size; 1208 1209 current_size = A_SIZE_8(agp_bridge->current_size); 1210 1211 /* aperture size */ 1212 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1213 1214 /* address to map to */ 1215 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1216 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1217 1218 /* attbase - aperture base */ 1219 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1220 1221 /* agpctrl */ 1222 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1223 1224 /* mcgcfg */ 1225 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1226 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1227 /* clear any possible AGP-related error conditions */ 1228 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1229 return 0; 1230} 1231 1232static int intel_860_configure(void) 1233{ 1234 u32 temp; 1235 u16 temp2; 1236 struct aper_size_info_8 *current_size; 1237 1238 current_size = A_SIZE_8(agp_bridge->current_size); 1239 1240 /* aperture size */ 1241 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1242 1243 /* address to map to */ 1244 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1245 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1246 1247 /* attbase - aperture base */ 1248 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1249 1250 /* agpctrl */ 1251 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1252 1253 /* mcgcfg */ 1254 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1255 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1256 /* clear any possible AGP-related error conditions */ 1257 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1258 return 0; 1259} 1260 1261static int intel_830mp_configure(void) 1262{ 1263 u32 temp; 1264 u16 temp2; 1265 struct aper_size_info_8 *current_size; 1266 1267 current_size = A_SIZE_8(agp_bridge->current_size); 1268 1269 /* aperture size */ 1270 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1271 1272 /* address to map to */ 1273 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1274 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1275 1276 /* attbase - aperture base */ 1277 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1278 1279 /* agpctrl */ 1280 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1281 1282 /* gmch */ 1283 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1284 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1285 /* clear any possible AGP-related error conditions */ 1286 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1287 return 0; 1288} 1289 1290static int intel_7505_configure(void) 1291{ 1292 u32 temp; 1293 u16 temp2; 1294 struct aper_size_info_8 *current_size; 1295 1296 current_size = A_SIZE_8(agp_bridge->current_size); 1297 1298 /* aperture size */ 1299 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1300 1301 /* address to map to */ 1302 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1303 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1304 1305 /* attbase - aperture base */ 1306 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1307 1308 /* agpctrl */ 1309 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1310 1311 /* mchcfg */ 1312 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1313 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1314 1315 return 0; 1316} 1317 1318/* Setup function */ 1319static struct gatt_mask intel_generic_masks[] = 1320{ 1321 {.mask = 0x00000017, .type = 0} 1322}; 1323 1324static struct aper_size_info_8 intel_815_sizes[2] = 1325{ 1326 {64, 16384, 4, 0}, 1327 {32, 8192, 3, 8}, 1328}; 1329 1330static struct aper_size_info_8 intel_8xx_sizes[7] = 1331{ 1332 {256, 65536, 6, 0}, 1333 {128, 32768, 5, 32}, 1334 {64, 16384, 4, 48}, 1335 {32, 8192, 3, 56}, 1336 {16, 4096, 2, 60}, 1337 {8, 2048, 1, 62}, 1338 {4, 1024, 0, 63} 1339}; 1340 1341static struct aper_size_info_16 intel_generic_sizes[7] = 1342{ 1343 {256, 65536, 6, 0}, 1344 {128, 32768, 5, 32}, 1345 {64, 16384, 4, 48}, 1346 {32, 8192, 3, 56}, 1347 {16, 4096, 2, 60}, 1348 {8, 2048, 1, 62}, 1349 {4, 1024, 0, 63} 1350}; 1351 1352static struct aper_size_info_8 intel_830mp_sizes[4] = 1353{ 1354 {256, 65536, 6, 0}, 1355 {128, 32768, 5, 32}, 1356 {64, 16384, 4, 48}, 1357 {32, 8192, 3, 56} 1358}; 1359 1360static struct agp_bridge_driver intel_generic_driver = { 1361 .owner = THIS_MODULE, 1362 .aperture_sizes = intel_generic_sizes, 1363 .size_type = U16_APER_SIZE, 1364 .num_aperture_sizes = 7, 1365 .configure = intel_configure, 1366 .fetch_size = intel_fetch_size, 1367 .cleanup = intel_cleanup, 1368 .tlb_flush = intel_tlbflush, 1369 .mask_memory = agp_generic_mask_memory, 1370 .masks = intel_generic_masks, 1371 .agp_enable = agp_generic_enable, 1372 .cache_flush = global_cache_flush, 1373 .create_gatt_table = agp_generic_create_gatt_table, 1374 .free_gatt_table = agp_generic_free_gatt_table, 1375 .insert_memory = agp_generic_insert_memory, 1376 .remove_memory = agp_generic_remove_memory, 1377 .alloc_by_type = agp_generic_alloc_by_type, 1378 .free_by_type = agp_generic_free_by_type, 1379 .agp_alloc_page = agp_generic_alloc_page, 1380 .agp_destroy_page = agp_generic_destroy_page, 1381}; 1382 1383static struct agp_bridge_driver intel_810_driver = { 1384 .owner = THIS_MODULE, 1385 .aperture_sizes = intel_i810_sizes, 1386 .size_type = FIXED_APER_SIZE, 1387 .num_aperture_sizes = 2, 1388 .needs_scratch_page = TRUE, 1389 .configure = intel_i810_configure, 1390 .fetch_size = intel_i810_fetch_size, 1391 .cleanup = intel_i810_cleanup, 1392 .tlb_flush = intel_i810_tlbflush, 1393 .mask_memory = intel_i810_mask_memory, 1394 .masks = intel_i810_masks, 1395 .agp_enable = intel_i810_agp_enable, 1396 .cache_flush = global_cache_flush, 1397 .create_gatt_table = agp_generic_create_gatt_table, 1398 .free_gatt_table = agp_generic_free_gatt_table, 1399 .insert_memory = intel_i810_insert_entries, 1400 .remove_memory = intel_i810_remove_entries, 1401 .alloc_by_type = intel_i810_alloc_by_type, 1402 .free_by_type = intel_i810_free_by_type, 1403 .agp_alloc_page = agp_generic_alloc_page, 1404 .agp_destroy_page = agp_generic_destroy_page, 1405}; 1406 1407static struct agp_bridge_driver intel_815_driver = { 1408 .owner = THIS_MODULE, 1409 .aperture_sizes = intel_815_sizes, 1410 .size_type = U8_APER_SIZE, 1411 .num_aperture_sizes = 2, 1412 .configure = intel_815_configure, 1413 .fetch_size = intel_815_fetch_size, 1414 .cleanup = intel_8xx_cleanup, 1415 .tlb_flush = intel_8xx_tlbflush, 1416 .mask_memory = agp_generic_mask_memory, 1417 .masks = intel_generic_masks, 1418 .agp_enable = agp_generic_enable, 1419 .cache_flush = global_cache_flush, 1420 .create_gatt_table = agp_generic_create_gatt_table, 1421 .free_gatt_table = agp_generic_free_gatt_table, 1422 .insert_memory = agp_generic_insert_memory, 1423 .remove_memory = agp_generic_remove_memory, 1424 .alloc_by_type = agp_generic_alloc_by_type, 1425 .free_by_type = agp_generic_free_by_type, 1426 .agp_alloc_page = agp_generic_alloc_page, 1427 .agp_destroy_page = agp_generic_destroy_page, 1428}; 1429 1430static struct agp_bridge_driver intel_830_driver = { 1431 .owner = THIS_MODULE, 1432 .aperture_sizes = intel_i830_sizes, 1433 .size_type = FIXED_APER_SIZE, 1434 .num_aperture_sizes = 4, 1435 .needs_scratch_page = TRUE, 1436 .configure = intel_i830_configure, 1437 .fetch_size = intel_i830_fetch_size, 1438 .cleanup = intel_i830_cleanup, 1439 .tlb_flush = intel_i810_tlbflush, 1440 .mask_memory = intel_i810_mask_memory, 1441 .masks = intel_i810_masks, 1442 .agp_enable = intel_i810_agp_enable, 1443 .cache_flush = global_cache_flush, 1444 .create_gatt_table = intel_i830_create_gatt_table, 1445 .free_gatt_table = intel_i830_free_gatt_table, 1446 .insert_memory = intel_i830_insert_entries, 1447 .remove_memory = intel_i830_remove_entries, 1448 .alloc_by_type = intel_i830_alloc_by_type, 1449 .free_by_type = intel_i810_free_by_type, 1450 .agp_alloc_page = agp_generic_alloc_page, 1451 .agp_destroy_page = agp_generic_destroy_page, 1452}; 1453 1454static struct agp_bridge_driver intel_820_driver = { 1455 .owner = THIS_MODULE, 1456 .aperture_sizes = intel_8xx_sizes, 1457 .size_type = U8_APER_SIZE, 1458 .num_aperture_sizes = 7, 1459 .configure = intel_820_configure, 1460 .fetch_size = intel_8xx_fetch_size, 1461 .cleanup = intel_820_cleanup, 1462 .tlb_flush = intel_820_tlbflush, 1463 .mask_memory = agp_generic_mask_memory, 1464 .masks = intel_generic_masks, 1465 .agp_enable = agp_generic_enable, 1466 .cache_flush = global_cache_flush, 1467 .create_gatt_table = agp_generic_create_gatt_table, 1468 .free_gatt_table = agp_generic_free_gatt_table, 1469 .insert_memory = agp_generic_insert_memory, 1470 .remove_memory = agp_generic_remove_memory, 1471 .alloc_by_type = agp_generic_alloc_by_type, 1472 .free_by_type = agp_generic_free_by_type, 1473 .agp_alloc_page = agp_generic_alloc_page, 1474 .agp_destroy_page = agp_generic_destroy_page, 1475}; 1476 1477static struct agp_bridge_driver intel_830mp_driver = { 1478 .owner = THIS_MODULE, 1479 .aperture_sizes = intel_830mp_sizes, 1480 .size_type = U8_APER_SIZE, 1481 .num_aperture_sizes = 4, 1482 .configure = intel_830mp_configure, 1483 .fetch_size = intel_8xx_fetch_size, 1484 .cleanup = intel_8xx_cleanup, 1485 .tlb_flush = intel_8xx_tlbflush, 1486 .mask_memory = agp_generic_mask_memory, 1487 .masks = intel_generic_masks, 1488 .agp_enable = agp_generic_enable, 1489 .cache_flush = global_cache_flush, 1490 .create_gatt_table = agp_generic_create_gatt_table, 1491 .free_gatt_table = agp_generic_free_gatt_table, 1492 .insert_memory = agp_generic_insert_memory, 1493 .remove_memory = agp_generic_remove_memory, 1494 .alloc_by_type = agp_generic_alloc_by_type, 1495 .free_by_type = agp_generic_free_by_type, 1496 .agp_alloc_page = agp_generic_alloc_page, 1497 .agp_destroy_page = agp_generic_destroy_page, 1498}; 1499 1500static struct agp_bridge_driver intel_840_driver = { 1501 .owner = THIS_MODULE, 1502 .aperture_sizes = intel_8xx_sizes, 1503 .size_type = U8_APER_SIZE, 1504 .num_aperture_sizes = 7, 1505 .configure = intel_840_configure, 1506 .fetch_size = intel_8xx_fetch_size, 1507 .cleanup = intel_8xx_cleanup, 1508 .tlb_flush = intel_8xx_tlbflush, 1509 .mask_memory = agp_generic_mask_memory, 1510 .masks = intel_generic_masks, 1511 .agp_enable = agp_generic_enable, 1512 .cache_flush = global_cache_flush, 1513 .create_gatt_table = agp_generic_create_gatt_table, 1514 .free_gatt_table = agp_generic_free_gatt_table, 1515 .insert_memory = agp_generic_insert_memory, 1516 .remove_memory = agp_generic_remove_memory, 1517 .alloc_by_type = agp_generic_alloc_by_type, 1518 .free_by_type = agp_generic_free_by_type, 1519 .agp_alloc_page = agp_generic_alloc_page, 1520 .agp_destroy_page = agp_generic_destroy_page, 1521}; 1522 1523static struct agp_bridge_driver intel_845_driver = { 1524 .owner = THIS_MODULE, 1525 .aperture_sizes = intel_8xx_sizes, 1526 .size_type = U8_APER_SIZE, 1527 .num_aperture_sizes = 7, 1528 .configure = intel_845_configure, 1529 .fetch_size = intel_8xx_fetch_size, 1530 .cleanup = intel_8xx_cleanup, 1531 .tlb_flush = intel_8xx_tlbflush, 1532 .mask_memory = agp_generic_mask_memory, 1533 .masks = intel_generic_masks, 1534 .agp_enable = agp_generic_enable, 1535 .cache_flush = global_cache_flush, 1536 .create_gatt_table = agp_generic_create_gatt_table, 1537 .free_gatt_table = agp_generic_free_gatt_table, 1538 .insert_memory = agp_generic_insert_memory, 1539 .remove_memory = agp_generic_remove_memory, 1540 .alloc_by_type = agp_generic_alloc_by_type, 1541 .free_by_type = agp_generic_free_by_type, 1542 .agp_alloc_page = agp_generic_alloc_page, 1543 .agp_destroy_page = agp_generic_destroy_page, 1544}; 1545 1546static struct agp_bridge_driver intel_850_driver = { 1547 .owner = THIS_MODULE, 1548 .aperture_sizes = intel_8xx_sizes, 1549 .size_type = U8_APER_SIZE, 1550 .num_aperture_sizes = 7, 1551 .configure = intel_850_configure, 1552 .fetch_size = intel_8xx_fetch_size, 1553 .cleanup = intel_8xx_cleanup, 1554 .tlb_flush = intel_8xx_tlbflush, 1555 .mask_memory = agp_generic_mask_memory, 1556 .masks = intel_generic_masks, 1557 .agp_enable = agp_generic_enable, 1558 .cache_flush = global_cache_flush, 1559 .create_gatt_table = agp_generic_create_gatt_table, 1560 .free_gatt_table = agp_generic_free_gatt_table, 1561 .insert_memory = agp_generic_insert_memory, 1562 .remove_memory = agp_generic_remove_memory, 1563 .alloc_by_type = agp_generic_alloc_by_type, 1564 .free_by_type = agp_generic_free_by_type, 1565 .agp_alloc_page = agp_generic_alloc_page, 1566 .agp_destroy_page = agp_generic_destroy_page, 1567}; 1568 1569static struct agp_bridge_driver intel_860_driver = { 1570 .owner = THIS_MODULE, 1571 .aperture_sizes = intel_8xx_sizes, 1572 .size_type = U8_APER_SIZE, 1573 .num_aperture_sizes = 7, 1574 .configure = intel_860_configure, 1575 .fetch_size = intel_8xx_fetch_size, 1576 .cleanup = intel_8xx_cleanup, 1577 .tlb_flush = intel_8xx_tlbflush, 1578 .mask_memory = agp_generic_mask_memory, 1579 .masks = intel_generic_masks, 1580 .agp_enable = agp_generic_enable, 1581 .cache_flush = global_cache_flush, 1582 .create_gatt_table = agp_generic_create_gatt_table, 1583 .free_gatt_table = agp_generic_free_gatt_table, 1584 .insert_memory = agp_generic_insert_memory, 1585 .remove_memory = agp_generic_remove_memory, 1586 .alloc_by_type = agp_generic_alloc_by_type, 1587 .free_by_type = agp_generic_free_by_type, 1588 .agp_alloc_page = agp_generic_alloc_page, 1589 .agp_destroy_page = agp_generic_destroy_page, 1590}; 1591 1592static struct agp_bridge_driver intel_915_driver = { 1593 .owner = THIS_MODULE, 1594 .aperture_sizes = intel_i830_sizes, 1595 .size_type = FIXED_APER_SIZE, 1596 .num_aperture_sizes = 4, 1597 .needs_scratch_page = TRUE, 1598 .configure = intel_i915_configure, 1599 .fetch_size = intel_i915_fetch_size, 1600 .cleanup = intel_i915_cleanup, 1601 .tlb_flush = intel_i810_tlbflush, 1602 .mask_memory = intel_i810_mask_memory, 1603 .masks = intel_i810_masks, 1604 .agp_enable = intel_i810_agp_enable, 1605 .cache_flush = global_cache_flush, 1606 .create_gatt_table = intel_i915_create_gatt_table, 1607 .free_gatt_table = intel_i830_free_gatt_table, 1608 .insert_memory = intel_i915_insert_entries, 1609 .remove_memory = intel_i915_remove_entries, 1610 .alloc_by_type = intel_i830_alloc_by_type, 1611 .free_by_type = intel_i810_free_by_type, 1612 .agp_alloc_page = agp_generic_alloc_page, 1613 .agp_destroy_page = agp_generic_destroy_page, 1614}; 1615 1616static struct agp_bridge_driver intel_i965_driver = { 1617 .owner = THIS_MODULE, 1618 .aperture_sizes = intel_i830_sizes, 1619 .size_type = FIXED_APER_SIZE, 1620 .num_aperture_sizes = 4, 1621 .needs_scratch_page = TRUE, 1622 .configure = intel_i915_configure, 1623 .fetch_size = intel_i965_fetch_size, 1624 .cleanup = intel_i915_cleanup, 1625 .tlb_flush = intel_i810_tlbflush, 1626 .mask_memory = intel_i965_mask_memory, 1627 .masks = intel_i810_masks, 1628 .agp_enable = intel_i810_agp_enable, 1629 .cache_flush = global_cache_flush, 1630 .create_gatt_table = intel_i965_create_gatt_table, 1631 .free_gatt_table = intel_i830_free_gatt_table, 1632 .insert_memory = intel_i915_insert_entries, 1633 .remove_memory = intel_i915_remove_entries, 1634 .alloc_by_type = intel_i830_alloc_by_type, 1635 .free_by_type = intel_i810_free_by_type, 1636 .agp_alloc_page = agp_generic_alloc_page, 1637 .agp_destroy_page = agp_generic_destroy_page, 1638}; 1639 1640static struct agp_bridge_driver intel_7505_driver = { 1641 .owner = THIS_MODULE, 1642 .aperture_sizes = intel_8xx_sizes, 1643 .size_type = U8_APER_SIZE, 1644 .num_aperture_sizes = 7, 1645 .configure = intel_7505_configure, 1646 .fetch_size = intel_8xx_fetch_size, 1647 .cleanup = intel_8xx_cleanup, 1648 .tlb_flush = intel_8xx_tlbflush, 1649 .mask_memory = agp_generic_mask_memory, 1650 .masks = intel_generic_masks, 1651 .agp_enable = agp_generic_enable, 1652 .cache_flush = global_cache_flush, 1653 .create_gatt_table = agp_generic_create_gatt_table, 1654 .free_gatt_table = agp_generic_free_gatt_table, 1655 .insert_memory = agp_generic_insert_memory, 1656 .remove_memory = agp_generic_remove_memory, 1657 .alloc_by_type = agp_generic_alloc_by_type, 1658 .free_by_type = agp_generic_free_by_type, 1659 .agp_alloc_page = agp_generic_alloc_page, 1660 .agp_destroy_page = agp_generic_destroy_page, 1661}; 1662 1663static int find_i810(u16 device) 1664{ 1665 struct pci_dev *i810_dev; 1666 1667 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1668 if (!i810_dev) 1669 return 0; 1670 intel_i810_private.i810_dev = i810_dev; 1671 return 1; 1672} 1673 1674static int find_i830(u16 device) 1675{ 1676 struct pci_dev *i830_dev; 1677 1678 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1679 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) { 1680 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 1681 device, i830_dev); 1682 } 1683 1684 if (!i830_dev) 1685 return 0; 1686 1687 intel_i830_private.i830_dev = i830_dev; 1688 return 1; 1689} 1690 1691static int __devinit agp_intel_probe(struct pci_dev *pdev, 1692 const struct pci_device_id *ent) 1693{ 1694 struct agp_bridge_data *bridge; 1695 char *name = "(unknown)"; 1696 u8 cap_ptr = 0; 1697 struct resource *r; 1698 1699 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1700 1701 bridge = agp_alloc_bridge(); 1702 if (!bridge) 1703 return -ENOMEM; 1704 1705 switch (pdev->device) { 1706 case PCI_DEVICE_ID_INTEL_82443LX_0: 1707 bridge->driver = &intel_generic_driver; 1708 name = "440LX"; 1709 break; 1710 case PCI_DEVICE_ID_INTEL_82443BX_0: 1711 bridge->driver = &intel_generic_driver; 1712 name = "440BX"; 1713 break; 1714 case PCI_DEVICE_ID_INTEL_82443GX_0: 1715 bridge->driver = &intel_generic_driver; 1716 name = "440GX"; 1717 break; 1718 case PCI_DEVICE_ID_INTEL_82810_MC1: 1719 name = "i810"; 1720 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1)) 1721 goto fail; 1722 bridge->driver = &intel_810_driver; 1723 break; 1724 case PCI_DEVICE_ID_INTEL_82810_MC3: 1725 name = "i810 DC100"; 1726 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3)) 1727 goto fail; 1728 bridge->driver = &intel_810_driver; 1729 break; 1730 case PCI_DEVICE_ID_INTEL_82810E_MC: 1731 name = "i810 E"; 1732 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG)) 1733 goto fail; 1734 bridge->driver = &intel_810_driver; 1735 break; 1736 case PCI_DEVICE_ID_INTEL_82815_MC: 1737 /* 1738 * The i815 can operate either as an i810 style 1739 * integrated device, or as an AGP4X motherboard. 1740 */ 1741 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC)) 1742 bridge->driver = &intel_810_driver; 1743 else 1744 bridge->driver = &intel_815_driver; 1745 name = "i815"; 1746 break; 1747 case PCI_DEVICE_ID_INTEL_82820_HB: 1748 case PCI_DEVICE_ID_INTEL_82820_UP_HB: 1749 bridge->driver = &intel_820_driver; 1750 name = "i820"; 1751 break; 1752 case PCI_DEVICE_ID_INTEL_82830_HB: 1753 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) 1754 bridge->driver = &intel_830_driver; 1755 else 1756 bridge->driver = &intel_830mp_driver; 1757 name = "830M"; 1758 break; 1759 case PCI_DEVICE_ID_INTEL_82840_HB: 1760 bridge->driver = &intel_840_driver; 1761 name = "i840"; 1762 break; 1763 case PCI_DEVICE_ID_INTEL_82845_HB: 1764 bridge->driver = &intel_845_driver; 1765 name = "i845"; 1766 break; 1767 case PCI_DEVICE_ID_INTEL_82845G_HB: 1768 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) 1769 bridge->driver = &intel_830_driver; 1770 else 1771 bridge->driver = &intel_845_driver; 1772 name = "845G"; 1773 break; 1774 case PCI_DEVICE_ID_INTEL_82850_HB: 1775 bridge->driver = &intel_850_driver; 1776 name = "i850"; 1777 break; 1778 case PCI_DEVICE_ID_INTEL_82855PM_HB: 1779 bridge->driver = &intel_845_driver; 1780 name = "855PM"; 1781 break; 1782 case PCI_DEVICE_ID_INTEL_82855GM_HB: 1783 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) { 1784 bridge->driver = &intel_830_driver; 1785 name = "855"; 1786 } else { 1787 bridge->driver = &intel_845_driver; 1788 name = "855GM"; 1789 } 1790 break; 1791 case PCI_DEVICE_ID_INTEL_82860_HB: 1792 bridge->driver = &intel_860_driver; 1793 name = "i860"; 1794 break; 1795 case PCI_DEVICE_ID_INTEL_82865_HB: 1796 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) 1797 bridge->driver = &intel_830_driver; 1798 else 1799 bridge->driver = &intel_845_driver; 1800 name = "865"; 1801 break; 1802 case PCI_DEVICE_ID_INTEL_82875_HB: 1803 bridge->driver = &intel_845_driver; 1804 name = "i875"; 1805 break; 1806 case PCI_DEVICE_ID_INTEL_82915G_HB: 1807 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) 1808 bridge->driver = &intel_915_driver; 1809 else 1810 bridge->driver = &intel_845_driver; 1811 name = "915G"; 1812 break; 1813 case PCI_DEVICE_ID_INTEL_82915GM_HB: 1814 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) 1815 bridge->driver = &intel_915_driver; 1816 else 1817 bridge->driver = &intel_845_driver; 1818 name = "915GM"; 1819 break; 1820 case PCI_DEVICE_ID_INTEL_82945G_HB: 1821 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) 1822 bridge->driver = &intel_915_driver; 1823 else 1824 bridge->driver = &intel_845_driver; 1825 name = "945G"; 1826 break; 1827 case PCI_DEVICE_ID_INTEL_82945GM_HB: 1828 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG)) 1829 bridge->driver = &intel_915_driver; 1830 else 1831 bridge->driver = &intel_845_driver; 1832 name = "945GM"; 1833 break; 1834 case PCI_DEVICE_ID_INTEL_82946GZ_HB: 1835 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG)) 1836 bridge->driver = &intel_i965_driver; 1837 else 1838 bridge->driver = &intel_845_driver; 1839 name = "946GZ"; 1840 break; 1841 case PCI_DEVICE_ID_INTEL_82965G_1_HB: 1842 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG)) 1843 bridge->driver = &intel_i965_driver; 1844 else 1845 bridge->driver = &intel_845_driver; 1846 name = "965G"; 1847 break; 1848 case PCI_DEVICE_ID_INTEL_82965Q_HB: 1849 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG)) 1850 bridge->driver = &intel_i965_driver; 1851 else 1852 bridge->driver = &intel_845_driver; 1853 name = "965Q"; 1854 break; 1855 case PCI_DEVICE_ID_INTEL_82965G_HB: 1856 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG)) 1857 bridge->driver = &intel_i965_driver; 1858 else 1859 bridge->driver = &intel_845_driver; 1860 name = "965G"; 1861 break; 1862 1863 case PCI_DEVICE_ID_INTEL_7505_0: 1864 bridge->driver = &intel_7505_driver; 1865 name = "E7505"; 1866 break; 1867 case PCI_DEVICE_ID_INTEL_7205_0: 1868 bridge->driver = &intel_7505_driver; 1869 name = "E7205"; 1870 break; 1871 default: 1872 if (cap_ptr) 1873 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n", 1874 pdev->device); 1875 agp_put_bridge(bridge); 1876 return -ENODEV; 1877 }; 1878 1879 bridge->dev = pdev; 1880 bridge->capndx = cap_ptr; 1881 1882 if (bridge->driver == &intel_810_driver) 1883 bridge->dev_private_data = &intel_i810_private; 1884 else if (bridge->driver == &intel_830_driver) 1885 bridge->dev_private_data = &intel_i830_private; 1886 1887 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); 1888 1889 /* 1890 * The following fixes the case where the BIOS has "forgotten" to 1891 * provide an address range for the GART. 1892 * 20030610 - hamish@zot.org 1893 */ 1894 r = &pdev->resource[0]; 1895 if (!r->start && r->end) { 1896 if (pci_assign_resource(pdev, 0)) { 1897 printk(KERN_ERR PFX "could not assign resource 0\n"); 1898 agp_put_bridge(bridge); 1899 return -ENODEV; 1900 } 1901 } 1902 1903 /* 1904 * If the device has not been properly setup, the following will catch 1905 * the problem and should stop the system from crashing. 1906 * 20030610 - hamish@zot.org 1907 */ 1908 if (pci_enable_device(pdev)) { 1909 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1910 agp_put_bridge(bridge); 1911 return -ENODEV; 1912 } 1913 1914 /* Fill in the mode register */ 1915 if (cap_ptr) { 1916 pci_read_config_dword(pdev, 1917 bridge->capndx+PCI_AGP_STATUS, 1918 &bridge->mode); 1919 } 1920 1921 pci_set_drvdata(pdev, bridge); 1922 return agp_add_bridge(bridge); 1923 1924fail: 1925 printk(KERN_ERR PFX "Detected an Intel %s chipset, " 1926 "but could not find the secondary device.\n", name); 1927 agp_put_bridge(bridge); 1928 return -ENODEV; 1929} 1930 1931static void __devexit agp_intel_remove(struct pci_dev *pdev) 1932{ 1933 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1934 1935 agp_remove_bridge(bridge); 1936 1937 if (intel_i810_private.i810_dev) 1938 pci_dev_put(intel_i810_private.i810_dev); 1939 if (intel_i830_private.i830_dev) 1940 pci_dev_put(intel_i830_private.i830_dev); 1941 1942 agp_put_bridge(bridge); 1943} 1944 1945#ifdef CONFIG_PM 1946static int agp_intel_resume(struct pci_dev *pdev) 1947{ 1948 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1949 1950 pci_restore_state(pdev); 1951 1952 if (bridge->driver == &intel_generic_driver) 1953 intel_configure(); 1954 else if (bridge->driver == &intel_850_driver) 1955 intel_850_configure(); 1956 else if (bridge->driver == &intel_845_driver) 1957 intel_845_configure(); 1958 else if (bridge->driver == &intel_830mp_driver) 1959 intel_830mp_configure(); 1960 else if (bridge->driver == &intel_915_driver) 1961 intel_i915_configure(); 1962 else if (bridge->driver == &intel_830_driver) 1963 intel_i830_configure(); 1964 else if (bridge->driver == &intel_810_driver) 1965 intel_i810_configure(); 1966 else if (bridge->driver == &intel_i965_driver) 1967 intel_i915_configure(); 1968 1969 return 0; 1970} 1971#endif 1972 1973static struct pci_device_id agp_intel_pci_table[] = { 1974#define ID(x) \ 1975 { \ 1976 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 1977 .class_mask = ~0, \ 1978 .vendor = PCI_VENDOR_ID_INTEL, \ 1979 .device = x, \ 1980 .subvendor = PCI_ANY_ID, \ 1981 .subdevice = PCI_ANY_ID, \ 1982 } 1983 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 1984 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 1985 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 1986 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 1987 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 1988 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 1989 ID(PCI_DEVICE_ID_INTEL_82815_MC), 1990 ID(PCI_DEVICE_ID_INTEL_82820_HB), 1991 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 1992 ID(PCI_DEVICE_ID_INTEL_82830_HB), 1993 ID(PCI_DEVICE_ID_INTEL_82840_HB), 1994 ID(PCI_DEVICE_ID_INTEL_82845_HB), 1995 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 1996 ID(PCI_DEVICE_ID_INTEL_82850_HB), 1997 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 1998 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 1999 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2000 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2001 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2002 ID(PCI_DEVICE_ID_INTEL_7505_0), 2003 ID(PCI_DEVICE_ID_INTEL_7205_0), 2004 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2005 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2006 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2007 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2008 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2009 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB), 2010 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2011 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2012 { } 2013}; 2014 2015MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2016 2017static struct pci_driver agp_intel_pci_driver = { 2018 .name = "agpgart-intel", 2019 .id_table = agp_intel_pci_table, 2020 .probe = agp_intel_probe, 2021 .remove = __devexit_p(agp_intel_remove), 2022#ifdef CONFIG_PM 2023 .resume = agp_intel_resume, 2024#endif 2025}; 2026 2027static int __init agp_intel_init(void) 2028{ 2029 if (agp_off) 2030 return -EINVAL; 2031 return pci_register_driver(&agp_intel_pci_driver); 2032} 2033 2034static void __exit agp_intel_cleanup(void) 2035{ 2036 pci_unregister_driver(&agp_intel_pci_driver); 2037} 2038 2039module_init(agp_intel_init); 2040module_exit(agp_intel_cleanup); 2041 2042MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 2043MODULE_LICENSE("GPL and additional rights"); 2044