intel-agp.c revision 5e64499f3d39c633de49320e399479642c2b1743
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include <asm/smp.h> 12#include "agp.h" 13 14int intel_agp_enabled; 15EXPORT_SYMBOL(intel_agp_enabled); 16 17/* 18 * If we have Intel graphics, we're not going to have anything other than 19 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 20 * on the Intel IOMMU support (CONFIG_DMAR). 21 * Only newer chipsets need to bother with this, of course. 22 */ 23#ifdef CONFIG_DMAR 24#define USE_PCI_DMA_API 1 25#endif 26 27#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 28#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 29#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 30#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 31#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 32#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 33#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 34#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 35#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 36#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 37#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 38#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 39#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 40#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 41#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 42#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 43#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 44#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 45#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 46#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 47#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 48#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 49#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 50#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 51#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 52#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 53#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 54#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 55#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 56#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 57#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 58#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 59#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 60#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 61#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 62#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 63#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 64#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 65#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 66#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 67#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 68#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 69#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a 70#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 71#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 72#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 73#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 74#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106 75 76/* cover 915 and 945 variants */ 77#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 83 84#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) 90 91#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ 94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 96 97#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 99 100#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ 101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) 102 103#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ 104 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 106 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ 109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ 110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ 111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ 112 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ 113 IS_SNB) 114 115extern int agp_memory_reserved; 116 117 118/* Intel 815 register */ 119#define INTEL_815_APCONT 0x51 120#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 121 122/* Intel i820 registers */ 123#define INTEL_I820_RDCR 0x51 124#define INTEL_I820_ERRSTS 0xc8 125 126/* Intel i840 registers */ 127#define INTEL_I840_MCHCFG 0x50 128#define INTEL_I840_ERRSTS 0xc8 129 130/* Intel i850 registers */ 131#define INTEL_I850_MCHCFG 0x50 132#define INTEL_I850_ERRSTS 0xc8 133 134/* intel 915G registers */ 135#define I915_GMADDR 0x18 136#define I915_MMADDR 0x10 137#define I915_PTEADDR 0x1C 138#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 139#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 140#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 141#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 142#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 143#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 144#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 145#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 146 147#define I915_IFPADDR 0x60 148 149/* Intel 965G registers */ 150#define I965_MSAC 0x62 151#define I965_IFPADDR 0x70 152 153/* Intel 7505 registers */ 154#define INTEL_I7505_APSIZE 0x74 155#define INTEL_I7505_NCAPID 0x60 156#define INTEL_I7505_NISTAT 0x6c 157#define INTEL_I7505_ATTBASE 0x78 158#define INTEL_I7505_ERRSTS 0x42 159#define INTEL_I7505_AGPCTRL 0x70 160#define INTEL_I7505_MCHCFG 0x50 161 162#define SNB_GMCH_CTRL 0x50 163#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 164#define SNB_GMCH_GMS_STOLEN_32M (1 << 3) 165#define SNB_GMCH_GMS_STOLEN_64M (2 << 3) 166#define SNB_GMCH_GMS_STOLEN_96M (3 << 3) 167#define SNB_GMCH_GMS_STOLEN_128M (4 << 3) 168#define SNB_GMCH_GMS_STOLEN_160M (5 << 3) 169#define SNB_GMCH_GMS_STOLEN_192M (6 << 3) 170#define SNB_GMCH_GMS_STOLEN_224M (7 << 3) 171#define SNB_GMCH_GMS_STOLEN_256M (8 << 3) 172#define SNB_GMCH_GMS_STOLEN_288M (9 << 3) 173#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) 174#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) 175#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) 176#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) 177#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 178#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 179#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 180#define SNB_GTT_SIZE_0M (0 << 8) 181#define SNB_GTT_SIZE_1M (1 << 8) 182#define SNB_GTT_SIZE_2M (2 << 8) 183#define SNB_GTT_SIZE_MASK (3 << 8) 184 185static const struct aper_size_info_fixed intel_i810_sizes[] = 186{ 187 {64, 16384, 4}, 188 /* The 32M mode still requires a 64k gatt */ 189 {32, 8192, 4} 190}; 191 192#define AGP_DCACHE_MEMORY 1 193#define AGP_PHYS_MEMORY 2 194#define INTEL_AGP_CACHED_MEMORY 3 195 196static struct gatt_mask intel_i810_masks[] = 197{ 198 {.mask = I810_PTE_VALID, .type = 0}, 199 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 200 {.mask = I810_PTE_VALID, .type = 0}, 201 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 202 .type = INTEL_AGP_CACHED_MEMORY} 203}; 204 205static struct _intel_private { 206 struct pci_dev *pcidev; /* device one */ 207 u8 __iomem *registers; 208 u32 __iomem *gtt; /* I915G */ 209 int num_dcache_entries; 210 /* gtt_entries is the number of gtt entries that are already mapped 211 * to stolen memory. Stolen memory is larger than the memory mapped 212 * through gtt_entries, as it includes some reserved space for the BIOS 213 * popup and for the GTT. 214 */ 215 int gtt_entries; /* i830+ */ 216 int gtt_total_size; 217 union { 218 void __iomem *i9xx_flush_page; 219 void *i8xx_flush_page; 220 }; 221 struct page *i8xx_page; 222 struct resource ifp_resource; 223 int resource_valid; 224} intel_private; 225 226#ifdef USE_PCI_DMA_API 227static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 228{ 229 *ret = pci_map_page(intel_private.pcidev, page, 0, 230 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 231 if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 232 return -EINVAL; 233 return 0; 234} 235 236static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 237{ 238 pci_unmap_page(intel_private.pcidev, dma, 239 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 240} 241 242static void intel_agp_free_sglist(struct agp_memory *mem) 243{ 244 struct sg_table st; 245 246 st.sgl = mem->sg_list; 247 st.orig_nents = st.nents = mem->page_count; 248 249 sg_free_table(&st); 250 251 mem->sg_list = NULL; 252 mem->num_sg = 0; 253} 254 255static int intel_agp_map_memory(struct agp_memory *mem) 256{ 257 struct sg_table st; 258 struct scatterlist *sg; 259 int i; 260 261 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 262 263 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 264 return -ENOMEM; 265 266 mem->sg_list = sg = st.sgl; 267 268 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 269 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 270 271 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 272 mem->page_count, PCI_DMA_BIDIRECTIONAL); 273 if (unlikely(!mem->num_sg)) { 274 intel_agp_free_sglist(mem); 275 return -ENOMEM; 276 } 277 return 0; 278} 279 280static void intel_agp_unmap_memory(struct agp_memory *mem) 281{ 282 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 283 284 pci_unmap_sg(intel_private.pcidev, mem->sg_list, 285 mem->page_count, PCI_DMA_BIDIRECTIONAL); 286 intel_agp_free_sglist(mem); 287} 288 289static void intel_agp_insert_sg_entries(struct agp_memory *mem, 290 off_t pg_start, int mask_type) 291{ 292 struct scatterlist *sg; 293 int i, j; 294 295 j = pg_start; 296 297 WARN_ON(!mem->num_sg); 298 299 if (mem->num_sg == mem->page_count) { 300 for_each_sg(mem->sg_list, sg, mem->page_count, i) { 301 writel(agp_bridge->driver->mask_memory(agp_bridge, 302 sg_dma_address(sg), mask_type), 303 intel_private.gtt+j); 304 j++; 305 } 306 } else { 307 /* sg may merge pages, but we have to separate 308 * per-page addr for GTT */ 309 unsigned int len, m; 310 311 for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 312 len = sg_dma_len(sg) / PAGE_SIZE; 313 for (m = 0; m < len; m++) { 314 writel(agp_bridge->driver->mask_memory(agp_bridge, 315 sg_dma_address(sg) + m * PAGE_SIZE, 316 mask_type), 317 intel_private.gtt+j); 318 j++; 319 } 320 } 321 } 322 readl(intel_private.gtt+j-1); 323} 324 325#else 326 327static void intel_agp_insert_sg_entries(struct agp_memory *mem, 328 off_t pg_start, int mask_type) 329{ 330 int i, j; 331 u32 cache_bits = 0; 332 333 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || 334 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) 335 { 336 cache_bits = I830_PTE_SYSTEM_CACHED; 337 } 338 339 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 340 writel(agp_bridge->driver->mask_memory(agp_bridge, 341 page_to_phys(mem->pages[i]), mask_type), 342 intel_private.gtt+j); 343 } 344 345 readl(intel_private.gtt+j-1); 346} 347 348#endif 349 350static int intel_i810_fetch_size(void) 351{ 352 u32 smram_miscc; 353 struct aper_size_info_fixed *values; 354 355 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 356 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 357 358 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 359 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 360 return 0; 361 } 362 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 363 agp_bridge->previous_size = 364 agp_bridge->current_size = (void *) (values + 1); 365 agp_bridge->aperture_size_idx = 1; 366 return values[1].size; 367 } else { 368 agp_bridge->previous_size = 369 agp_bridge->current_size = (void *) (values); 370 agp_bridge->aperture_size_idx = 0; 371 return values[0].size; 372 } 373 374 return 0; 375} 376 377static int intel_i810_configure(void) 378{ 379 struct aper_size_info_fixed *current_size; 380 u32 temp; 381 int i; 382 383 current_size = A_SIZE_FIX(agp_bridge->current_size); 384 385 if (!intel_private.registers) { 386 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 387 temp &= 0xfff80000; 388 389 intel_private.registers = ioremap(temp, 128 * 4096); 390 if (!intel_private.registers) { 391 dev_err(&intel_private.pcidev->dev, 392 "can't remap memory\n"); 393 return -ENOMEM; 394 } 395 } 396 397 if ((readl(intel_private.registers+I810_DRAM_CTL) 398 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 399 /* This will need to be dynamically assigned */ 400 dev_info(&intel_private.pcidev->dev, 401 "detected 4MB dedicated video ram\n"); 402 intel_private.num_dcache_entries = 1024; 403 } 404 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 405 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 406 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 407 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 408 409 if (agp_bridge->driver->needs_scratch_page) { 410 for (i = 0; i < current_size->num_entries; i++) { 411 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 412 } 413 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 414 } 415 global_cache_flush(); 416 return 0; 417} 418 419static void intel_i810_cleanup(void) 420{ 421 writel(0, intel_private.registers+I810_PGETBL_CTL); 422 readl(intel_private.registers); /* PCI Posting. */ 423 iounmap(intel_private.registers); 424} 425 426static void intel_i810_tlbflush(struct agp_memory *mem) 427{ 428 return; 429} 430 431static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 432{ 433 return; 434} 435 436/* Exists to support ARGB cursors */ 437static struct page *i8xx_alloc_pages(void) 438{ 439 struct page *page; 440 441 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 442 if (page == NULL) 443 return NULL; 444 445 if (set_pages_uc(page, 4) < 0) { 446 set_pages_wb(page, 4); 447 __free_pages(page, 2); 448 return NULL; 449 } 450 get_page(page); 451 atomic_inc(&agp_bridge->current_memory_agp); 452 return page; 453} 454 455static void i8xx_destroy_pages(struct page *page) 456{ 457 if (page == NULL) 458 return; 459 460 set_pages_wb(page, 4); 461 put_page(page); 462 __free_pages(page, 2); 463 atomic_dec(&agp_bridge->current_memory_agp); 464} 465 466static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 467 int type) 468{ 469 if (type < AGP_USER_TYPES) 470 return type; 471 else if (type == AGP_USER_CACHED_MEMORY) 472 return INTEL_AGP_CACHED_MEMORY; 473 else 474 return 0; 475} 476 477static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 478 int type) 479{ 480 int i, j, num_entries; 481 void *temp; 482 int ret = -EINVAL; 483 int mask_type; 484 485 if (mem->page_count == 0) 486 goto out; 487 488 temp = agp_bridge->current_size; 489 num_entries = A_SIZE_FIX(temp)->num_entries; 490 491 if ((pg_start + mem->page_count) > num_entries) 492 goto out_err; 493 494 495 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 496 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 497 ret = -EBUSY; 498 goto out_err; 499 } 500 } 501 502 if (type != mem->type) 503 goto out_err; 504 505 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 506 507 switch (mask_type) { 508 case AGP_DCACHE_MEMORY: 509 if (!mem->is_flushed) 510 global_cache_flush(); 511 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 512 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 513 intel_private.registers+I810_PTE_BASE+(i*4)); 514 } 515 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 516 break; 517 case AGP_PHYS_MEMORY: 518 case AGP_NORMAL_MEMORY: 519 if (!mem->is_flushed) 520 global_cache_flush(); 521 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 522 writel(agp_bridge->driver->mask_memory(agp_bridge, 523 page_to_phys(mem->pages[i]), mask_type), 524 intel_private.registers+I810_PTE_BASE+(j*4)); 525 } 526 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 527 break; 528 default: 529 goto out_err; 530 } 531 532 agp_bridge->driver->tlb_flush(mem); 533out: 534 ret = 0; 535out_err: 536 mem->is_flushed = true; 537 return ret; 538} 539 540static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 541 int type) 542{ 543 int i; 544 545 if (mem->page_count == 0) 546 return 0; 547 548 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 549 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 550 } 551 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 552 553 agp_bridge->driver->tlb_flush(mem); 554 return 0; 555} 556 557/* 558 * The i810/i830 requires a physical address to program its mouse 559 * pointer into hardware. 560 * However the Xserver still writes to it through the agp aperture. 561 */ 562static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 563{ 564 struct agp_memory *new; 565 struct page *page; 566 567 switch (pg_count) { 568 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 569 break; 570 case 4: 571 /* kludge to get 4 physical pages for ARGB cursor */ 572 page = i8xx_alloc_pages(); 573 break; 574 default: 575 return NULL; 576 } 577 578 if (page == NULL) 579 return NULL; 580 581 new = agp_create_memory(pg_count); 582 if (new == NULL) 583 return NULL; 584 585 new->pages[0] = page; 586 if (pg_count == 4) { 587 /* kludge to get 4 physical pages for ARGB cursor */ 588 new->pages[1] = new->pages[0] + 1; 589 new->pages[2] = new->pages[1] + 1; 590 new->pages[3] = new->pages[2] + 1; 591 } 592 new->page_count = pg_count; 593 new->num_scratch_pages = pg_count; 594 new->type = AGP_PHYS_MEMORY; 595 new->physical = page_to_phys(new->pages[0]); 596 return new; 597} 598 599static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 600{ 601 struct agp_memory *new; 602 603 if (type == AGP_DCACHE_MEMORY) { 604 if (pg_count != intel_private.num_dcache_entries) 605 return NULL; 606 607 new = agp_create_memory(1); 608 if (new == NULL) 609 return NULL; 610 611 new->type = AGP_DCACHE_MEMORY; 612 new->page_count = pg_count; 613 new->num_scratch_pages = 0; 614 agp_free_page_array(new); 615 return new; 616 } 617 if (type == AGP_PHYS_MEMORY) 618 return alloc_agpphysmem_i8xx(pg_count, type); 619 return NULL; 620} 621 622static void intel_i810_free_by_type(struct agp_memory *curr) 623{ 624 agp_free_key(curr->key); 625 if (curr->type == AGP_PHYS_MEMORY) { 626 if (curr->page_count == 4) 627 i8xx_destroy_pages(curr->pages[0]); 628 else { 629 agp_bridge->driver->agp_destroy_page(curr->pages[0], 630 AGP_PAGE_DESTROY_UNMAP); 631 agp_bridge->driver->agp_destroy_page(curr->pages[0], 632 AGP_PAGE_DESTROY_FREE); 633 } 634 agp_free_page_array(curr); 635 } 636 kfree(curr); 637} 638 639static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 640 dma_addr_t addr, int type) 641{ 642 /* Type checking must be done elsewhere */ 643 return addr | bridge->driver->masks[type].mask; 644} 645 646static struct aper_size_info_fixed intel_i830_sizes[] = 647{ 648 {128, 32768, 5}, 649 /* The 64M mode still requires a 128k gatt */ 650 {64, 16384, 5}, 651 {256, 65536, 6}, 652 {512, 131072, 7}, 653}; 654 655static void intel_i830_init_gtt_entries(void) 656{ 657 u16 gmch_ctrl; 658 int gtt_entries = 0; 659 u8 rdct; 660 int local = 0; 661 static const int ddt[4] = { 0, 16, 32, 64 }; 662 int size; /* reserved space (in kb) at the top of stolen memory */ 663 664 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 665 666 if (IS_I965) { 667 u32 pgetbl_ctl; 668 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 669 670 /* The 965 has a field telling us the size of the GTT, 671 * which may be larger than what is necessary to map the 672 * aperture. 673 */ 674 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 675 case I965_PGETBL_SIZE_128KB: 676 size = 128; 677 break; 678 case I965_PGETBL_SIZE_256KB: 679 size = 256; 680 break; 681 case I965_PGETBL_SIZE_512KB: 682 size = 512; 683 break; 684 case I965_PGETBL_SIZE_1MB: 685 size = 1024; 686 break; 687 case I965_PGETBL_SIZE_2MB: 688 size = 2048; 689 break; 690 case I965_PGETBL_SIZE_1_5MB: 691 size = 1024 + 512; 692 break; 693 default: 694 dev_info(&intel_private.pcidev->dev, 695 "unknown page table size, assuming 512KB\n"); 696 size = 512; 697 } 698 size += 4; /* add in BIOS popup space */ 699 } else if (IS_G33 && !IS_PINEVIEW) { 700 /* G33's GTT size defined in gmch_ctrl */ 701 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 702 case G33_PGETBL_SIZE_1M: 703 size = 1024; 704 break; 705 case G33_PGETBL_SIZE_2M: 706 size = 2048; 707 break; 708 default: 709 dev_info(&agp_bridge->dev->dev, 710 "unknown page table size 0x%x, assuming 512KB\n", 711 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 712 size = 512; 713 } 714 size += 4; 715 } else if (IS_G4X || IS_PINEVIEW) { 716 /* On 4 series hardware, GTT stolen is separate from graphics 717 * stolen, ignore it in stolen gtt entries counting. However, 718 * 4KB of the stolen memory doesn't get mapped to the GTT. 719 */ 720 size = 4; 721 } else { 722 /* On previous hardware, the GTT size was just what was 723 * required to map the aperture. 724 */ 725 size = agp_bridge->driver->fetch_size() + 4; 726 } 727 728 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 729 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 730 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 731 case I830_GMCH_GMS_STOLEN_512: 732 gtt_entries = KB(512) - KB(size); 733 break; 734 case I830_GMCH_GMS_STOLEN_1024: 735 gtt_entries = MB(1) - KB(size); 736 break; 737 case I830_GMCH_GMS_STOLEN_8192: 738 gtt_entries = MB(8) - KB(size); 739 break; 740 case I830_GMCH_GMS_LOCAL: 741 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 742 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 743 MB(ddt[I830_RDRAM_DDT(rdct)]); 744 local = 1; 745 break; 746 default: 747 gtt_entries = 0; 748 break; 749 } 750 } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || 751 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) { 752 /* 753 * SandyBridge has new memory control reg at 0x50.w 754 */ 755 u16 snb_gmch_ctl; 756 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 757 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 758 case SNB_GMCH_GMS_STOLEN_32M: 759 gtt_entries = MB(32) - KB(size); 760 break; 761 case SNB_GMCH_GMS_STOLEN_64M: 762 gtt_entries = MB(64) - KB(size); 763 break; 764 case SNB_GMCH_GMS_STOLEN_96M: 765 gtt_entries = MB(96) - KB(size); 766 break; 767 case SNB_GMCH_GMS_STOLEN_128M: 768 gtt_entries = MB(128) - KB(size); 769 break; 770 case SNB_GMCH_GMS_STOLEN_160M: 771 gtt_entries = MB(160) - KB(size); 772 break; 773 case SNB_GMCH_GMS_STOLEN_192M: 774 gtt_entries = MB(192) - KB(size); 775 break; 776 case SNB_GMCH_GMS_STOLEN_224M: 777 gtt_entries = MB(224) - KB(size); 778 break; 779 case SNB_GMCH_GMS_STOLEN_256M: 780 gtt_entries = MB(256) - KB(size); 781 break; 782 case SNB_GMCH_GMS_STOLEN_288M: 783 gtt_entries = MB(288) - KB(size); 784 break; 785 case SNB_GMCH_GMS_STOLEN_320M: 786 gtt_entries = MB(320) - KB(size); 787 break; 788 case SNB_GMCH_GMS_STOLEN_352M: 789 gtt_entries = MB(352) - KB(size); 790 break; 791 case SNB_GMCH_GMS_STOLEN_384M: 792 gtt_entries = MB(384) - KB(size); 793 break; 794 case SNB_GMCH_GMS_STOLEN_416M: 795 gtt_entries = MB(416) - KB(size); 796 break; 797 case SNB_GMCH_GMS_STOLEN_448M: 798 gtt_entries = MB(448) - KB(size); 799 break; 800 case SNB_GMCH_GMS_STOLEN_480M: 801 gtt_entries = MB(480) - KB(size); 802 break; 803 case SNB_GMCH_GMS_STOLEN_512M: 804 gtt_entries = MB(512) - KB(size); 805 break; 806 } 807 } else { 808 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 809 case I855_GMCH_GMS_STOLEN_1M: 810 gtt_entries = MB(1) - KB(size); 811 break; 812 case I855_GMCH_GMS_STOLEN_4M: 813 gtt_entries = MB(4) - KB(size); 814 break; 815 case I855_GMCH_GMS_STOLEN_8M: 816 gtt_entries = MB(8) - KB(size); 817 break; 818 case I855_GMCH_GMS_STOLEN_16M: 819 gtt_entries = MB(16) - KB(size); 820 break; 821 case I855_GMCH_GMS_STOLEN_32M: 822 gtt_entries = MB(32) - KB(size); 823 break; 824 case I915_GMCH_GMS_STOLEN_48M: 825 /* Check it's really I915G */ 826 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 827 gtt_entries = MB(48) - KB(size); 828 else 829 gtt_entries = 0; 830 break; 831 case I915_GMCH_GMS_STOLEN_64M: 832 /* Check it's really I915G */ 833 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 834 gtt_entries = MB(64) - KB(size); 835 else 836 gtt_entries = 0; 837 break; 838 case G33_GMCH_GMS_STOLEN_128M: 839 if (IS_G33 || IS_I965 || IS_G4X) 840 gtt_entries = MB(128) - KB(size); 841 else 842 gtt_entries = 0; 843 break; 844 case G33_GMCH_GMS_STOLEN_256M: 845 if (IS_G33 || IS_I965 || IS_G4X) 846 gtt_entries = MB(256) - KB(size); 847 else 848 gtt_entries = 0; 849 break; 850 case INTEL_GMCH_GMS_STOLEN_96M: 851 if (IS_I965 || IS_G4X) 852 gtt_entries = MB(96) - KB(size); 853 else 854 gtt_entries = 0; 855 break; 856 case INTEL_GMCH_GMS_STOLEN_160M: 857 if (IS_I965 || IS_G4X) 858 gtt_entries = MB(160) - KB(size); 859 else 860 gtt_entries = 0; 861 break; 862 case INTEL_GMCH_GMS_STOLEN_224M: 863 if (IS_I965 || IS_G4X) 864 gtt_entries = MB(224) - KB(size); 865 else 866 gtt_entries = 0; 867 break; 868 case INTEL_GMCH_GMS_STOLEN_352M: 869 if (IS_I965 || IS_G4X) 870 gtt_entries = MB(352) - KB(size); 871 else 872 gtt_entries = 0; 873 break; 874 default: 875 gtt_entries = 0; 876 break; 877 } 878 } 879 if (gtt_entries > 0) { 880 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 881 gtt_entries / KB(1), local ? "local" : "stolen"); 882 gtt_entries /= KB(4); 883 } else { 884 dev_info(&agp_bridge->dev->dev, 885 "no pre-allocated video memory detected\n"); 886 gtt_entries = 0; 887 } 888 889 intel_private.gtt_entries = gtt_entries; 890} 891 892static void intel_i830_fini_flush(void) 893{ 894 kunmap(intel_private.i8xx_page); 895 intel_private.i8xx_flush_page = NULL; 896 unmap_page_from_agp(intel_private.i8xx_page); 897 898 __free_page(intel_private.i8xx_page); 899 intel_private.i8xx_page = NULL; 900} 901 902static void intel_i830_setup_flush(void) 903{ 904 /* return if we've already set the flush mechanism up */ 905 if (intel_private.i8xx_page) 906 return; 907 908 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 909 if (!intel_private.i8xx_page) 910 return; 911 912 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 913 if (!intel_private.i8xx_flush_page) 914 intel_i830_fini_flush(); 915} 916 917/* The chipset_flush interface needs to get data that has already been 918 * flushed out of the CPU all the way out to main memory, because the GPU 919 * doesn't snoop those buffers. 920 * 921 * The 8xx series doesn't have the same lovely interface for flushing the 922 * chipset write buffers that the later chips do. According to the 865 923 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 924 * that buffer out, we just fill 1KB and clflush it out, on the assumption 925 * that it'll push whatever was in there out. It appears to work. 926 */ 927static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 928{ 929 unsigned int *pg = intel_private.i8xx_flush_page; 930 931 memset(pg, 0, 1024); 932 933 if (cpu_has_clflush) 934 clflush_cache_range(pg, 1024); 935 else if (wbinvd_on_all_cpus() != 0) 936 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 937} 938 939/* The intel i830 automatically initializes the agp aperture during POST. 940 * Use the memory already set aside for in the GTT. 941 */ 942static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 943{ 944 int page_order; 945 struct aper_size_info_fixed *size; 946 int num_entries; 947 u32 temp; 948 949 size = agp_bridge->current_size; 950 page_order = size->page_order; 951 num_entries = size->num_entries; 952 agp_bridge->gatt_table_real = NULL; 953 954 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 955 temp &= 0xfff80000; 956 957 intel_private.registers = ioremap(temp, 128 * 4096); 958 if (!intel_private.registers) 959 return -ENOMEM; 960 961 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 962 global_cache_flush(); /* FIXME: ?? */ 963 964 /* we have to call this as early as possible after the MMIO base address is known */ 965 intel_i830_init_gtt_entries(); 966 967 agp_bridge->gatt_table = NULL; 968 969 agp_bridge->gatt_bus_addr = temp; 970 971 return 0; 972} 973 974/* Return the gatt table to a sane state. Use the top of stolen 975 * memory for the GTT. 976 */ 977static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 978{ 979 return 0; 980} 981 982static int intel_i830_fetch_size(void) 983{ 984 u16 gmch_ctrl; 985 struct aper_size_info_fixed *values; 986 987 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 988 989 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 990 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 991 /* 855GM/852GM/865G has 128MB aperture size */ 992 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 993 agp_bridge->aperture_size_idx = 0; 994 return values[0].size; 995 } 996 997 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 998 999 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 1000 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 1001 agp_bridge->aperture_size_idx = 0; 1002 return values[0].size; 1003 } else { 1004 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 1005 agp_bridge->aperture_size_idx = 1; 1006 return values[1].size; 1007 } 1008 1009 return 0; 1010} 1011 1012static int intel_i830_configure(void) 1013{ 1014 struct aper_size_info_fixed *current_size; 1015 u32 temp; 1016 u16 gmch_ctrl; 1017 int i; 1018 1019 current_size = A_SIZE_FIX(agp_bridge->current_size); 1020 1021 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 1022 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1023 1024 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1025 gmch_ctrl |= I830_GMCH_ENABLED; 1026 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1027 1028 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1029 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1030 1031 if (agp_bridge->driver->needs_scratch_page) { 1032 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 1033 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 1034 } 1035 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 1036 } 1037 1038 global_cache_flush(); 1039 1040 intel_i830_setup_flush(); 1041 return 0; 1042} 1043 1044static void intel_i830_cleanup(void) 1045{ 1046 iounmap(intel_private.registers); 1047} 1048 1049static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 1050 int type) 1051{ 1052 int i, j, num_entries; 1053 void *temp; 1054 int ret = -EINVAL; 1055 int mask_type; 1056 1057 if (mem->page_count == 0) 1058 goto out; 1059 1060 temp = agp_bridge->current_size; 1061 num_entries = A_SIZE_FIX(temp)->num_entries; 1062 1063 if (pg_start < intel_private.gtt_entries) { 1064 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1065 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1066 pg_start, intel_private.gtt_entries); 1067 1068 dev_info(&intel_private.pcidev->dev, 1069 "trying to insert into local/stolen memory\n"); 1070 goto out_err; 1071 } 1072 1073 if ((pg_start + mem->page_count) > num_entries) 1074 goto out_err; 1075 1076 /* The i830 can't check the GTT for entries since its read only, 1077 * depend on the caller to make the correct offset decisions. 1078 */ 1079 1080 if (type != mem->type) 1081 goto out_err; 1082 1083 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1084 1085 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1086 mask_type != INTEL_AGP_CACHED_MEMORY) 1087 goto out_err; 1088 1089 if (!mem->is_flushed) 1090 global_cache_flush(); 1091 1092 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1093 writel(agp_bridge->driver->mask_memory(agp_bridge, 1094 page_to_phys(mem->pages[i]), mask_type), 1095 intel_private.registers+I810_PTE_BASE+(j*4)); 1096 } 1097 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 1098 agp_bridge->driver->tlb_flush(mem); 1099 1100out: 1101 ret = 0; 1102out_err: 1103 mem->is_flushed = true; 1104 return ret; 1105} 1106 1107static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1108 int type) 1109{ 1110 int i; 1111 1112 if (mem->page_count == 0) 1113 return 0; 1114 1115 if (pg_start < intel_private.gtt_entries) { 1116 dev_info(&intel_private.pcidev->dev, 1117 "trying to disable local/stolen memory\n"); 1118 return -EINVAL; 1119 } 1120 1121 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1122 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 1123 } 1124 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 1125 1126 agp_bridge->driver->tlb_flush(mem); 1127 return 0; 1128} 1129 1130static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 1131{ 1132 if (type == AGP_PHYS_MEMORY) 1133 return alloc_agpphysmem_i8xx(pg_count, type); 1134 /* always return NULL for other allocation types for now */ 1135 return NULL; 1136} 1137 1138static int intel_alloc_chipset_flush_resource(void) 1139{ 1140 int ret; 1141 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1142 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1143 pcibios_align_resource, agp_bridge->dev); 1144 1145 return ret; 1146} 1147 1148static void intel_i915_setup_chipset_flush(void) 1149{ 1150 int ret; 1151 u32 temp; 1152 1153 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 1154 if (!(temp & 0x1)) { 1155 intel_alloc_chipset_flush_resource(); 1156 intel_private.resource_valid = 1; 1157 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1158 } else { 1159 temp &= ~1; 1160 1161 intel_private.resource_valid = 1; 1162 intel_private.ifp_resource.start = temp; 1163 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1164 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1165 /* some BIOSes reserve this area in a pnp some don't */ 1166 if (ret) 1167 intel_private.resource_valid = 0; 1168 } 1169} 1170 1171static void intel_i965_g33_setup_chipset_flush(void) 1172{ 1173 u32 temp_hi, temp_lo; 1174 int ret; 1175 1176 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1177 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1178 1179 if (!(temp_lo & 0x1)) { 1180 1181 intel_alloc_chipset_flush_resource(); 1182 1183 intel_private.resource_valid = 1; 1184 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1185 upper_32_bits(intel_private.ifp_resource.start)); 1186 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1187 } else { 1188 u64 l64; 1189 1190 temp_lo &= ~0x1; 1191 l64 = ((u64)temp_hi << 32) | temp_lo; 1192 1193 intel_private.resource_valid = 1; 1194 intel_private.ifp_resource.start = l64; 1195 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1196 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1197 /* some BIOSes reserve this area in a pnp some don't */ 1198 if (ret) 1199 intel_private.resource_valid = 0; 1200 } 1201} 1202 1203static void intel_i9xx_setup_flush(void) 1204{ 1205 /* return if already configured */ 1206 if (intel_private.ifp_resource.start) 1207 return; 1208 1209 if (IS_SNB) 1210 return; 1211 1212 /* setup a resource for this object */ 1213 intel_private.ifp_resource.name = "Intel Flush Page"; 1214 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1215 1216 /* Setup chipset flush for 915 */ 1217 if (IS_I965 || IS_G33 || IS_G4X) { 1218 intel_i965_g33_setup_chipset_flush(); 1219 } else { 1220 intel_i915_setup_chipset_flush(); 1221 } 1222 1223 if (intel_private.ifp_resource.start) { 1224 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1225 if (!intel_private.i9xx_flush_page) 1226 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 1227 } 1228} 1229 1230static int intel_i915_configure(void) 1231{ 1232 struct aper_size_info_fixed *current_size; 1233 u32 temp; 1234 u16 gmch_ctrl; 1235 int i; 1236 1237 current_size = A_SIZE_FIX(agp_bridge->current_size); 1238 1239 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1240 1241 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1242 1243 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1244 gmch_ctrl |= I830_GMCH_ENABLED; 1245 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 1246 1247 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 1248 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 1249 1250 if (agp_bridge->driver->needs_scratch_page) { 1251 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { 1252 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1253 } 1254 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1255 } 1256 1257 global_cache_flush(); 1258 1259 intel_i9xx_setup_flush(); 1260 1261 return 0; 1262} 1263 1264static void intel_i915_cleanup(void) 1265{ 1266 if (intel_private.i9xx_flush_page) 1267 iounmap(intel_private.i9xx_flush_page); 1268 if (intel_private.resource_valid) 1269 release_resource(&intel_private.ifp_resource); 1270 intel_private.ifp_resource.start = 0; 1271 intel_private.resource_valid = 0; 1272 iounmap(intel_private.gtt); 1273 iounmap(intel_private.registers); 1274} 1275 1276static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1277{ 1278 if (intel_private.i9xx_flush_page) 1279 writel(1, intel_private.i9xx_flush_page); 1280} 1281 1282static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1283 int type) 1284{ 1285 int num_entries; 1286 void *temp; 1287 int ret = -EINVAL; 1288 int mask_type; 1289 1290 if (mem->page_count == 0) 1291 goto out; 1292 1293 temp = agp_bridge->current_size; 1294 num_entries = A_SIZE_FIX(temp)->num_entries; 1295 1296 if (pg_start < intel_private.gtt_entries) { 1297 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1298 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1299 pg_start, intel_private.gtt_entries); 1300 1301 dev_info(&intel_private.pcidev->dev, 1302 "trying to insert into local/stolen memory\n"); 1303 goto out_err; 1304 } 1305 1306 if ((pg_start + mem->page_count) > num_entries) 1307 goto out_err; 1308 1309 /* The i915 can't check the GTT for entries since it's read only; 1310 * depend on the caller to make the correct offset decisions. 1311 */ 1312 1313 if (type != mem->type) 1314 goto out_err; 1315 1316 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1317 1318 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1319 mask_type != INTEL_AGP_CACHED_MEMORY) 1320 goto out_err; 1321 1322 if (!mem->is_flushed) 1323 global_cache_flush(); 1324 1325 intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1326 agp_bridge->driver->tlb_flush(mem); 1327 1328 out: 1329 ret = 0; 1330 out_err: 1331 mem->is_flushed = true; 1332 return ret; 1333} 1334 1335static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1336 int type) 1337{ 1338 int i; 1339 1340 if (mem->page_count == 0) 1341 return 0; 1342 1343 if (pg_start < intel_private.gtt_entries) { 1344 dev_info(&intel_private.pcidev->dev, 1345 "trying to disable local/stolen memory\n"); 1346 return -EINVAL; 1347 } 1348 1349 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1350 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1351 1352 readl(intel_private.gtt+i-1); 1353 1354 agp_bridge->driver->tlb_flush(mem); 1355 return 0; 1356} 1357 1358/* Return the aperture size by just checking the resource length. The effect 1359 * described in the spec of the MSAC registers is just changing of the 1360 * resource size. 1361 */ 1362static int intel_i9xx_fetch_size(void) 1363{ 1364 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1365 int aper_size; /* size in megabytes */ 1366 int i; 1367 1368 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1369 1370 for (i = 0; i < num_sizes; i++) { 1371 if (aper_size == intel_i830_sizes[i].size) { 1372 agp_bridge->current_size = intel_i830_sizes + i; 1373 agp_bridge->previous_size = agp_bridge->current_size; 1374 return aper_size; 1375 } 1376 } 1377 1378 return 0; 1379} 1380 1381/* The intel i915 automatically initializes the agp aperture during POST. 1382 * Use the memory already set aside for in the GTT. 1383 */ 1384static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1385{ 1386 int page_order; 1387 struct aper_size_info_fixed *size; 1388 int num_entries; 1389 u32 temp, temp2; 1390 int gtt_map_size = 256 * 1024; 1391 1392 size = agp_bridge->current_size; 1393 page_order = size->page_order; 1394 num_entries = size->num_entries; 1395 agp_bridge->gatt_table_real = NULL; 1396 1397 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1398 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1399 1400 if (IS_G33) 1401 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1402 intel_private.gtt = ioremap(temp2, gtt_map_size); 1403 if (!intel_private.gtt) 1404 return -ENOMEM; 1405 1406 intel_private.gtt_total_size = gtt_map_size / 4; 1407 1408 temp &= 0xfff80000; 1409 1410 intel_private.registers = ioremap(temp, 128 * 4096); 1411 if (!intel_private.registers) { 1412 iounmap(intel_private.gtt); 1413 return -ENOMEM; 1414 } 1415 1416 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1417 global_cache_flush(); /* FIXME: ? */ 1418 1419 /* we have to call this as early as possible after the MMIO base address is known */ 1420 intel_i830_init_gtt_entries(); 1421 1422 agp_bridge->gatt_table = NULL; 1423 1424 agp_bridge->gatt_bus_addr = temp; 1425 1426 return 0; 1427} 1428 1429/* 1430 * The i965 supports 36-bit physical addresses, but to keep 1431 * the format of the GTT the same, the bits that don't fit 1432 * in a 32-bit word are shifted down to bits 4..7. 1433 * 1434 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1435 * is always zero on 32-bit architectures, so no need to make 1436 * this conditional. 1437 */ 1438static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1439 dma_addr_t addr, int type) 1440{ 1441 /* Shift high bits down */ 1442 addr |= (addr >> 28) & 0xf0; 1443 1444 /* Type checking must be done elsewhere */ 1445 return addr | bridge->driver->masks[type].mask; 1446} 1447 1448static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1449{ 1450 u16 snb_gmch_ctl; 1451 1452 switch (agp_bridge->dev->device) { 1453 case PCI_DEVICE_ID_INTEL_GM45_HB: 1454 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: 1455 case PCI_DEVICE_ID_INTEL_Q45_HB: 1456 case PCI_DEVICE_ID_INTEL_G45_HB: 1457 case PCI_DEVICE_ID_INTEL_G41_HB: 1458 case PCI_DEVICE_ID_INTEL_B43_HB: 1459 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB: 1460 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: 1461 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: 1462 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: 1463 *gtt_offset = *gtt_size = MB(2); 1464 break; 1465 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: 1466 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: 1467 *gtt_offset = MB(2); 1468 1469 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 1470 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 1471 default: 1472 case SNB_GTT_SIZE_0M: 1473 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 1474 *gtt_size = MB(0); 1475 break; 1476 case SNB_GTT_SIZE_1M: 1477 *gtt_size = MB(1); 1478 break; 1479 case SNB_GTT_SIZE_2M: 1480 *gtt_size = MB(2); 1481 break; 1482 } 1483 break; 1484 default: 1485 *gtt_offset = *gtt_size = KB(512); 1486 } 1487} 1488 1489/* The intel i965 automatically initializes the agp aperture during POST. 1490 * Use the memory already set aside for in the GTT. 1491 */ 1492static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1493{ 1494 int page_order; 1495 struct aper_size_info_fixed *size; 1496 int num_entries; 1497 u32 temp; 1498 int gtt_offset, gtt_size; 1499 1500 size = agp_bridge->current_size; 1501 page_order = size->page_order; 1502 num_entries = size->num_entries; 1503 agp_bridge->gatt_table_real = NULL; 1504 1505 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1506 1507 temp &= 0xfff00000; 1508 1509 intel_i965_get_gtt_range(>t_offset, >t_size); 1510 1511 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1512 1513 if (!intel_private.gtt) 1514 return -ENOMEM; 1515 1516 intel_private.gtt_total_size = gtt_size / 4; 1517 1518 intel_private.registers = ioremap(temp, 128 * 4096); 1519 if (!intel_private.registers) { 1520 iounmap(intel_private.gtt); 1521 return -ENOMEM; 1522 } 1523 1524 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1525 global_cache_flush(); /* FIXME: ? */ 1526 1527 /* we have to call this as early as possible after the MMIO base address is known */ 1528 intel_i830_init_gtt_entries(); 1529 1530 agp_bridge->gatt_table = NULL; 1531 1532 agp_bridge->gatt_bus_addr = temp; 1533 1534 return 0; 1535} 1536 1537 1538static int intel_fetch_size(void) 1539{ 1540 int i; 1541 u16 temp; 1542 struct aper_size_info_16 *values; 1543 1544 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1545 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1546 1547 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1548 if (temp == values[i].size_value) { 1549 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1550 agp_bridge->aperture_size_idx = i; 1551 return values[i].size; 1552 } 1553 } 1554 1555 return 0; 1556} 1557 1558static int __intel_8xx_fetch_size(u8 temp) 1559{ 1560 int i; 1561 struct aper_size_info_8 *values; 1562 1563 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1564 1565 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1566 if (temp == values[i].size_value) { 1567 agp_bridge->previous_size = 1568 agp_bridge->current_size = (void *) (values + i); 1569 agp_bridge->aperture_size_idx = i; 1570 return values[i].size; 1571 } 1572 } 1573 return 0; 1574} 1575 1576static int intel_8xx_fetch_size(void) 1577{ 1578 u8 temp; 1579 1580 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1581 return __intel_8xx_fetch_size(temp); 1582} 1583 1584static int intel_815_fetch_size(void) 1585{ 1586 u8 temp; 1587 1588 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1589 * one non-reserved bit, so mask the others out ... */ 1590 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1591 temp &= (1 << 3); 1592 1593 return __intel_8xx_fetch_size(temp); 1594} 1595 1596static void intel_tlbflush(struct agp_memory *mem) 1597{ 1598 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1599 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1600} 1601 1602 1603static void intel_8xx_tlbflush(struct agp_memory *mem) 1604{ 1605 u32 temp; 1606 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1607 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1608 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1609 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1610} 1611 1612 1613static void intel_cleanup(void) 1614{ 1615 u16 temp; 1616 struct aper_size_info_16 *previous_size; 1617 1618 previous_size = A_SIZE_16(agp_bridge->previous_size); 1619 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1620 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1621 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1622} 1623 1624 1625static void intel_8xx_cleanup(void) 1626{ 1627 u16 temp; 1628 struct aper_size_info_8 *previous_size; 1629 1630 previous_size = A_SIZE_8(agp_bridge->previous_size); 1631 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1632 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1633 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1634} 1635 1636 1637static int intel_configure(void) 1638{ 1639 u32 temp; 1640 u16 temp2; 1641 struct aper_size_info_16 *current_size; 1642 1643 current_size = A_SIZE_16(agp_bridge->current_size); 1644 1645 /* aperture size */ 1646 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1647 1648 /* address to map to */ 1649 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1650 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1651 1652 /* attbase - aperture base */ 1653 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1654 1655 /* agpctrl */ 1656 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1657 1658 /* paccfg/nbxcfg */ 1659 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1660 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1661 (temp2 & ~(1 << 10)) | (1 << 9)); 1662 /* clear any possible error conditions */ 1663 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1664 return 0; 1665} 1666 1667static int intel_815_configure(void) 1668{ 1669 u32 temp, addr; 1670 u8 temp2; 1671 struct aper_size_info_8 *current_size; 1672 1673 /* attbase - aperture base */ 1674 /* the Intel 815 chipset spec. says that bits 29-31 in the 1675 * ATTBASE register are reserved -> try not to write them */ 1676 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1677 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1678 return -EINVAL; 1679 } 1680 1681 current_size = A_SIZE_8(agp_bridge->current_size); 1682 1683 /* aperture size */ 1684 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1685 current_size->size_value); 1686 1687 /* address to map to */ 1688 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1689 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1690 1691 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1692 addr &= INTEL_815_ATTBASE_MASK; 1693 addr |= agp_bridge->gatt_bus_addr; 1694 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1695 1696 /* agpctrl */ 1697 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1698 1699 /* apcont */ 1700 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1701 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1702 1703 /* clear any possible error conditions */ 1704 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1705 return 0; 1706} 1707 1708static void intel_820_tlbflush(struct agp_memory *mem) 1709{ 1710 return; 1711} 1712 1713static void intel_820_cleanup(void) 1714{ 1715 u8 temp; 1716 struct aper_size_info_8 *previous_size; 1717 1718 previous_size = A_SIZE_8(agp_bridge->previous_size); 1719 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1720 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1721 temp & ~(1 << 1)); 1722 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1723 previous_size->size_value); 1724} 1725 1726 1727static int intel_820_configure(void) 1728{ 1729 u32 temp; 1730 u8 temp2; 1731 struct aper_size_info_8 *current_size; 1732 1733 current_size = A_SIZE_8(agp_bridge->current_size); 1734 1735 /* aperture size */ 1736 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1737 1738 /* address to map to */ 1739 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1740 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1741 1742 /* attbase - aperture base */ 1743 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1744 1745 /* agpctrl */ 1746 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1747 1748 /* global enable aperture access */ 1749 /* This flag is not accessed through MCHCFG register as in */ 1750 /* i850 chipset. */ 1751 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1752 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1753 /* clear any possible AGP-related error conditions */ 1754 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1755 return 0; 1756} 1757 1758static int intel_840_configure(void) 1759{ 1760 u32 temp; 1761 u16 temp2; 1762 struct aper_size_info_8 *current_size; 1763 1764 current_size = A_SIZE_8(agp_bridge->current_size); 1765 1766 /* aperture size */ 1767 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1768 1769 /* address to map to */ 1770 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1771 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1772 1773 /* attbase - aperture base */ 1774 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1775 1776 /* agpctrl */ 1777 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1778 1779 /* mcgcfg */ 1780 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1781 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1782 /* clear any possible error conditions */ 1783 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1784 return 0; 1785} 1786 1787static int intel_845_configure(void) 1788{ 1789 u32 temp; 1790 u8 temp2; 1791 struct aper_size_info_8 *current_size; 1792 1793 current_size = A_SIZE_8(agp_bridge->current_size); 1794 1795 /* aperture size */ 1796 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1797 1798 if (agp_bridge->apbase_config != 0) { 1799 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1800 agp_bridge->apbase_config); 1801 } else { 1802 /* address to map to */ 1803 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1804 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1805 agp_bridge->apbase_config = temp; 1806 } 1807 1808 /* attbase - aperture base */ 1809 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1810 1811 /* agpctrl */ 1812 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1813 1814 /* agpm */ 1815 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1816 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1817 /* clear any possible error conditions */ 1818 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1819 return 0; 1820} 1821 1822static int intel_850_configure(void) 1823{ 1824 u32 temp; 1825 u16 temp2; 1826 struct aper_size_info_8 *current_size; 1827 1828 current_size = A_SIZE_8(agp_bridge->current_size); 1829 1830 /* aperture size */ 1831 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1832 1833 /* address to map to */ 1834 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1835 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1836 1837 /* attbase - aperture base */ 1838 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1839 1840 /* agpctrl */ 1841 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1842 1843 /* mcgcfg */ 1844 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1845 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1846 /* clear any possible AGP-related error conditions */ 1847 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1848 return 0; 1849} 1850 1851static int intel_860_configure(void) 1852{ 1853 u32 temp; 1854 u16 temp2; 1855 struct aper_size_info_8 *current_size; 1856 1857 current_size = A_SIZE_8(agp_bridge->current_size); 1858 1859 /* aperture size */ 1860 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1861 1862 /* address to map to */ 1863 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1864 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1865 1866 /* attbase - aperture base */ 1867 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1868 1869 /* agpctrl */ 1870 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1871 1872 /* mcgcfg */ 1873 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1874 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1875 /* clear any possible AGP-related error conditions */ 1876 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1877 return 0; 1878} 1879 1880static int intel_830mp_configure(void) 1881{ 1882 u32 temp; 1883 u16 temp2; 1884 struct aper_size_info_8 *current_size; 1885 1886 current_size = A_SIZE_8(agp_bridge->current_size); 1887 1888 /* aperture size */ 1889 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1890 1891 /* address to map to */ 1892 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1893 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1894 1895 /* attbase - aperture base */ 1896 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1897 1898 /* agpctrl */ 1899 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1900 1901 /* gmch */ 1902 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1903 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1904 /* clear any possible AGP-related error conditions */ 1905 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1906 return 0; 1907} 1908 1909static int intel_7505_configure(void) 1910{ 1911 u32 temp; 1912 u16 temp2; 1913 struct aper_size_info_8 *current_size; 1914 1915 current_size = A_SIZE_8(agp_bridge->current_size); 1916 1917 /* aperture size */ 1918 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1919 1920 /* address to map to */ 1921 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1922 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1923 1924 /* attbase - aperture base */ 1925 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1926 1927 /* agpctrl */ 1928 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1929 1930 /* mchcfg */ 1931 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1932 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1933 1934 return 0; 1935} 1936 1937/* Setup function */ 1938static const struct gatt_mask intel_generic_masks[] = 1939{ 1940 {.mask = 0x00000017, .type = 0} 1941}; 1942 1943static const struct aper_size_info_8 intel_815_sizes[2] = 1944{ 1945 {64, 16384, 4, 0}, 1946 {32, 8192, 3, 8}, 1947}; 1948 1949static const struct aper_size_info_8 intel_8xx_sizes[7] = 1950{ 1951 {256, 65536, 6, 0}, 1952 {128, 32768, 5, 32}, 1953 {64, 16384, 4, 48}, 1954 {32, 8192, 3, 56}, 1955 {16, 4096, 2, 60}, 1956 {8, 2048, 1, 62}, 1957 {4, 1024, 0, 63} 1958}; 1959 1960static const struct aper_size_info_16 intel_generic_sizes[7] = 1961{ 1962 {256, 65536, 6, 0}, 1963 {128, 32768, 5, 32}, 1964 {64, 16384, 4, 48}, 1965 {32, 8192, 3, 56}, 1966 {16, 4096, 2, 60}, 1967 {8, 2048, 1, 62}, 1968 {4, 1024, 0, 63} 1969}; 1970 1971static const struct aper_size_info_8 intel_830mp_sizes[4] = 1972{ 1973 {256, 65536, 6, 0}, 1974 {128, 32768, 5, 32}, 1975 {64, 16384, 4, 48}, 1976 {32, 8192, 3, 56} 1977}; 1978 1979static const struct agp_bridge_driver intel_generic_driver = { 1980 .owner = THIS_MODULE, 1981 .aperture_sizes = intel_generic_sizes, 1982 .size_type = U16_APER_SIZE, 1983 .num_aperture_sizes = 7, 1984 .configure = intel_configure, 1985 .fetch_size = intel_fetch_size, 1986 .cleanup = intel_cleanup, 1987 .tlb_flush = intel_tlbflush, 1988 .mask_memory = agp_generic_mask_memory, 1989 .masks = intel_generic_masks, 1990 .agp_enable = agp_generic_enable, 1991 .cache_flush = global_cache_flush, 1992 .create_gatt_table = agp_generic_create_gatt_table, 1993 .free_gatt_table = agp_generic_free_gatt_table, 1994 .insert_memory = agp_generic_insert_memory, 1995 .remove_memory = agp_generic_remove_memory, 1996 .alloc_by_type = agp_generic_alloc_by_type, 1997 .free_by_type = agp_generic_free_by_type, 1998 .agp_alloc_page = agp_generic_alloc_page, 1999 .agp_alloc_pages = agp_generic_alloc_pages, 2000 .agp_destroy_page = agp_generic_destroy_page, 2001 .agp_destroy_pages = agp_generic_destroy_pages, 2002 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2003}; 2004 2005static const struct agp_bridge_driver intel_810_driver = { 2006 .owner = THIS_MODULE, 2007 .aperture_sizes = intel_i810_sizes, 2008 .size_type = FIXED_APER_SIZE, 2009 .num_aperture_sizes = 2, 2010 .needs_scratch_page = true, 2011 .configure = intel_i810_configure, 2012 .fetch_size = intel_i810_fetch_size, 2013 .cleanup = intel_i810_cleanup, 2014 .tlb_flush = intel_i810_tlbflush, 2015 .mask_memory = intel_i810_mask_memory, 2016 .masks = intel_i810_masks, 2017 .agp_enable = intel_i810_agp_enable, 2018 .cache_flush = global_cache_flush, 2019 .create_gatt_table = agp_generic_create_gatt_table, 2020 .free_gatt_table = agp_generic_free_gatt_table, 2021 .insert_memory = intel_i810_insert_entries, 2022 .remove_memory = intel_i810_remove_entries, 2023 .alloc_by_type = intel_i810_alloc_by_type, 2024 .free_by_type = intel_i810_free_by_type, 2025 .agp_alloc_page = agp_generic_alloc_page, 2026 .agp_alloc_pages = agp_generic_alloc_pages, 2027 .agp_destroy_page = agp_generic_destroy_page, 2028 .agp_destroy_pages = agp_generic_destroy_pages, 2029 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2030}; 2031 2032static const struct agp_bridge_driver intel_815_driver = { 2033 .owner = THIS_MODULE, 2034 .aperture_sizes = intel_815_sizes, 2035 .size_type = U8_APER_SIZE, 2036 .num_aperture_sizes = 2, 2037 .configure = intel_815_configure, 2038 .fetch_size = intel_815_fetch_size, 2039 .cleanup = intel_8xx_cleanup, 2040 .tlb_flush = intel_8xx_tlbflush, 2041 .mask_memory = agp_generic_mask_memory, 2042 .masks = intel_generic_masks, 2043 .agp_enable = agp_generic_enable, 2044 .cache_flush = global_cache_flush, 2045 .create_gatt_table = agp_generic_create_gatt_table, 2046 .free_gatt_table = agp_generic_free_gatt_table, 2047 .insert_memory = agp_generic_insert_memory, 2048 .remove_memory = agp_generic_remove_memory, 2049 .alloc_by_type = agp_generic_alloc_by_type, 2050 .free_by_type = agp_generic_free_by_type, 2051 .agp_alloc_page = agp_generic_alloc_page, 2052 .agp_alloc_pages = agp_generic_alloc_pages, 2053 .agp_destroy_page = agp_generic_destroy_page, 2054 .agp_destroy_pages = agp_generic_destroy_pages, 2055 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2056}; 2057 2058static const struct agp_bridge_driver intel_830_driver = { 2059 .owner = THIS_MODULE, 2060 .aperture_sizes = intel_i830_sizes, 2061 .size_type = FIXED_APER_SIZE, 2062 .num_aperture_sizes = 4, 2063 .needs_scratch_page = true, 2064 .configure = intel_i830_configure, 2065 .fetch_size = intel_i830_fetch_size, 2066 .cleanup = intel_i830_cleanup, 2067 .tlb_flush = intel_i810_tlbflush, 2068 .mask_memory = intel_i810_mask_memory, 2069 .masks = intel_i810_masks, 2070 .agp_enable = intel_i810_agp_enable, 2071 .cache_flush = global_cache_flush, 2072 .create_gatt_table = intel_i830_create_gatt_table, 2073 .free_gatt_table = intel_i830_free_gatt_table, 2074 .insert_memory = intel_i830_insert_entries, 2075 .remove_memory = intel_i830_remove_entries, 2076 .alloc_by_type = intel_i830_alloc_by_type, 2077 .free_by_type = intel_i810_free_by_type, 2078 .agp_alloc_page = agp_generic_alloc_page, 2079 .agp_alloc_pages = agp_generic_alloc_pages, 2080 .agp_destroy_page = agp_generic_destroy_page, 2081 .agp_destroy_pages = agp_generic_destroy_pages, 2082 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2083 .chipset_flush = intel_i830_chipset_flush, 2084}; 2085 2086static const struct agp_bridge_driver intel_820_driver = { 2087 .owner = THIS_MODULE, 2088 .aperture_sizes = intel_8xx_sizes, 2089 .size_type = U8_APER_SIZE, 2090 .num_aperture_sizes = 7, 2091 .configure = intel_820_configure, 2092 .fetch_size = intel_8xx_fetch_size, 2093 .cleanup = intel_820_cleanup, 2094 .tlb_flush = intel_820_tlbflush, 2095 .mask_memory = agp_generic_mask_memory, 2096 .masks = intel_generic_masks, 2097 .agp_enable = agp_generic_enable, 2098 .cache_flush = global_cache_flush, 2099 .create_gatt_table = agp_generic_create_gatt_table, 2100 .free_gatt_table = agp_generic_free_gatt_table, 2101 .insert_memory = agp_generic_insert_memory, 2102 .remove_memory = agp_generic_remove_memory, 2103 .alloc_by_type = agp_generic_alloc_by_type, 2104 .free_by_type = agp_generic_free_by_type, 2105 .agp_alloc_page = agp_generic_alloc_page, 2106 .agp_alloc_pages = agp_generic_alloc_pages, 2107 .agp_destroy_page = agp_generic_destroy_page, 2108 .agp_destroy_pages = agp_generic_destroy_pages, 2109 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2110}; 2111 2112static const struct agp_bridge_driver intel_830mp_driver = { 2113 .owner = THIS_MODULE, 2114 .aperture_sizes = intel_830mp_sizes, 2115 .size_type = U8_APER_SIZE, 2116 .num_aperture_sizes = 4, 2117 .configure = intel_830mp_configure, 2118 .fetch_size = intel_8xx_fetch_size, 2119 .cleanup = intel_8xx_cleanup, 2120 .tlb_flush = intel_8xx_tlbflush, 2121 .mask_memory = agp_generic_mask_memory, 2122 .masks = intel_generic_masks, 2123 .agp_enable = agp_generic_enable, 2124 .cache_flush = global_cache_flush, 2125 .create_gatt_table = agp_generic_create_gatt_table, 2126 .free_gatt_table = agp_generic_free_gatt_table, 2127 .insert_memory = agp_generic_insert_memory, 2128 .remove_memory = agp_generic_remove_memory, 2129 .alloc_by_type = agp_generic_alloc_by_type, 2130 .free_by_type = agp_generic_free_by_type, 2131 .agp_alloc_page = agp_generic_alloc_page, 2132 .agp_alloc_pages = agp_generic_alloc_pages, 2133 .agp_destroy_page = agp_generic_destroy_page, 2134 .agp_destroy_pages = agp_generic_destroy_pages, 2135 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2136}; 2137 2138static const struct agp_bridge_driver intel_840_driver = { 2139 .owner = THIS_MODULE, 2140 .aperture_sizes = intel_8xx_sizes, 2141 .size_type = U8_APER_SIZE, 2142 .num_aperture_sizes = 7, 2143 .configure = intel_840_configure, 2144 .fetch_size = intel_8xx_fetch_size, 2145 .cleanup = intel_8xx_cleanup, 2146 .tlb_flush = intel_8xx_tlbflush, 2147 .mask_memory = agp_generic_mask_memory, 2148 .masks = intel_generic_masks, 2149 .agp_enable = agp_generic_enable, 2150 .cache_flush = global_cache_flush, 2151 .create_gatt_table = agp_generic_create_gatt_table, 2152 .free_gatt_table = agp_generic_free_gatt_table, 2153 .insert_memory = agp_generic_insert_memory, 2154 .remove_memory = agp_generic_remove_memory, 2155 .alloc_by_type = agp_generic_alloc_by_type, 2156 .free_by_type = agp_generic_free_by_type, 2157 .agp_alloc_page = agp_generic_alloc_page, 2158 .agp_alloc_pages = agp_generic_alloc_pages, 2159 .agp_destroy_page = agp_generic_destroy_page, 2160 .agp_destroy_pages = agp_generic_destroy_pages, 2161 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2162}; 2163 2164static const struct agp_bridge_driver intel_845_driver = { 2165 .owner = THIS_MODULE, 2166 .aperture_sizes = intel_8xx_sizes, 2167 .size_type = U8_APER_SIZE, 2168 .num_aperture_sizes = 7, 2169 .configure = intel_845_configure, 2170 .fetch_size = intel_8xx_fetch_size, 2171 .cleanup = intel_8xx_cleanup, 2172 .tlb_flush = intel_8xx_tlbflush, 2173 .mask_memory = agp_generic_mask_memory, 2174 .masks = intel_generic_masks, 2175 .agp_enable = agp_generic_enable, 2176 .cache_flush = global_cache_flush, 2177 .create_gatt_table = agp_generic_create_gatt_table, 2178 .free_gatt_table = agp_generic_free_gatt_table, 2179 .insert_memory = agp_generic_insert_memory, 2180 .remove_memory = agp_generic_remove_memory, 2181 .alloc_by_type = agp_generic_alloc_by_type, 2182 .free_by_type = agp_generic_free_by_type, 2183 .agp_alloc_page = agp_generic_alloc_page, 2184 .agp_alloc_pages = agp_generic_alloc_pages, 2185 .agp_destroy_page = agp_generic_destroy_page, 2186 .agp_destroy_pages = agp_generic_destroy_pages, 2187 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2188}; 2189 2190static const struct agp_bridge_driver intel_850_driver = { 2191 .owner = THIS_MODULE, 2192 .aperture_sizes = intel_8xx_sizes, 2193 .size_type = U8_APER_SIZE, 2194 .num_aperture_sizes = 7, 2195 .configure = intel_850_configure, 2196 .fetch_size = intel_8xx_fetch_size, 2197 .cleanup = intel_8xx_cleanup, 2198 .tlb_flush = intel_8xx_tlbflush, 2199 .mask_memory = agp_generic_mask_memory, 2200 .masks = intel_generic_masks, 2201 .agp_enable = agp_generic_enable, 2202 .cache_flush = global_cache_flush, 2203 .create_gatt_table = agp_generic_create_gatt_table, 2204 .free_gatt_table = agp_generic_free_gatt_table, 2205 .insert_memory = agp_generic_insert_memory, 2206 .remove_memory = agp_generic_remove_memory, 2207 .alloc_by_type = agp_generic_alloc_by_type, 2208 .free_by_type = agp_generic_free_by_type, 2209 .agp_alloc_page = agp_generic_alloc_page, 2210 .agp_alloc_pages = agp_generic_alloc_pages, 2211 .agp_destroy_page = agp_generic_destroy_page, 2212 .agp_destroy_pages = agp_generic_destroy_pages, 2213 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2214}; 2215 2216static const struct agp_bridge_driver intel_860_driver = { 2217 .owner = THIS_MODULE, 2218 .aperture_sizes = intel_8xx_sizes, 2219 .size_type = U8_APER_SIZE, 2220 .num_aperture_sizes = 7, 2221 .configure = intel_860_configure, 2222 .fetch_size = intel_8xx_fetch_size, 2223 .cleanup = intel_8xx_cleanup, 2224 .tlb_flush = intel_8xx_tlbflush, 2225 .mask_memory = agp_generic_mask_memory, 2226 .masks = intel_generic_masks, 2227 .agp_enable = agp_generic_enable, 2228 .cache_flush = global_cache_flush, 2229 .create_gatt_table = agp_generic_create_gatt_table, 2230 .free_gatt_table = agp_generic_free_gatt_table, 2231 .insert_memory = agp_generic_insert_memory, 2232 .remove_memory = agp_generic_remove_memory, 2233 .alloc_by_type = agp_generic_alloc_by_type, 2234 .free_by_type = agp_generic_free_by_type, 2235 .agp_alloc_page = agp_generic_alloc_page, 2236 .agp_alloc_pages = agp_generic_alloc_pages, 2237 .agp_destroy_page = agp_generic_destroy_page, 2238 .agp_destroy_pages = agp_generic_destroy_pages, 2239 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2240}; 2241 2242static const struct agp_bridge_driver intel_915_driver = { 2243 .owner = THIS_MODULE, 2244 .aperture_sizes = intel_i830_sizes, 2245 .size_type = FIXED_APER_SIZE, 2246 .num_aperture_sizes = 4, 2247 .needs_scratch_page = true, 2248 .configure = intel_i915_configure, 2249 .fetch_size = intel_i9xx_fetch_size, 2250 .cleanup = intel_i915_cleanup, 2251 .tlb_flush = intel_i810_tlbflush, 2252 .mask_memory = intel_i810_mask_memory, 2253 .masks = intel_i810_masks, 2254 .agp_enable = intel_i810_agp_enable, 2255 .cache_flush = global_cache_flush, 2256 .create_gatt_table = intel_i915_create_gatt_table, 2257 .free_gatt_table = intel_i830_free_gatt_table, 2258 .insert_memory = intel_i915_insert_entries, 2259 .remove_memory = intel_i915_remove_entries, 2260 .alloc_by_type = intel_i830_alloc_by_type, 2261 .free_by_type = intel_i810_free_by_type, 2262 .agp_alloc_page = agp_generic_alloc_page, 2263 .agp_alloc_pages = agp_generic_alloc_pages, 2264 .agp_destroy_page = agp_generic_destroy_page, 2265 .agp_destroy_pages = agp_generic_destroy_pages, 2266 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2267 .chipset_flush = intel_i915_chipset_flush, 2268#ifdef USE_PCI_DMA_API 2269 .agp_map_page = intel_agp_map_page, 2270 .agp_unmap_page = intel_agp_unmap_page, 2271 .agp_map_memory = intel_agp_map_memory, 2272 .agp_unmap_memory = intel_agp_unmap_memory, 2273#endif 2274}; 2275 2276static const struct agp_bridge_driver intel_i965_driver = { 2277 .owner = THIS_MODULE, 2278 .aperture_sizes = intel_i830_sizes, 2279 .size_type = FIXED_APER_SIZE, 2280 .num_aperture_sizes = 4, 2281 .needs_scratch_page = true, 2282 .configure = intel_i915_configure, 2283 .fetch_size = intel_i9xx_fetch_size, 2284 .cleanup = intel_i915_cleanup, 2285 .tlb_flush = intel_i810_tlbflush, 2286 .mask_memory = intel_i965_mask_memory, 2287 .masks = intel_i810_masks, 2288 .agp_enable = intel_i810_agp_enable, 2289 .cache_flush = global_cache_flush, 2290 .create_gatt_table = intel_i965_create_gatt_table, 2291 .free_gatt_table = intel_i830_free_gatt_table, 2292 .insert_memory = intel_i915_insert_entries, 2293 .remove_memory = intel_i915_remove_entries, 2294 .alloc_by_type = intel_i830_alloc_by_type, 2295 .free_by_type = intel_i810_free_by_type, 2296 .agp_alloc_page = agp_generic_alloc_page, 2297 .agp_alloc_pages = agp_generic_alloc_pages, 2298 .agp_destroy_page = agp_generic_destroy_page, 2299 .agp_destroy_pages = agp_generic_destroy_pages, 2300 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2301 .chipset_flush = intel_i915_chipset_flush, 2302#ifdef USE_PCI_DMA_API 2303 .agp_map_page = intel_agp_map_page, 2304 .agp_unmap_page = intel_agp_unmap_page, 2305 .agp_map_memory = intel_agp_map_memory, 2306 .agp_unmap_memory = intel_agp_unmap_memory, 2307#endif 2308}; 2309 2310static const struct agp_bridge_driver intel_7505_driver = { 2311 .owner = THIS_MODULE, 2312 .aperture_sizes = intel_8xx_sizes, 2313 .size_type = U8_APER_SIZE, 2314 .num_aperture_sizes = 7, 2315 .configure = intel_7505_configure, 2316 .fetch_size = intel_8xx_fetch_size, 2317 .cleanup = intel_8xx_cleanup, 2318 .tlb_flush = intel_8xx_tlbflush, 2319 .mask_memory = agp_generic_mask_memory, 2320 .masks = intel_generic_masks, 2321 .agp_enable = agp_generic_enable, 2322 .cache_flush = global_cache_flush, 2323 .create_gatt_table = agp_generic_create_gatt_table, 2324 .free_gatt_table = agp_generic_free_gatt_table, 2325 .insert_memory = agp_generic_insert_memory, 2326 .remove_memory = agp_generic_remove_memory, 2327 .alloc_by_type = agp_generic_alloc_by_type, 2328 .free_by_type = agp_generic_free_by_type, 2329 .agp_alloc_page = agp_generic_alloc_page, 2330 .agp_alloc_pages = agp_generic_alloc_pages, 2331 .agp_destroy_page = agp_generic_destroy_page, 2332 .agp_destroy_pages = agp_generic_destroy_pages, 2333 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2334}; 2335 2336static const struct agp_bridge_driver intel_g33_driver = { 2337 .owner = THIS_MODULE, 2338 .aperture_sizes = intel_i830_sizes, 2339 .size_type = FIXED_APER_SIZE, 2340 .num_aperture_sizes = 4, 2341 .needs_scratch_page = true, 2342 .configure = intel_i915_configure, 2343 .fetch_size = intel_i9xx_fetch_size, 2344 .cleanup = intel_i915_cleanup, 2345 .tlb_flush = intel_i810_tlbflush, 2346 .mask_memory = intel_i965_mask_memory, 2347 .masks = intel_i810_masks, 2348 .agp_enable = intel_i810_agp_enable, 2349 .cache_flush = global_cache_flush, 2350 .create_gatt_table = intel_i915_create_gatt_table, 2351 .free_gatt_table = intel_i830_free_gatt_table, 2352 .insert_memory = intel_i915_insert_entries, 2353 .remove_memory = intel_i915_remove_entries, 2354 .alloc_by_type = intel_i830_alloc_by_type, 2355 .free_by_type = intel_i810_free_by_type, 2356 .agp_alloc_page = agp_generic_alloc_page, 2357 .agp_alloc_pages = agp_generic_alloc_pages, 2358 .agp_destroy_page = agp_generic_destroy_page, 2359 .agp_destroy_pages = agp_generic_destroy_pages, 2360 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2361 .chipset_flush = intel_i915_chipset_flush, 2362#ifdef USE_PCI_DMA_API 2363 .agp_map_page = intel_agp_map_page, 2364 .agp_unmap_page = intel_agp_unmap_page, 2365 .agp_map_memory = intel_agp_map_memory, 2366 .agp_unmap_memory = intel_agp_unmap_memory, 2367#endif 2368}; 2369 2370static int find_gmch(u16 device) 2371{ 2372 struct pci_dev *gmch_device; 2373 2374 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2375 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2376 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2377 device, gmch_device); 2378 } 2379 2380 if (!gmch_device) 2381 return 0; 2382 2383 intel_private.pcidev = gmch_device; 2384 return 1; 2385} 2386 2387/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2388 * driver and gmch_driver must be non-null, and find_gmch will determine 2389 * which one should be used if a gmch_chip_id is present. 2390 */ 2391static const struct intel_driver_description { 2392 unsigned int chip_id; 2393 unsigned int gmch_chip_id; 2394 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2395 char *name; 2396 const struct agp_bridge_driver *driver; 2397 const struct agp_bridge_driver *gmch_driver; 2398} intel_agp_chipsets[] = { 2399 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2400 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2401 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2402 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2403 NULL, &intel_810_driver }, 2404 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2405 NULL, &intel_810_driver }, 2406 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2407 NULL, &intel_810_driver }, 2408 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2409 &intel_815_driver, &intel_810_driver }, 2410 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2411 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2412 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2413 &intel_830mp_driver, &intel_830_driver }, 2414 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2415 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2416 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2417 &intel_845_driver, &intel_830_driver }, 2418 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2419 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", 2420 &intel_845_driver, &intel_830_driver }, 2421 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2422 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2423 &intel_845_driver, &intel_830_driver }, 2424 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2425 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2426 &intel_845_driver, &intel_830_driver }, 2427 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2428 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2429 NULL, &intel_915_driver }, 2430 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2431 NULL, &intel_915_driver }, 2432 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2433 NULL, &intel_915_driver }, 2434 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2435 NULL, &intel_915_driver }, 2436 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2437 NULL, &intel_915_driver }, 2438 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2439 NULL, &intel_915_driver }, 2440 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2441 NULL, &intel_i965_driver }, 2442 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2443 NULL, &intel_i965_driver }, 2444 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2445 NULL, &intel_i965_driver }, 2446 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2447 NULL, &intel_i965_driver }, 2448 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2449 NULL, &intel_i965_driver }, 2450 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2451 NULL, &intel_i965_driver }, 2452 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2453 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2454 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2455 NULL, &intel_g33_driver }, 2456 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2457 NULL, &intel_g33_driver }, 2458 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2459 NULL, &intel_g33_driver }, 2460 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150", 2461 NULL, &intel_g33_driver }, 2462 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150", 2463 NULL, &intel_g33_driver }, 2464 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2465 "GM45", NULL, &intel_i965_driver }, 2466 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0, 2467 "Eaglelake", NULL, &intel_i965_driver }, 2468 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2469 "Q45/Q43", NULL, &intel_i965_driver }, 2470 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2471 "G45/G43", NULL, &intel_i965_driver }, 2472 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, 2473 "B43", NULL, &intel_i965_driver }, 2474 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2475 "G41", NULL, &intel_i965_driver }, 2476 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0, 2477 "HD Graphics", NULL, &intel_i965_driver }, 2478 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2479 "HD Graphics", NULL, &intel_i965_driver }, 2480 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2481 "HD Graphics", NULL, &intel_i965_driver }, 2482 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, 2483 "HD Graphics", NULL, &intel_i965_driver }, 2484 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, 2485 "Sandybridge", NULL, &intel_i965_driver }, 2486 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0, 2487 "Sandybridge", NULL, &intel_i965_driver }, 2488 { 0, 0, 0, NULL, NULL, NULL } 2489}; 2490 2491static int __devinit agp_intel_probe(struct pci_dev *pdev, 2492 const struct pci_device_id *ent) 2493{ 2494 struct agp_bridge_data *bridge; 2495 u8 cap_ptr = 0; 2496 struct resource *r; 2497 int i, err; 2498 2499 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2500 2501 bridge = agp_alloc_bridge(); 2502 if (!bridge) 2503 return -ENOMEM; 2504 2505 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2506 /* In case that multiple models of gfx chip may 2507 stand on same host bridge type, this can be 2508 sure we detect the right IGD. */ 2509 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2510 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2511 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2512 bridge->driver = 2513 intel_agp_chipsets[i].gmch_driver; 2514 break; 2515 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2516 continue; 2517 } else { 2518 bridge->driver = intel_agp_chipsets[i].driver; 2519 break; 2520 } 2521 } 2522 } 2523 2524 if (intel_agp_chipsets[i].name == NULL) { 2525 if (cap_ptr) 2526 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2527 pdev->vendor, pdev->device); 2528 agp_put_bridge(bridge); 2529 return -ENODEV; 2530 } 2531 2532 if (bridge->driver == NULL) { 2533 /* bridge has no AGP and no IGD detected */ 2534 if (cap_ptr) 2535 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2536 intel_agp_chipsets[i].gmch_chip_id); 2537 agp_put_bridge(bridge); 2538 return -ENODEV; 2539 } 2540 2541 bridge->dev = pdev; 2542 bridge->capndx = cap_ptr; 2543 bridge->dev_private_data = &intel_private; 2544 2545 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2546 2547 /* 2548 * The following fixes the case where the BIOS has "forgotten" to 2549 * provide an address range for the GART. 2550 * 20030610 - hamish@zot.org 2551 */ 2552 r = &pdev->resource[0]; 2553 if (!r->start && r->end) { 2554 if (pci_assign_resource(pdev, 0)) { 2555 dev_err(&pdev->dev, "can't assign resource 0\n"); 2556 agp_put_bridge(bridge); 2557 return -ENODEV; 2558 } 2559 } 2560 2561 /* 2562 * If the device has not been properly setup, the following will catch 2563 * the problem and should stop the system from crashing. 2564 * 20030610 - hamish@zot.org 2565 */ 2566 if (pci_enable_device(pdev)) { 2567 dev_err(&pdev->dev, "can't enable PCI device\n"); 2568 agp_put_bridge(bridge); 2569 return -ENODEV; 2570 } 2571 2572 /* Fill in the mode register */ 2573 if (cap_ptr) { 2574 pci_read_config_dword(pdev, 2575 bridge->capndx+PCI_AGP_STATUS, 2576 &bridge->mode); 2577 } 2578 2579 if (bridge->driver->mask_memory == intel_i965_mask_memory) { 2580 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) 2581 dev_err(&intel_private.pcidev->dev, 2582 "set gfx device dma mask 36bit failed!\n"); 2583 else 2584 pci_set_consistent_dma_mask(intel_private.pcidev, 2585 DMA_BIT_MASK(36)); 2586 } 2587 2588 pci_set_drvdata(pdev, bridge); 2589 err = agp_add_bridge(bridge); 2590 if (!err) 2591 intel_agp_enabled = 1; 2592 return err; 2593} 2594 2595static void __devexit agp_intel_remove(struct pci_dev *pdev) 2596{ 2597 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2598 2599 agp_remove_bridge(bridge); 2600 2601 if (intel_private.pcidev) 2602 pci_dev_put(intel_private.pcidev); 2603 2604 agp_put_bridge(bridge); 2605} 2606 2607#ifdef CONFIG_PM 2608static int agp_intel_resume(struct pci_dev *pdev) 2609{ 2610 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2611 int ret_val; 2612 2613 if (bridge->driver == &intel_generic_driver) 2614 intel_configure(); 2615 else if (bridge->driver == &intel_850_driver) 2616 intel_850_configure(); 2617 else if (bridge->driver == &intel_845_driver) 2618 intel_845_configure(); 2619 else if (bridge->driver == &intel_830mp_driver) 2620 intel_830mp_configure(); 2621 else if (bridge->driver == &intel_915_driver) 2622 intel_i915_configure(); 2623 else if (bridge->driver == &intel_830_driver) 2624 intel_i830_configure(); 2625 else if (bridge->driver == &intel_810_driver) 2626 intel_i810_configure(); 2627 else if (bridge->driver == &intel_i965_driver) 2628 intel_i915_configure(); 2629 2630 ret_val = agp_rebind_memory(); 2631 if (ret_val != 0) 2632 return ret_val; 2633 2634 return 0; 2635} 2636#endif 2637 2638static struct pci_device_id agp_intel_pci_table[] = { 2639#define ID(x) \ 2640 { \ 2641 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2642 .class_mask = ~0, \ 2643 .vendor = PCI_VENDOR_ID_INTEL, \ 2644 .device = x, \ 2645 .subvendor = PCI_ANY_ID, \ 2646 .subdevice = PCI_ANY_ID, \ 2647 } 2648 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2649 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2650 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2651 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2652 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2653 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2654 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2655 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2656 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2657 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2658 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2659 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2660 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2661 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2662 ID(PCI_DEVICE_ID_INTEL_82854_HB), 2663 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2664 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2665 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2666 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2667 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2668 ID(PCI_DEVICE_ID_INTEL_7505_0), 2669 ID(PCI_DEVICE_ID_INTEL_7205_0), 2670 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2671 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2672 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2673 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2674 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2675 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2676 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB), 2677 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB), 2678 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2679 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2680 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2681 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2682 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2683 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2684 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2685 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2686 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2687 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2688 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB), 2689 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2690 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2691 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2692 ID(PCI_DEVICE_ID_INTEL_B43_HB), 2693 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), 2694 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), 2695 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), 2696 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), 2697 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), 2698 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), 2699 { } 2700}; 2701 2702MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2703 2704static struct pci_driver agp_intel_pci_driver = { 2705 .name = "agpgart-intel", 2706 .id_table = agp_intel_pci_table, 2707 .probe = agp_intel_probe, 2708 .remove = __devexit_p(agp_intel_remove), 2709#ifdef CONFIG_PM 2710 .resume = agp_intel_resume, 2711#endif 2712}; 2713 2714static int __init agp_intel_init(void) 2715{ 2716 if (agp_off) 2717 return -EINVAL; 2718 return pci_register_driver(&agp_intel_pci_driver); 2719} 2720 2721static void __exit agp_intel_cleanup(void) 2722{ 2723 pci_unregister_driver(&agp_intel_pci_driver); 2724} 2725 2726module_init(agp_intel_init); 2727module_exit(agp_intel_cleanup); 2728 2729MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 2730MODULE_LICENSE("GPL and additional rights"); 2731