intel-agp.c revision a51b34593f691a0837d752a1394dcee19483c607
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include "agp.h" 12 13#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 14#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 15#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980 16#define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982 17#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 18#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 19#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 20#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 21#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 22#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 23#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 24#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 25#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 26#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 27#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 28#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 29#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 30#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 31 32#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 33 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \ 34 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 35 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 36 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB) 37 38#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 41 42extern int agp_memory_reserved; 43 44 45/* Intel 815 register */ 46#define INTEL_815_APCONT 0x51 47#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 48 49/* Intel i820 registers */ 50#define INTEL_I820_RDCR 0x51 51#define INTEL_I820_ERRSTS 0xc8 52 53/* Intel i840 registers */ 54#define INTEL_I840_MCHCFG 0x50 55#define INTEL_I840_ERRSTS 0xc8 56 57/* Intel i850 registers */ 58#define INTEL_I850_MCHCFG 0x50 59#define INTEL_I850_ERRSTS 0xc8 60 61/* intel 915G registers */ 62#define I915_GMADDR 0x18 63#define I915_MMADDR 0x10 64#define I915_PTEADDR 0x1C 65#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 66#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 67#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 68#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 69 70/* Intel 965G registers */ 71#define I965_MSAC 0x62 72 73/* Intel 7505 registers */ 74#define INTEL_I7505_APSIZE 0x74 75#define INTEL_I7505_NCAPID 0x60 76#define INTEL_I7505_NISTAT 0x6c 77#define INTEL_I7505_ATTBASE 0x78 78#define INTEL_I7505_ERRSTS 0x42 79#define INTEL_I7505_AGPCTRL 0x70 80#define INTEL_I7505_MCHCFG 0x50 81 82static const struct aper_size_info_fixed intel_i810_sizes[] = 83{ 84 {64, 16384, 4}, 85 /* The 32M mode still requires a 64k gatt */ 86 {32, 8192, 4} 87}; 88 89#define AGP_DCACHE_MEMORY 1 90#define AGP_PHYS_MEMORY 2 91#define INTEL_AGP_CACHED_MEMORY 3 92 93static struct gatt_mask intel_i810_masks[] = 94{ 95 {.mask = I810_PTE_VALID, .type = 0}, 96 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 97 {.mask = I810_PTE_VALID, .type = 0}, 98 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 99 .type = INTEL_AGP_CACHED_MEMORY} 100}; 101 102static struct _intel_private { 103 struct pci_dev *pcidev; /* device one */ 104 u8 __iomem *registers; 105 u32 __iomem *gtt; /* I915G */ 106 int num_dcache_entries; 107 /* gtt_entries is the number of gtt entries that are already mapped 108 * to stolen memory. Stolen memory is larger than the memory mapped 109 * through gtt_entries, as it includes some reserved space for the BIOS 110 * popup and for the GTT. 111 */ 112 int gtt_entries; /* i830+ */ 113} intel_private; 114 115static int intel_i810_fetch_size(void) 116{ 117 u32 smram_miscc; 118 struct aper_size_info_fixed *values; 119 120 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 121 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 122 123 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 124 printk(KERN_WARNING PFX "i810 is disabled\n"); 125 return 0; 126 } 127 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 128 agp_bridge->previous_size = 129 agp_bridge->current_size = (void *) (values + 1); 130 agp_bridge->aperture_size_idx = 1; 131 return values[1].size; 132 } else { 133 agp_bridge->previous_size = 134 agp_bridge->current_size = (void *) (values); 135 agp_bridge->aperture_size_idx = 0; 136 return values[0].size; 137 } 138 139 return 0; 140} 141 142static int intel_i810_configure(void) 143{ 144 struct aper_size_info_fixed *current_size; 145 u32 temp; 146 int i; 147 148 current_size = A_SIZE_FIX(agp_bridge->current_size); 149 150 if (!intel_private.registers) { 151 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 152 temp &= 0xfff80000; 153 154 intel_private.registers = ioremap(temp, 128 * 4096); 155 if (!intel_private.registers) { 156 printk(KERN_ERR PFX "Unable to remap memory.\n"); 157 return -ENOMEM; 158 } 159 } 160 161 if ((readl(intel_private.registers+I810_DRAM_CTL) 162 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 163 /* This will need to be dynamically assigned */ 164 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 165 intel_private.num_dcache_entries = 1024; 166 } 167 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 168 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 169 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 170 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 171 172 if (agp_bridge->driver->needs_scratch_page) { 173 for (i = 0; i < current_size->num_entries; i++) { 174 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 175 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 176 } 177 } 178 global_cache_flush(); 179 return 0; 180} 181 182static void intel_i810_cleanup(void) 183{ 184 writel(0, intel_private.registers+I810_PGETBL_CTL); 185 readl(intel_private.registers); /* PCI Posting. */ 186 iounmap(intel_private.registers); 187} 188 189static void intel_i810_tlbflush(struct agp_memory *mem) 190{ 191 return; 192} 193 194static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 195{ 196 return; 197} 198 199/* Exists to support ARGB cursors */ 200static void *i8xx_alloc_pages(void) 201{ 202 struct page * page; 203 204 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 205 if (page == NULL) 206 return NULL; 207 208 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 209 change_page_attr(page, 4, PAGE_KERNEL); 210 global_flush_tlb(); 211 __free_pages(page, 2); 212 return NULL; 213 } 214 global_flush_tlb(); 215 get_page(page); 216 atomic_inc(&agp_bridge->current_memory_agp); 217 return page_address(page); 218} 219 220static void i8xx_destroy_pages(void *addr) 221{ 222 struct page *page; 223 224 if (addr == NULL) 225 return; 226 227 page = virt_to_page(addr); 228 change_page_attr(page, 4, PAGE_KERNEL); 229 global_flush_tlb(); 230 put_page(page); 231 __free_pages(page, 2); 232 atomic_dec(&agp_bridge->current_memory_agp); 233} 234 235static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 236 int type) 237{ 238 if (type < AGP_USER_TYPES) 239 return type; 240 else if (type == AGP_USER_CACHED_MEMORY) 241 return INTEL_AGP_CACHED_MEMORY; 242 else 243 return 0; 244} 245 246static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 247 int type) 248{ 249 int i, j, num_entries; 250 void *temp; 251 int ret = -EINVAL; 252 int mask_type; 253 254 if (mem->page_count == 0) 255 goto out; 256 257 temp = agp_bridge->current_size; 258 num_entries = A_SIZE_FIX(temp)->num_entries; 259 260 if ((pg_start + mem->page_count) > num_entries) 261 goto out_err; 262 263 264 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 265 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 266 ret = -EBUSY; 267 goto out_err; 268 } 269 } 270 271 if (type != mem->type) 272 goto out_err; 273 274 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 275 276 switch (mask_type) { 277 case AGP_DCACHE_MEMORY: 278 if (!mem->is_flushed) 279 global_cache_flush(); 280 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 281 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 282 intel_private.registers+I810_PTE_BASE+(i*4)); 283 } 284 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 285 break; 286 case AGP_PHYS_MEMORY: 287 case AGP_NORMAL_MEMORY: 288 if (!mem->is_flushed) 289 global_cache_flush(); 290 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 291 writel(agp_bridge->driver->mask_memory(agp_bridge, 292 mem->memory[i], 293 mask_type), 294 intel_private.registers+I810_PTE_BASE+(j*4)); 295 } 296 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 297 break; 298 default: 299 goto out_err; 300 } 301 302 agp_bridge->driver->tlb_flush(mem); 303out: 304 ret = 0; 305out_err: 306 mem->is_flushed = 1; 307 return ret; 308} 309 310static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 311 int type) 312{ 313 int i; 314 315 if (mem->page_count == 0) 316 return 0; 317 318 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 319 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 320 } 321 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 322 323 agp_bridge->driver->tlb_flush(mem); 324 return 0; 325} 326 327/* 328 * The i810/i830 requires a physical address to program its mouse 329 * pointer into hardware. 330 * However the Xserver still writes to it through the agp aperture. 331 */ 332static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 333{ 334 struct agp_memory *new; 335 void *addr; 336 337 switch (pg_count) { 338 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 339 global_flush_tlb(); 340 break; 341 case 4: 342 /* kludge to get 4 physical pages for ARGB cursor */ 343 addr = i8xx_alloc_pages(); 344 break; 345 default: 346 return NULL; 347 } 348 349 if (addr == NULL) 350 return NULL; 351 352 new = agp_create_memory(pg_count); 353 if (new == NULL) 354 return NULL; 355 356 new->memory[0] = virt_to_gart(addr); 357 if (pg_count == 4) { 358 /* kludge to get 4 physical pages for ARGB cursor */ 359 new->memory[1] = new->memory[0] + PAGE_SIZE; 360 new->memory[2] = new->memory[1] + PAGE_SIZE; 361 new->memory[3] = new->memory[2] + PAGE_SIZE; 362 } 363 new->page_count = pg_count; 364 new->num_scratch_pages = pg_count; 365 new->type = AGP_PHYS_MEMORY; 366 new->physical = new->memory[0]; 367 return new; 368} 369 370static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 371{ 372 struct agp_memory *new; 373 374 if (type == AGP_DCACHE_MEMORY) { 375 if (pg_count != intel_private.num_dcache_entries) 376 return NULL; 377 378 new = agp_create_memory(1); 379 if (new == NULL) 380 return NULL; 381 382 new->type = AGP_DCACHE_MEMORY; 383 new->page_count = pg_count; 384 new->num_scratch_pages = 0; 385 agp_free_page_array(new); 386 return new; 387 } 388 if (type == AGP_PHYS_MEMORY) 389 return alloc_agpphysmem_i8xx(pg_count, type); 390 return NULL; 391} 392 393static void intel_i810_free_by_type(struct agp_memory *curr) 394{ 395 agp_free_key(curr->key); 396 if (curr->type == AGP_PHYS_MEMORY) { 397 if (curr->page_count == 4) 398 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 399 else { 400 agp_bridge->driver->agp_destroy_page( 401 gart_to_virt(curr->memory[0])); 402 global_flush_tlb(); 403 } 404 agp_free_page_array(curr); 405 } 406 kfree(curr); 407} 408 409static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 410 unsigned long addr, int type) 411{ 412 /* Type checking must be done elsewhere */ 413 return addr | bridge->driver->masks[type].mask; 414} 415 416static struct aper_size_info_fixed intel_i830_sizes[] = 417{ 418 {128, 32768, 5}, 419 /* The 64M mode still requires a 128k gatt */ 420 {64, 16384, 5}, 421 {256, 65536, 6}, 422 {512, 131072, 7}, 423}; 424 425static void intel_i830_init_gtt_entries(void) 426{ 427 u16 gmch_ctrl; 428 int gtt_entries; 429 u8 rdct; 430 int local = 0; 431 static const int ddt[4] = { 0, 16, 32, 64 }; 432 int size; /* reserved space (in kb) at the top of stolen memory */ 433 434 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 435 436 if (IS_I965) { 437 u32 pgetbl_ctl; 438 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 439 440 /* The 965 has a field telling us the size of the GTT, 441 * which may be larger than what is necessary to map the 442 * aperture. 443 */ 444 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 445 case I965_PGETBL_SIZE_128KB: 446 size = 128; 447 break; 448 case I965_PGETBL_SIZE_256KB: 449 size = 256; 450 break; 451 case I965_PGETBL_SIZE_512KB: 452 size = 512; 453 break; 454 default: 455 printk(KERN_INFO PFX "Unknown page table size, " 456 "assuming 512KB\n"); 457 size = 512; 458 } 459 size += 4; /* add in BIOS popup space */ 460 } else if (IS_G33) { 461 /* G33's GTT size defined in gmch_ctrl */ 462 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 463 case G33_PGETBL_SIZE_1M: 464 size = 1024; 465 break; 466 case G33_PGETBL_SIZE_2M: 467 size = 2048; 468 break; 469 default: 470 printk(KERN_INFO PFX "Unknown page table size 0x%x, " 471 "assuming 512KB\n", 472 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 473 size = 512; 474 } 475 size += 4; 476 } else { 477 /* On previous hardware, the GTT size was just what was 478 * required to map the aperture. 479 */ 480 size = agp_bridge->driver->fetch_size() + 4; 481 } 482 483 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 484 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 485 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 486 case I830_GMCH_GMS_STOLEN_512: 487 gtt_entries = KB(512) - KB(size); 488 break; 489 case I830_GMCH_GMS_STOLEN_1024: 490 gtt_entries = MB(1) - KB(size); 491 break; 492 case I830_GMCH_GMS_STOLEN_8192: 493 gtt_entries = MB(8) - KB(size); 494 break; 495 case I830_GMCH_GMS_LOCAL: 496 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 497 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 498 MB(ddt[I830_RDRAM_DDT(rdct)]); 499 local = 1; 500 break; 501 default: 502 gtt_entries = 0; 503 break; 504 } 505 } else { 506 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 507 case I855_GMCH_GMS_STOLEN_1M: 508 gtt_entries = MB(1) - KB(size); 509 break; 510 case I855_GMCH_GMS_STOLEN_4M: 511 gtt_entries = MB(4) - KB(size); 512 break; 513 case I855_GMCH_GMS_STOLEN_8M: 514 gtt_entries = MB(8) - KB(size); 515 break; 516 case I855_GMCH_GMS_STOLEN_16M: 517 gtt_entries = MB(16) - KB(size); 518 break; 519 case I855_GMCH_GMS_STOLEN_32M: 520 gtt_entries = MB(32) - KB(size); 521 break; 522 case I915_GMCH_GMS_STOLEN_48M: 523 /* Check it's really I915G */ 524 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 525 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 526 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 527 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || 528 IS_I965 || IS_G33) 529 gtt_entries = MB(48) - KB(size); 530 else 531 gtt_entries = 0; 532 break; 533 case I915_GMCH_GMS_STOLEN_64M: 534 /* Check it's really I915G */ 535 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 536 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 537 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 538 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || 539 IS_I965 || IS_G33) 540 gtt_entries = MB(64) - KB(size); 541 else 542 gtt_entries = 0; 543 break; 544 case G33_GMCH_GMS_STOLEN_128M: 545 if (IS_G33) 546 gtt_entries = MB(128) - KB(size); 547 else 548 gtt_entries = 0; 549 break; 550 case G33_GMCH_GMS_STOLEN_256M: 551 if (IS_G33) 552 gtt_entries = MB(256) - KB(size); 553 else 554 gtt_entries = 0; 555 break; 556 default: 557 gtt_entries = 0; 558 break; 559 } 560 } 561 if (gtt_entries > 0) 562 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 563 gtt_entries / KB(1), local ? "local" : "stolen"); 564 else 565 printk(KERN_INFO PFX 566 "No pre-allocated video memory detected.\n"); 567 gtt_entries /= KB(4); 568 569 intel_private.gtt_entries = gtt_entries; 570} 571 572/* The intel i830 automatically initializes the agp aperture during POST. 573 * Use the memory already set aside for in the GTT. 574 */ 575static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 576{ 577 int page_order; 578 struct aper_size_info_fixed *size; 579 int num_entries; 580 u32 temp; 581 582 size = agp_bridge->current_size; 583 page_order = size->page_order; 584 num_entries = size->num_entries; 585 agp_bridge->gatt_table_real = NULL; 586 587 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp); 588 temp &= 0xfff80000; 589 590 intel_private.registers = ioremap(temp,128 * 4096); 591 if (!intel_private.registers) 592 return -ENOMEM; 593 594 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 595 global_cache_flush(); /* FIXME: ?? */ 596 597 /* we have to call this as early as possible after the MMIO base address is known */ 598 intel_i830_init_gtt_entries(); 599 600 agp_bridge->gatt_table = NULL; 601 602 agp_bridge->gatt_bus_addr = temp; 603 604 return 0; 605} 606 607/* Return the gatt table to a sane state. Use the top of stolen 608 * memory for the GTT. 609 */ 610static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 611{ 612 return 0; 613} 614 615static int intel_i830_fetch_size(void) 616{ 617 u16 gmch_ctrl; 618 struct aper_size_info_fixed *values; 619 620 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 621 622 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 623 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 624 /* 855GM/852GM/865G has 128MB aperture size */ 625 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 626 agp_bridge->aperture_size_idx = 0; 627 return values[0].size; 628 } 629 630 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 631 632 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 633 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 634 agp_bridge->aperture_size_idx = 0; 635 return values[0].size; 636 } else { 637 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 638 agp_bridge->aperture_size_idx = 1; 639 return values[1].size; 640 } 641 642 return 0; 643} 644 645static int intel_i830_configure(void) 646{ 647 struct aper_size_info_fixed *current_size; 648 u32 temp; 649 u16 gmch_ctrl; 650 int i; 651 652 current_size = A_SIZE_FIX(agp_bridge->current_size); 653 654 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp); 655 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 656 657 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 658 gmch_ctrl |= I830_GMCH_ENABLED; 659 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 660 661 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 662 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 663 664 if (agp_bridge->driver->needs_scratch_page) { 665 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 666 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 667 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 668 } 669 } 670 671 global_cache_flush(); 672 return 0; 673} 674 675static void intel_i830_cleanup(void) 676{ 677 iounmap(intel_private.registers); 678} 679 680static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 681{ 682 int i,j,num_entries; 683 void *temp; 684 int ret = -EINVAL; 685 int mask_type; 686 687 if (mem->page_count == 0) 688 goto out; 689 690 temp = agp_bridge->current_size; 691 num_entries = A_SIZE_FIX(temp)->num_entries; 692 693 if (pg_start < intel_private.gtt_entries) { 694 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", 695 pg_start,intel_private.gtt_entries); 696 697 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 698 goto out_err; 699 } 700 701 if ((pg_start + mem->page_count) > num_entries) 702 goto out_err; 703 704 /* The i830 can't check the GTT for entries since its read only, 705 * depend on the caller to make the correct offset decisions. 706 */ 707 708 if (type != mem->type) 709 goto out_err; 710 711 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 712 713 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 714 mask_type != INTEL_AGP_CACHED_MEMORY) 715 goto out_err; 716 717 if (!mem->is_flushed) 718 global_cache_flush(); 719 720 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 721 writel(agp_bridge->driver->mask_memory(agp_bridge, 722 mem->memory[i], mask_type), 723 intel_private.registers+I810_PTE_BASE+(j*4)); 724 } 725 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 726 agp_bridge->driver->tlb_flush(mem); 727 728out: 729 ret = 0; 730out_err: 731 mem->is_flushed = 1; 732 return ret; 733} 734 735static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 736 int type) 737{ 738 int i; 739 740 if (mem->page_count == 0) 741 return 0; 742 743 if (pg_start < intel_private.gtt_entries) { 744 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 745 return -EINVAL; 746 } 747 748 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 749 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 750 } 751 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 752 753 agp_bridge->driver->tlb_flush(mem); 754 return 0; 755} 756 757static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 758{ 759 if (type == AGP_PHYS_MEMORY) 760 return alloc_agpphysmem_i8xx(pg_count, type); 761 /* always return NULL for other allocation types for now */ 762 return NULL; 763} 764 765static int intel_i915_configure(void) 766{ 767 struct aper_size_info_fixed *current_size; 768 u32 temp; 769 u16 gmch_ctrl; 770 int i; 771 772 current_size = A_SIZE_FIX(agp_bridge->current_size); 773 774 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 775 776 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 777 778 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 779 gmch_ctrl |= I830_GMCH_ENABLED; 780 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 781 782 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 783 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 784 785 if (agp_bridge->driver->needs_scratch_page) { 786 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 787 writel(agp_bridge->scratch_page, intel_private.gtt+i); 788 readl(intel_private.gtt+i); /* PCI Posting. */ 789 } 790 } 791 792 global_cache_flush(); 793 return 0; 794} 795 796static void intel_i915_cleanup(void) 797{ 798 iounmap(intel_private.gtt); 799 iounmap(intel_private.registers); 800} 801 802static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 803 int type) 804{ 805 int i,j,num_entries; 806 void *temp; 807 int ret = -EINVAL; 808 int mask_type; 809 810 if (mem->page_count == 0) 811 goto out; 812 813 temp = agp_bridge->current_size; 814 num_entries = A_SIZE_FIX(temp)->num_entries; 815 816 if (pg_start < intel_private.gtt_entries) { 817 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", 818 pg_start,intel_private.gtt_entries); 819 820 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 821 goto out_err; 822 } 823 824 if ((pg_start + mem->page_count) > num_entries) 825 goto out_err; 826 827 /* The i915 can't check the GTT for entries since its read only, 828 * depend on the caller to make the correct offset decisions. 829 */ 830 831 if (type != mem->type) 832 goto out_err; 833 834 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 835 836 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 837 mask_type != INTEL_AGP_CACHED_MEMORY) 838 goto out_err; 839 840 if (!mem->is_flushed) 841 global_cache_flush(); 842 843 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 844 writel(agp_bridge->driver->mask_memory(agp_bridge, 845 mem->memory[i], mask_type), intel_private.gtt+j); 846 } 847 848 readl(intel_private.gtt+j-1); 849 agp_bridge->driver->tlb_flush(mem); 850 851 out: 852 ret = 0; 853 out_err: 854 mem->is_flushed = 1; 855 return ret; 856} 857 858static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 859 int type) 860{ 861 int i; 862 863 if (mem->page_count == 0) 864 return 0; 865 866 if (pg_start < intel_private.gtt_entries) { 867 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 868 return -EINVAL; 869 } 870 871 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 872 writel(agp_bridge->scratch_page, intel_private.gtt+i); 873 } 874 readl(intel_private.gtt+i-1); 875 876 agp_bridge->driver->tlb_flush(mem); 877 return 0; 878} 879 880/* Return the aperture size by just checking the resource length. The effect 881 * described in the spec of the MSAC registers is just changing of the 882 * resource size. 883 */ 884static int intel_i9xx_fetch_size(void) 885{ 886 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 887 int aper_size; /* size in megabytes */ 888 int i; 889 890 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 891 892 for (i = 0; i < num_sizes; i++) { 893 if (aper_size == intel_i830_sizes[i].size) { 894 agp_bridge->current_size = intel_i830_sizes + i; 895 agp_bridge->previous_size = agp_bridge->current_size; 896 return aper_size; 897 } 898 } 899 900 return 0; 901} 902 903/* The intel i915 automatically initializes the agp aperture during POST. 904 * Use the memory already set aside for in the GTT. 905 */ 906static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 907{ 908 int page_order; 909 struct aper_size_info_fixed *size; 910 int num_entries; 911 u32 temp, temp2; 912 913 size = agp_bridge->current_size; 914 page_order = size->page_order; 915 num_entries = size->num_entries; 916 agp_bridge->gatt_table_real = NULL; 917 918 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 919 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2); 920 921 intel_private.gtt = ioremap(temp2, 256 * 1024); 922 if (!intel_private.gtt) 923 return -ENOMEM; 924 925 temp &= 0xfff80000; 926 927 intel_private.registers = ioremap(temp,128 * 4096); 928 if (!intel_private.registers) 929 return -ENOMEM; 930 931 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 932 global_cache_flush(); /* FIXME: ? */ 933 934 /* we have to call this as early as possible after the MMIO base address is known */ 935 intel_i830_init_gtt_entries(); 936 937 agp_bridge->gatt_table = NULL; 938 939 agp_bridge->gatt_bus_addr = temp; 940 941 return 0; 942} 943 944/* 945 * The i965 supports 36-bit physical addresses, but to keep 946 * the format of the GTT the same, the bits that don't fit 947 * in a 32-bit word are shifted down to bits 4..7. 948 * 949 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 950 * is always zero on 32-bit architectures, so no need to make 951 * this conditional. 952 */ 953static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 954 unsigned long addr, int type) 955{ 956 /* Shift high bits down */ 957 addr |= (addr >> 28) & 0xf0; 958 959 /* Type checking must be done elsewhere */ 960 return addr | bridge->driver->masks[type].mask; 961} 962 963/* The intel i965 automatically initializes the agp aperture during POST. 964 * Use the memory already set aside for in the GTT. 965 */ 966static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 967{ 968 int page_order; 969 struct aper_size_info_fixed *size; 970 int num_entries; 971 u32 temp; 972 973 size = agp_bridge->current_size; 974 page_order = size->page_order; 975 num_entries = size->num_entries; 976 agp_bridge->gatt_table_real = NULL; 977 978 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 979 980 temp &= 0xfff00000; 981 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); 982 983 if (!intel_private.gtt) 984 return -ENOMEM; 985 986 987 intel_private.registers = ioremap(temp,128 * 4096); 988 if (!intel_private.registers) 989 return -ENOMEM; 990 991 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 992 global_cache_flush(); /* FIXME: ? */ 993 994 /* we have to call this as early as possible after the MMIO base address is known */ 995 intel_i830_init_gtt_entries(); 996 997 agp_bridge->gatt_table = NULL; 998 999 agp_bridge->gatt_bus_addr = temp; 1000 1001 return 0; 1002} 1003 1004 1005static int intel_fetch_size(void) 1006{ 1007 int i; 1008 u16 temp; 1009 struct aper_size_info_16 *values; 1010 1011 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1012 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1013 1014 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1015 if (temp == values[i].size_value) { 1016 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1017 agp_bridge->aperture_size_idx = i; 1018 return values[i].size; 1019 } 1020 } 1021 1022 return 0; 1023} 1024 1025static int __intel_8xx_fetch_size(u8 temp) 1026{ 1027 int i; 1028 struct aper_size_info_8 *values; 1029 1030 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1031 1032 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1033 if (temp == values[i].size_value) { 1034 agp_bridge->previous_size = 1035 agp_bridge->current_size = (void *) (values + i); 1036 agp_bridge->aperture_size_idx = i; 1037 return values[i].size; 1038 } 1039 } 1040 return 0; 1041} 1042 1043static int intel_8xx_fetch_size(void) 1044{ 1045 u8 temp; 1046 1047 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1048 return __intel_8xx_fetch_size(temp); 1049} 1050 1051static int intel_815_fetch_size(void) 1052{ 1053 u8 temp; 1054 1055 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1056 * one non-reserved bit, so mask the others out ... */ 1057 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1058 temp &= (1 << 3); 1059 1060 return __intel_8xx_fetch_size(temp); 1061} 1062 1063static void intel_tlbflush(struct agp_memory *mem) 1064{ 1065 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1066 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1067} 1068 1069 1070static void intel_8xx_tlbflush(struct agp_memory *mem) 1071{ 1072 u32 temp; 1073 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1074 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1075 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1076 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1077} 1078 1079 1080static void intel_cleanup(void) 1081{ 1082 u16 temp; 1083 struct aper_size_info_16 *previous_size; 1084 1085 previous_size = A_SIZE_16(agp_bridge->previous_size); 1086 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1087 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1088 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1089} 1090 1091 1092static void intel_8xx_cleanup(void) 1093{ 1094 u16 temp; 1095 struct aper_size_info_8 *previous_size; 1096 1097 previous_size = A_SIZE_8(agp_bridge->previous_size); 1098 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1099 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1100 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1101} 1102 1103 1104static int intel_configure(void) 1105{ 1106 u32 temp; 1107 u16 temp2; 1108 struct aper_size_info_16 *current_size; 1109 1110 current_size = A_SIZE_16(agp_bridge->current_size); 1111 1112 /* aperture size */ 1113 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1114 1115 /* address to map to */ 1116 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1117 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1118 1119 /* attbase - aperture base */ 1120 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1121 1122 /* agpctrl */ 1123 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1124 1125 /* paccfg/nbxcfg */ 1126 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1127 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1128 (temp2 & ~(1 << 10)) | (1 << 9)); 1129 /* clear any possible error conditions */ 1130 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1131 return 0; 1132} 1133 1134static int intel_815_configure(void) 1135{ 1136 u32 temp, addr; 1137 u8 temp2; 1138 struct aper_size_info_8 *current_size; 1139 1140 /* attbase - aperture base */ 1141 /* the Intel 815 chipset spec. says that bits 29-31 in the 1142 * ATTBASE register are reserved -> try not to write them */ 1143 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1144 printk (KERN_EMERG PFX "gatt bus addr too high"); 1145 return -EINVAL; 1146 } 1147 1148 current_size = A_SIZE_8(agp_bridge->current_size); 1149 1150 /* aperture size */ 1151 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1152 current_size->size_value); 1153 1154 /* address to map to */ 1155 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1156 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1157 1158 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1159 addr &= INTEL_815_ATTBASE_MASK; 1160 addr |= agp_bridge->gatt_bus_addr; 1161 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1162 1163 /* agpctrl */ 1164 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1165 1166 /* apcont */ 1167 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1168 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1169 1170 /* clear any possible error conditions */ 1171 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1172 return 0; 1173} 1174 1175static void intel_820_tlbflush(struct agp_memory *mem) 1176{ 1177 return; 1178} 1179 1180static void intel_820_cleanup(void) 1181{ 1182 u8 temp; 1183 struct aper_size_info_8 *previous_size; 1184 1185 previous_size = A_SIZE_8(agp_bridge->previous_size); 1186 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1187 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1188 temp & ~(1 << 1)); 1189 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1190 previous_size->size_value); 1191} 1192 1193 1194static int intel_820_configure(void) 1195{ 1196 u32 temp; 1197 u8 temp2; 1198 struct aper_size_info_8 *current_size; 1199 1200 current_size = A_SIZE_8(agp_bridge->current_size); 1201 1202 /* aperture size */ 1203 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1204 1205 /* address to map to */ 1206 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1207 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1208 1209 /* attbase - aperture base */ 1210 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1211 1212 /* agpctrl */ 1213 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1214 1215 /* global enable aperture access */ 1216 /* This flag is not accessed through MCHCFG register as in */ 1217 /* i850 chipset. */ 1218 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1219 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1220 /* clear any possible AGP-related error conditions */ 1221 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1222 return 0; 1223} 1224 1225static int intel_840_configure(void) 1226{ 1227 u32 temp; 1228 u16 temp2; 1229 struct aper_size_info_8 *current_size; 1230 1231 current_size = A_SIZE_8(agp_bridge->current_size); 1232 1233 /* aperture size */ 1234 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1235 1236 /* address to map to */ 1237 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1238 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1239 1240 /* attbase - aperture base */ 1241 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1242 1243 /* agpctrl */ 1244 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1245 1246 /* mcgcfg */ 1247 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1248 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1249 /* clear any possible error conditions */ 1250 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1251 return 0; 1252} 1253 1254static int intel_845_configure(void) 1255{ 1256 u32 temp; 1257 u8 temp2; 1258 struct aper_size_info_8 *current_size; 1259 1260 current_size = A_SIZE_8(agp_bridge->current_size); 1261 1262 /* aperture size */ 1263 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1264 1265 if (agp_bridge->apbase_config != 0) { 1266 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1267 agp_bridge->apbase_config); 1268 } else { 1269 /* address to map to */ 1270 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1271 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1272 agp_bridge->apbase_config = temp; 1273 } 1274 1275 /* attbase - aperture base */ 1276 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1277 1278 /* agpctrl */ 1279 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1280 1281 /* agpm */ 1282 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1283 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1284 /* clear any possible error conditions */ 1285 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1286 return 0; 1287} 1288 1289static int intel_850_configure(void) 1290{ 1291 u32 temp; 1292 u16 temp2; 1293 struct aper_size_info_8 *current_size; 1294 1295 current_size = A_SIZE_8(agp_bridge->current_size); 1296 1297 /* aperture size */ 1298 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1299 1300 /* address to map to */ 1301 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1302 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1303 1304 /* attbase - aperture base */ 1305 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1306 1307 /* agpctrl */ 1308 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1309 1310 /* mcgcfg */ 1311 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1312 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1313 /* clear any possible AGP-related error conditions */ 1314 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1315 return 0; 1316} 1317 1318static int intel_860_configure(void) 1319{ 1320 u32 temp; 1321 u16 temp2; 1322 struct aper_size_info_8 *current_size; 1323 1324 current_size = A_SIZE_8(agp_bridge->current_size); 1325 1326 /* aperture size */ 1327 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1328 1329 /* address to map to */ 1330 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1331 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1332 1333 /* attbase - aperture base */ 1334 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1335 1336 /* agpctrl */ 1337 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1338 1339 /* mcgcfg */ 1340 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1341 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1342 /* clear any possible AGP-related error conditions */ 1343 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1344 return 0; 1345} 1346 1347static int intel_830mp_configure(void) 1348{ 1349 u32 temp; 1350 u16 temp2; 1351 struct aper_size_info_8 *current_size; 1352 1353 current_size = A_SIZE_8(agp_bridge->current_size); 1354 1355 /* aperture size */ 1356 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1357 1358 /* address to map to */ 1359 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1360 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1361 1362 /* attbase - aperture base */ 1363 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1364 1365 /* agpctrl */ 1366 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1367 1368 /* gmch */ 1369 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1370 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1371 /* clear any possible AGP-related error conditions */ 1372 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1373 return 0; 1374} 1375 1376static int intel_7505_configure(void) 1377{ 1378 u32 temp; 1379 u16 temp2; 1380 struct aper_size_info_8 *current_size; 1381 1382 current_size = A_SIZE_8(agp_bridge->current_size); 1383 1384 /* aperture size */ 1385 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1386 1387 /* address to map to */ 1388 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1389 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1390 1391 /* attbase - aperture base */ 1392 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1393 1394 /* agpctrl */ 1395 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1396 1397 /* mchcfg */ 1398 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1399 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1400 1401 return 0; 1402} 1403 1404/* Setup function */ 1405static const struct gatt_mask intel_generic_masks[] = 1406{ 1407 {.mask = 0x00000017, .type = 0} 1408}; 1409 1410static const struct aper_size_info_8 intel_815_sizes[2] = 1411{ 1412 {64, 16384, 4, 0}, 1413 {32, 8192, 3, 8}, 1414}; 1415 1416static const struct aper_size_info_8 intel_8xx_sizes[7] = 1417{ 1418 {256, 65536, 6, 0}, 1419 {128, 32768, 5, 32}, 1420 {64, 16384, 4, 48}, 1421 {32, 8192, 3, 56}, 1422 {16, 4096, 2, 60}, 1423 {8, 2048, 1, 62}, 1424 {4, 1024, 0, 63} 1425}; 1426 1427static const struct aper_size_info_16 intel_generic_sizes[7] = 1428{ 1429 {256, 65536, 6, 0}, 1430 {128, 32768, 5, 32}, 1431 {64, 16384, 4, 48}, 1432 {32, 8192, 3, 56}, 1433 {16, 4096, 2, 60}, 1434 {8, 2048, 1, 62}, 1435 {4, 1024, 0, 63} 1436}; 1437 1438static const struct aper_size_info_8 intel_830mp_sizes[4] = 1439{ 1440 {256, 65536, 6, 0}, 1441 {128, 32768, 5, 32}, 1442 {64, 16384, 4, 48}, 1443 {32, 8192, 3, 56} 1444}; 1445 1446static const struct agp_bridge_driver intel_generic_driver = { 1447 .owner = THIS_MODULE, 1448 .aperture_sizes = intel_generic_sizes, 1449 .size_type = U16_APER_SIZE, 1450 .num_aperture_sizes = 7, 1451 .configure = intel_configure, 1452 .fetch_size = intel_fetch_size, 1453 .cleanup = intel_cleanup, 1454 .tlb_flush = intel_tlbflush, 1455 .mask_memory = agp_generic_mask_memory, 1456 .masks = intel_generic_masks, 1457 .agp_enable = agp_generic_enable, 1458 .cache_flush = global_cache_flush, 1459 .create_gatt_table = agp_generic_create_gatt_table, 1460 .free_gatt_table = agp_generic_free_gatt_table, 1461 .insert_memory = agp_generic_insert_memory, 1462 .remove_memory = agp_generic_remove_memory, 1463 .alloc_by_type = agp_generic_alloc_by_type, 1464 .free_by_type = agp_generic_free_by_type, 1465 .agp_alloc_page = agp_generic_alloc_page, 1466 .agp_destroy_page = agp_generic_destroy_page, 1467 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1468}; 1469 1470static const struct agp_bridge_driver intel_810_driver = { 1471 .owner = THIS_MODULE, 1472 .aperture_sizes = intel_i810_sizes, 1473 .size_type = FIXED_APER_SIZE, 1474 .num_aperture_sizes = 2, 1475 .needs_scratch_page = TRUE, 1476 .configure = intel_i810_configure, 1477 .fetch_size = intel_i810_fetch_size, 1478 .cleanup = intel_i810_cleanup, 1479 .tlb_flush = intel_i810_tlbflush, 1480 .mask_memory = intel_i810_mask_memory, 1481 .masks = intel_i810_masks, 1482 .agp_enable = intel_i810_agp_enable, 1483 .cache_flush = global_cache_flush, 1484 .create_gatt_table = agp_generic_create_gatt_table, 1485 .free_gatt_table = agp_generic_free_gatt_table, 1486 .insert_memory = intel_i810_insert_entries, 1487 .remove_memory = intel_i810_remove_entries, 1488 .alloc_by_type = intel_i810_alloc_by_type, 1489 .free_by_type = intel_i810_free_by_type, 1490 .agp_alloc_page = agp_generic_alloc_page, 1491 .agp_destroy_page = agp_generic_destroy_page, 1492 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1493}; 1494 1495static const struct agp_bridge_driver intel_815_driver = { 1496 .owner = THIS_MODULE, 1497 .aperture_sizes = intel_815_sizes, 1498 .size_type = U8_APER_SIZE, 1499 .num_aperture_sizes = 2, 1500 .configure = intel_815_configure, 1501 .fetch_size = intel_815_fetch_size, 1502 .cleanup = intel_8xx_cleanup, 1503 .tlb_flush = intel_8xx_tlbflush, 1504 .mask_memory = agp_generic_mask_memory, 1505 .masks = intel_generic_masks, 1506 .agp_enable = agp_generic_enable, 1507 .cache_flush = global_cache_flush, 1508 .create_gatt_table = agp_generic_create_gatt_table, 1509 .free_gatt_table = agp_generic_free_gatt_table, 1510 .insert_memory = agp_generic_insert_memory, 1511 .remove_memory = agp_generic_remove_memory, 1512 .alloc_by_type = agp_generic_alloc_by_type, 1513 .free_by_type = agp_generic_free_by_type, 1514 .agp_alloc_page = agp_generic_alloc_page, 1515 .agp_destroy_page = agp_generic_destroy_page, 1516 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1517}; 1518 1519static const struct agp_bridge_driver intel_830_driver = { 1520 .owner = THIS_MODULE, 1521 .aperture_sizes = intel_i830_sizes, 1522 .size_type = FIXED_APER_SIZE, 1523 .num_aperture_sizes = 4, 1524 .needs_scratch_page = TRUE, 1525 .configure = intel_i830_configure, 1526 .fetch_size = intel_i830_fetch_size, 1527 .cleanup = intel_i830_cleanup, 1528 .tlb_flush = intel_i810_tlbflush, 1529 .mask_memory = intel_i810_mask_memory, 1530 .masks = intel_i810_masks, 1531 .agp_enable = intel_i810_agp_enable, 1532 .cache_flush = global_cache_flush, 1533 .create_gatt_table = intel_i830_create_gatt_table, 1534 .free_gatt_table = intel_i830_free_gatt_table, 1535 .insert_memory = intel_i830_insert_entries, 1536 .remove_memory = intel_i830_remove_entries, 1537 .alloc_by_type = intel_i830_alloc_by_type, 1538 .free_by_type = intel_i810_free_by_type, 1539 .agp_alloc_page = agp_generic_alloc_page, 1540 .agp_destroy_page = agp_generic_destroy_page, 1541 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1542}; 1543 1544static const struct agp_bridge_driver intel_820_driver = { 1545 .owner = THIS_MODULE, 1546 .aperture_sizes = intel_8xx_sizes, 1547 .size_type = U8_APER_SIZE, 1548 .num_aperture_sizes = 7, 1549 .configure = intel_820_configure, 1550 .fetch_size = intel_8xx_fetch_size, 1551 .cleanup = intel_820_cleanup, 1552 .tlb_flush = intel_820_tlbflush, 1553 .mask_memory = agp_generic_mask_memory, 1554 .masks = intel_generic_masks, 1555 .agp_enable = agp_generic_enable, 1556 .cache_flush = global_cache_flush, 1557 .create_gatt_table = agp_generic_create_gatt_table, 1558 .free_gatt_table = agp_generic_free_gatt_table, 1559 .insert_memory = agp_generic_insert_memory, 1560 .remove_memory = agp_generic_remove_memory, 1561 .alloc_by_type = agp_generic_alloc_by_type, 1562 .free_by_type = agp_generic_free_by_type, 1563 .agp_alloc_page = agp_generic_alloc_page, 1564 .agp_destroy_page = agp_generic_destroy_page, 1565 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1566}; 1567 1568static const struct agp_bridge_driver intel_830mp_driver = { 1569 .owner = THIS_MODULE, 1570 .aperture_sizes = intel_830mp_sizes, 1571 .size_type = U8_APER_SIZE, 1572 .num_aperture_sizes = 4, 1573 .configure = intel_830mp_configure, 1574 .fetch_size = intel_8xx_fetch_size, 1575 .cleanup = intel_8xx_cleanup, 1576 .tlb_flush = intel_8xx_tlbflush, 1577 .mask_memory = agp_generic_mask_memory, 1578 .masks = intel_generic_masks, 1579 .agp_enable = agp_generic_enable, 1580 .cache_flush = global_cache_flush, 1581 .create_gatt_table = agp_generic_create_gatt_table, 1582 .free_gatt_table = agp_generic_free_gatt_table, 1583 .insert_memory = agp_generic_insert_memory, 1584 .remove_memory = agp_generic_remove_memory, 1585 .alloc_by_type = agp_generic_alloc_by_type, 1586 .free_by_type = agp_generic_free_by_type, 1587 .agp_alloc_page = agp_generic_alloc_page, 1588 .agp_destroy_page = agp_generic_destroy_page, 1589 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1590}; 1591 1592static const struct agp_bridge_driver intel_840_driver = { 1593 .owner = THIS_MODULE, 1594 .aperture_sizes = intel_8xx_sizes, 1595 .size_type = U8_APER_SIZE, 1596 .num_aperture_sizes = 7, 1597 .configure = intel_840_configure, 1598 .fetch_size = intel_8xx_fetch_size, 1599 .cleanup = intel_8xx_cleanup, 1600 .tlb_flush = intel_8xx_tlbflush, 1601 .mask_memory = agp_generic_mask_memory, 1602 .masks = intel_generic_masks, 1603 .agp_enable = agp_generic_enable, 1604 .cache_flush = global_cache_flush, 1605 .create_gatt_table = agp_generic_create_gatt_table, 1606 .free_gatt_table = agp_generic_free_gatt_table, 1607 .insert_memory = agp_generic_insert_memory, 1608 .remove_memory = agp_generic_remove_memory, 1609 .alloc_by_type = agp_generic_alloc_by_type, 1610 .free_by_type = agp_generic_free_by_type, 1611 .agp_alloc_page = agp_generic_alloc_page, 1612 .agp_destroy_page = agp_generic_destroy_page, 1613 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1614}; 1615 1616static const struct agp_bridge_driver intel_845_driver = { 1617 .owner = THIS_MODULE, 1618 .aperture_sizes = intel_8xx_sizes, 1619 .size_type = U8_APER_SIZE, 1620 .num_aperture_sizes = 7, 1621 .configure = intel_845_configure, 1622 .fetch_size = intel_8xx_fetch_size, 1623 .cleanup = intel_8xx_cleanup, 1624 .tlb_flush = intel_8xx_tlbflush, 1625 .mask_memory = agp_generic_mask_memory, 1626 .masks = intel_generic_masks, 1627 .agp_enable = agp_generic_enable, 1628 .cache_flush = global_cache_flush, 1629 .create_gatt_table = agp_generic_create_gatt_table, 1630 .free_gatt_table = agp_generic_free_gatt_table, 1631 .insert_memory = agp_generic_insert_memory, 1632 .remove_memory = agp_generic_remove_memory, 1633 .alloc_by_type = agp_generic_alloc_by_type, 1634 .free_by_type = agp_generic_free_by_type, 1635 .agp_alloc_page = agp_generic_alloc_page, 1636 .agp_destroy_page = agp_generic_destroy_page, 1637 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1638}; 1639 1640static const struct agp_bridge_driver intel_850_driver = { 1641 .owner = THIS_MODULE, 1642 .aperture_sizes = intel_8xx_sizes, 1643 .size_type = U8_APER_SIZE, 1644 .num_aperture_sizes = 7, 1645 .configure = intel_850_configure, 1646 .fetch_size = intel_8xx_fetch_size, 1647 .cleanup = intel_8xx_cleanup, 1648 .tlb_flush = intel_8xx_tlbflush, 1649 .mask_memory = agp_generic_mask_memory, 1650 .masks = intel_generic_masks, 1651 .agp_enable = agp_generic_enable, 1652 .cache_flush = global_cache_flush, 1653 .create_gatt_table = agp_generic_create_gatt_table, 1654 .free_gatt_table = agp_generic_free_gatt_table, 1655 .insert_memory = agp_generic_insert_memory, 1656 .remove_memory = agp_generic_remove_memory, 1657 .alloc_by_type = agp_generic_alloc_by_type, 1658 .free_by_type = agp_generic_free_by_type, 1659 .agp_alloc_page = agp_generic_alloc_page, 1660 .agp_destroy_page = agp_generic_destroy_page, 1661 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1662}; 1663 1664static const struct agp_bridge_driver intel_860_driver = { 1665 .owner = THIS_MODULE, 1666 .aperture_sizes = intel_8xx_sizes, 1667 .size_type = U8_APER_SIZE, 1668 .num_aperture_sizes = 7, 1669 .configure = intel_860_configure, 1670 .fetch_size = intel_8xx_fetch_size, 1671 .cleanup = intel_8xx_cleanup, 1672 .tlb_flush = intel_8xx_tlbflush, 1673 .mask_memory = agp_generic_mask_memory, 1674 .masks = intel_generic_masks, 1675 .agp_enable = agp_generic_enable, 1676 .cache_flush = global_cache_flush, 1677 .create_gatt_table = agp_generic_create_gatt_table, 1678 .free_gatt_table = agp_generic_free_gatt_table, 1679 .insert_memory = agp_generic_insert_memory, 1680 .remove_memory = agp_generic_remove_memory, 1681 .alloc_by_type = agp_generic_alloc_by_type, 1682 .free_by_type = agp_generic_free_by_type, 1683 .agp_alloc_page = agp_generic_alloc_page, 1684 .agp_destroy_page = agp_generic_destroy_page, 1685 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1686}; 1687 1688static const struct agp_bridge_driver intel_915_driver = { 1689 .owner = THIS_MODULE, 1690 .aperture_sizes = intel_i830_sizes, 1691 .size_type = FIXED_APER_SIZE, 1692 .num_aperture_sizes = 4, 1693 .needs_scratch_page = TRUE, 1694 .configure = intel_i915_configure, 1695 .fetch_size = intel_i9xx_fetch_size, 1696 .cleanup = intel_i915_cleanup, 1697 .tlb_flush = intel_i810_tlbflush, 1698 .mask_memory = intel_i810_mask_memory, 1699 .masks = intel_i810_masks, 1700 .agp_enable = intel_i810_agp_enable, 1701 .cache_flush = global_cache_flush, 1702 .create_gatt_table = intel_i915_create_gatt_table, 1703 .free_gatt_table = intel_i830_free_gatt_table, 1704 .insert_memory = intel_i915_insert_entries, 1705 .remove_memory = intel_i915_remove_entries, 1706 .alloc_by_type = intel_i830_alloc_by_type, 1707 .free_by_type = intel_i810_free_by_type, 1708 .agp_alloc_page = agp_generic_alloc_page, 1709 .agp_destroy_page = agp_generic_destroy_page, 1710 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1711}; 1712 1713static const struct agp_bridge_driver intel_i965_driver = { 1714 .owner = THIS_MODULE, 1715 .aperture_sizes = intel_i830_sizes, 1716 .size_type = FIXED_APER_SIZE, 1717 .num_aperture_sizes = 4, 1718 .needs_scratch_page = TRUE, 1719 .configure = intel_i915_configure, 1720 .fetch_size = intel_i9xx_fetch_size, 1721 .cleanup = intel_i915_cleanup, 1722 .tlb_flush = intel_i810_tlbflush, 1723 .mask_memory = intel_i965_mask_memory, 1724 .masks = intel_i810_masks, 1725 .agp_enable = intel_i810_agp_enable, 1726 .cache_flush = global_cache_flush, 1727 .create_gatt_table = intel_i965_create_gatt_table, 1728 .free_gatt_table = intel_i830_free_gatt_table, 1729 .insert_memory = intel_i915_insert_entries, 1730 .remove_memory = intel_i915_remove_entries, 1731 .alloc_by_type = intel_i830_alloc_by_type, 1732 .free_by_type = intel_i810_free_by_type, 1733 .agp_alloc_page = agp_generic_alloc_page, 1734 .agp_destroy_page = agp_generic_destroy_page, 1735 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1736}; 1737 1738static const struct agp_bridge_driver intel_7505_driver = { 1739 .owner = THIS_MODULE, 1740 .aperture_sizes = intel_8xx_sizes, 1741 .size_type = U8_APER_SIZE, 1742 .num_aperture_sizes = 7, 1743 .configure = intel_7505_configure, 1744 .fetch_size = intel_8xx_fetch_size, 1745 .cleanup = intel_8xx_cleanup, 1746 .tlb_flush = intel_8xx_tlbflush, 1747 .mask_memory = agp_generic_mask_memory, 1748 .masks = intel_generic_masks, 1749 .agp_enable = agp_generic_enable, 1750 .cache_flush = global_cache_flush, 1751 .create_gatt_table = agp_generic_create_gatt_table, 1752 .free_gatt_table = agp_generic_free_gatt_table, 1753 .insert_memory = agp_generic_insert_memory, 1754 .remove_memory = agp_generic_remove_memory, 1755 .alloc_by_type = agp_generic_alloc_by_type, 1756 .free_by_type = agp_generic_free_by_type, 1757 .agp_alloc_page = agp_generic_alloc_page, 1758 .agp_destroy_page = agp_generic_destroy_page, 1759 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1760}; 1761 1762static const struct agp_bridge_driver intel_g33_driver = { 1763 .owner = THIS_MODULE, 1764 .aperture_sizes = intel_i830_sizes, 1765 .size_type = FIXED_APER_SIZE, 1766 .num_aperture_sizes = 4, 1767 .needs_scratch_page = TRUE, 1768 .configure = intel_i915_configure, 1769 .fetch_size = intel_i9xx_fetch_size, 1770 .cleanup = intel_i915_cleanup, 1771 .tlb_flush = intel_i810_tlbflush, 1772 .mask_memory = intel_i965_mask_memory, 1773 .masks = intel_i810_masks, 1774 .agp_enable = intel_i810_agp_enable, 1775 .cache_flush = global_cache_flush, 1776 .create_gatt_table = intel_i915_create_gatt_table, 1777 .free_gatt_table = intel_i830_free_gatt_table, 1778 .insert_memory = intel_i915_insert_entries, 1779 .remove_memory = intel_i915_remove_entries, 1780 .alloc_by_type = intel_i830_alloc_by_type, 1781 .free_by_type = intel_i810_free_by_type, 1782 .agp_alloc_page = agp_generic_alloc_page, 1783 .agp_destroy_page = agp_generic_destroy_page, 1784 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1785}; 1786 1787static int find_gmch(u16 device) 1788{ 1789 struct pci_dev *gmch_device; 1790 1791 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1792 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1793 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1794 device, gmch_device); 1795 } 1796 1797 if (!gmch_device) 1798 return 0; 1799 1800 intel_private.pcidev = gmch_device; 1801 return 1; 1802} 1803 1804/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1805 * driver and gmch_driver must be non-null, and find_gmch will determine 1806 * which one should be used if a gmch_chip_id is present. 1807 */ 1808static const struct intel_driver_description { 1809 unsigned int chip_id; 1810 unsigned int gmch_chip_id; 1811 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 1812 char *name; 1813 const struct agp_bridge_driver *driver; 1814 const struct agp_bridge_driver *gmch_driver; 1815} intel_agp_chipsets[] = { 1816 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 1817 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 1818 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 1819 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 1820 NULL, &intel_810_driver }, 1821 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 1822 NULL, &intel_810_driver }, 1823 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 1824 NULL, &intel_810_driver }, 1825 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 1826 &intel_815_driver, &intel_810_driver }, 1827 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 1828 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 1829 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 1830 &intel_830mp_driver, &intel_830_driver }, 1831 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 1832 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 1833 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 1834 &intel_845_driver, &intel_830_driver }, 1835 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 1836 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 1837 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 1838 &intel_845_driver, &intel_830_driver }, 1839 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 1840 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 1841 &intel_845_driver, &intel_830_driver }, 1842 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 1843 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 1844 NULL, &intel_915_driver }, 1845 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 1846 NULL, &intel_915_driver }, 1847 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 1848 NULL, &intel_915_driver }, 1849 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 1, "945GM", 1850 NULL, &intel_915_driver }, 1851 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 1852 NULL, &intel_915_driver }, 1853 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 1854 NULL, &intel_i965_driver }, 1855 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G", 1856 NULL, &intel_i965_driver }, 1857 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 1858 NULL, &intel_i965_driver }, 1859 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 1860 NULL, &intel_i965_driver }, 1861 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 1, "965GM", 1862 NULL, &intel_i965_driver }, 1863 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 1864 NULL, &intel_i965_driver }, 1865 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 1866 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 1867 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 1868 NULL, &intel_g33_driver }, 1869 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 1870 NULL, &intel_g33_driver }, 1871 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 1872 NULL, &intel_g33_driver }, 1873 { 0, 0, 0, NULL, NULL, NULL } 1874}; 1875 1876static int __devinit agp_intel_probe(struct pci_dev *pdev, 1877 const struct pci_device_id *ent) 1878{ 1879 struct agp_bridge_data *bridge; 1880 u8 cap_ptr = 0; 1881 struct resource *r; 1882 int i; 1883 1884 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1885 1886 bridge = agp_alloc_bridge(); 1887 if (!bridge) 1888 return -ENOMEM; 1889 1890 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 1891 /* In case that multiple models of gfx chip may 1892 stand on same host bridge type, this can be 1893 sure we detect the right IGD. */ 1894 if (pdev->device == intel_agp_chipsets[i].chip_id) { 1895 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 1896 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 1897 bridge->driver = 1898 intel_agp_chipsets[i].gmch_driver; 1899 break; 1900 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 1901 continue; 1902 } else { 1903 bridge->driver = intel_agp_chipsets[i].driver; 1904 break; 1905 } 1906 } 1907 } 1908 1909 if (intel_agp_chipsets[i].name == NULL) { 1910 if (cap_ptr) 1911 printk(KERN_WARNING PFX "Unsupported Intel chipset" 1912 "(device id: %04x)\n", pdev->device); 1913 agp_put_bridge(bridge); 1914 return -ENODEV; 1915 } 1916 1917 if (bridge->driver == NULL) { 1918 /* bridge has no AGP and no IGD detected */ 1919 if (cap_ptr) 1920 printk(KERN_WARNING PFX "Failed to find bridge device " 1921 "(chip_id: %04x)\n", 1922 intel_agp_chipsets[i].gmch_chip_id); 1923 agp_put_bridge(bridge); 1924 return -ENODEV; 1925 } 1926 1927 bridge->dev = pdev; 1928 bridge->capndx = cap_ptr; 1929 bridge->dev_private_data = &intel_private; 1930 1931 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", 1932 intel_agp_chipsets[i].name); 1933 1934 /* 1935 * The following fixes the case where the BIOS has "forgotten" to 1936 * provide an address range for the GART. 1937 * 20030610 - hamish@zot.org 1938 */ 1939 r = &pdev->resource[0]; 1940 if (!r->start && r->end) { 1941 if (pci_assign_resource(pdev, 0)) { 1942 printk(KERN_ERR PFX "could not assign resource 0\n"); 1943 agp_put_bridge(bridge); 1944 return -ENODEV; 1945 } 1946 } 1947 1948 /* 1949 * If the device has not been properly setup, the following will catch 1950 * the problem and should stop the system from crashing. 1951 * 20030610 - hamish@zot.org 1952 */ 1953 if (pci_enable_device(pdev)) { 1954 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1955 agp_put_bridge(bridge); 1956 return -ENODEV; 1957 } 1958 1959 /* Fill in the mode register */ 1960 if (cap_ptr) { 1961 pci_read_config_dword(pdev, 1962 bridge->capndx+PCI_AGP_STATUS, 1963 &bridge->mode); 1964 } 1965 1966 pci_set_drvdata(pdev, bridge); 1967 return agp_add_bridge(bridge); 1968} 1969 1970static void __devexit agp_intel_remove(struct pci_dev *pdev) 1971{ 1972 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1973 1974 agp_remove_bridge(bridge); 1975 1976 if (intel_private.pcidev) 1977 pci_dev_put(intel_private.pcidev); 1978 1979 agp_put_bridge(bridge); 1980} 1981 1982#ifdef CONFIG_PM 1983static int agp_intel_resume(struct pci_dev *pdev) 1984{ 1985 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1986 1987 pci_restore_state(pdev); 1988 1989 /* We should restore our graphics device's config space, 1990 * as host bridge (00:00) resumes before graphics device (02:00), 1991 * then our access to its pci space can work right. 1992 */ 1993 if (intel_private.pcidev) 1994 pci_restore_state(intel_private.pcidev); 1995 1996 if (bridge->driver == &intel_generic_driver) 1997 intel_configure(); 1998 else if (bridge->driver == &intel_850_driver) 1999 intel_850_configure(); 2000 else if (bridge->driver == &intel_845_driver) 2001 intel_845_configure(); 2002 else if (bridge->driver == &intel_830mp_driver) 2003 intel_830mp_configure(); 2004 else if (bridge->driver == &intel_915_driver) 2005 intel_i915_configure(); 2006 else if (bridge->driver == &intel_830_driver) 2007 intel_i830_configure(); 2008 else if (bridge->driver == &intel_810_driver) 2009 intel_i810_configure(); 2010 else if (bridge->driver == &intel_i965_driver) 2011 intel_i915_configure(); 2012 2013 return 0; 2014} 2015#endif 2016 2017static struct pci_device_id agp_intel_pci_table[] = { 2018#define ID(x) \ 2019 { \ 2020 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2021 .class_mask = ~0, \ 2022 .vendor = PCI_VENDOR_ID_INTEL, \ 2023 .device = x, \ 2024 .subvendor = PCI_ANY_ID, \ 2025 .subdevice = PCI_ANY_ID, \ 2026 } 2027 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2028 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2029 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2030 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2031 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2032 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2033 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2034 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2035 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2036 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2037 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2038 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2039 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2040 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2041 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2042 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2043 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2044 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2045 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2046 ID(PCI_DEVICE_ID_INTEL_7505_0), 2047 ID(PCI_DEVICE_ID_INTEL_7205_0), 2048 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2049 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2050 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2051 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2052 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2053 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB), 2054 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2055 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2056 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2057 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2058 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2059 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2060 { } 2061}; 2062 2063MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2064 2065static struct pci_driver agp_intel_pci_driver = { 2066 .name = "agpgart-intel", 2067 .id_table = agp_intel_pci_table, 2068 .probe = agp_intel_probe, 2069 .remove = __devexit_p(agp_intel_remove), 2070#ifdef CONFIG_PM 2071 .resume = agp_intel_resume, 2072#endif 2073}; 2074 2075static int __init agp_intel_init(void) 2076{ 2077 if (agp_off) 2078 return -EINVAL; 2079 return pci_register_driver(&agp_intel_pci_driver); 2080} 2081 2082static void __exit agp_intel_cleanup(void) 2083{ 2084 pci_unregister_driver(&agp_intel_pci_driver); 2085} 2086 2087module_init(agp_intel_init); 2088module_exit(agp_intel_cleanup); 2089 2090MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 2091MODULE_LICENSE("GPL and additional rights"); 2092