intel-agp.c revision a8c84df9f71e4a7b14bdd41687a70d366c087eef
1/* 2 * Intel AGPGART routines. 3 */ 4 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/init.h> 8#include <linux/kernel.h> 9#include <linux/pagemap.h> 10#include <linux/agp_backend.h> 11#include "agp.h" 12 13#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 15#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 17#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 19#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 23#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 25#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 26#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 27#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC 28#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 29#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 30#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 31#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 32#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 33#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 35#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 36#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 37#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 43 44/* cover 915 and 945 variants */ 45#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 46 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 51 52#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 53 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 54 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ 56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ 57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \ 58 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB) 59 60#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 63 64#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ 65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB) 67 68extern int agp_memory_reserved; 69 70 71/* Intel 815 register */ 72#define INTEL_815_APCONT 0x51 73#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 74 75/* Intel i820 registers */ 76#define INTEL_I820_RDCR 0x51 77#define INTEL_I820_ERRSTS 0xc8 78 79/* Intel i840 registers */ 80#define INTEL_I840_MCHCFG 0x50 81#define INTEL_I840_ERRSTS 0xc8 82 83/* Intel i850 registers */ 84#define INTEL_I850_MCHCFG 0x50 85#define INTEL_I850_ERRSTS 0xc8 86 87/* intel 915G registers */ 88#define I915_GMADDR 0x18 89#define I915_MMADDR 0x10 90#define I915_PTEADDR 0x1C 91#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 92#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 93#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 94#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 95#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 96#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 97#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 98#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 99 100#define I915_IFPADDR 0x60 101 102/* Intel 965G registers */ 103#define I965_MSAC 0x62 104#define I965_IFPADDR 0x70 105 106/* Intel 7505 registers */ 107#define INTEL_I7505_APSIZE 0x74 108#define INTEL_I7505_NCAPID 0x60 109#define INTEL_I7505_NISTAT 0x6c 110#define INTEL_I7505_ATTBASE 0x78 111#define INTEL_I7505_ERRSTS 0x42 112#define INTEL_I7505_AGPCTRL 0x70 113#define INTEL_I7505_MCHCFG 0x50 114 115static const struct aper_size_info_fixed intel_i810_sizes[] = 116{ 117 {64, 16384, 4}, 118 /* The 32M mode still requires a 64k gatt */ 119 {32, 8192, 4} 120}; 121 122#define AGP_DCACHE_MEMORY 1 123#define AGP_PHYS_MEMORY 2 124#define INTEL_AGP_CACHED_MEMORY 3 125 126static struct gatt_mask intel_i810_masks[] = 127{ 128 {.mask = I810_PTE_VALID, .type = 0}, 129 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 130 {.mask = I810_PTE_VALID, .type = 0}, 131 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 132 .type = INTEL_AGP_CACHED_MEMORY} 133}; 134 135static struct _intel_private { 136 struct pci_dev *pcidev; /* device one */ 137 u8 __iomem *registers; 138 u32 __iomem *gtt; /* I915G */ 139 int num_dcache_entries; 140 /* gtt_entries is the number of gtt entries that are already mapped 141 * to stolen memory. Stolen memory is larger than the memory mapped 142 * through gtt_entries, as it includes some reserved space for the BIOS 143 * popup and for the GTT. 144 */ 145 int gtt_entries; /* i830+ */ 146 union { 147 void __iomem *i9xx_flush_page; 148 void *i8xx_flush_page; 149 }; 150 struct page *i8xx_page; 151 struct resource ifp_resource; 152 int resource_valid; 153} intel_private; 154 155static int intel_i810_fetch_size(void) 156{ 157 u32 smram_miscc; 158 struct aper_size_info_fixed *values; 159 160 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 161 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 162 163 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 164 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 165 return 0; 166 } 167 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 168 agp_bridge->previous_size = 169 agp_bridge->current_size = (void *) (values + 1); 170 agp_bridge->aperture_size_idx = 1; 171 return values[1].size; 172 } else { 173 agp_bridge->previous_size = 174 agp_bridge->current_size = (void *) (values); 175 agp_bridge->aperture_size_idx = 0; 176 return values[0].size; 177 } 178 179 return 0; 180} 181 182static int intel_i810_configure(void) 183{ 184 struct aper_size_info_fixed *current_size; 185 u32 temp; 186 int i; 187 188 current_size = A_SIZE_FIX(agp_bridge->current_size); 189 190 if (!intel_private.registers) { 191 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 192 temp &= 0xfff80000; 193 194 intel_private.registers = ioremap(temp, 128 * 4096); 195 if (!intel_private.registers) { 196 dev_err(&intel_private.pcidev->dev, 197 "can't remap memory\n"); 198 return -ENOMEM; 199 } 200 } 201 202 if ((readl(intel_private.registers+I810_DRAM_CTL) 203 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 204 /* This will need to be dynamically assigned */ 205 dev_info(&intel_private.pcidev->dev, 206 "detected 4MB dedicated video ram\n"); 207 intel_private.num_dcache_entries = 1024; 208 } 209 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 210 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 211 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 212 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 213 214 if (agp_bridge->driver->needs_scratch_page) { 215 for (i = 0; i < current_size->num_entries; i++) { 216 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 217 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 218 } 219 } 220 global_cache_flush(); 221 return 0; 222} 223 224static void intel_i810_cleanup(void) 225{ 226 writel(0, intel_private.registers+I810_PGETBL_CTL); 227 readl(intel_private.registers); /* PCI Posting. */ 228 iounmap(intel_private.registers); 229} 230 231static void intel_i810_tlbflush(struct agp_memory *mem) 232{ 233 return; 234} 235 236static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 237{ 238 return; 239} 240 241/* Exists to support ARGB cursors */ 242static void *i8xx_alloc_pages(void) 243{ 244 struct page *page; 245 246 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 247 if (page == NULL) 248 return NULL; 249 250 if (set_pages_uc(page, 4) < 0) { 251 set_pages_wb(page, 4); 252 __free_pages(page, 2); 253 return NULL; 254 } 255 get_page(page); 256 atomic_inc(&agp_bridge->current_memory_agp); 257 return page_address(page); 258} 259 260static void i8xx_destroy_pages(void *addr) 261{ 262 struct page *page; 263 264 if (addr == NULL) 265 return; 266 267 page = virt_to_page(addr); 268 set_pages_wb(page, 4); 269 put_page(page); 270 __free_pages(page, 2); 271 atomic_dec(&agp_bridge->current_memory_agp); 272} 273 274static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 275 int type) 276{ 277 if (type < AGP_USER_TYPES) 278 return type; 279 else if (type == AGP_USER_CACHED_MEMORY) 280 return INTEL_AGP_CACHED_MEMORY; 281 else 282 return 0; 283} 284 285static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 286 int type) 287{ 288 int i, j, num_entries; 289 void *temp; 290 int ret = -EINVAL; 291 int mask_type; 292 293 if (mem->page_count == 0) 294 goto out; 295 296 temp = agp_bridge->current_size; 297 num_entries = A_SIZE_FIX(temp)->num_entries; 298 299 if ((pg_start + mem->page_count) > num_entries) 300 goto out_err; 301 302 303 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 304 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 305 ret = -EBUSY; 306 goto out_err; 307 } 308 } 309 310 if (type != mem->type) 311 goto out_err; 312 313 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 314 315 switch (mask_type) { 316 case AGP_DCACHE_MEMORY: 317 if (!mem->is_flushed) 318 global_cache_flush(); 319 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 320 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 321 intel_private.registers+I810_PTE_BASE+(i*4)); 322 } 323 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 324 break; 325 case AGP_PHYS_MEMORY: 326 case AGP_NORMAL_MEMORY: 327 if (!mem->is_flushed) 328 global_cache_flush(); 329 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 330 writel(agp_bridge->driver->mask_memory(agp_bridge, 331 mem->memory[i], 332 mask_type), 333 intel_private.registers+I810_PTE_BASE+(j*4)); 334 } 335 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 336 break; 337 default: 338 goto out_err; 339 } 340 341 agp_bridge->driver->tlb_flush(mem); 342out: 343 ret = 0; 344out_err: 345 mem->is_flushed = true; 346 return ret; 347} 348 349static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 350 int type) 351{ 352 int i; 353 354 if (mem->page_count == 0) 355 return 0; 356 357 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 358 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 359 } 360 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 361 362 agp_bridge->driver->tlb_flush(mem); 363 return 0; 364} 365 366/* 367 * The i810/i830 requires a physical address to program its mouse 368 * pointer into hardware. 369 * However the Xserver still writes to it through the agp aperture. 370 */ 371static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 372{ 373 struct agp_memory *new; 374 void *addr; 375 376 switch (pg_count) { 377 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 378 break; 379 case 4: 380 /* kludge to get 4 physical pages for ARGB cursor */ 381 addr = i8xx_alloc_pages(); 382 break; 383 default: 384 return NULL; 385 } 386 387 if (addr == NULL) 388 return NULL; 389 390 new = agp_create_memory(pg_count); 391 if (new == NULL) 392 return NULL; 393 394 new->memory[0] = virt_to_gart(addr); 395 if (pg_count == 4) { 396 /* kludge to get 4 physical pages for ARGB cursor */ 397 new->memory[1] = new->memory[0] + PAGE_SIZE; 398 new->memory[2] = new->memory[1] + PAGE_SIZE; 399 new->memory[3] = new->memory[2] + PAGE_SIZE; 400 } 401 new->page_count = pg_count; 402 new->num_scratch_pages = pg_count; 403 new->type = AGP_PHYS_MEMORY; 404 new->physical = new->memory[0]; 405 return new; 406} 407 408static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 409{ 410 struct agp_memory *new; 411 412 if (type == AGP_DCACHE_MEMORY) { 413 if (pg_count != intel_private.num_dcache_entries) 414 return NULL; 415 416 new = agp_create_memory(1); 417 if (new == NULL) 418 return NULL; 419 420 new->type = AGP_DCACHE_MEMORY; 421 new->page_count = pg_count; 422 new->num_scratch_pages = 0; 423 agp_free_page_array(new); 424 return new; 425 } 426 if (type == AGP_PHYS_MEMORY) 427 return alloc_agpphysmem_i8xx(pg_count, type); 428 return NULL; 429} 430 431static void intel_i810_free_by_type(struct agp_memory *curr) 432{ 433 agp_free_key(curr->key); 434 if (curr->type == AGP_PHYS_MEMORY) { 435 if (curr->page_count == 4) 436 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 437 else { 438 void *va = gart_to_virt(curr->memory[0]); 439 440 agp_bridge->driver->agp_destroy_page(va, 441 AGP_PAGE_DESTROY_UNMAP); 442 agp_bridge->driver->agp_destroy_page(va, 443 AGP_PAGE_DESTROY_FREE); 444 } 445 agp_free_page_array(curr); 446 } 447 kfree(curr); 448} 449 450static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 451 unsigned long addr, int type) 452{ 453 /* Type checking must be done elsewhere */ 454 return addr | bridge->driver->masks[type].mask; 455} 456 457static struct aper_size_info_fixed intel_i830_sizes[] = 458{ 459 {128, 32768, 5}, 460 /* The 64M mode still requires a 128k gatt */ 461 {64, 16384, 5}, 462 {256, 65536, 6}, 463 {512, 131072, 7}, 464}; 465 466static void intel_i830_init_gtt_entries(void) 467{ 468 u16 gmch_ctrl; 469 int gtt_entries; 470 u8 rdct; 471 int local = 0; 472 static const int ddt[4] = { 0, 16, 32, 64 }; 473 int size; /* reserved space (in kb) at the top of stolen memory */ 474 475 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 476 477 if (IS_I965) { 478 u32 pgetbl_ctl; 479 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 480 481 /* The 965 has a field telling us the size of the GTT, 482 * which may be larger than what is necessary to map the 483 * aperture. 484 */ 485 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 486 case I965_PGETBL_SIZE_128KB: 487 size = 128; 488 break; 489 case I965_PGETBL_SIZE_256KB: 490 size = 256; 491 break; 492 case I965_PGETBL_SIZE_512KB: 493 size = 512; 494 break; 495 case I965_PGETBL_SIZE_1MB: 496 size = 1024; 497 break; 498 case I965_PGETBL_SIZE_2MB: 499 size = 2048; 500 break; 501 case I965_PGETBL_SIZE_1_5MB: 502 size = 1024 + 512; 503 break; 504 default: 505 dev_info(&intel_private.pcidev->dev, 506 "unknown page table size, assuming 512KB\n"); 507 size = 512; 508 } 509 size += 4; /* add in BIOS popup space */ 510 } else if (IS_G33) { 511 /* G33's GTT size defined in gmch_ctrl */ 512 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { 513 case G33_PGETBL_SIZE_1M: 514 size = 1024; 515 break; 516 case G33_PGETBL_SIZE_2M: 517 size = 2048; 518 break; 519 default: 520 dev_info(&agp_bridge->dev->dev, 521 "unknown page table size 0x%x, assuming 512KB\n", 522 (gmch_ctrl & G33_PGETBL_SIZE_MASK)); 523 size = 512; 524 } 525 size += 4; 526 } else if (IS_G4X) { 527 /* On 4 series hardware, GTT stolen is separate from graphics 528 * stolen, ignore it in stolen gtt entries counting */ 529 size = 0; 530 } else { 531 /* On previous hardware, the GTT size was just what was 532 * required to map the aperture. 533 */ 534 size = agp_bridge->driver->fetch_size() + 4; 535 } 536 537 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 538 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 539 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 540 case I830_GMCH_GMS_STOLEN_512: 541 gtt_entries = KB(512) - KB(size); 542 break; 543 case I830_GMCH_GMS_STOLEN_1024: 544 gtt_entries = MB(1) - KB(size); 545 break; 546 case I830_GMCH_GMS_STOLEN_8192: 547 gtt_entries = MB(8) - KB(size); 548 break; 549 case I830_GMCH_GMS_LOCAL: 550 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 551 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 552 MB(ddt[I830_RDRAM_DDT(rdct)]); 553 local = 1; 554 break; 555 default: 556 gtt_entries = 0; 557 break; 558 } 559 } else { 560 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 561 case I855_GMCH_GMS_STOLEN_1M: 562 gtt_entries = MB(1) - KB(size); 563 break; 564 case I855_GMCH_GMS_STOLEN_4M: 565 gtt_entries = MB(4) - KB(size); 566 break; 567 case I855_GMCH_GMS_STOLEN_8M: 568 gtt_entries = MB(8) - KB(size); 569 break; 570 case I855_GMCH_GMS_STOLEN_16M: 571 gtt_entries = MB(16) - KB(size); 572 break; 573 case I855_GMCH_GMS_STOLEN_32M: 574 gtt_entries = MB(32) - KB(size); 575 break; 576 case I915_GMCH_GMS_STOLEN_48M: 577 /* Check it's really I915G */ 578 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 579 gtt_entries = MB(48) - KB(size); 580 else 581 gtt_entries = 0; 582 break; 583 case I915_GMCH_GMS_STOLEN_64M: 584 /* Check it's really I915G */ 585 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) 586 gtt_entries = MB(64) - KB(size); 587 else 588 gtt_entries = 0; 589 break; 590 case G33_GMCH_GMS_STOLEN_128M: 591 if (IS_G33 || IS_I965 || IS_G4X) 592 gtt_entries = MB(128) - KB(size); 593 else 594 gtt_entries = 0; 595 break; 596 case G33_GMCH_GMS_STOLEN_256M: 597 if (IS_G33 || IS_I965 || IS_G4X) 598 gtt_entries = MB(256) - KB(size); 599 else 600 gtt_entries = 0; 601 break; 602 case INTEL_GMCH_GMS_STOLEN_96M: 603 if (IS_I965 || IS_G4X) 604 gtt_entries = MB(96) - KB(size); 605 else 606 gtt_entries = 0; 607 break; 608 case INTEL_GMCH_GMS_STOLEN_160M: 609 if (IS_I965 || IS_G4X) 610 gtt_entries = MB(160) - KB(size); 611 else 612 gtt_entries = 0; 613 break; 614 case INTEL_GMCH_GMS_STOLEN_224M: 615 if (IS_I965 || IS_G4X) 616 gtt_entries = MB(224) - KB(size); 617 else 618 gtt_entries = 0; 619 break; 620 case INTEL_GMCH_GMS_STOLEN_352M: 621 if (IS_I965 || IS_G4X) 622 gtt_entries = MB(352) - KB(size); 623 else 624 gtt_entries = 0; 625 break; 626 default: 627 gtt_entries = 0; 628 break; 629 } 630 } 631 if (gtt_entries > 0) 632 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 633 gtt_entries / KB(1), local ? "local" : "stolen"); 634 else 635 dev_info(&agp_bridge->dev->dev, 636 "no pre-allocated video memory detected\n"); 637 gtt_entries /= KB(4); 638 639 intel_private.gtt_entries = gtt_entries; 640} 641 642static void intel_i830_fini_flush(void) 643{ 644 kunmap(intel_private.i8xx_page); 645 intel_private.i8xx_flush_page = NULL; 646 unmap_page_from_agp(intel_private.i8xx_page); 647 648 __free_page(intel_private.i8xx_page); 649 intel_private.i8xx_page = NULL; 650} 651 652static void intel_i830_setup_flush(void) 653{ 654 /* return if we've already set the flush mechanism up */ 655 if (intel_private.i8xx_page) 656 return; 657 658 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 659 if (!intel_private.i8xx_page) 660 return; 661 662 /* make page uncached */ 663 map_page_into_agp(intel_private.i8xx_page); 664 665 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 666 if (!intel_private.i8xx_flush_page) 667 intel_i830_fini_flush(); 668} 669 670static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 671{ 672 unsigned int *pg = intel_private.i8xx_flush_page; 673 int i; 674 675 for (i = 0; i < 256; i += 2) 676 *(pg + i) = i; 677 678 wmb(); 679} 680 681/* The intel i830 automatically initializes the agp aperture during POST. 682 * Use the memory already set aside for in the GTT. 683 */ 684static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 685{ 686 int page_order; 687 struct aper_size_info_fixed *size; 688 int num_entries; 689 u32 temp; 690 691 size = agp_bridge->current_size; 692 page_order = size->page_order; 693 num_entries = size->num_entries; 694 agp_bridge->gatt_table_real = NULL; 695 696 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 697 temp &= 0xfff80000; 698 699 intel_private.registers = ioremap(temp, 128 * 4096); 700 if (!intel_private.registers) 701 return -ENOMEM; 702 703 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 704 global_cache_flush(); /* FIXME: ?? */ 705 706 /* we have to call this as early as possible after the MMIO base address is known */ 707 intel_i830_init_gtt_entries(); 708 709 agp_bridge->gatt_table = NULL; 710 711 agp_bridge->gatt_bus_addr = temp; 712 713 return 0; 714} 715 716/* Return the gatt table to a sane state. Use the top of stolen 717 * memory for the GTT. 718 */ 719static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 720{ 721 return 0; 722} 723 724static int intel_i830_fetch_size(void) 725{ 726 u16 gmch_ctrl; 727 struct aper_size_info_fixed *values; 728 729 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 730 731 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 732 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 733 /* 855GM/852GM/865G has 128MB aperture size */ 734 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 735 agp_bridge->aperture_size_idx = 0; 736 return values[0].size; 737 } 738 739 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 740 741 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 742 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 743 agp_bridge->aperture_size_idx = 0; 744 return values[0].size; 745 } else { 746 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 747 agp_bridge->aperture_size_idx = 1; 748 return values[1].size; 749 } 750 751 return 0; 752} 753 754static int intel_i830_configure(void) 755{ 756 struct aper_size_info_fixed *current_size; 757 u32 temp; 758 u16 gmch_ctrl; 759 int i; 760 761 current_size = A_SIZE_FIX(agp_bridge->current_size); 762 763 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 764 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 765 766 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 767 gmch_ctrl |= I830_GMCH_ENABLED; 768 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 769 770 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 771 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 772 773 if (agp_bridge->driver->needs_scratch_page) { 774 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 775 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 776 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 777 } 778 } 779 780 global_cache_flush(); 781 782 intel_i830_setup_flush(); 783 return 0; 784} 785 786static void intel_i830_cleanup(void) 787{ 788 iounmap(intel_private.registers); 789} 790 791static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 792 int type) 793{ 794 int i, j, num_entries; 795 void *temp; 796 int ret = -EINVAL; 797 int mask_type; 798 799 if (mem->page_count == 0) 800 goto out; 801 802 temp = agp_bridge->current_size; 803 num_entries = A_SIZE_FIX(temp)->num_entries; 804 805 if (pg_start < intel_private.gtt_entries) { 806 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 807 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 808 pg_start, intel_private.gtt_entries); 809 810 dev_info(&intel_private.pcidev->dev, 811 "trying to insert into local/stolen memory\n"); 812 goto out_err; 813 } 814 815 if ((pg_start + mem->page_count) > num_entries) 816 goto out_err; 817 818 /* The i830 can't check the GTT for entries since its read only, 819 * depend on the caller to make the correct offset decisions. 820 */ 821 822 if (type != mem->type) 823 goto out_err; 824 825 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 826 827 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 828 mask_type != INTEL_AGP_CACHED_MEMORY) 829 goto out_err; 830 831 if (!mem->is_flushed) 832 global_cache_flush(); 833 834 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 835 writel(agp_bridge->driver->mask_memory(agp_bridge, 836 mem->memory[i], mask_type), 837 intel_private.registers+I810_PTE_BASE+(j*4)); 838 } 839 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 840 agp_bridge->driver->tlb_flush(mem); 841 842out: 843 ret = 0; 844out_err: 845 mem->is_flushed = true; 846 return ret; 847} 848 849static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 850 int type) 851{ 852 int i; 853 854 if (mem->page_count == 0) 855 return 0; 856 857 if (pg_start < intel_private.gtt_entries) { 858 dev_info(&intel_private.pcidev->dev, 859 "trying to disable local/stolen memory\n"); 860 return -EINVAL; 861 } 862 863 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 864 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 865 } 866 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 867 868 agp_bridge->driver->tlb_flush(mem); 869 return 0; 870} 871 872static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 873{ 874 if (type == AGP_PHYS_MEMORY) 875 return alloc_agpphysmem_i8xx(pg_count, type); 876 /* always return NULL for other allocation types for now */ 877 return NULL; 878} 879 880static int intel_alloc_chipset_flush_resource(void) 881{ 882 int ret; 883 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 884 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 885 pcibios_align_resource, agp_bridge->dev); 886 887 return ret; 888} 889 890static void intel_i915_setup_chipset_flush(void) 891{ 892 int ret; 893 u32 temp; 894 895 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 896 if (!(temp & 0x1)) { 897 intel_alloc_chipset_flush_resource(); 898 intel_private.resource_valid = 1; 899 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 900 } else { 901 temp &= ~1; 902 903 intel_private.resource_valid = 1; 904 intel_private.ifp_resource.start = temp; 905 intel_private.ifp_resource.end = temp + PAGE_SIZE; 906 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 907 /* some BIOSes reserve this area in a pnp some don't */ 908 if (ret) 909 intel_private.resource_valid = 0; 910 } 911} 912 913static void intel_i965_g33_setup_chipset_flush(void) 914{ 915 u32 temp_hi, temp_lo; 916 int ret; 917 918 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 919 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 920 921 if (!(temp_lo & 0x1)) { 922 923 intel_alloc_chipset_flush_resource(); 924 925 intel_private.resource_valid = 1; 926 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 927 upper_32_bits(intel_private.ifp_resource.start)); 928 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 929 } else { 930 u64 l64; 931 932 temp_lo &= ~0x1; 933 l64 = ((u64)temp_hi << 32) | temp_lo; 934 935 intel_private.resource_valid = 1; 936 intel_private.ifp_resource.start = l64; 937 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 938 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 939 /* some BIOSes reserve this area in a pnp some don't */ 940 if (ret) 941 intel_private.resource_valid = 0; 942 } 943} 944 945static void intel_i9xx_setup_flush(void) 946{ 947 /* return if already configured */ 948 if (intel_private.ifp_resource.start) 949 return; 950 951 /* setup a resource for this object */ 952 intel_private.ifp_resource.name = "Intel Flush Page"; 953 intel_private.ifp_resource.flags = IORESOURCE_MEM; 954 955 /* Setup chipset flush for 915 */ 956 if (IS_I965 || IS_G33 || IS_G4X) { 957 intel_i965_g33_setup_chipset_flush(); 958 } else { 959 intel_i915_setup_chipset_flush(); 960 } 961 962 if (intel_private.ifp_resource.start) { 963 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 964 if (!intel_private.i9xx_flush_page) 965 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); 966 } 967} 968 969static int intel_i915_configure(void) 970{ 971 struct aper_size_info_fixed *current_size; 972 u32 temp; 973 u16 gmch_ctrl; 974 int i; 975 976 current_size = A_SIZE_FIX(agp_bridge->current_size); 977 978 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 979 980 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 981 982 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 983 gmch_ctrl |= I830_GMCH_ENABLED; 984 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 985 986 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 987 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 988 989 if (agp_bridge->driver->needs_scratch_page) { 990 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 991 writel(agp_bridge->scratch_page, intel_private.gtt+i); 992 readl(intel_private.gtt+i); /* PCI Posting. */ 993 } 994 } 995 996 global_cache_flush(); 997 998 intel_i9xx_setup_flush(); 999 1000 return 0; 1001} 1002 1003static void intel_i915_cleanup(void) 1004{ 1005 if (intel_private.i9xx_flush_page) 1006 iounmap(intel_private.i9xx_flush_page); 1007 if (intel_private.resource_valid) 1008 release_resource(&intel_private.ifp_resource); 1009 intel_private.ifp_resource.start = 0; 1010 intel_private.resource_valid = 0; 1011 iounmap(intel_private.gtt); 1012 iounmap(intel_private.registers); 1013} 1014 1015static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1016{ 1017 if (intel_private.i9xx_flush_page) 1018 writel(1, intel_private.i9xx_flush_page); 1019} 1020 1021static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1022 int type) 1023{ 1024 int i, j, num_entries; 1025 void *temp; 1026 int ret = -EINVAL; 1027 int mask_type; 1028 1029 if (mem->page_count == 0) 1030 goto out; 1031 1032 temp = agp_bridge->current_size; 1033 num_entries = A_SIZE_FIX(temp)->num_entries; 1034 1035 if (pg_start < intel_private.gtt_entries) { 1036 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1037 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1038 pg_start, intel_private.gtt_entries); 1039 1040 dev_info(&intel_private.pcidev->dev, 1041 "trying to insert into local/stolen memory\n"); 1042 goto out_err; 1043 } 1044 1045 if ((pg_start + mem->page_count) > num_entries) 1046 goto out_err; 1047 1048 /* The i915 can't check the GTT for entries since its read only, 1049 * depend on the caller to make the correct offset decisions. 1050 */ 1051 1052 if (type != mem->type) 1053 goto out_err; 1054 1055 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1056 1057 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1058 mask_type != INTEL_AGP_CACHED_MEMORY) 1059 goto out_err; 1060 1061 if (!mem->is_flushed) 1062 global_cache_flush(); 1063 1064 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1065 writel(agp_bridge->driver->mask_memory(agp_bridge, 1066 mem->memory[i], mask_type), intel_private.gtt+j); 1067 } 1068 1069 readl(intel_private.gtt+j-1); 1070 agp_bridge->driver->tlb_flush(mem); 1071 1072 out: 1073 ret = 0; 1074 out_err: 1075 mem->is_flushed = true; 1076 return ret; 1077} 1078 1079static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1080 int type) 1081{ 1082 int i; 1083 1084 if (mem->page_count == 0) 1085 return 0; 1086 1087 if (pg_start < intel_private.gtt_entries) { 1088 dev_info(&intel_private.pcidev->dev, 1089 "trying to disable local/stolen memory\n"); 1090 return -EINVAL; 1091 } 1092 1093 for (i = pg_start; i < (mem->page_count + pg_start); i++) 1094 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1095 1096 readl(intel_private.gtt+i-1); 1097 1098 agp_bridge->driver->tlb_flush(mem); 1099 return 0; 1100} 1101 1102/* Return the aperture size by just checking the resource length. The effect 1103 * described in the spec of the MSAC registers is just changing of the 1104 * resource size. 1105 */ 1106static int intel_i9xx_fetch_size(void) 1107{ 1108 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1109 int aper_size; /* size in megabytes */ 1110 int i; 1111 1112 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1113 1114 for (i = 0; i < num_sizes; i++) { 1115 if (aper_size == intel_i830_sizes[i].size) { 1116 agp_bridge->current_size = intel_i830_sizes + i; 1117 agp_bridge->previous_size = agp_bridge->current_size; 1118 return aper_size; 1119 } 1120 } 1121 1122 return 0; 1123} 1124 1125/* The intel i915 automatically initializes the agp aperture during POST. 1126 * Use the memory already set aside for in the GTT. 1127 */ 1128static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 1129{ 1130 int page_order; 1131 struct aper_size_info_fixed *size; 1132 int num_entries; 1133 u32 temp, temp2; 1134 int gtt_map_size = 256 * 1024; 1135 1136 size = agp_bridge->current_size; 1137 page_order = size->page_order; 1138 num_entries = size->num_entries; 1139 agp_bridge->gatt_table_real = NULL; 1140 1141 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1142 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); 1143 1144 if (IS_G33) 1145 gtt_map_size = 1024 * 1024; /* 1M on G33 */ 1146 intel_private.gtt = ioremap(temp2, gtt_map_size); 1147 if (!intel_private.gtt) 1148 return -ENOMEM; 1149 1150 temp &= 0xfff80000; 1151 1152 intel_private.registers = ioremap(temp, 128 * 4096); 1153 if (!intel_private.registers) { 1154 iounmap(intel_private.gtt); 1155 return -ENOMEM; 1156 } 1157 1158 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1159 global_cache_flush(); /* FIXME: ? */ 1160 1161 /* we have to call this as early as possible after the MMIO base address is known */ 1162 intel_i830_init_gtt_entries(); 1163 1164 agp_bridge->gatt_table = NULL; 1165 1166 agp_bridge->gatt_bus_addr = temp; 1167 1168 return 0; 1169} 1170 1171/* 1172 * The i965 supports 36-bit physical addresses, but to keep 1173 * the format of the GTT the same, the bits that don't fit 1174 * in a 32-bit word are shifted down to bits 4..7. 1175 * 1176 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1177 * is always zero on 32-bit architectures, so no need to make 1178 * this conditional. 1179 */ 1180static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1181 unsigned long addr, int type) 1182{ 1183 /* Shift high bits down */ 1184 addr |= (addr >> 28) & 0xf0; 1185 1186 /* Type checking must be done elsewhere */ 1187 return addr | bridge->driver->masks[type].mask; 1188} 1189 1190static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1191{ 1192 switch (agp_bridge->dev->device) { 1193 case PCI_DEVICE_ID_INTEL_GM45_HB: 1194 case PCI_DEVICE_ID_INTEL_IGD_E_HB: 1195 case PCI_DEVICE_ID_INTEL_Q45_HB: 1196 case PCI_DEVICE_ID_INTEL_G45_HB: 1197 *gtt_offset = *gtt_size = MB(2); 1198 break; 1199 default: 1200 *gtt_offset = *gtt_size = KB(512); 1201 } 1202} 1203 1204/* The intel i965 automatically initializes the agp aperture during POST. 1205 * Use the memory already set aside for in the GTT. 1206 */ 1207static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 1208{ 1209 int page_order; 1210 struct aper_size_info_fixed *size; 1211 int num_entries; 1212 u32 temp; 1213 int gtt_offset, gtt_size; 1214 1215 size = agp_bridge->current_size; 1216 page_order = size->page_order; 1217 num_entries = size->num_entries; 1218 agp_bridge->gatt_table_real = NULL; 1219 1220 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1221 1222 temp &= 0xfff00000; 1223 1224 intel_i965_get_gtt_range(>t_offset, >t_size); 1225 1226 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1227 1228 if (!intel_private.gtt) 1229 return -ENOMEM; 1230 1231 intel_private.registers = ioremap(temp, 128 * 4096); 1232 if (!intel_private.registers) { 1233 iounmap(intel_private.gtt); 1234 return -ENOMEM; 1235 } 1236 1237 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1238 global_cache_flush(); /* FIXME: ? */ 1239 1240 /* we have to call this as early as possible after the MMIO base address is known */ 1241 intel_i830_init_gtt_entries(); 1242 1243 agp_bridge->gatt_table = NULL; 1244 1245 agp_bridge->gatt_bus_addr = temp; 1246 1247 return 0; 1248} 1249 1250 1251static int intel_fetch_size(void) 1252{ 1253 int i; 1254 u16 temp; 1255 struct aper_size_info_16 *values; 1256 1257 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 1258 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 1259 1260 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1261 if (temp == values[i].size_value) { 1262 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 1263 agp_bridge->aperture_size_idx = i; 1264 return values[i].size; 1265 } 1266 } 1267 1268 return 0; 1269} 1270 1271static int __intel_8xx_fetch_size(u8 temp) 1272{ 1273 int i; 1274 struct aper_size_info_8 *values; 1275 1276 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 1277 1278 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 1279 if (temp == values[i].size_value) { 1280 agp_bridge->previous_size = 1281 agp_bridge->current_size = (void *) (values + i); 1282 agp_bridge->aperture_size_idx = i; 1283 return values[i].size; 1284 } 1285 } 1286 return 0; 1287} 1288 1289static int intel_8xx_fetch_size(void) 1290{ 1291 u8 temp; 1292 1293 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1294 return __intel_8xx_fetch_size(temp); 1295} 1296 1297static int intel_815_fetch_size(void) 1298{ 1299 u8 temp; 1300 1301 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1302 * one non-reserved bit, so mask the others out ... */ 1303 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1304 temp &= (1 << 3); 1305 1306 return __intel_8xx_fetch_size(temp); 1307} 1308 1309static void intel_tlbflush(struct agp_memory *mem) 1310{ 1311 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1312 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1313} 1314 1315 1316static void intel_8xx_tlbflush(struct agp_memory *mem) 1317{ 1318 u32 temp; 1319 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1320 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1321 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1322 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1323} 1324 1325 1326static void intel_cleanup(void) 1327{ 1328 u16 temp; 1329 struct aper_size_info_16 *previous_size; 1330 1331 previous_size = A_SIZE_16(agp_bridge->previous_size); 1332 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1333 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1334 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1335} 1336 1337 1338static void intel_8xx_cleanup(void) 1339{ 1340 u16 temp; 1341 struct aper_size_info_8 *previous_size; 1342 1343 previous_size = A_SIZE_8(agp_bridge->previous_size); 1344 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1345 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1346 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1347} 1348 1349 1350static int intel_configure(void) 1351{ 1352 u32 temp; 1353 u16 temp2; 1354 struct aper_size_info_16 *current_size; 1355 1356 current_size = A_SIZE_16(agp_bridge->current_size); 1357 1358 /* aperture size */ 1359 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1360 1361 /* address to map to */ 1362 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1363 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1364 1365 /* attbase - aperture base */ 1366 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1367 1368 /* agpctrl */ 1369 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1370 1371 /* paccfg/nbxcfg */ 1372 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1373 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1374 (temp2 & ~(1 << 10)) | (1 << 9)); 1375 /* clear any possible error conditions */ 1376 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1377 return 0; 1378} 1379 1380static int intel_815_configure(void) 1381{ 1382 u32 temp, addr; 1383 u8 temp2; 1384 struct aper_size_info_8 *current_size; 1385 1386 /* attbase - aperture base */ 1387 /* the Intel 815 chipset spec. says that bits 29-31 in the 1388 * ATTBASE register are reserved -> try not to write them */ 1389 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1390 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); 1391 return -EINVAL; 1392 } 1393 1394 current_size = A_SIZE_8(agp_bridge->current_size); 1395 1396 /* aperture size */ 1397 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1398 current_size->size_value); 1399 1400 /* address to map to */ 1401 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1402 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1403 1404 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1405 addr &= INTEL_815_ATTBASE_MASK; 1406 addr |= agp_bridge->gatt_bus_addr; 1407 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1408 1409 /* agpctrl */ 1410 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1411 1412 /* apcont */ 1413 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1414 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1415 1416 /* clear any possible error conditions */ 1417 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1418 return 0; 1419} 1420 1421static void intel_820_tlbflush(struct agp_memory *mem) 1422{ 1423 return; 1424} 1425 1426static void intel_820_cleanup(void) 1427{ 1428 u8 temp; 1429 struct aper_size_info_8 *previous_size; 1430 1431 previous_size = A_SIZE_8(agp_bridge->previous_size); 1432 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1433 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1434 temp & ~(1 << 1)); 1435 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1436 previous_size->size_value); 1437} 1438 1439 1440static int intel_820_configure(void) 1441{ 1442 u32 temp; 1443 u8 temp2; 1444 struct aper_size_info_8 *current_size; 1445 1446 current_size = A_SIZE_8(agp_bridge->current_size); 1447 1448 /* aperture size */ 1449 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1450 1451 /* address to map to */ 1452 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1453 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1454 1455 /* attbase - aperture base */ 1456 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1457 1458 /* agpctrl */ 1459 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1460 1461 /* global enable aperture access */ 1462 /* This flag is not accessed through MCHCFG register as in */ 1463 /* i850 chipset. */ 1464 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1465 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1466 /* clear any possible AGP-related error conditions */ 1467 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1468 return 0; 1469} 1470 1471static int intel_840_configure(void) 1472{ 1473 u32 temp; 1474 u16 temp2; 1475 struct aper_size_info_8 *current_size; 1476 1477 current_size = A_SIZE_8(agp_bridge->current_size); 1478 1479 /* aperture size */ 1480 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1481 1482 /* address to map to */ 1483 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1484 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1485 1486 /* attbase - aperture base */ 1487 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1488 1489 /* agpctrl */ 1490 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1491 1492 /* mcgcfg */ 1493 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1494 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1495 /* clear any possible error conditions */ 1496 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1497 return 0; 1498} 1499 1500static int intel_845_configure(void) 1501{ 1502 u32 temp; 1503 u8 temp2; 1504 struct aper_size_info_8 *current_size; 1505 1506 current_size = A_SIZE_8(agp_bridge->current_size); 1507 1508 /* aperture size */ 1509 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1510 1511 if (agp_bridge->apbase_config != 0) { 1512 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1513 agp_bridge->apbase_config); 1514 } else { 1515 /* address to map to */ 1516 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1517 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1518 agp_bridge->apbase_config = temp; 1519 } 1520 1521 /* attbase - aperture base */ 1522 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1523 1524 /* agpctrl */ 1525 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1526 1527 /* agpm */ 1528 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1529 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1530 /* clear any possible error conditions */ 1531 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1532 1533 intel_i830_setup_flush(); 1534 return 0; 1535} 1536 1537static int intel_850_configure(void) 1538{ 1539 u32 temp; 1540 u16 temp2; 1541 struct aper_size_info_8 *current_size; 1542 1543 current_size = A_SIZE_8(agp_bridge->current_size); 1544 1545 /* aperture size */ 1546 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1547 1548 /* address to map to */ 1549 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1550 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1551 1552 /* attbase - aperture base */ 1553 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1554 1555 /* agpctrl */ 1556 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1557 1558 /* mcgcfg */ 1559 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1560 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1561 /* clear any possible AGP-related error conditions */ 1562 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1563 return 0; 1564} 1565 1566static int intel_860_configure(void) 1567{ 1568 u32 temp; 1569 u16 temp2; 1570 struct aper_size_info_8 *current_size; 1571 1572 current_size = A_SIZE_8(agp_bridge->current_size); 1573 1574 /* aperture size */ 1575 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1576 1577 /* address to map to */ 1578 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1579 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1580 1581 /* attbase - aperture base */ 1582 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1583 1584 /* agpctrl */ 1585 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1586 1587 /* mcgcfg */ 1588 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1589 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1590 /* clear any possible AGP-related error conditions */ 1591 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1592 return 0; 1593} 1594 1595static int intel_830mp_configure(void) 1596{ 1597 u32 temp; 1598 u16 temp2; 1599 struct aper_size_info_8 *current_size; 1600 1601 current_size = A_SIZE_8(agp_bridge->current_size); 1602 1603 /* aperture size */ 1604 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1605 1606 /* address to map to */ 1607 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1608 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1609 1610 /* attbase - aperture base */ 1611 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1612 1613 /* agpctrl */ 1614 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1615 1616 /* gmch */ 1617 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1618 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1619 /* clear any possible AGP-related error conditions */ 1620 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1621 return 0; 1622} 1623 1624static int intel_7505_configure(void) 1625{ 1626 u32 temp; 1627 u16 temp2; 1628 struct aper_size_info_8 *current_size; 1629 1630 current_size = A_SIZE_8(agp_bridge->current_size); 1631 1632 /* aperture size */ 1633 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1634 1635 /* address to map to */ 1636 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1637 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1638 1639 /* attbase - aperture base */ 1640 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1641 1642 /* agpctrl */ 1643 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1644 1645 /* mchcfg */ 1646 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1647 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1648 1649 return 0; 1650} 1651 1652/* Setup function */ 1653static const struct gatt_mask intel_generic_masks[] = 1654{ 1655 {.mask = 0x00000017, .type = 0} 1656}; 1657 1658static const struct aper_size_info_8 intel_815_sizes[2] = 1659{ 1660 {64, 16384, 4, 0}, 1661 {32, 8192, 3, 8}, 1662}; 1663 1664static const struct aper_size_info_8 intel_8xx_sizes[7] = 1665{ 1666 {256, 65536, 6, 0}, 1667 {128, 32768, 5, 32}, 1668 {64, 16384, 4, 48}, 1669 {32, 8192, 3, 56}, 1670 {16, 4096, 2, 60}, 1671 {8, 2048, 1, 62}, 1672 {4, 1024, 0, 63} 1673}; 1674 1675static const struct aper_size_info_16 intel_generic_sizes[7] = 1676{ 1677 {256, 65536, 6, 0}, 1678 {128, 32768, 5, 32}, 1679 {64, 16384, 4, 48}, 1680 {32, 8192, 3, 56}, 1681 {16, 4096, 2, 60}, 1682 {8, 2048, 1, 62}, 1683 {4, 1024, 0, 63} 1684}; 1685 1686static const struct aper_size_info_8 intel_830mp_sizes[4] = 1687{ 1688 {256, 65536, 6, 0}, 1689 {128, 32768, 5, 32}, 1690 {64, 16384, 4, 48}, 1691 {32, 8192, 3, 56} 1692}; 1693 1694static const struct agp_bridge_driver intel_generic_driver = { 1695 .owner = THIS_MODULE, 1696 .aperture_sizes = intel_generic_sizes, 1697 .size_type = U16_APER_SIZE, 1698 .num_aperture_sizes = 7, 1699 .configure = intel_configure, 1700 .fetch_size = intel_fetch_size, 1701 .cleanup = intel_cleanup, 1702 .tlb_flush = intel_tlbflush, 1703 .mask_memory = agp_generic_mask_memory, 1704 .masks = intel_generic_masks, 1705 .agp_enable = agp_generic_enable, 1706 .cache_flush = global_cache_flush, 1707 .create_gatt_table = agp_generic_create_gatt_table, 1708 .free_gatt_table = agp_generic_free_gatt_table, 1709 .insert_memory = agp_generic_insert_memory, 1710 .remove_memory = agp_generic_remove_memory, 1711 .alloc_by_type = agp_generic_alloc_by_type, 1712 .free_by_type = agp_generic_free_by_type, 1713 .agp_alloc_page = agp_generic_alloc_page, 1714 .agp_destroy_page = agp_generic_destroy_page, 1715 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1716}; 1717 1718static const struct agp_bridge_driver intel_810_driver = { 1719 .owner = THIS_MODULE, 1720 .aperture_sizes = intel_i810_sizes, 1721 .size_type = FIXED_APER_SIZE, 1722 .num_aperture_sizes = 2, 1723 .needs_scratch_page = true, 1724 .configure = intel_i810_configure, 1725 .fetch_size = intel_i810_fetch_size, 1726 .cleanup = intel_i810_cleanup, 1727 .tlb_flush = intel_i810_tlbflush, 1728 .mask_memory = intel_i810_mask_memory, 1729 .masks = intel_i810_masks, 1730 .agp_enable = intel_i810_agp_enable, 1731 .cache_flush = global_cache_flush, 1732 .create_gatt_table = agp_generic_create_gatt_table, 1733 .free_gatt_table = agp_generic_free_gatt_table, 1734 .insert_memory = intel_i810_insert_entries, 1735 .remove_memory = intel_i810_remove_entries, 1736 .alloc_by_type = intel_i810_alloc_by_type, 1737 .free_by_type = intel_i810_free_by_type, 1738 .agp_alloc_page = agp_generic_alloc_page, 1739 .agp_destroy_page = agp_generic_destroy_page, 1740 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1741}; 1742 1743static const struct agp_bridge_driver intel_815_driver = { 1744 .owner = THIS_MODULE, 1745 .aperture_sizes = intel_815_sizes, 1746 .size_type = U8_APER_SIZE, 1747 .num_aperture_sizes = 2, 1748 .configure = intel_815_configure, 1749 .fetch_size = intel_815_fetch_size, 1750 .cleanup = intel_8xx_cleanup, 1751 .tlb_flush = intel_8xx_tlbflush, 1752 .mask_memory = agp_generic_mask_memory, 1753 .masks = intel_generic_masks, 1754 .agp_enable = agp_generic_enable, 1755 .cache_flush = global_cache_flush, 1756 .create_gatt_table = agp_generic_create_gatt_table, 1757 .free_gatt_table = agp_generic_free_gatt_table, 1758 .insert_memory = agp_generic_insert_memory, 1759 .remove_memory = agp_generic_remove_memory, 1760 .alloc_by_type = agp_generic_alloc_by_type, 1761 .free_by_type = agp_generic_free_by_type, 1762 .agp_alloc_page = agp_generic_alloc_page, 1763 .agp_destroy_page = agp_generic_destroy_page, 1764 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1765}; 1766 1767static const struct agp_bridge_driver intel_830_driver = { 1768 .owner = THIS_MODULE, 1769 .aperture_sizes = intel_i830_sizes, 1770 .size_type = FIXED_APER_SIZE, 1771 .num_aperture_sizes = 4, 1772 .needs_scratch_page = true, 1773 .configure = intel_i830_configure, 1774 .fetch_size = intel_i830_fetch_size, 1775 .cleanup = intel_i830_cleanup, 1776 .tlb_flush = intel_i810_tlbflush, 1777 .mask_memory = intel_i810_mask_memory, 1778 .masks = intel_i810_masks, 1779 .agp_enable = intel_i810_agp_enable, 1780 .cache_flush = global_cache_flush, 1781 .create_gatt_table = intel_i830_create_gatt_table, 1782 .free_gatt_table = intel_i830_free_gatt_table, 1783 .insert_memory = intel_i830_insert_entries, 1784 .remove_memory = intel_i830_remove_entries, 1785 .alloc_by_type = intel_i830_alloc_by_type, 1786 .free_by_type = intel_i810_free_by_type, 1787 .agp_alloc_page = agp_generic_alloc_page, 1788 .agp_destroy_page = agp_generic_destroy_page, 1789 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1790 .chipset_flush = intel_i830_chipset_flush, 1791}; 1792 1793static const struct agp_bridge_driver intel_820_driver = { 1794 .owner = THIS_MODULE, 1795 .aperture_sizes = intel_8xx_sizes, 1796 .size_type = U8_APER_SIZE, 1797 .num_aperture_sizes = 7, 1798 .configure = intel_820_configure, 1799 .fetch_size = intel_8xx_fetch_size, 1800 .cleanup = intel_820_cleanup, 1801 .tlb_flush = intel_820_tlbflush, 1802 .mask_memory = agp_generic_mask_memory, 1803 .masks = intel_generic_masks, 1804 .agp_enable = agp_generic_enable, 1805 .cache_flush = global_cache_flush, 1806 .create_gatt_table = agp_generic_create_gatt_table, 1807 .free_gatt_table = agp_generic_free_gatt_table, 1808 .insert_memory = agp_generic_insert_memory, 1809 .remove_memory = agp_generic_remove_memory, 1810 .alloc_by_type = agp_generic_alloc_by_type, 1811 .free_by_type = agp_generic_free_by_type, 1812 .agp_alloc_page = agp_generic_alloc_page, 1813 .agp_destroy_page = agp_generic_destroy_page, 1814 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1815}; 1816 1817static const struct agp_bridge_driver intel_830mp_driver = { 1818 .owner = THIS_MODULE, 1819 .aperture_sizes = intel_830mp_sizes, 1820 .size_type = U8_APER_SIZE, 1821 .num_aperture_sizes = 4, 1822 .configure = intel_830mp_configure, 1823 .fetch_size = intel_8xx_fetch_size, 1824 .cleanup = intel_8xx_cleanup, 1825 .tlb_flush = intel_8xx_tlbflush, 1826 .mask_memory = agp_generic_mask_memory, 1827 .masks = intel_generic_masks, 1828 .agp_enable = agp_generic_enable, 1829 .cache_flush = global_cache_flush, 1830 .create_gatt_table = agp_generic_create_gatt_table, 1831 .free_gatt_table = agp_generic_free_gatt_table, 1832 .insert_memory = agp_generic_insert_memory, 1833 .remove_memory = agp_generic_remove_memory, 1834 .alloc_by_type = agp_generic_alloc_by_type, 1835 .free_by_type = agp_generic_free_by_type, 1836 .agp_alloc_page = agp_generic_alloc_page, 1837 .agp_destroy_page = agp_generic_destroy_page, 1838 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1839}; 1840 1841static const struct agp_bridge_driver intel_840_driver = { 1842 .owner = THIS_MODULE, 1843 .aperture_sizes = intel_8xx_sizes, 1844 .size_type = U8_APER_SIZE, 1845 .num_aperture_sizes = 7, 1846 .configure = intel_840_configure, 1847 .fetch_size = intel_8xx_fetch_size, 1848 .cleanup = intel_8xx_cleanup, 1849 .tlb_flush = intel_8xx_tlbflush, 1850 .mask_memory = agp_generic_mask_memory, 1851 .masks = intel_generic_masks, 1852 .agp_enable = agp_generic_enable, 1853 .cache_flush = global_cache_flush, 1854 .create_gatt_table = agp_generic_create_gatt_table, 1855 .free_gatt_table = agp_generic_free_gatt_table, 1856 .insert_memory = agp_generic_insert_memory, 1857 .remove_memory = agp_generic_remove_memory, 1858 .alloc_by_type = agp_generic_alloc_by_type, 1859 .free_by_type = agp_generic_free_by_type, 1860 .agp_alloc_page = agp_generic_alloc_page, 1861 .agp_destroy_page = agp_generic_destroy_page, 1862 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1863}; 1864 1865static const struct agp_bridge_driver intel_845_driver = { 1866 .owner = THIS_MODULE, 1867 .aperture_sizes = intel_8xx_sizes, 1868 .size_type = U8_APER_SIZE, 1869 .num_aperture_sizes = 7, 1870 .configure = intel_845_configure, 1871 .fetch_size = intel_8xx_fetch_size, 1872 .cleanup = intel_8xx_cleanup, 1873 .tlb_flush = intel_8xx_tlbflush, 1874 .mask_memory = agp_generic_mask_memory, 1875 .masks = intel_generic_masks, 1876 .agp_enable = agp_generic_enable, 1877 .cache_flush = global_cache_flush, 1878 .create_gatt_table = agp_generic_create_gatt_table, 1879 .free_gatt_table = agp_generic_free_gatt_table, 1880 .insert_memory = agp_generic_insert_memory, 1881 .remove_memory = agp_generic_remove_memory, 1882 .alloc_by_type = agp_generic_alloc_by_type, 1883 .free_by_type = agp_generic_free_by_type, 1884 .agp_alloc_page = agp_generic_alloc_page, 1885 .agp_destroy_page = agp_generic_destroy_page, 1886 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1887 .chipset_flush = intel_i830_chipset_flush, 1888}; 1889 1890static const struct agp_bridge_driver intel_850_driver = { 1891 .owner = THIS_MODULE, 1892 .aperture_sizes = intel_8xx_sizes, 1893 .size_type = U8_APER_SIZE, 1894 .num_aperture_sizes = 7, 1895 .configure = intel_850_configure, 1896 .fetch_size = intel_8xx_fetch_size, 1897 .cleanup = intel_8xx_cleanup, 1898 .tlb_flush = intel_8xx_tlbflush, 1899 .mask_memory = agp_generic_mask_memory, 1900 .masks = intel_generic_masks, 1901 .agp_enable = agp_generic_enable, 1902 .cache_flush = global_cache_flush, 1903 .create_gatt_table = agp_generic_create_gatt_table, 1904 .free_gatt_table = agp_generic_free_gatt_table, 1905 .insert_memory = agp_generic_insert_memory, 1906 .remove_memory = agp_generic_remove_memory, 1907 .alloc_by_type = agp_generic_alloc_by_type, 1908 .free_by_type = agp_generic_free_by_type, 1909 .agp_alloc_page = agp_generic_alloc_page, 1910 .agp_destroy_page = agp_generic_destroy_page, 1911 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1912}; 1913 1914static const struct agp_bridge_driver intel_860_driver = { 1915 .owner = THIS_MODULE, 1916 .aperture_sizes = intel_8xx_sizes, 1917 .size_type = U8_APER_SIZE, 1918 .num_aperture_sizes = 7, 1919 .configure = intel_860_configure, 1920 .fetch_size = intel_8xx_fetch_size, 1921 .cleanup = intel_8xx_cleanup, 1922 .tlb_flush = intel_8xx_tlbflush, 1923 .mask_memory = agp_generic_mask_memory, 1924 .masks = intel_generic_masks, 1925 .agp_enable = agp_generic_enable, 1926 .cache_flush = global_cache_flush, 1927 .create_gatt_table = agp_generic_create_gatt_table, 1928 .free_gatt_table = agp_generic_free_gatt_table, 1929 .insert_memory = agp_generic_insert_memory, 1930 .remove_memory = agp_generic_remove_memory, 1931 .alloc_by_type = agp_generic_alloc_by_type, 1932 .free_by_type = agp_generic_free_by_type, 1933 .agp_alloc_page = agp_generic_alloc_page, 1934 .agp_destroy_page = agp_generic_destroy_page, 1935 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1936}; 1937 1938static const struct agp_bridge_driver intel_915_driver = { 1939 .owner = THIS_MODULE, 1940 .aperture_sizes = intel_i830_sizes, 1941 .size_type = FIXED_APER_SIZE, 1942 .num_aperture_sizes = 4, 1943 .needs_scratch_page = true, 1944 .configure = intel_i915_configure, 1945 .fetch_size = intel_i9xx_fetch_size, 1946 .cleanup = intel_i915_cleanup, 1947 .tlb_flush = intel_i810_tlbflush, 1948 .mask_memory = intel_i810_mask_memory, 1949 .masks = intel_i810_masks, 1950 .agp_enable = intel_i810_agp_enable, 1951 .cache_flush = global_cache_flush, 1952 .create_gatt_table = intel_i915_create_gatt_table, 1953 .free_gatt_table = intel_i830_free_gatt_table, 1954 .insert_memory = intel_i915_insert_entries, 1955 .remove_memory = intel_i915_remove_entries, 1956 .alloc_by_type = intel_i830_alloc_by_type, 1957 .free_by_type = intel_i810_free_by_type, 1958 .agp_alloc_page = agp_generic_alloc_page, 1959 .agp_destroy_page = agp_generic_destroy_page, 1960 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1961 .chipset_flush = intel_i915_chipset_flush, 1962}; 1963 1964static const struct agp_bridge_driver intel_i965_driver = { 1965 .owner = THIS_MODULE, 1966 .aperture_sizes = intel_i830_sizes, 1967 .size_type = FIXED_APER_SIZE, 1968 .num_aperture_sizes = 4, 1969 .needs_scratch_page = true, 1970 .configure = intel_i915_configure, 1971 .fetch_size = intel_i9xx_fetch_size, 1972 .cleanup = intel_i915_cleanup, 1973 .tlb_flush = intel_i810_tlbflush, 1974 .mask_memory = intel_i965_mask_memory, 1975 .masks = intel_i810_masks, 1976 .agp_enable = intel_i810_agp_enable, 1977 .cache_flush = global_cache_flush, 1978 .create_gatt_table = intel_i965_create_gatt_table, 1979 .free_gatt_table = intel_i830_free_gatt_table, 1980 .insert_memory = intel_i915_insert_entries, 1981 .remove_memory = intel_i915_remove_entries, 1982 .alloc_by_type = intel_i830_alloc_by_type, 1983 .free_by_type = intel_i810_free_by_type, 1984 .agp_alloc_page = agp_generic_alloc_page, 1985 .agp_destroy_page = agp_generic_destroy_page, 1986 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1987 .chipset_flush = intel_i915_chipset_flush, 1988}; 1989 1990static const struct agp_bridge_driver intel_7505_driver = { 1991 .owner = THIS_MODULE, 1992 .aperture_sizes = intel_8xx_sizes, 1993 .size_type = U8_APER_SIZE, 1994 .num_aperture_sizes = 7, 1995 .configure = intel_7505_configure, 1996 .fetch_size = intel_8xx_fetch_size, 1997 .cleanup = intel_8xx_cleanup, 1998 .tlb_flush = intel_8xx_tlbflush, 1999 .mask_memory = agp_generic_mask_memory, 2000 .masks = intel_generic_masks, 2001 .agp_enable = agp_generic_enable, 2002 .cache_flush = global_cache_flush, 2003 .create_gatt_table = agp_generic_create_gatt_table, 2004 .free_gatt_table = agp_generic_free_gatt_table, 2005 .insert_memory = agp_generic_insert_memory, 2006 .remove_memory = agp_generic_remove_memory, 2007 .alloc_by_type = agp_generic_alloc_by_type, 2008 .free_by_type = agp_generic_free_by_type, 2009 .agp_alloc_page = agp_generic_alloc_page, 2010 .agp_destroy_page = agp_generic_destroy_page, 2011 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 2012}; 2013 2014static const struct agp_bridge_driver intel_g33_driver = { 2015 .owner = THIS_MODULE, 2016 .aperture_sizes = intel_i830_sizes, 2017 .size_type = FIXED_APER_SIZE, 2018 .num_aperture_sizes = 4, 2019 .needs_scratch_page = true, 2020 .configure = intel_i915_configure, 2021 .fetch_size = intel_i9xx_fetch_size, 2022 .cleanup = intel_i915_cleanup, 2023 .tlb_flush = intel_i810_tlbflush, 2024 .mask_memory = intel_i965_mask_memory, 2025 .masks = intel_i810_masks, 2026 .agp_enable = intel_i810_agp_enable, 2027 .cache_flush = global_cache_flush, 2028 .create_gatt_table = intel_i915_create_gatt_table, 2029 .free_gatt_table = intel_i830_free_gatt_table, 2030 .insert_memory = intel_i915_insert_entries, 2031 .remove_memory = intel_i915_remove_entries, 2032 .alloc_by_type = intel_i830_alloc_by_type, 2033 .free_by_type = intel_i810_free_by_type, 2034 .agp_alloc_page = agp_generic_alloc_page, 2035 .agp_destroy_page = agp_generic_destroy_page, 2036 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 2037 .chipset_flush = intel_i915_chipset_flush, 2038}; 2039 2040static int find_gmch(u16 device) 2041{ 2042 struct pci_dev *gmch_device; 2043 2044 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2045 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 2046 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 2047 device, gmch_device); 2048 } 2049 2050 if (!gmch_device) 2051 return 0; 2052 2053 intel_private.pcidev = gmch_device; 2054 return 1; 2055} 2056 2057/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 2058 * driver and gmch_driver must be non-null, and find_gmch will determine 2059 * which one should be used if a gmch_chip_id is present. 2060 */ 2061static const struct intel_driver_description { 2062 unsigned int chip_id; 2063 unsigned int gmch_chip_id; 2064 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ 2065 char *name; 2066 const struct agp_bridge_driver *driver; 2067 const struct agp_bridge_driver *gmch_driver; 2068} intel_agp_chipsets[] = { 2069 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, 2070 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, 2071 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, 2072 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", 2073 NULL, &intel_810_driver }, 2074 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", 2075 NULL, &intel_810_driver }, 2076 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", 2077 NULL, &intel_810_driver }, 2078 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", 2079 &intel_815_driver, &intel_810_driver }, 2080 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2081 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, 2082 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", 2083 &intel_830mp_driver, &intel_830_driver }, 2084 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, 2085 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, 2086 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", 2087 &intel_845_driver, &intel_830_driver }, 2088 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, 2089 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, 2090 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", 2091 &intel_845_driver, &intel_830_driver }, 2092 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, 2093 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", 2094 &intel_845_driver, &intel_830_driver }, 2095 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, 2096 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", 2097 NULL, &intel_915_driver }, 2098 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", 2099 NULL, &intel_915_driver }, 2100 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", 2101 NULL, &intel_915_driver }, 2102 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", 2103 NULL, &intel_915_driver }, 2104 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", 2105 NULL, &intel_915_driver }, 2106 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", 2107 NULL, &intel_915_driver }, 2108 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", 2109 NULL, &intel_i965_driver }, 2110 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", 2111 NULL, &intel_i965_driver }, 2112 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", 2113 NULL, &intel_i965_driver }, 2114 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", 2115 NULL, &intel_i965_driver }, 2116 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", 2117 NULL, &intel_i965_driver }, 2118 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", 2119 NULL, &intel_i965_driver }, 2120 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, 2121 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, 2122 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", 2123 NULL, &intel_g33_driver }, 2124 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", 2125 NULL, &intel_g33_driver }, 2126 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", 2127 NULL, &intel_g33_driver }, 2128 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, 2129 "Mobile Intel? GM45 Express", NULL, &intel_i965_driver }, 2130 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, 2131 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2132 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, 2133 "Q45/Q43", NULL, &intel_i965_driver }, 2134 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2135 "G45/G43", NULL, &intel_i965_driver }, 2136 { 0, 0, 0, NULL, NULL, NULL } 2137}; 2138 2139static int __devinit agp_intel_probe(struct pci_dev *pdev, 2140 const struct pci_device_id *ent) 2141{ 2142 struct agp_bridge_data *bridge; 2143 u8 cap_ptr = 0; 2144 struct resource *r; 2145 int i; 2146 2147 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 2148 2149 bridge = agp_alloc_bridge(); 2150 if (!bridge) 2151 return -ENOMEM; 2152 2153 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { 2154 /* In case that multiple models of gfx chip may 2155 stand on same host bridge type, this can be 2156 sure we detect the right IGD. */ 2157 if (pdev->device == intel_agp_chipsets[i].chip_id) { 2158 if ((intel_agp_chipsets[i].gmch_chip_id != 0) && 2159 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { 2160 bridge->driver = 2161 intel_agp_chipsets[i].gmch_driver; 2162 break; 2163 } else if (intel_agp_chipsets[i].multi_gmch_chip) { 2164 continue; 2165 } else { 2166 bridge->driver = intel_agp_chipsets[i].driver; 2167 break; 2168 } 2169 } 2170 } 2171 2172 if (intel_agp_chipsets[i].name == NULL) { 2173 if (cap_ptr) 2174 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 2175 pdev->vendor, pdev->device); 2176 agp_put_bridge(bridge); 2177 return -ENODEV; 2178 } 2179 2180 if (bridge->driver == NULL) { 2181 /* bridge has no AGP and no IGD detected */ 2182 if (cap_ptr) 2183 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", 2184 intel_agp_chipsets[i].gmch_chip_id); 2185 agp_put_bridge(bridge); 2186 return -ENODEV; 2187 } 2188 2189 bridge->dev = pdev; 2190 bridge->capndx = cap_ptr; 2191 bridge->dev_private_data = &intel_private; 2192 2193 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 2194 2195 /* 2196 * The following fixes the case where the BIOS has "forgotten" to 2197 * provide an address range for the GART. 2198 * 20030610 - hamish@zot.org 2199 */ 2200 r = &pdev->resource[0]; 2201 if (!r->start && r->end) { 2202 if (pci_assign_resource(pdev, 0)) { 2203 dev_err(&pdev->dev, "can't assign resource 0\n"); 2204 agp_put_bridge(bridge); 2205 return -ENODEV; 2206 } 2207 } 2208 2209 /* 2210 * If the device has not been properly setup, the following will catch 2211 * the problem and should stop the system from crashing. 2212 * 20030610 - hamish@zot.org 2213 */ 2214 if (pci_enable_device(pdev)) { 2215 dev_err(&pdev->dev, "can't enable PCI device\n"); 2216 agp_put_bridge(bridge); 2217 return -ENODEV; 2218 } 2219 2220 /* Fill in the mode register */ 2221 if (cap_ptr) { 2222 pci_read_config_dword(pdev, 2223 bridge->capndx+PCI_AGP_STATUS, 2224 &bridge->mode); 2225 } 2226 2227 pci_set_drvdata(pdev, bridge); 2228 return agp_add_bridge(bridge); 2229} 2230 2231static void __devexit agp_intel_remove(struct pci_dev *pdev) 2232{ 2233 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2234 2235 agp_remove_bridge(bridge); 2236 2237 if (intel_private.pcidev) 2238 pci_dev_put(intel_private.pcidev); 2239 2240 agp_put_bridge(bridge); 2241} 2242 2243#ifdef CONFIG_PM 2244static int agp_intel_resume(struct pci_dev *pdev) 2245{ 2246 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2247 int ret_val; 2248 2249 pci_restore_state(pdev); 2250 2251 /* We should restore our graphics device's config space, 2252 * as host bridge (00:00) resumes before graphics device (02:00), 2253 * then our access to its pci space can work right. 2254 */ 2255 if (intel_private.pcidev) 2256 pci_restore_state(intel_private.pcidev); 2257 2258 if (bridge->driver == &intel_generic_driver) 2259 intel_configure(); 2260 else if (bridge->driver == &intel_850_driver) 2261 intel_850_configure(); 2262 else if (bridge->driver == &intel_845_driver) 2263 intel_845_configure(); 2264 else if (bridge->driver == &intel_830mp_driver) 2265 intel_830mp_configure(); 2266 else if (bridge->driver == &intel_915_driver) 2267 intel_i915_configure(); 2268 else if (bridge->driver == &intel_830_driver) 2269 intel_i830_configure(); 2270 else if (bridge->driver == &intel_810_driver) 2271 intel_i810_configure(); 2272 else if (bridge->driver == &intel_i965_driver) 2273 intel_i915_configure(); 2274 2275 ret_val = agp_rebind_memory(); 2276 if (ret_val != 0) 2277 return ret_val; 2278 2279 return 0; 2280} 2281#endif 2282 2283static struct pci_device_id agp_intel_pci_table[] = { 2284#define ID(x) \ 2285 { \ 2286 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2287 .class_mask = ~0, \ 2288 .vendor = PCI_VENDOR_ID_INTEL, \ 2289 .device = x, \ 2290 .subvendor = PCI_ANY_ID, \ 2291 .subdevice = PCI_ANY_ID, \ 2292 } 2293 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2294 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2295 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2296 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2297 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2298 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2299 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2300 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2301 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2302 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2303 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2304 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2305 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2306 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2307 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2308 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2309 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2310 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2311 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2312 ID(PCI_DEVICE_ID_INTEL_7505_0), 2313 ID(PCI_DEVICE_ID_INTEL_7205_0), 2314 ID(PCI_DEVICE_ID_INTEL_E7221_HB), 2315 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2316 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2317 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2318 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2319 ID(PCI_DEVICE_ID_INTEL_82945GME_HB), 2320 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2321 ID(PCI_DEVICE_ID_INTEL_82G35_HB), 2322 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2323 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2324 ID(PCI_DEVICE_ID_INTEL_82965GM_HB), 2325 ID(PCI_DEVICE_ID_INTEL_82965GME_HB), 2326 ID(PCI_DEVICE_ID_INTEL_G33_HB), 2327 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2328 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2329 ID(PCI_DEVICE_ID_INTEL_GM45_HB), 2330 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), 2331 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2332 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2333 { } 2334}; 2335 2336MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2337 2338static struct pci_driver agp_intel_pci_driver = { 2339 .name = "agpgart-intel", 2340 .id_table = agp_intel_pci_table, 2341 .probe = agp_intel_probe, 2342 .remove = __devexit_p(agp_intel_remove), 2343#ifdef CONFIG_PM 2344 .resume = agp_intel_resume, 2345#endif 2346}; 2347 2348static int __init agp_intel_init(void) 2349{ 2350 if (agp_off) 2351 return -EINVAL; 2352 return pci_register_driver(&agp_intel_pci_driver); 2353} 2354 2355static void __exit agp_intel_cleanup(void) 2356{ 2357 pci_unregister_driver(&agp_intel_pci_driver); 2358} 2359 2360module_init(agp_intel_init); 2361module_exit(agp_intel_cleanup); 2362 2363MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 2364MODULE_LICENSE("GPL and additional rights"); 2365