synclink_cs.c revision 25985edcedea6396277003854657b5f3cb31a628
1/* 2 * linux/drivers/char/pcmcia/synclink_cs.c 3 * 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $ 5 * 6 * Device driver for Microgate SyncLink PC Card 7 * multiprotocol serial adapter. 8 * 9 * written by Paul Fulghum for Microgate Corporation 10 * paulkf@microgate.com 11 * 12 * Microgate and SyncLink are trademarks of Microgate Corporation 13 * 14 * This code is released under the GNU General Public License (GPL) 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 26 * OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 30#if defined(__i386__) 31# define BREAKPOINT() asm(" int $3"); 32#else 33# define BREAKPOINT() { } 34#endif 35 36#define MAX_DEVICE_COUNT 4 37 38#include <linux/module.h> 39#include <linux/errno.h> 40#include <linux/signal.h> 41#include <linux/sched.h> 42#include <linux/timer.h> 43#include <linux/time.h> 44#include <linux/interrupt.h> 45#include <linux/tty.h> 46#include <linux/tty_flip.h> 47#include <linux/serial.h> 48#include <linux/major.h> 49#include <linux/string.h> 50#include <linux/fcntl.h> 51#include <linux/ptrace.h> 52#include <linux/ioport.h> 53#include <linux/mm.h> 54#include <linux/seq_file.h> 55#include <linux/slab.h> 56#include <linux/netdevice.h> 57#include <linux/vmalloc.h> 58#include <linux/init.h> 59#include <linux/delay.h> 60#include <linux/ioctl.h> 61#include <linux/synclink.h> 62 63#include <asm/system.h> 64#include <asm/io.h> 65#include <asm/irq.h> 66#include <asm/dma.h> 67#include <linux/bitops.h> 68#include <asm/types.h> 69#include <linux/termios.h> 70#include <linux/workqueue.h> 71#include <linux/hdlc.h> 72 73#include <pcmcia/cistpl.h> 74#include <pcmcia/cisreg.h> 75#include <pcmcia/ds.h> 76 77#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE)) 78#define SYNCLINK_GENERIC_HDLC 1 79#else 80#define SYNCLINK_GENERIC_HDLC 0 81#endif 82 83#define GET_USER(error,value,addr) error = get_user(value,addr) 84#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 85#define PUT_USER(error,value,addr) error = put_user(value,addr) 86#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 87 88#include <asm/uaccess.h> 89 90static MGSL_PARAMS default_params = { 91 MGSL_MODE_HDLC, /* unsigned long mode */ 92 0, /* unsigned char loopback; */ 93 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ 94 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ 95 0, /* unsigned long clock_speed; */ 96 0xff, /* unsigned char addr_filter; */ 97 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ 98 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ 99 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ 100 9600, /* unsigned long data_rate; */ 101 8, /* unsigned char data_bits; */ 102 1, /* unsigned char stop_bits; */ 103 ASYNC_PARITY_NONE /* unsigned char parity; */ 104}; 105 106typedef struct 107{ 108 int count; 109 unsigned char status; 110 char data[1]; 111} RXBUF; 112 113/* The queue of BH actions to be performed */ 114 115#define BH_RECEIVE 1 116#define BH_TRANSMIT 2 117#define BH_STATUS 4 118 119#define IO_PIN_SHUTDOWN_LIMIT 100 120 121#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) 122 123struct _input_signal_events { 124 int ri_up; 125 int ri_down; 126 int dsr_up; 127 int dsr_down; 128 int dcd_up; 129 int dcd_down; 130 int cts_up; 131 int cts_down; 132}; 133 134 135/* 136 * Device instance data structure 137 */ 138 139typedef struct _mgslpc_info { 140 struct tty_port port; 141 void *if_ptr; /* General purpose pointer (used by SPPP) */ 142 int magic; 143 int line; 144 145 struct mgsl_icount icount; 146 147 int timeout; 148 int x_char; /* xon/xoff character */ 149 unsigned char read_status_mask; 150 unsigned char ignore_status_mask; 151 152 unsigned char *tx_buf; 153 int tx_put; 154 int tx_get; 155 int tx_count; 156 157 /* circular list of fixed length rx buffers */ 158 159 unsigned char *rx_buf; /* memory allocated for all rx buffers */ 160 int rx_buf_total_size; /* size of memory allocated for rx buffers */ 161 int rx_put; /* index of next empty rx buffer */ 162 int rx_get; /* index of next full rx buffer */ 163 int rx_buf_size; /* size in bytes of single rx buffer */ 164 int rx_buf_count; /* total number of rx buffers */ 165 int rx_frame_count; /* number of full rx buffers */ 166 167 wait_queue_head_t status_event_wait_q; 168 wait_queue_head_t event_wait_q; 169 struct timer_list tx_timer; /* HDLC transmit timeout timer */ 170 struct _mgslpc_info *next_device; /* device list link */ 171 172 unsigned short imra_value; 173 unsigned short imrb_value; 174 unsigned char pim_value; 175 176 spinlock_t lock; 177 struct work_struct task; /* task structure for scheduling bh */ 178 179 u32 max_frame_size; 180 181 u32 pending_bh; 182 183 bool bh_running; 184 bool bh_requested; 185 186 int dcd_chkcount; /* check counts to prevent */ 187 int cts_chkcount; /* too many IRQs if a signal */ 188 int dsr_chkcount; /* is floating */ 189 int ri_chkcount; 190 191 bool rx_enabled; 192 bool rx_overflow; 193 194 bool tx_enabled; 195 bool tx_active; 196 bool tx_aborting; 197 u32 idle_mode; 198 199 int if_mode; /* serial interface selection (RS-232, v.35 etc) */ 200 201 char device_name[25]; /* device instance name */ 202 203 unsigned int io_base; /* base I/O address of adapter */ 204 unsigned int irq_level; 205 206 MGSL_PARAMS params; /* communications parameters */ 207 208 unsigned char serial_signals; /* current serial signal states */ 209 210 bool irq_occurred; /* for diagnostics use */ 211 char testing_irq; 212 unsigned int init_error; /* startup error (DIAGS) */ 213 214 char flag_buf[MAX_ASYNC_BUFFER_SIZE]; 215 bool drop_rts_on_tx_done; 216 217 struct _input_signal_events input_signal_events; 218 219 /* PCMCIA support */ 220 struct pcmcia_device *p_dev; 221 int stop; 222 223 /* SPPP/Cisco HDLC device parts */ 224 int netcount; 225 spinlock_t netlock; 226 227#if SYNCLINK_GENERIC_HDLC 228 struct net_device *netdev; 229#endif 230 231} MGSLPC_INFO; 232 233#define MGSLPC_MAGIC 0x5402 234 235/* 236 * The size of the serial xmit buffer is 1 page, or 4096 bytes 237 */ 238#define TXBUFSIZE 4096 239 240 241#define CHA 0x00 /* channel A offset */ 242#define CHB 0x40 /* channel B offset */ 243 244/* 245 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it. 246 */ 247#undef PVR 248 249#define RXFIFO 0 250#define TXFIFO 0 251#define STAR 0x20 252#define CMDR 0x20 253#define RSTA 0x21 254#define PRE 0x21 255#define MODE 0x22 256#define TIMR 0x23 257#define XAD1 0x24 258#define XAD2 0x25 259#define RAH1 0x26 260#define RAH2 0x27 261#define DAFO 0x27 262#define RAL1 0x28 263#define RFC 0x28 264#define RHCR 0x29 265#define RAL2 0x29 266#define RBCL 0x2a 267#define XBCL 0x2a 268#define RBCH 0x2b 269#define XBCH 0x2b 270#define CCR0 0x2c 271#define CCR1 0x2d 272#define CCR2 0x2e 273#define CCR3 0x2f 274#define VSTR 0x34 275#define BGR 0x34 276#define RLCR 0x35 277#define AML 0x36 278#define AMH 0x37 279#define GIS 0x38 280#define IVA 0x38 281#define IPC 0x39 282#define ISR 0x3a 283#define IMR 0x3a 284#define PVR 0x3c 285#define PIS 0x3d 286#define PIM 0x3d 287#define PCR 0x3e 288#define CCR4 0x3f 289 290// IMR/ISR 291 292#define IRQ_BREAK_ON BIT15 // rx break detected 293#define IRQ_DATAOVERRUN BIT14 // receive data overflow 294#define IRQ_ALLSENT BIT13 // all sent 295#define IRQ_UNDERRUN BIT12 // transmit data underrun 296#define IRQ_TIMER BIT11 // timer interrupt 297#define IRQ_CTS BIT10 // CTS status change 298#define IRQ_TXREPEAT BIT9 // tx message repeat 299#define IRQ_TXFIFO BIT8 // transmit pool ready 300#define IRQ_RXEOM BIT7 // receive message end 301#define IRQ_EXITHUNT BIT6 // receive frame start 302#define IRQ_RXTIME BIT6 // rx char timeout 303#define IRQ_DCD BIT2 // carrier detect status change 304#define IRQ_OVERRUN BIT1 // receive frame overflow 305#define IRQ_RXFIFO BIT0 // receive pool full 306 307// STAR 308 309#define XFW BIT6 // transmit FIFO write enable 310#define CEC BIT2 // command executing 311#define CTS BIT1 // CTS state 312 313#define PVR_DTR BIT0 314#define PVR_DSR BIT1 315#define PVR_RI BIT2 316#define PVR_AUTOCTS BIT3 317#define PVR_RS232 0x20 /* 0010b */ 318#define PVR_V35 0xe0 /* 1110b */ 319#define PVR_RS422 0x40 /* 0100b */ 320 321/* Register access functions */ 322 323#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) 324#define read_reg(info, reg) inb((info)->io_base + (reg)) 325 326#define read_reg16(info, reg) inw((info)->io_base + (reg)) 327#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg)) 328 329#define set_reg_bits(info, reg, mask) \ 330 write_reg(info, (reg), \ 331 (unsigned char) (read_reg(info, (reg)) | (mask))) 332#define clear_reg_bits(info, reg, mask) \ 333 write_reg(info, (reg), \ 334 (unsigned char) (read_reg(info, (reg)) & ~(mask))) 335/* 336 * interrupt enable/disable routines 337 */ 338static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) 339{ 340 if (channel == CHA) { 341 info->imra_value |= mask; 342 write_reg16(info, CHA + IMR, info->imra_value); 343 } else { 344 info->imrb_value |= mask; 345 write_reg16(info, CHB + IMR, info->imrb_value); 346 } 347} 348static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) 349{ 350 if (channel == CHA) { 351 info->imra_value &= ~mask; 352 write_reg16(info, CHA + IMR, info->imra_value); 353 } else { 354 info->imrb_value &= ~mask; 355 write_reg16(info, CHB + IMR, info->imrb_value); 356 } 357} 358 359#define port_irq_disable(info, mask) \ 360 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); } 361 362#define port_irq_enable(info, mask) \ 363 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); } 364 365static void rx_start(MGSLPC_INFO *info); 366static void rx_stop(MGSLPC_INFO *info); 367 368static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty); 369static void tx_stop(MGSLPC_INFO *info); 370static void tx_set_idle(MGSLPC_INFO *info); 371 372static void get_signals(MGSLPC_INFO *info); 373static void set_signals(MGSLPC_INFO *info); 374 375static void reset_device(MGSLPC_INFO *info); 376 377static void hdlc_mode(MGSLPC_INFO *info); 378static void async_mode(MGSLPC_INFO *info); 379 380static void tx_timeout(unsigned long context); 381 382static int carrier_raised(struct tty_port *port); 383static void dtr_rts(struct tty_port *port, int onoff); 384 385#if SYNCLINK_GENERIC_HDLC 386#define dev_to_port(D) (dev_to_hdlc(D)->priv) 387static void hdlcdev_tx_done(MGSLPC_INFO *info); 388static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size); 389static int hdlcdev_init(MGSLPC_INFO *info); 390static void hdlcdev_exit(MGSLPC_INFO *info); 391#endif 392 393static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit); 394 395static bool register_test(MGSLPC_INFO *info); 396static bool irq_test(MGSLPC_INFO *info); 397static int adapter_test(MGSLPC_INFO *info); 398 399static int claim_resources(MGSLPC_INFO *info); 400static void release_resources(MGSLPC_INFO *info); 401static void mgslpc_add_device(MGSLPC_INFO *info); 402static void mgslpc_remove_device(MGSLPC_INFO *info); 403 404static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty); 405static void rx_reset_buffers(MGSLPC_INFO *info); 406static int rx_alloc_buffers(MGSLPC_INFO *info); 407static void rx_free_buffers(MGSLPC_INFO *info); 408 409static irqreturn_t mgslpc_isr(int irq, void *dev_id); 410 411/* 412 * Bottom half interrupt handlers 413 */ 414static void bh_handler(struct work_struct *work); 415static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty); 416static void bh_status(MGSLPC_INFO *info); 417 418/* 419 * ioctl handlers 420 */ 421static int tiocmget(struct tty_struct *tty); 422static int tiocmset(struct tty_struct *tty, 423 unsigned int set, unsigned int clear); 424static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount); 425static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params); 426static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty); 427static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode); 428static int set_txidle(MGSLPC_INFO *info, int idle_mode); 429static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty); 430static int tx_abort(MGSLPC_INFO *info); 431static int set_rxenable(MGSLPC_INFO *info, int enable); 432static int wait_events(MGSLPC_INFO *info, int __user *mask); 433 434static MGSLPC_INFO *mgslpc_device_list = NULL; 435static int mgslpc_device_count = 0; 436 437/* 438 * Set this param to non-zero to load eax with the 439 * .text section address and breakpoint on module load. 440 * This is useful for use with gdb and add-symbol-file command. 441 */ 442static int break_on_load=0; 443 444/* 445 * Driver major number, defaults to zero to get auto 446 * assigned major number. May be forced as module parameter. 447 */ 448static int ttymajor=0; 449 450static int debug_level = 0; 451static int maxframe[MAX_DEVICE_COUNT] = {0,}; 452 453module_param(break_on_load, bool, 0); 454module_param(ttymajor, int, 0); 455module_param(debug_level, int, 0); 456module_param_array(maxframe, int, NULL, 0); 457 458MODULE_LICENSE("GPL"); 459 460static char *driver_name = "SyncLink PC Card driver"; 461static char *driver_version = "$Revision: 4.34 $"; 462 463static struct tty_driver *serial_driver; 464 465/* number of characters left in xmit buffer before we ask for more */ 466#define WAKEUP_CHARS 256 467 468static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty); 469static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout); 470 471/* PCMCIA prototypes */ 472 473static int mgslpc_config(struct pcmcia_device *link); 474static void mgslpc_release(u_long arg); 475static void mgslpc_detach(struct pcmcia_device *p_dev); 476 477/* 478 * 1st function defined in .text section. Calling this function in 479 * init_module() followed by a breakpoint allows a remote debugger 480 * (gdb) to get the .text address for the add-symbol-file command. 481 * This allows remote debugging of dynamically loadable modules. 482 */ 483static void* mgslpc_get_text_ptr(void) 484{ 485 return mgslpc_get_text_ptr; 486} 487 488/** 489 * line discipline callback wrappers 490 * 491 * The wrappers maintain line discipline references 492 * while calling into the line discipline. 493 * 494 * ldisc_receive_buf - pass receive data to line discipline 495 */ 496 497static void ldisc_receive_buf(struct tty_struct *tty, 498 const __u8 *data, char *flags, int count) 499{ 500 struct tty_ldisc *ld; 501 if (!tty) 502 return; 503 ld = tty_ldisc_ref(tty); 504 if (ld) { 505 if (ld->ops->receive_buf) 506 ld->ops->receive_buf(tty, data, flags, count); 507 tty_ldisc_deref(ld); 508 } 509} 510 511static const struct tty_port_operations mgslpc_port_ops = { 512 .carrier_raised = carrier_raised, 513 .dtr_rts = dtr_rts 514}; 515 516static int mgslpc_probe(struct pcmcia_device *link) 517{ 518 MGSLPC_INFO *info; 519 int ret; 520 521 if (debug_level >= DEBUG_LEVEL_INFO) 522 printk("mgslpc_attach\n"); 523 524 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL); 525 if (!info) { 526 printk("Error can't allocate device instance data\n"); 527 return -ENOMEM; 528 } 529 530 info->magic = MGSLPC_MAGIC; 531 tty_port_init(&info->port); 532 info->port.ops = &mgslpc_port_ops; 533 INIT_WORK(&info->task, bh_handler); 534 info->max_frame_size = 4096; 535 info->port.close_delay = 5*HZ/10; 536 info->port.closing_wait = 30*HZ; 537 init_waitqueue_head(&info->status_event_wait_q); 538 init_waitqueue_head(&info->event_wait_q); 539 spin_lock_init(&info->lock); 540 spin_lock_init(&info->netlock); 541 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 542 info->idle_mode = HDLC_TXIDLE_FLAGS; 543 info->imra_value = 0xffff; 544 info->imrb_value = 0xffff; 545 info->pim_value = 0xff; 546 547 info->p_dev = link; 548 link->priv = info; 549 550 /* Initialize the struct pcmcia_device structure */ 551 552 ret = mgslpc_config(link); 553 if (ret) 554 return ret; 555 556 mgslpc_add_device(info); 557 558 return 0; 559} 560 561/* Card has been inserted. 562 */ 563 564static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data) 565{ 566 return pcmcia_request_io(p_dev); 567} 568 569static int mgslpc_config(struct pcmcia_device *link) 570{ 571 MGSLPC_INFO *info = link->priv; 572 int ret; 573 574 if (debug_level >= DEBUG_LEVEL_INFO) 575 printk("mgslpc_config(0x%p)\n", link); 576 577 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO; 578 579 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL); 580 if (ret != 0) 581 goto failed; 582 583 link->config_index = 8; 584 link->config_regs = PRESENT_OPTION; 585 586 ret = pcmcia_request_irq(link, mgslpc_isr); 587 if (ret) 588 goto failed; 589 ret = pcmcia_enable_device(link); 590 if (ret) 591 goto failed; 592 593 info->io_base = link->resource[0]->start; 594 info->irq_level = link->irq; 595 return 0; 596 597failed: 598 mgslpc_release((u_long)link); 599 return -ENODEV; 600} 601 602/* Card has been removed. 603 * Unregister device and release PCMCIA configuration. 604 * If device is open, postpone until it is closed. 605 */ 606static void mgslpc_release(u_long arg) 607{ 608 struct pcmcia_device *link = (struct pcmcia_device *)arg; 609 610 if (debug_level >= DEBUG_LEVEL_INFO) 611 printk("mgslpc_release(0x%p)\n", link); 612 613 pcmcia_disable_device(link); 614} 615 616static void mgslpc_detach(struct pcmcia_device *link) 617{ 618 if (debug_level >= DEBUG_LEVEL_INFO) 619 printk("mgslpc_detach(0x%p)\n", link); 620 621 ((MGSLPC_INFO *)link->priv)->stop = 1; 622 mgslpc_release((u_long)link); 623 624 mgslpc_remove_device((MGSLPC_INFO *)link->priv); 625} 626 627static int mgslpc_suspend(struct pcmcia_device *link) 628{ 629 MGSLPC_INFO *info = link->priv; 630 631 info->stop = 1; 632 633 return 0; 634} 635 636static int mgslpc_resume(struct pcmcia_device *link) 637{ 638 MGSLPC_INFO *info = link->priv; 639 640 info->stop = 0; 641 642 return 0; 643} 644 645 646static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info, 647 char *name, const char *routine) 648{ 649#ifdef MGSLPC_PARANOIA_CHECK 650 static const char *badmagic = 651 "Warning: bad magic number for mgsl struct (%s) in %s\n"; 652 static const char *badinfo = 653 "Warning: null mgslpc_info for (%s) in %s\n"; 654 655 if (!info) { 656 printk(badinfo, name, routine); 657 return true; 658 } 659 if (info->magic != MGSLPC_MAGIC) { 660 printk(badmagic, name, routine); 661 return true; 662 } 663#else 664 if (!info) 665 return true; 666#endif 667 return false; 668} 669 670 671#define CMD_RXFIFO BIT7 // release current rx FIFO 672#define CMD_RXRESET BIT6 // receiver reset 673#define CMD_RXFIFO_READ BIT5 674#define CMD_START_TIMER BIT4 675#define CMD_TXFIFO BIT3 // release current tx FIFO 676#define CMD_TXEOM BIT1 // transmit end message 677#define CMD_TXRESET BIT0 // transmit reset 678 679static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel) 680{ 681 int i = 0; 682 /* wait for command completion */ 683 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { 684 udelay(1); 685 if (i++ == 1000) 686 return false; 687 } 688 return true; 689} 690 691static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd) 692{ 693 wait_command_complete(info, channel); 694 write_reg(info, (unsigned char) (channel + CMDR), cmd); 695} 696 697static void tx_pause(struct tty_struct *tty) 698{ 699 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 700 unsigned long flags; 701 702 if (mgslpc_paranoia_check(info, tty->name, "tx_pause")) 703 return; 704 if (debug_level >= DEBUG_LEVEL_INFO) 705 printk("tx_pause(%s)\n",info->device_name); 706 707 spin_lock_irqsave(&info->lock,flags); 708 if (info->tx_enabled) 709 tx_stop(info); 710 spin_unlock_irqrestore(&info->lock,flags); 711} 712 713static void tx_release(struct tty_struct *tty) 714{ 715 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 716 unsigned long flags; 717 718 if (mgslpc_paranoia_check(info, tty->name, "tx_release")) 719 return; 720 if (debug_level >= DEBUG_LEVEL_INFO) 721 printk("tx_release(%s)\n",info->device_name); 722 723 spin_lock_irqsave(&info->lock,flags); 724 if (!info->tx_enabled) 725 tx_start(info, tty); 726 spin_unlock_irqrestore(&info->lock,flags); 727} 728 729/* Return next bottom half action to perform. 730 * or 0 if nothing to do. 731 */ 732static int bh_action(MGSLPC_INFO *info) 733{ 734 unsigned long flags; 735 int rc = 0; 736 737 spin_lock_irqsave(&info->lock,flags); 738 739 if (info->pending_bh & BH_RECEIVE) { 740 info->pending_bh &= ~BH_RECEIVE; 741 rc = BH_RECEIVE; 742 } else if (info->pending_bh & BH_TRANSMIT) { 743 info->pending_bh &= ~BH_TRANSMIT; 744 rc = BH_TRANSMIT; 745 } else if (info->pending_bh & BH_STATUS) { 746 info->pending_bh &= ~BH_STATUS; 747 rc = BH_STATUS; 748 } 749 750 if (!rc) { 751 /* Mark BH routine as complete */ 752 info->bh_running = false; 753 info->bh_requested = false; 754 } 755 756 spin_unlock_irqrestore(&info->lock,flags); 757 758 return rc; 759} 760 761static void bh_handler(struct work_struct *work) 762{ 763 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task); 764 struct tty_struct *tty; 765 int action; 766 767 if (!info) 768 return; 769 770 if (debug_level >= DEBUG_LEVEL_BH) 771 printk( "%s(%d):bh_handler(%s) entry\n", 772 __FILE__,__LINE__,info->device_name); 773 774 info->bh_running = true; 775 tty = tty_port_tty_get(&info->port); 776 777 while((action = bh_action(info)) != 0) { 778 779 /* Process work item */ 780 if ( debug_level >= DEBUG_LEVEL_BH ) 781 printk( "%s(%d):bh_handler() work item action=%d\n", 782 __FILE__,__LINE__,action); 783 784 switch (action) { 785 786 case BH_RECEIVE: 787 while(rx_get_frame(info, tty)); 788 break; 789 case BH_TRANSMIT: 790 bh_transmit(info, tty); 791 break; 792 case BH_STATUS: 793 bh_status(info); 794 break; 795 default: 796 /* unknown work item ID */ 797 printk("Unknown work item ID=%08X!\n", action); 798 break; 799 } 800 } 801 802 tty_kref_put(tty); 803 if (debug_level >= DEBUG_LEVEL_BH) 804 printk( "%s(%d):bh_handler(%s) exit\n", 805 __FILE__,__LINE__,info->device_name); 806} 807 808static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty) 809{ 810 if (debug_level >= DEBUG_LEVEL_BH) 811 printk("bh_transmit() entry on %s\n", info->device_name); 812 813 if (tty) 814 tty_wakeup(tty); 815} 816 817static void bh_status(MGSLPC_INFO *info) 818{ 819 info->ri_chkcount = 0; 820 info->dsr_chkcount = 0; 821 info->dcd_chkcount = 0; 822 info->cts_chkcount = 0; 823} 824 825/* eom: non-zero = end of frame */ 826static void rx_ready_hdlc(MGSLPC_INFO *info, int eom) 827{ 828 unsigned char data[2]; 829 unsigned char fifo_count, read_count, i; 830 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size)); 831 832 if (debug_level >= DEBUG_LEVEL_ISR) 833 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom); 834 835 if (!info->rx_enabled) 836 return; 837 838 if (info->rx_frame_count >= info->rx_buf_count) { 839 /* no more free buffers */ 840 issue_command(info, CHA, CMD_RXRESET); 841 info->pending_bh |= BH_RECEIVE; 842 info->rx_overflow = true; 843 info->icount.buf_overrun++; 844 return; 845 } 846 847 if (eom) { 848 /* end of frame, get FIFO count from RBCL register */ 849 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f))) 850 fifo_count = 32; 851 } else 852 fifo_count = 32; 853 854 do { 855 if (fifo_count == 1) { 856 read_count = 1; 857 data[0] = read_reg(info, CHA + RXFIFO); 858 } else { 859 read_count = 2; 860 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO); 861 } 862 fifo_count -= read_count; 863 if (!fifo_count && eom) 864 buf->status = data[--read_count]; 865 866 for (i = 0; i < read_count; i++) { 867 if (buf->count >= info->max_frame_size) { 868 /* frame too large, reset receiver and reset current buffer */ 869 issue_command(info, CHA, CMD_RXRESET); 870 buf->count = 0; 871 return; 872 } 873 *(buf->data + buf->count) = data[i]; 874 buf->count++; 875 } 876 } while (fifo_count); 877 878 if (eom) { 879 info->pending_bh |= BH_RECEIVE; 880 info->rx_frame_count++; 881 info->rx_put++; 882 if (info->rx_put >= info->rx_buf_count) 883 info->rx_put = 0; 884 } 885 issue_command(info, CHA, CMD_RXFIFO); 886} 887 888static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty) 889{ 890 unsigned char data, status, flag; 891 int fifo_count; 892 int work = 0; 893 struct mgsl_icount *icount = &info->icount; 894 895 if (tcd) { 896 /* early termination, get FIFO count from RBCL register */ 897 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f); 898 899 /* Zero fifo count could mean 0 or 32 bytes available. 900 * If BIT5 of STAR is set then at least 1 byte is available. 901 */ 902 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) 903 fifo_count = 32; 904 } else 905 fifo_count = 32; 906 907 tty_buffer_request_room(tty, fifo_count); 908 /* Flush received async data to receive data buffer. */ 909 while (fifo_count) { 910 data = read_reg(info, CHA + RXFIFO); 911 status = read_reg(info, CHA + RXFIFO); 912 fifo_count -= 2; 913 914 icount->rx++; 915 flag = TTY_NORMAL; 916 917 // if no frameing/crc error then save data 918 // BIT7:parity error 919 // BIT6:framing error 920 921 if (status & (BIT7 + BIT6)) { 922 if (status & BIT7) 923 icount->parity++; 924 else 925 icount->frame++; 926 927 /* discard char if tty control flags say so */ 928 if (status & info->ignore_status_mask) 929 continue; 930 931 status &= info->read_status_mask; 932 933 if (status & BIT7) 934 flag = TTY_PARITY; 935 else if (status & BIT6) 936 flag = TTY_FRAME; 937 } 938 work += tty_insert_flip_char(tty, data, flag); 939 } 940 issue_command(info, CHA, CMD_RXFIFO); 941 942 if (debug_level >= DEBUG_LEVEL_ISR) { 943 printk("%s(%d):rx_ready_async", 944 __FILE__,__LINE__); 945 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n", 946 __FILE__,__LINE__,icount->rx,icount->brk, 947 icount->parity,icount->frame,icount->overrun); 948 } 949 950 if (work) 951 tty_flip_buffer_push(tty); 952} 953 954 955static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty) 956{ 957 if (!info->tx_active) 958 return; 959 960 info->tx_active = false; 961 info->tx_aborting = false; 962 963 if (info->params.mode == MGSL_MODE_ASYNC) 964 return; 965 966 info->tx_count = info->tx_put = info->tx_get = 0; 967 del_timer(&info->tx_timer); 968 969 if (info->drop_rts_on_tx_done) { 970 get_signals(info); 971 if (info->serial_signals & SerialSignal_RTS) { 972 info->serial_signals &= ~SerialSignal_RTS; 973 set_signals(info); 974 } 975 info->drop_rts_on_tx_done = false; 976 } 977 978#if SYNCLINK_GENERIC_HDLC 979 if (info->netcount) 980 hdlcdev_tx_done(info); 981 else 982#endif 983 { 984 if (tty->stopped || tty->hw_stopped) { 985 tx_stop(info); 986 return; 987 } 988 info->pending_bh |= BH_TRANSMIT; 989 } 990} 991 992static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty) 993{ 994 unsigned char fifo_count = 32; 995 int c; 996 997 if (debug_level >= DEBUG_LEVEL_ISR) 998 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name); 999 1000 if (info->params.mode == MGSL_MODE_HDLC) { 1001 if (!info->tx_active) 1002 return; 1003 } else { 1004 if (tty->stopped || tty->hw_stopped) { 1005 tx_stop(info); 1006 return; 1007 } 1008 if (!info->tx_count) 1009 info->tx_active = false; 1010 } 1011 1012 if (!info->tx_count) 1013 return; 1014 1015 while (info->tx_count && fifo_count) { 1016 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get))); 1017 1018 if (c == 1) { 1019 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get)); 1020 } else { 1021 write_reg16(info, CHA + TXFIFO, 1022 *((unsigned short*)(info->tx_buf + info->tx_get))); 1023 } 1024 info->tx_count -= c; 1025 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1); 1026 fifo_count -= c; 1027 } 1028 1029 if (info->params.mode == MGSL_MODE_ASYNC) { 1030 if (info->tx_count < WAKEUP_CHARS) 1031 info->pending_bh |= BH_TRANSMIT; 1032 issue_command(info, CHA, CMD_TXFIFO); 1033 } else { 1034 if (info->tx_count) 1035 issue_command(info, CHA, CMD_TXFIFO); 1036 else 1037 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM); 1038 } 1039} 1040 1041static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty) 1042{ 1043 get_signals(info); 1044 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) 1045 irq_disable(info, CHB, IRQ_CTS); 1046 info->icount.cts++; 1047 if (info->serial_signals & SerialSignal_CTS) 1048 info->input_signal_events.cts_up++; 1049 else 1050 info->input_signal_events.cts_down++; 1051 wake_up_interruptible(&info->status_event_wait_q); 1052 wake_up_interruptible(&info->event_wait_q); 1053 1054 if (info->port.flags & ASYNC_CTS_FLOW) { 1055 if (tty->hw_stopped) { 1056 if (info->serial_signals & SerialSignal_CTS) { 1057 if (debug_level >= DEBUG_LEVEL_ISR) 1058 printk("CTS tx start..."); 1059 if (tty) 1060 tty->hw_stopped = 0; 1061 tx_start(info, tty); 1062 info->pending_bh |= BH_TRANSMIT; 1063 return; 1064 } 1065 } else { 1066 if (!(info->serial_signals & SerialSignal_CTS)) { 1067 if (debug_level >= DEBUG_LEVEL_ISR) 1068 printk("CTS tx stop..."); 1069 if (tty) 1070 tty->hw_stopped = 1; 1071 tx_stop(info); 1072 } 1073 } 1074 } 1075 info->pending_bh |= BH_STATUS; 1076} 1077 1078static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty) 1079{ 1080 get_signals(info); 1081 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) 1082 irq_disable(info, CHB, IRQ_DCD); 1083 info->icount.dcd++; 1084 if (info->serial_signals & SerialSignal_DCD) { 1085 info->input_signal_events.dcd_up++; 1086 } 1087 else 1088 info->input_signal_events.dcd_down++; 1089#if SYNCLINK_GENERIC_HDLC 1090 if (info->netcount) { 1091 if (info->serial_signals & SerialSignal_DCD) 1092 netif_carrier_on(info->netdev); 1093 else 1094 netif_carrier_off(info->netdev); 1095 } 1096#endif 1097 wake_up_interruptible(&info->status_event_wait_q); 1098 wake_up_interruptible(&info->event_wait_q); 1099 1100 if (info->port.flags & ASYNC_CHECK_CD) { 1101 if (debug_level >= DEBUG_LEVEL_ISR) 1102 printk("%s CD now %s...", info->device_name, 1103 (info->serial_signals & SerialSignal_DCD) ? "on" : "off"); 1104 if (info->serial_signals & SerialSignal_DCD) 1105 wake_up_interruptible(&info->port.open_wait); 1106 else { 1107 if (debug_level >= DEBUG_LEVEL_ISR) 1108 printk("doing serial hangup..."); 1109 if (tty) 1110 tty_hangup(tty); 1111 } 1112 } 1113 info->pending_bh |= BH_STATUS; 1114} 1115 1116static void dsr_change(MGSLPC_INFO *info) 1117{ 1118 get_signals(info); 1119 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) 1120 port_irq_disable(info, PVR_DSR); 1121 info->icount.dsr++; 1122 if (info->serial_signals & SerialSignal_DSR) 1123 info->input_signal_events.dsr_up++; 1124 else 1125 info->input_signal_events.dsr_down++; 1126 wake_up_interruptible(&info->status_event_wait_q); 1127 wake_up_interruptible(&info->event_wait_q); 1128 info->pending_bh |= BH_STATUS; 1129} 1130 1131static void ri_change(MGSLPC_INFO *info) 1132{ 1133 get_signals(info); 1134 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) 1135 port_irq_disable(info, PVR_RI); 1136 info->icount.rng++; 1137 if (info->serial_signals & SerialSignal_RI) 1138 info->input_signal_events.ri_up++; 1139 else 1140 info->input_signal_events.ri_down++; 1141 wake_up_interruptible(&info->status_event_wait_q); 1142 wake_up_interruptible(&info->event_wait_q); 1143 info->pending_bh |= BH_STATUS; 1144} 1145 1146/* Interrupt service routine entry point. 1147 * 1148 * Arguments: 1149 * 1150 * irq interrupt number that caused interrupt 1151 * dev_id device ID supplied during interrupt registration 1152 */ 1153static irqreturn_t mgslpc_isr(int dummy, void *dev_id) 1154{ 1155 MGSLPC_INFO *info = dev_id; 1156 struct tty_struct *tty; 1157 unsigned short isr; 1158 unsigned char gis, pis; 1159 int count=0; 1160 1161 if (debug_level >= DEBUG_LEVEL_ISR) 1162 printk("mgslpc_isr(%d) entry.\n", info->irq_level); 1163 1164 if (!(info->p_dev->_locked)) 1165 return IRQ_HANDLED; 1166 1167 tty = tty_port_tty_get(&info->port); 1168 1169 spin_lock(&info->lock); 1170 1171 while ((gis = read_reg(info, CHA + GIS))) { 1172 if (debug_level >= DEBUG_LEVEL_ISR) 1173 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis); 1174 1175 if ((gis & 0x70) || count > 1000) { 1176 printk("synclink_cs:hardware failed or ejected\n"); 1177 break; 1178 } 1179 count++; 1180 1181 if (gis & (BIT1 + BIT0)) { 1182 isr = read_reg16(info, CHB + ISR); 1183 if (isr & IRQ_DCD) 1184 dcd_change(info, tty); 1185 if (isr & IRQ_CTS) 1186 cts_change(info, tty); 1187 } 1188 if (gis & (BIT3 + BIT2)) 1189 { 1190 isr = read_reg16(info, CHA + ISR); 1191 if (isr & IRQ_TIMER) { 1192 info->irq_occurred = true; 1193 irq_disable(info, CHA, IRQ_TIMER); 1194 } 1195 1196 /* receive IRQs */ 1197 if (isr & IRQ_EXITHUNT) { 1198 info->icount.exithunt++; 1199 wake_up_interruptible(&info->event_wait_q); 1200 } 1201 if (isr & IRQ_BREAK_ON) { 1202 info->icount.brk++; 1203 if (info->port.flags & ASYNC_SAK) 1204 do_SAK(tty); 1205 } 1206 if (isr & IRQ_RXTIME) { 1207 issue_command(info, CHA, CMD_RXFIFO_READ); 1208 } 1209 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) { 1210 if (info->params.mode == MGSL_MODE_HDLC) 1211 rx_ready_hdlc(info, isr & IRQ_RXEOM); 1212 else 1213 rx_ready_async(info, isr & IRQ_RXEOM, tty); 1214 } 1215 1216 /* transmit IRQs */ 1217 if (isr & IRQ_UNDERRUN) { 1218 if (info->tx_aborting) 1219 info->icount.txabort++; 1220 else 1221 info->icount.txunder++; 1222 tx_done(info, tty); 1223 } 1224 else if (isr & IRQ_ALLSENT) { 1225 info->icount.txok++; 1226 tx_done(info, tty); 1227 } 1228 else if (isr & IRQ_TXFIFO) 1229 tx_ready(info, tty); 1230 } 1231 if (gis & BIT7) { 1232 pis = read_reg(info, CHA + PIS); 1233 if (pis & BIT1) 1234 dsr_change(info); 1235 if (pis & BIT2) 1236 ri_change(info); 1237 } 1238 } 1239 1240 /* Request bottom half processing if there's something 1241 * for it to do and the bh is not already running 1242 */ 1243 1244 if (info->pending_bh && !info->bh_running && !info->bh_requested) { 1245 if ( debug_level >= DEBUG_LEVEL_ISR ) 1246 printk("%s(%d):%s queueing bh task.\n", 1247 __FILE__,__LINE__,info->device_name); 1248 schedule_work(&info->task); 1249 info->bh_requested = true; 1250 } 1251 1252 spin_unlock(&info->lock); 1253 tty_kref_put(tty); 1254 1255 if (debug_level >= DEBUG_LEVEL_ISR) 1256 printk("%s(%d):mgslpc_isr(%d)exit.\n", 1257 __FILE__, __LINE__, info->irq_level); 1258 1259 return IRQ_HANDLED; 1260} 1261 1262/* Initialize and start device. 1263 */ 1264static int startup(MGSLPC_INFO * info, struct tty_struct *tty) 1265{ 1266 int retval = 0; 1267 1268 if (debug_level >= DEBUG_LEVEL_INFO) 1269 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name); 1270 1271 if (info->port.flags & ASYNC_INITIALIZED) 1272 return 0; 1273 1274 if (!info->tx_buf) { 1275 /* allocate a page of memory for a transmit buffer */ 1276 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL); 1277 if (!info->tx_buf) { 1278 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", 1279 __FILE__,__LINE__,info->device_name); 1280 return -ENOMEM; 1281 } 1282 } 1283 1284 info->pending_bh = 0; 1285 1286 memset(&info->icount, 0, sizeof(info->icount)); 1287 1288 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 1289 1290 /* Allocate and claim adapter resources */ 1291 retval = claim_resources(info); 1292 1293 /* perform existence check and diagnostics */ 1294 if ( !retval ) 1295 retval = adapter_test(info); 1296 1297 if ( retval ) { 1298 if (capable(CAP_SYS_ADMIN) && tty) 1299 set_bit(TTY_IO_ERROR, &tty->flags); 1300 release_resources(info); 1301 return retval; 1302 } 1303 1304 /* program hardware for current parameters */ 1305 mgslpc_change_params(info, tty); 1306 1307 if (tty) 1308 clear_bit(TTY_IO_ERROR, &tty->flags); 1309 1310 info->port.flags |= ASYNC_INITIALIZED; 1311 1312 return 0; 1313} 1314 1315/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware 1316 */ 1317static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty) 1318{ 1319 unsigned long flags; 1320 1321 if (!(info->port.flags & ASYNC_INITIALIZED)) 1322 return; 1323 1324 if (debug_level >= DEBUG_LEVEL_INFO) 1325 printk("%s(%d):mgslpc_shutdown(%s)\n", 1326 __FILE__,__LINE__, info->device_name ); 1327 1328 /* clear status wait queue because status changes */ 1329 /* can't happen after shutting down the hardware */ 1330 wake_up_interruptible(&info->status_event_wait_q); 1331 wake_up_interruptible(&info->event_wait_q); 1332 1333 del_timer_sync(&info->tx_timer); 1334 1335 if (info->tx_buf) { 1336 free_page((unsigned long) info->tx_buf); 1337 info->tx_buf = NULL; 1338 } 1339 1340 spin_lock_irqsave(&info->lock,flags); 1341 1342 rx_stop(info); 1343 tx_stop(info); 1344 1345 /* TODO:disable interrupts instead of reset to preserve signal states */ 1346 reset_device(info); 1347 1348 if (!tty || tty->termios->c_cflag & HUPCL) { 1349 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); 1350 set_signals(info); 1351 } 1352 1353 spin_unlock_irqrestore(&info->lock,flags); 1354 1355 release_resources(info); 1356 1357 if (tty) 1358 set_bit(TTY_IO_ERROR, &tty->flags); 1359 1360 info->port.flags &= ~ASYNC_INITIALIZED; 1361} 1362 1363static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty) 1364{ 1365 unsigned long flags; 1366 1367 spin_lock_irqsave(&info->lock,flags); 1368 1369 rx_stop(info); 1370 tx_stop(info); 1371 info->tx_count = info->tx_put = info->tx_get = 0; 1372 1373 if (info->params.mode == MGSL_MODE_HDLC || info->netcount) 1374 hdlc_mode(info); 1375 else 1376 async_mode(info); 1377 1378 set_signals(info); 1379 1380 info->dcd_chkcount = 0; 1381 info->cts_chkcount = 0; 1382 info->ri_chkcount = 0; 1383 info->dsr_chkcount = 0; 1384 1385 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); 1386 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI); 1387 get_signals(info); 1388 1389 if (info->netcount || (tty && (tty->termios->c_cflag & CREAD))) 1390 rx_start(info); 1391 1392 spin_unlock_irqrestore(&info->lock,flags); 1393} 1394 1395/* Reconfigure adapter based on new parameters 1396 */ 1397static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty) 1398{ 1399 unsigned cflag; 1400 int bits_per_char; 1401 1402 if (!tty || !tty->termios) 1403 return; 1404 1405 if (debug_level >= DEBUG_LEVEL_INFO) 1406 printk("%s(%d):mgslpc_change_params(%s)\n", 1407 __FILE__,__LINE__, info->device_name ); 1408 1409 cflag = tty->termios->c_cflag; 1410 1411 /* if B0 rate (hangup) specified then negate DTR and RTS */ 1412 /* otherwise assert DTR and RTS */ 1413 if (cflag & CBAUD) 1414 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 1415 else 1416 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); 1417 1418 /* byte size and parity */ 1419 1420 switch (cflag & CSIZE) { 1421 case CS5: info->params.data_bits = 5; break; 1422 case CS6: info->params.data_bits = 6; break; 1423 case CS7: info->params.data_bits = 7; break; 1424 case CS8: info->params.data_bits = 8; break; 1425 default: info->params.data_bits = 7; break; 1426 } 1427 1428 if (cflag & CSTOPB) 1429 info->params.stop_bits = 2; 1430 else 1431 info->params.stop_bits = 1; 1432 1433 info->params.parity = ASYNC_PARITY_NONE; 1434 if (cflag & PARENB) { 1435 if (cflag & PARODD) 1436 info->params.parity = ASYNC_PARITY_ODD; 1437 else 1438 info->params.parity = ASYNC_PARITY_EVEN; 1439#ifdef CMSPAR 1440 if (cflag & CMSPAR) 1441 info->params.parity = ASYNC_PARITY_SPACE; 1442#endif 1443 } 1444 1445 /* calculate number of jiffies to transmit a full 1446 * FIFO (32 bytes) at specified data rate 1447 */ 1448 bits_per_char = info->params.data_bits + 1449 info->params.stop_bits + 1; 1450 1451 /* if port data rate is set to 460800 or less then 1452 * allow tty settings to override, otherwise keep the 1453 * current data rate. 1454 */ 1455 if (info->params.data_rate <= 460800) { 1456 info->params.data_rate = tty_get_baud_rate(tty); 1457 } 1458 1459 if ( info->params.data_rate ) { 1460 info->timeout = (32*HZ*bits_per_char) / 1461 info->params.data_rate; 1462 } 1463 info->timeout += HZ/50; /* Add .02 seconds of slop */ 1464 1465 if (cflag & CRTSCTS) 1466 info->port.flags |= ASYNC_CTS_FLOW; 1467 else 1468 info->port.flags &= ~ASYNC_CTS_FLOW; 1469 1470 if (cflag & CLOCAL) 1471 info->port.flags &= ~ASYNC_CHECK_CD; 1472 else 1473 info->port.flags |= ASYNC_CHECK_CD; 1474 1475 /* process tty input control flags */ 1476 1477 info->read_status_mask = 0; 1478 if (I_INPCK(tty)) 1479 info->read_status_mask |= BIT7 | BIT6; 1480 if (I_IGNPAR(tty)) 1481 info->ignore_status_mask |= BIT7 | BIT6; 1482 1483 mgslpc_program_hw(info, tty); 1484} 1485 1486/* Add a character to the transmit buffer 1487 */ 1488static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch) 1489{ 1490 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1491 unsigned long flags; 1492 1493 if (debug_level >= DEBUG_LEVEL_INFO) { 1494 printk( "%s(%d):mgslpc_put_char(%d) on %s\n", 1495 __FILE__,__LINE__,ch,info->device_name); 1496 } 1497 1498 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char")) 1499 return 0; 1500 1501 if (!info->tx_buf) 1502 return 0; 1503 1504 spin_lock_irqsave(&info->lock,flags); 1505 1506 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) { 1507 if (info->tx_count < TXBUFSIZE - 1) { 1508 info->tx_buf[info->tx_put++] = ch; 1509 info->tx_put &= TXBUFSIZE-1; 1510 info->tx_count++; 1511 } 1512 } 1513 1514 spin_unlock_irqrestore(&info->lock,flags); 1515 return 1; 1516} 1517 1518/* Enable transmitter so remaining characters in the 1519 * transmit buffer are sent. 1520 */ 1521static void mgslpc_flush_chars(struct tty_struct *tty) 1522{ 1523 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1524 unsigned long flags; 1525 1526 if (debug_level >= DEBUG_LEVEL_INFO) 1527 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n", 1528 __FILE__,__LINE__,info->device_name,info->tx_count); 1529 1530 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars")) 1531 return; 1532 1533 if (info->tx_count <= 0 || tty->stopped || 1534 tty->hw_stopped || !info->tx_buf) 1535 return; 1536 1537 if (debug_level >= DEBUG_LEVEL_INFO) 1538 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n", 1539 __FILE__,__LINE__,info->device_name); 1540 1541 spin_lock_irqsave(&info->lock,flags); 1542 if (!info->tx_active) 1543 tx_start(info, tty); 1544 spin_unlock_irqrestore(&info->lock,flags); 1545} 1546 1547/* Send a block of data 1548 * 1549 * Arguments: 1550 * 1551 * tty pointer to tty information structure 1552 * buf pointer to buffer containing send data 1553 * count size of send data in bytes 1554 * 1555 * Returns: number of characters written 1556 */ 1557static int mgslpc_write(struct tty_struct * tty, 1558 const unsigned char *buf, int count) 1559{ 1560 int c, ret = 0; 1561 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1562 unsigned long flags; 1563 1564 if (debug_level >= DEBUG_LEVEL_INFO) 1565 printk( "%s(%d):mgslpc_write(%s) count=%d\n", 1566 __FILE__,__LINE__,info->device_name,count); 1567 1568 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") || 1569 !info->tx_buf) 1570 goto cleanup; 1571 1572 if (info->params.mode == MGSL_MODE_HDLC) { 1573 if (count > TXBUFSIZE) { 1574 ret = -EIO; 1575 goto cleanup; 1576 } 1577 if (info->tx_active) 1578 goto cleanup; 1579 else if (info->tx_count) 1580 goto start; 1581 } 1582 1583 for (;;) { 1584 c = min(count, 1585 min(TXBUFSIZE - info->tx_count - 1, 1586 TXBUFSIZE - info->tx_put)); 1587 if (c <= 0) 1588 break; 1589 1590 memcpy(info->tx_buf + info->tx_put, buf, c); 1591 1592 spin_lock_irqsave(&info->lock,flags); 1593 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1); 1594 info->tx_count += c; 1595 spin_unlock_irqrestore(&info->lock,flags); 1596 1597 buf += c; 1598 count -= c; 1599 ret += c; 1600 } 1601start: 1602 if (info->tx_count && !tty->stopped && !tty->hw_stopped) { 1603 spin_lock_irqsave(&info->lock,flags); 1604 if (!info->tx_active) 1605 tx_start(info, tty); 1606 spin_unlock_irqrestore(&info->lock,flags); 1607 } 1608cleanup: 1609 if (debug_level >= DEBUG_LEVEL_INFO) 1610 printk( "%s(%d):mgslpc_write(%s) returning=%d\n", 1611 __FILE__,__LINE__,info->device_name,ret); 1612 return ret; 1613} 1614 1615/* Return the count of free bytes in transmit buffer 1616 */ 1617static int mgslpc_write_room(struct tty_struct *tty) 1618{ 1619 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1620 int ret; 1621 1622 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room")) 1623 return 0; 1624 1625 if (info->params.mode == MGSL_MODE_HDLC) { 1626 /* HDLC (frame oriented) mode */ 1627 if (info->tx_active) 1628 return 0; 1629 else 1630 return HDLC_MAX_FRAME_SIZE; 1631 } else { 1632 ret = TXBUFSIZE - info->tx_count - 1; 1633 if (ret < 0) 1634 ret = 0; 1635 } 1636 1637 if (debug_level >= DEBUG_LEVEL_INFO) 1638 printk("%s(%d):mgslpc_write_room(%s)=%d\n", 1639 __FILE__,__LINE__, info->device_name, ret); 1640 return ret; 1641} 1642 1643/* Return the count of bytes in transmit buffer 1644 */ 1645static int mgslpc_chars_in_buffer(struct tty_struct *tty) 1646{ 1647 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1648 int rc; 1649 1650 if (debug_level >= DEBUG_LEVEL_INFO) 1651 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n", 1652 __FILE__,__LINE__, info->device_name ); 1653 1654 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer")) 1655 return 0; 1656 1657 if (info->params.mode == MGSL_MODE_HDLC) 1658 rc = info->tx_active ? info->max_frame_size : 0; 1659 else 1660 rc = info->tx_count; 1661 1662 if (debug_level >= DEBUG_LEVEL_INFO) 1663 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n", 1664 __FILE__,__LINE__, info->device_name, rc); 1665 1666 return rc; 1667} 1668 1669/* Discard all data in the send buffer 1670 */ 1671static void mgslpc_flush_buffer(struct tty_struct *tty) 1672{ 1673 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1674 unsigned long flags; 1675 1676 if (debug_level >= DEBUG_LEVEL_INFO) 1677 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n", 1678 __FILE__,__LINE__, info->device_name ); 1679 1680 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer")) 1681 return; 1682 1683 spin_lock_irqsave(&info->lock,flags); 1684 info->tx_count = info->tx_put = info->tx_get = 0; 1685 del_timer(&info->tx_timer); 1686 spin_unlock_irqrestore(&info->lock,flags); 1687 1688 wake_up_interruptible(&tty->write_wait); 1689 tty_wakeup(tty); 1690} 1691 1692/* Send a high-priority XON/XOFF character 1693 */ 1694static void mgslpc_send_xchar(struct tty_struct *tty, char ch) 1695{ 1696 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1697 unsigned long flags; 1698 1699 if (debug_level >= DEBUG_LEVEL_INFO) 1700 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n", 1701 __FILE__,__LINE__, info->device_name, ch ); 1702 1703 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar")) 1704 return; 1705 1706 info->x_char = ch; 1707 if (ch) { 1708 spin_lock_irqsave(&info->lock,flags); 1709 if (!info->tx_enabled) 1710 tx_start(info, tty); 1711 spin_unlock_irqrestore(&info->lock,flags); 1712 } 1713} 1714 1715/* Signal remote device to throttle send data (our receive data) 1716 */ 1717static void mgslpc_throttle(struct tty_struct * tty) 1718{ 1719 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1720 unsigned long flags; 1721 1722 if (debug_level >= DEBUG_LEVEL_INFO) 1723 printk("%s(%d):mgslpc_throttle(%s) entry\n", 1724 __FILE__,__LINE__, info->device_name ); 1725 1726 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle")) 1727 return; 1728 1729 if (I_IXOFF(tty)) 1730 mgslpc_send_xchar(tty, STOP_CHAR(tty)); 1731 1732 if (tty->termios->c_cflag & CRTSCTS) { 1733 spin_lock_irqsave(&info->lock,flags); 1734 info->serial_signals &= ~SerialSignal_RTS; 1735 set_signals(info); 1736 spin_unlock_irqrestore(&info->lock,flags); 1737 } 1738} 1739 1740/* Signal remote device to stop throttling send data (our receive data) 1741 */ 1742static void mgslpc_unthrottle(struct tty_struct * tty) 1743{ 1744 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 1745 unsigned long flags; 1746 1747 if (debug_level >= DEBUG_LEVEL_INFO) 1748 printk("%s(%d):mgslpc_unthrottle(%s) entry\n", 1749 __FILE__,__LINE__, info->device_name ); 1750 1751 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle")) 1752 return; 1753 1754 if (I_IXOFF(tty)) { 1755 if (info->x_char) 1756 info->x_char = 0; 1757 else 1758 mgslpc_send_xchar(tty, START_CHAR(tty)); 1759 } 1760 1761 if (tty->termios->c_cflag & CRTSCTS) { 1762 spin_lock_irqsave(&info->lock,flags); 1763 info->serial_signals |= SerialSignal_RTS; 1764 set_signals(info); 1765 spin_unlock_irqrestore(&info->lock,flags); 1766 } 1767} 1768 1769/* get the current serial statistics 1770 */ 1771static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount) 1772{ 1773 int err; 1774 if (debug_level >= DEBUG_LEVEL_INFO) 1775 printk("get_params(%s)\n", info->device_name); 1776 if (!user_icount) { 1777 memset(&info->icount, 0, sizeof(info->icount)); 1778 } else { 1779 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); 1780 if (err) 1781 return -EFAULT; 1782 } 1783 return 0; 1784} 1785 1786/* get the current serial parameters 1787 */ 1788static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params) 1789{ 1790 int err; 1791 if (debug_level >= DEBUG_LEVEL_INFO) 1792 printk("get_params(%s)\n", info->device_name); 1793 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); 1794 if (err) 1795 return -EFAULT; 1796 return 0; 1797} 1798 1799/* set the serial parameters 1800 * 1801 * Arguments: 1802 * 1803 * info pointer to device instance data 1804 * new_params user buffer containing new serial params 1805 * 1806 * Returns: 0 if success, otherwise error code 1807 */ 1808static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty) 1809{ 1810 unsigned long flags; 1811 MGSL_PARAMS tmp_params; 1812 int err; 1813 1814 if (debug_level >= DEBUG_LEVEL_INFO) 1815 printk("%s(%d):set_params %s\n", __FILE__,__LINE__, 1816 info->device_name ); 1817 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); 1818 if (err) { 1819 if ( debug_level >= DEBUG_LEVEL_INFO ) 1820 printk( "%s(%d):set_params(%s) user buffer copy failed\n", 1821 __FILE__,__LINE__,info->device_name); 1822 return -EFAULT; 1823 } 1824 1825 spin_lock_irqsave(&info->lock,flags); 1826 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); 1827 spin_unlock_irqrestore(&info->lock,flags); 1828 1829 mgslpc_change_params(info, tty); 1830 1831 return 0; 1832} 1833 1834static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode) 1835{ 1836 int err; 1837 if (debug_level >= DEBUG_LEVEL_INFO) 1838 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode); 1839 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); 1840 if (err) 1841 return -EFAULT; 1842 return 0; 1843} 1844 1845static int set_txidle(MGSLPC_INFO * info, int idle_mode) 1846{ 1847 unsigned long flags; 1848 if (debug_level >= DEBUG_LEVEL_INFO) 1849 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode); 1850 spin_lock_irqsave(&info->lock,flags); 1851 info->idle_mode = idle_mode; 1852 tx_set_idle(info); 1853 spin_unlock_irqrestore(&info->lock,flags); 1854 return 0; 1855} 1856 1857static int get_interface(MGSLPC_INFO * info, int __user *if_mode) 1858{ 1859 int err; 1860 if (debug_level >= DEBUG_LEVEL_INFO) 1861 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode); 1862 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int)); 1863 if (err) 1864 return -EFAULT; 1865 return 0; 1866} 1867 1868static int set_interface(MGSLPC_INFO * info, int if_mode) 1869{ 1870 unsigned long flags; 1871 unsigned char val; 1872 if (debug_level >= DEBUG_LEVEL_INFO) 1873 printk("set_interface(%s,%d)\n", info->device_name, if_mode); 1874 spin_lock_irqsave(&info->lock,flags); 1875 info->if_mode = if_mode; 1876 1877 val = read_reg(info, PVR) & 0x0f; 1878 switch (info->if_mode) 1879 { 1880 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break; 1881 case MGSL_INTERFACE_V35: val |= PVR_V35; break; 1882 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break; 1883 } 1884 write_reg(info, PVR, val); 1885 1886 spin_unlock_irqrestore(&info->lock,flags); 1887 return 0; 1888} 1889 1890static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty) 1891{ 1892 unsigned long flags; 1893 1894 if (debug_level >= DEBUG_LEVEL_INFO) 1895 printk("set_txenable(%s,%d)\n", info->device_name, enable); 1896 1897 spin_lock_irqsave(&info->lock,flags); 1898 if (enable) { 1899 if (!info->tx_enabled) 1900 tx_start(info, tty); 1901 } else { 1902 if (info->tx_enabled) 1903 tx_stop(info); 1904 } 1905 spin_unlock_irqrestore(&info->lock,flags); 1906 return 0; 1907} 1908 1909static int tx_abort(MGSLPC_INFO * info) 1910{ 1911 unsigned long flags; 1912 1913 if (debug_level >= DEBUG_LEVEL_INFO) 1914 printk("tx_abort(%s)\n", info->device_name); 1915 1916 spin_lock_irqsave(&info->lock,flags); 1917 if (info->tx_active && info->tx_count && 1918 info->params.mode == MGSL_MODE_HDLC) { 1919 /* clear data count so FIFO is not filled on next IRQ. 1920 * This results in underrun and abort transmission. 1921 */ 1922 info->tx_count = info->tx_put = info->tx_get = 0; 1923 info->tx_aborting = true; 1924 } 1925 spin_unlock_irqrestore(&info->lock,flags); 1926 return 0; 1927} 1928 1929static int set_rxenable(MGSLPC_INFO * info, int enable) 1930{ 1931 unsigned long flags; 1932 1933 if (debug_level >= DEBUG_LEVEL_INFO) 1934 printk("set_rxenable(%s,%d)\n", info->device_name, enable); 1935 1936 spin_lock_irqsave(&info->lock,flags); 1937 if (enable) { 1938 if (!info->rx_enabled) 1939 rx_start(info); 1940 } else { 1941 if (info->rx_enabled) 1942 rx_stop(info); 1943 } 1944 spin_unlock_irqrestore(&info->lock,flags); 1945 return 0; 1946} 1947 1948/* wait for specified event to occur 1949 * 1950 * Arguments: info pointer to device instance data 1951 * mask pointer to bitmask of events to wait for 1952 * Return Value: 0 if successful and bit mask updated with 1953 * of events triggerred, 1954 * otherwise error code 1955 */ 1956static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr) 1957{ 1958 unsigned long flags; 1959 int s; 1960 int rc=0; 1961 struct mgsl_icount cprev, cnow; 1962 int events; 1963 int mask; 1964 struct _input_signal_events oldsigs, newsigs; 1965 DECLARE_WAITQUEUE(wait, current); 1966 1967 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); 1968 if (rc) 1969 return -EFAULT; 1970 1971 if (debug_level >= DEBUG_LEVEL_INFO) 1972 printk("wait_events(%s,%d)\n", info->device_name, mask); 1973 1974 spin_lock_irqsave(&info->lock,flags); 1975 1976 /* return immediately if state matches requested events */ 1977 get_signals(info); 1978 s = info->serial_signals; 1979 events = mask & 1980 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 1981 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 1982 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 1983 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 1984 if (events) { 1985 spin_unlock_irqrestore(&info->lock,flags); 1986 goto exit; 1987 } 1988 1989 /* save current irq counts */ 1990 cprev = info->icount; 1991 oldsigs = info->input_signal_events; 1992 1993 if ((info->params.mode == MGSL_MODE_HDLC) && 1994 (mask & MgslEvent_ExitHuntMode)) 1995 irq_enable(info, CHA, IRQ_EXITHUNT); 1996 1997 set_current_state(TASK_INTERRUPTIBLE); 1998 add_wait_queue(&info->event_wait_q, &wait); 1999 2000 spin_unlock_irqrestore(&info->lock,flags); 2001 2002 2003 for(;;) { 2004 schedule(); 2005 if (signal_pending(current)) { 2006 rc = -ERESTARTSYS; 2007 break; 2008 } 2009 2010 /* get current irq counts */ 2011 spin_lock_irqsave(&info->lock,flags); 2012 cnow = info->icount; 2013 newsigs = info->input_signal_events; 2014 set_current_state(TASK_INTERRUPTIBLE); 2015 spin_unlock_irqrestore(&info->lock,flags); 2016 2017 /* if no change, wait aborted for some reason */ 2018 if (newsigs.dsr_up == oldsigs.dsr_up && 2019 newsigs.dsr_down == oldsigs.dsr_down && 2020 newsigs.dcd_up == oldsigs.dcd_up && 2021 newsigs.dcd_down == oldsigs.dcd_down && 2022 newsigs.cts_up == oldsigs.cts_up && 2023 newsigs.cts_down == oldsigs.cts_down && 2024 newsigs.ri_up == oldsigs.ri_up && 2025 newsigs.ri_down == oldsigs.ri_down && 2026 cnow.exithunt == cprev.exithunt && 2027 cnow.rxidle == cprev.rxidle) { 2028 rc = -EIO; 2029 break; 2030 } 2031 2032 events = mask & 2033 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2034 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2035 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2036 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2037 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2038 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2039 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2040 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2041 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2042 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2043 if (events) 2044 break; 2045 2046 cprev = cnow; 2047 oldsigs = newsigs; 2048 } 2049 2050 remove_wait_queue(&info->event_wait_q, &wait); 2051 set_current_state(TASK_RUNNING); 2052 2053 if (mask & MgslEvent_ExitHuntMode) { 2054 spin_lock_irqsave(&info->lock,flags); 2055 if (!waitqueue_active(&info->event_wait_q)) 2056 irq_disable(info, CHA, IRQ_EXITHUNT); 2057 spin_unlock_irqrestore(&info->lock,flags); 2058 } 2059exit: 2060 if (rc == 0) 2061 PUT_USER(rc, events, mask_ptr); 2062 return rc; 2063} 2064 2065static int modem_input_wait(MGSLPC_INFO *info,int arg) 2066{ 2067 unsigned long flags; 2068 int rc; 2069 struct mgsl_icount cprev, cnow; 2070 DECLARE_WAITQUEUE(wait, current); 2071 2072 /* save current irq counts */ 2073 spin_lock_irqsave(&info->lock,flags); 2074 cprev = info->icount; 2075 add_wait_queue(&info->status_event_wait_q, &wait); 2076 set_current_state(TASK_INTERRUPTIBLE); 2077 spin_unlock_irqrestore(&info->lock,flags); 2078 2079 for(;;) { 2080 schedule(); 2081 if (signal_pending(current)) { 2082 rc = -ERESTARTSYS; 2083 break; 2084 } 2085 2086 /* get new irq counts */ 2087 spin_lock_irqsave(&info->lock,flags); 2088 cnow = info->icount; 2089 set_current_state(TASK_INTERRUPTIBLE); 2090 spin_unlock_irqrestore(&info->lock,flags); 2091 2092 /* if no change, wait aborted for some reason */ 2093 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 2094 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 2095 rc = -EIO; 2096 break; 2097 } 2098 2099 /* check for change in caller specified modem input */ 2100 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 2101 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 2102 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 2103 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 2104 rc = 0; 2105 break; 2106 } 2107 2108 cprev = cnow; 2109 } 2110 remove_wait_queue(&info->status_event_wait_q, &wait); 2111 set_current_state(TASK_RUNNING); 2112 return rc; 2113} 2114 2115/* return the state of the serial control and status signals 2116 */ 2117static int tiocmget(struct tty_struct *tty) 2118{ 2119 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 2120 unsigned int result; 2121 unsigned long flags; 2122 2123 spin_lock_irqsave(&info->lock,flags); 2124 get_signals(info); 2125 spin_unlock_irqrestore(&info->lock,flags); 2126 2127 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 2128 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 2129 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 2130 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + 2131 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 2132 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); 2133 2134 if (debug_level >= DEBUG_LEVEL_INFO) 2135 printk("%s(%d):%s tiocmget() value=%08X\n", 2136 __FILE__,__LINE__, info->device_name, result ); 2137 return result; 2138} 2139 2140/* set modem control signals (DTR/RTS) 2141 */ 2142static int tiocmset(struct tty_struct *tty, 2143 unsigned int set, unsigned int clear) 2144{ 2145 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 2146 unsigned long flags; 2147 2148 if (debug_level >= DEBUG_LEVEL_INFO) 2149 printk("%s(%d):%s tiocmset(%x,%x)\n", 2150 __FILE__,__LINE__,info->device_name, set, clear); 2151 2152 if (set & TIOCM_RTS) 2153 info->serial_signals |= SerialSignal_RTS; 2154 if (set & TIOCM_DTR) 2155 info->serial_signals |= SerialSignal_DTR; 2156 if (clear & TIOCM_RTS) 2157 info->serial_signals &= ~SerialSignal_RTS; 2158 if (clear & TIOCM_DTR) 2159 info->serial_signals &= ~SerialSignal_DTR; 2160 2161 spin_lock_irqsave(&info->lock,flags); 2162 set_signals(info); 2163 spin_unlock_irqrestore(&info->lock,flags); 2164 2165 return 0; 2166} 2167 2168/* Set or clear transmit break condition 2169 * 2170 * Arguments: tty pointer to tty instance data 2171 * break_state -1=set break condition, 0=clear 2172 */ 2173static int mgslpc_break(struct tty_struct *tty, int break_state) 2174{ 2175 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2176 unsigned long flags; 2177 2178 if (debug_level >= DEBUG_LEVEL_INFO) 2179 printk("%s(%d):mgslpc_break(%s,%d)\n", 2180 __FILE__,__LINE__, info->device_name, break_state); 2181 2182 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break")) 2183 return -EINVAL; 2184 2185 spin_lock_irqsave(&info->lock,flags); 2186 if (break_state == -1) 2187 set_reg_bits(info, CHA+DAFO, BIT6); 2188 else 2189 clear_reg_bits(info, CHA+DAFO, BIT6); 2190 spin_unlock_irqrestore(&info->lock,flags); 2191 return 0; 2192} 2193 2194static int mgslpc_get_icount(struct tty_struct *tty, 2195 struct serial_icounter_struct *icount) 2196{ 2197 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2198 struct mgsl_icount cnow; /* kernel counter temps */ 2199 unsigned long flags; 2200 2201 spin_lock_irqsave(&info->lock,flags); 2202 cnow = info->icount; 2203 spin_unlock_irqrestore(&info->lock,flags); 2204 2205 icount->cts = cnow.cts; 2206 icount->dsr = cnow.dsr; 2207 icount->rng = cnow.rng; 2208 icount->dcd = cnow.dcd; 2209 icount->rx = cnow.rx; 2210 icount->tx = cnow.tx; 2211 icount->frame = cnow.frame; 2212 icount->overrun = cnow.overrun; 2213 icount->parity = cnow.parity; 2214 icount->brk = cnow.brk; 2215 icount->buf_overrun = cnow.buf_overrun; 2216 2217 return 0; 2218} 2219 2220/* Service an IOCTL request 2221 * 2222 * Arguments: 2223 * 2224 * tty pointer to tty instance data 2225 * cmd IOCTL command code 2226 * arg command argument/context 2227 * 2228 * Return Value: 0 if success, otherwise error code 2229 */ 2230static int mgslpc_ioctl(struct tty_struct *tty, 2231 unsigned int cmd, unsigned long arg) 2232{ 2233 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2234 void __user *argp = (void __user *)arg; 2235 2236 if (debug_level >= DEBUG_LEVEL_INFO) 2237 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__, 2238 info->device_name, cmd ); 2239 2240 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl")) 2241 return -ENODEV; 2242 2243 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 2244 (cmd != TIOCMIWAIT)) { 2245 if (tty->flags & (1 << TTY_IO_ERROR)) 2246 return -EIO; 2247 } 2248 2249 switch (cmd) { 2250 case MGSL_IOCGPARAMS: 2251 return get_params(info, argp); 2252 case MGSL_IOCSPARAMS: 2253 return set_params(info, argp, tty); 2254 case MGSL_IOCGTXIDLE: 2255 return get_txidle(info, argp); 2256 case MGSL_IOCSTXIDLE: 2257 return set_txidle(info, (int)arg); 2258 case MGSL_IOCGIF: 2259 return get_interface(info, argp); 2260 case MGSL_IOCSIF: 2261 return set_interface(info,(int)arg); 2262 case MGSL_IOCTXENABLE: 2263 return set_txenable(info,(int)arg, tty); 2264 case MGSL_IOCRXENABLE: 2265 return set_rxenable(info,(int)arg); 2266 case MGSL_IOCTXABORT: 2267 return tx_abort(info); 2268 case MGSL_IOCGSTATS: 2269 return get_stats(info, argp); 2270 case MGSL_IOCWAITEVENT: 2271 return wait_events(info, argp); 2272 case TIOCMIWAIT: 2273 return modem_input_wait(info,(int)arg); 2274 default: 2275 return -ENOIOCTLCMD; 2276 } 2277 return 0; 2278} 2279 2280/* Set new termios settings 2281 * 2282 * Arguments: 2283 * 2284 * tty pointer to tty structure 2285 * termios pointer to buffer to hold returned old termios 2286 */ 2287static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 2288{ 2289 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data; 2290 unsigned long flags; 2291 2292 if (debug_level >= DEBUG_LEVEL_INFO) 2293 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__, 2294 tty->driver->name ); 2295 2296 /* just return if nothing has changed */ 2297 if ((tty->termios->c_cflag == old_termios->c_cflag) 2298 && (RELEVANT_IFLAG(tty->termios->c_iflag) 2299 == RELEVANT_IFLAG(old_termios->c_iflag))) 2300 return; 2301 2302 mgslpc_change_params(info, tty); 2303 2304 /* Handle transition to B0 status */ 2305 if (old_termios->c_cflag & CBAUD && 2306 !(tty->termios->c_cflag & CBAUD)) { 2307 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); 2308 spin_lock_irqsave(&info->lock,flags); 2309 set_signals(info); 2310 spin_unlock_irqrestore(&info->lock,flags); 2311 } 2312 2313 /* Handle transition away from B0 status */ 2314 if (!(old_termios->c_cflag & CBAUD) && 2315 tty->termios->c_cflag & CBAUD) { 2316 info->serial_signals |= SerialSignal_DTR; 2317 if (!(tty->termios->c_cflag & CRTSCTS) || 2318 !test_bit(TTY_THROTTLED, &tty->flags)) { 2319 info->serial_signals |= SerialSignal_RTS; 2320 } 2321 spin_lock_irqsave(&info->lock,flags); 2322 set_signals(info); 2323 spin_unlock_irqrestore(&info->lock,flags); 2324 } 2325 2326 /* Handle turning off CRTSCTS */ 2327 if (old_termios->c_cflag & CRTSCTS && 2328 !(tty->termios->c_cflag & CRTSCTS)) { 2329 tty->hw_stopped = 0; 2330 tx_release(tty); 2331 } 2332} 2333 2334static void mgslpc_close(struct tty_struct *tty, struct file * filp) 2335{ 2336 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2337 struct tty_port *port = &info->port; 2338 2339 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close")) 2340 return; 2341 2342 if (debug_level >= DEBUG_LEVEL_INFO) 2343 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n", 2344 __FILE__,__LINE__, info->device_name, port->count); 2345 2346 WARN_ON(!port->count); 2347 2348 if (tty_port_close_start(port, tty, filp) == 0) 2349 goto cleanup; 2350 2351 if (port->flags & ASYNC_INITIALIZED) 2352 mgslpc_wait_until_sent(tty, info->timeout); 2353 2354 mgslpc_flush_buffer(tty); 2355 2356 tty_ldisc_flush(tty); 2357 shutdown(info, tty); 2358 2359 tty_port_close_end(port, tty); 2360 tty_port_tty_set(port, NULL); 2361cleanup: 2362 if (debug_level >= DEBUG_LEVEL_INFO) 2363 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__, 2364 tty->driver->name, port->count); 2365} 2366 2367/* Wait until the transmitter is empty. 2368 */ 2369static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout) 2370{ 2371 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2372 unsigned long orig_jiffies, char_time; 2373 2374 if (!info ) 2375 return; 2376 2377 if (debug_level >= DEBUG_LEVEL_INFO) 2378 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n", 2379 __FILE__,__LINE__, info->device_name ); 2380 2381 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent")) 2382 return; 2383 2384 if (!(info->port.flags & ASYNC_INITIALIZED)) 2385 goto exit; 2386 2387 orig_jiffies = jiffies; 2388 2389 /* Set check interval to 1/5 of estimated time to 2390 * send a character, and make it at least 1. The check 2391 * interval should also be less than the timeout. 2392 * Note: use tight timings here to satisfy the NIST-PCTS. 2393 */ 2394 2395 if ( info->params.data_rate ) { 2396 char_time = info->timeout/(32 * 5); 2397 if (!char_time) 2398 char_time++; 2399 } else 2400 char_time = 1; 2401 2402 if (timeout) 2403 char_time = min_t(unsigned long, char_time, timeout); 2404 2405 if (info->params.mode == MGSL_MODE_HDLC) { 2406 while (info->tx_active) { 2407 msleep_interruptible(jiffies_to_msecs(char_time)); 2408 if (signal_pending(current)) 2409 break; 2410 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 2411 break; 2412 } 2413 } else { 2414 while ((info->tx_count || info->tx_active) && 2415 info->tx_enabled) { 2416 msleep_interruptible(jiffies_to_msecs(char_time)); 2417 if (signal_pending(current)) 2418 break; 2419 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 2420 break; 2421 } 2422 } 2423 2424exit: 2425 if (debug_level >= DEBUG_LEVEL_INFO) 2426 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n", 2427 __FILE__,__LINE__, info->device_name ); 2428} 2429 2430/* Called by tty_hangup() when a hangup is signaled. 2431 * This is the same as closing all open files for the port. 2432 */ 2433static void mgslpc_hangup(struct tty_struct *tty) 2434{ 2435 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data; 2436 2437 if (debug_level >= DEBUG_LEVEL_INFO) 2438 printk("%s(%d):mgslpc_hangup(%s)\n", 2439 __FILE__,__LINE__, info->device_name ); 2440 2441 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup")) 2442 return; 2443 2444 mgslpc_flush_buffer(tty); 2445 shutdown(info, tty); 2446 tty_port_hangup(&info->port); 2447} 2448 2449static int carrier_raised(struct tty_port *port) 2450{ 2451 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); 2452 unsigned long flags; 2453 2454 spin_lock_irqsave(&info->lock,flags); 2455 get_signals(info); 2456 spin_unlock_irqrestore(&info->lock,flags); 2457 2458 if (info->serial_signals & SerialSignal_DCD) 2459 return 1; 2460 return 0; 2461} 2462 2463static void dtr_rts(struct tty_port *port, int onoff) 2464{ 2465 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); 2466 unsigned long flags; 2467 2468 spin_lock_irqsave(&info->lock,flags); 2469 if (onoff) 2470 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 2471 else 2472 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR; 2473 set_signals(info); 2474 spin_unlock_irqrestore(&info->lock,flags); 2475} 2476 2477 2478static int mgslpc_open(struct tty_struct *tty, struct file * filp) 2479{ 2480 MGSLPC_INFO *info; 2481 struct tty_port *port; 2482 int retval, line; 2483 unsigned long flags; 2484 2485 /* verify range of specified line number */ 2486 line = tty->index; 2487 if ((line < 0) || (line >= mgslpc_device_count)) { 2488 printk("%s(%d):mgslpc_open with invalid line #%d.\n", 2489 __FILE__,__LINE__,line); 2490 return -ENODEV; 2491 } 2492 2493 /* find the info structure for the specified line */ 2494 info = mgslpc_device_list; 2495 while(info && info->line != line) 2496 info = info->next_device; 2497 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open")) 2498 return -ENODEV; 2499 2500 port = &info->port; 2501 tty->driver_data = info; 2502 tty_port_tty_set(port, tty); 2503 2504 if (debug_level >= DEBUG_LEVEL_INFO) 2505 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n", 2506 __FILE__,__LINE__,tty->driver->name, port->count); 2507 2508 /* If port is closing, signal caller to try again */ 2509 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){ 2510 if (port->flags & ASYNC_CLOSING) 2511 interruptible_sleep_on(&port->close_wait); 2512 retval = ((port->flags & ASYNC_HUP_NOTIFY) ? 2513 -EAGAIN : -ERESTARTSYS); 2514 goto cleanup; 2515 } 2516 2517 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0; 2518 2519 spin_lock_irqsave(&info->netlock, flags); 2520 if (info->netcount) { 2521 retval = -EBUSY; 2522 spin_unlock_irqrestore(&info->netlock, flags); 2523 goto cleanup; 2524 } 2525 spin_lock(&port->lock); 2526 port->count++; 2527 spin_unlock(&port->lock); 2528 spin_unlock_irqrestore(&info->netlock, flags); 2529 2530 if (port->count == 1) { 2531 /* 1st open on this device, init hardware */ 2532 retval = startup(info, tty); 2533 if (retval < 0) 2534 goto cleanup; 2535 } 2536 2537 retval = tty_port_block_til_ready(&info->port, tty, filp); 2538 if (retval) { 2539 if (debug_level >= DEBUG_LEVEL_INFO) 2540 printk("%s(%d):block_til_ready(%s) returned %d\n", 2541 __FILE__,__LINE__, info->device_name, retval); 2542 goto cleanup; 2543 } 2544 2545 if (debug_level >= DEBUG_LEVEL_INFO) 2546 printk("%s(%d):mgslpc_open(%s) success\n", 2547 __FILE__,__LINE__, info->device_name); 2548 retval = 0; 2549 2550cleanup: 2551 return retval; 2552} 2553 2554/* 2555 * /proc fs routines.... 2556 */ 2557 2558static inline void line_info(struct seq_file *m, MGSLPC_INFO *info) 2559{ 2560 char stat_buf[30]; 2561 unsigned long flags; 2562 2563 seq_printf(m, "%s:io:%04X irq:%d", 2564 info->device_name, info->io_base, info->irq_level); 2565 2566 /* output current serial signal states */ 2567 spin_lock_irqsave(&info->lock,flags); 2568 get_signals(info); 2569 spin_unlock_irqrestore(&info->lock,flags); 2570 2571 stat_buf[0] = 0; 2572 stat_buf[1] = 0; 2573 if (info->serial_signals & SerialSignal_RTS) 2574 strcat(stat_buf, "|RTS"); 2575 if (info->serial_signals & SerialSignal_CTS) 2576 strcat(stat_buf, "|CTS"); 2577 if (info->serial_signals & SerialSignal_DTR) 2578 strcat(stat_buf, "|DTR"); 2579 if (info->serial_signals & SerialSignal_DSR) 2580 strcat(stat_buf, "|DSR"); 2581 if (info->serial_signals & SerialSignal_DCD) 2582 strcat(stat_buf, "|CD"); 2583 if (info->serial_signals & SerialSignal_RI) 2584 strcat(stat_buf, "|RI"); 2585 2586 if (info->params.mode == MGSL_MODE_HDLC) { 2587 seq_printf(m, " HDLC txok:%d rxok:%d", 2588 info->icount.txok, info->icount.rxok); 2589 if (info->icount.txunder) 2590 seq_printf(m, " txunder:%d", info->icount.txunder); 2591 if (info->icount.txabort) 2592 seq_printf(m, " txabort:%d", info->icount.txabort); 2593 if (info->icount.rxshort) 2594 seq_printf(m, " rxshort:%d", info->icount.rxshort); 2595 if (info->icount.rxlong) 2596 seq_printf(m, " rxlong:%d", info->icount.rxlong); 2597 if (info->icount.rxover) 2598 seq_printf(m, " rxover:%d", info->icount.rxover); 2599 if (info->icount.rxcrc) 2600 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 2601 } else { 2602 seq_printf(m, " ASYNC tx:%d rx:%d", 2603 info->icount.tx, info->icount.rx); 2604 if (info->icount.frame) 2605 seq_printf(m, " fe:%d", info->icount.frame); 2606 if (info->icount.parity) 2607 seq_printf(m, " pe:%d", info->icount.parity); 2608 if (info->icount.brk) 2609 seq_printf(m, " brk:%d", info->icount.brk); 2610 if (info->icount.overrun) 2611 seq_printf(m, " oe:%d", info->icount.overrun); 2612 } 2613 2614 /* Append serial signal status to end */ 2615 seq_printf(m, " %s\n", stat_buf+1); 2616 2617 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 2618 info->tx_active,info->bh_requested,info->bh_running, 2619 info->pending_bh); 2620} 2621 2622/* Called to print information about devices 2623 */ 2624static int mgslpc_proc_show(struct seq_file *m, void *v) 2625{ 2626 MGSLPC_INFO *info; 2627 2628 seq_printf(m, "synclink driver:%s\n", driver_version); 2629 2630 info = mgslpc_device_list; 2631 while( info ) { 2632 line_info(m, info); 2633 info = info->next_device; 2634 } 2635 return 0; 2636} 2637 2638static int mgslpc_proc_open(struct inode *inode, struct file *file) 2639{ 2640 return single_open(file, mgslpc_proc_show, NULL); 2641} 2642 2643static const struct file_operations mgslpc_proc_fops = { 2644 .owner = THIS_MODULE, 2645 .open = mgslpc_proc_open, 2646 .read = seq_read, 2647 .llseek = seq_lseek, 2648 .release = single_release, 2649}; 2650 2651static int rx_alloc_buffers(MGSLPC_INFO *info) 2652{ 2653 /* each buffer has header and data */ 2654 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size; 2655 2656 /* calculate total allocation size for 8 buffers */ 2657 info->rx_buf_total_size = info->rx_buf_size * 8; 2658 2659 /* limit total allocated memory */ 2660 if (info->rx_buf_total_size > 0x10000) 2661 info->rx_buf_total_size = 0x10000; 2662 2663 /* calculate number of buffers */ 2664 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size; 2665 2666 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL); 2667 if (info->rx_buf == NULL) 2668 return -ENOMEM; 2669 2670 rx_reset_buffers(info); 2671 return 0; 2672} 2673 2674static void rx_free_buffers(MGSLPC_INFO *info) 2675{ 2676 kfree(info->rx_buf); 2677 info->rx_buf = NULL; 2678} 2679 2680static int claim_resources(MGSLPC_INFO *info) 2681{ 2682 if (rx_alloc_buffers(info) < 0 ) { 2683 printk( "Can't allocate rx buffer %s\n", info->device_name); 2684 release_resources(info); 2685 return -ENODEV; 2686 } 2687 return 0; 2688} 2689 2690static void release_resources(MGSLPC_INFO *info) 2691{ 2692 if (debug_level >= DEBUG_LEVEL_INFO) 2693 printk("release_resources(%s)\n", info->device_name); 2694 rx_free_buffers(info); 2695} 2696 2697/* Add the specified device instance data structure to the 2698 * global linked list of devices and increment the device count. 2699 * 2700 * Arguments: info pointer to device instance data 2701 */ 2702static void mgslpc_add_device(MGSLPC_INFO *info) 2703{ 2704 info->next_device = NULL; 2705 info->line = mgslpc_device_count; 2706 sprintf(info->device_name,"ttySLP%d",info->line); 2707 2708 if (info->line < MAX_DEVICE_COUNT) { 2709 if (maxframe[info->line]) 2710 info->max_frame_size = maxframe[info->line]; 2711 } 2712 2713 mgslpc_device_count++; 2714 2715 if (!mgslpc_device_list) 2716 mgslpc_device_list = info; 2717 else { 2718 MGSLPC_INFO *current_dev = mgslpc_device_list; 2719 while( current_dev->next_device ) 2720 current_dev = current_dev->next_device; 2721 current_dev->next_device = info; 2722 } 2723 2724 if (info->max_frame_size < 4096) 2725 info->max_frame_size = 4096; 2726 else if (info->max_frame_size > 65535) 2727 info->max_frame_size = 65535; 2728 2729 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n", 2730 info->device_name, info->io_base, info->irq_level); 2731 2732#if SYNCLINK_GENERIC_HDLC 2733 hdlcdev_init(info); 2734#endif 2735} 2736 2737static void mgslpc_remove_device(MGSLPC_INFO *remove_info) 2738{ 2739 MGSLPC_INFO *info = mgslpc_device_list; 2740 MGSLPC_INFO *last = NULL; 2741 2742 while(info) { 2743 if (info == remove_info) { 2744 if (last) 2745 last->next_device = info->next_device; 2746 else 2747 mgslpc_device_list = info->next_device; 2748#if SYNCLINK_GENERIC_HDLC 2749 hdlcdev_exit(info); 2750#endif 2751 release_resources(info); 2752 kfree(info); 2753 mgslpc_device_count--; 2754 return; 2755 } 2756 last = info; 2757 info = info->next_device; 2758 } 2759} 2760 2761static struct pcmcia_device_id mgslpc_ids[] = { 2762 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050), 2763 PCMCIA_DEVICE_NULL 2764}; 2765MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids); 2766 2767static struct pcmcia_driver mgslpc_driver = { 2768 .owner = THIS_MODULE, 2769 .name = "synclink_cs", 2770 .probe = mgslpc_probe, 2771 .remove = mgslpc_detach, 2772 .id_table = mgslpc_ids, 2773 .suspend = mgslpc_suspend, 2774 .resume = mgslpc_resume, 2775}; 2776 2777static const struct tty_operations mgslpc_ops = { 2778 .open = mgslpc_open, 2779 .close = mgslpc_close, 2780 .write = mgslpc_write, 2781 .put_char = mgslpc_put_char, 2782 .flush_chars = mgslpc_flush_chars, 2783 .write_room = mgslpc_write_room, 2784 .chars_in_buffer = mgslpc_chars_in_buffer, 2785 .flush_buffer = mgslpc_flush_buffer, 2786 .ioctl = mgslpc_ioctl, 2787 .throttle = mgslpc_throttle, 2788 .unthrottle = mgslpc_unthrottle, 2789 .send_xchar = mgslpc_send_xchar, 2790 .break_ctl = mgslpc_break, 2791 .wait_until_sent = mgslpc_wait_until_sent, 2792 .set_termios = mgslpc_set_termios, 2793 .stop = tx_pause, 2794 .start = tx_release, 2795 .hangup = mgslpc_hangup, 2796 .tiocmget = tiocmget, 2797 .tiocmset = tiocmset, 2798 .get_icount = mgslpc_get_icount, 2799 .proc_fops = &mgslpc_proc_fops, 2800}; 2801 2802static void synclink_cs_cleanup(void) 2803{ 2804 int rc; 2805 2806 while(mgslpc_device_list) 2807 mgslpc_remove_device(mgslpc_device_list); 2808 2809 if (serial_driver) { 2810 if ((rc = tty_unregister_driver(serial_driver))) 2811 printk("%s(%d) failed to unregister tty driver err=%d\n", 2812 __FILE__,__LINE__,rc); 2813 put_tty_driver(serial_driver); 2814 } 2815 2816 pcmcia_unregister_driver(&mgslpc_driver); 2817} 2818 2819static int __init synclink_cs_init(void) 2820{ 2821 int rc; 2822 2823 if (break_on_load) { 2824 mgslpc_get_text_ptr(); 2825 BREAKPOINT(); 2826 } 2827 2828 if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0) 2829 return rc; 2830 2831 serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT); 2832 if (!serial_driver) { 2833 rc = -ENOMEM; 2834 goto error; 2835 } 2836 2837 /* Initialize the tty_driver structure */ 2838 2839 serial_driver->owner = THIS_MODULE; 2840 serial_driver->driver_name = "synclink_cs"; 2841 serial_driver->name = "ttySLP"; 2842 serial_driver->major = ttymajor; 2843 serial_driver->minor_start = 64; 2844 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 2845 serial_driver->subtype = SERIAL_TYPE_NORMAL; 2846 serial_driver->init_termios = tty_std_termios; 2847 serial_driver->init_termios.c_cflag = 2848 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 2849 serial_driver->flags = TTY_DRIVER_REAL_RAW; 2850 tty_set_operations(serial_driver, &mgslpc_ops); 2851 2852 if ((rc = tty_register_driver(serial_driver)) < 0) { 2853 printk("%s(%d):Couldn't register serial driver\n", 2854 __FILE__,__LINE__); 2855 put_tty_driver(serial_driver); 2856 serial_driver = NULL; 2857 goto error; 2858 } 2859 2860 printk("%s %s, tty major#%d\n", 2861 driver_name, driver_version, 2862 serial_driver->major); 2863 2864 return 0; 2865 2866error: 2867 synclink_cs_cleanup(); 2868 return rc; 2869} 2870 2871static void __exit synclink_cs_exit(void) 2872{ 2873 synclink_cs_cleanup(); 2874} 2875 2876module_init(synclink_cs_init); 2877module_exit(synclink_cs_exit); 2878 2879static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate) 2880{ 2881 unsigned int M, N; 2882 unsigned char val; 2883 2884 /* note:standard BRG mode is broken in V3.2 chip 2885 * so enhanced mode is always used 2886 */ 2887 2888 if (rate) { 2889 N = 3686400 / rate; 2890 if (!N) 2891 N = 1; 2892 N >>= 1; 2893 for (M = 1; N > 64 && M < 16; M++) 2894 N >>= 1; 2895 N--; 2896 2897 /* BGR[5..0] = N 2898 * BGR[9..6] = M 2899 * BGR[7..0] contained in BGR register 2900 * BGR[9..8] contained in CCR2[7..6] 2901 * divisor = (N+1)*2^M 2902 * 2903 * Note: M *must* not be zero (causes asymetric duty cycle) 2904 */ 2905 write_reg(info, (unsigned char) (channel + BGR), 2906 (unsigned char) ((M << 6) + N)); 2907 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; 2908 val |= ((M << 4) & 0xc0); 2909 write_reg(info, (unsigned char) (channel + CCR2), val); 2910 } 2911} 2912 2913/* Enabled the AUX clock output at the specified frequency. 2914 */ 2915static void enable_auxclk(MGSLPC_INFO *info) 2916{ 2917 unsigned char val; 2918 2919 /* MODE 2920 * 2921 * 07..06 MDS[1..0] 10 = transparent HDLC mode 2922 * 05 ADM Address Mode, 0 = no addr recognition 2923 * 04 TMD Timer Mode, 0 = external 2924 * 03 RAC Receiver Active, 0 = inactive 2925 * 02 RTS 0=RTS active during xmit, 1=RTS always active 2926 * 01 TRS Timer Resolution, 1=512 2927 * 00 TLP Test Loop, 0 = no loop 2928 * 2929 * 1000 0010 2930 */ 2931 val = 0x82; 2932 2933 /* channel B RTS is used to enable AUXCLK driver on SP505 */ 2934 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) 2935 val |= BIT2; 2936 write_reg(info, CHB + MODE, val); 2937 2938 /* CCR0 2939 * 2940 * 07 PU Power Up, 1=active, 0=power down 2941 * 06 MCE Master Clock Enable, 1=enabled 2942 * 05 Reserved, 0 2943 * 04..02 SC[2..0] Encoding 2944 * 01..00 SM[1..0] Serial Mode, 00=HDLC 2945 * 2946 * 11000000 2947 */ 2948 write_reg(info, CHB + CCR0, 0xc0); 2949 2950 /* CCR1 2951 * 2952 * 07 SFLG Shared Flag, 0 = disable shared flags 2953 * 06 GALP Go Active On Loop, 0 = not used 2954 * 05 GLP Go On Loop, 0 = not used 2955 * 04 ODS Output Driver Select, 1=TxD is push-pull output 2956 * 03 ITF Interframe Time Fill, 0=mark, 1=flag 2957 * 02..00 CM[2..0] Clock Mode 2958 * 2959 * 0001 0111 2960 */ 2961 write_reg(info, CHB + CCR1, 0x17); 2962 2963 /* CCR2 (Channel B) 2964 * 2965 * 07..06 BGR[9..8] Baud rate bits 9..8 2966 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value 2967 * 04 SSEL Clock source select, 1=submode b 2968 * 03 TOE 0=TxCLK is input, 1=TxCLK is output 2969 * 02 RWX Read/Write Exchange 0=disabled 2970 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32 2971 * 00 DIV, data inversion 0=disabled, 1=enabled 2972 * 2973 * 0011 1000 2974 */ 2975 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) 2976 write_reg(info, CHB + CCR2, 0x38); 2977 else 2978 write_reg(info, CHB + CCR2, 0x30); 2979 2980 /* CCR4 2981 * 2982 * 07 MCK4 Master Clock Divide by 4, 1=enabled 2983 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled 2984 * 05 TST1 Test Pin, 0=normal operation 2985 * 04 ICD Ivert Carrier Detect, 1=enabled (active low) 2986 * 03..02 Reserved, must be 0 2987 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes 2988 * 2989 * 0101 0000 2990 */ 2991 write_reg(info, CHB + CCR4, 0x50); 2992 2993 /* if auxclk not enabled, set internal BRG so 2994 * CTS transitions can be detected (requires TxC) 2995 */ 2996 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) 2997 mgslpc_set_rate(info, CHB, info->params.clock_speed); 2998 else 2999 mgslpc_set_rate(info, CHB, 921600); 3000} 3001 3002static void loopback_enable(MGSLPC_INFO *info) 3003{ 3004 unsigned char val; 3005 3006 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */ 3007 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); 3008 write_reg(info, CHA + CCR1, val); 3009 3010 /* CCR2:04 SSEL Clock source select, 1=submode b */ 3011 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); 3012 write_reg(info, CHA + CCR2, val); 3013 3014 /* set LinkSpeed if available, otherwise default to 2Mbps */ 3015 if (info->params.clock_speed) 3016 mgslpc_set_rate(info, CHA, info->params.clock_speed); 3017 else 3018 mgslpc_set_rate(info, CHA, 1843200); 3019 3020 /* MODE:00 TLP Test Loop, 1=loopback enabled */ 3021 val = read_reg(info, CHA + MODE) | BIT0; 3022 write_reg(info, CHA + MODE, val); 3023} 3024 3025static void hdlc_mode(MGSLPC_INFO *info) 3026{ 3027 unsigned char val; 3028 unsigned char clkmode, clksubmode; 3029 3030 /* disable all interrupts */ 3031 irq_disable(info, CHA, 0xffff); 3032 irq_disable(info, CHB, 0xffff); 3033 port_irq_disable(info, 0xff); 3034 3035 /* assume clock mode 0a, rcv=RxC xmt=TxC */ 3036 clkmode = clksubmode = 0; 3037 if (info->params.flags & HDLC_FLAG_RXC_DPLL 3038 && info->params.flags & HDLC_FLAG_TXC_DPLL) { 3039 /* clock mode 7a, rcv = DPLL, xmt = DPLL */ 3040 clkmode = 7; 3041 } else if (info->params.flags & HDLC_FLAG_RXC_BRG 3042 && info->params.flags & HDLC_FLAG_TXC_BRG) { 3043 /* clock mode 7b, rcv = BRG, xmt = BRG */ 3044 clkmode = 7; 3045 clksubmode = 1; 3046 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) { 3047 if (info->params.flags & HDLC_FLAG_TXC_BRG) { 3048 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */ 3049 clkmode = 6; 3050 clksubmode = 1; 3051 } else { 3052 /* clock mode 6a, rcv = DPLL, xmt = TxC */ 3053 clkmode = 6; 3054 } 3055 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) { 3056 /* clock mode 0b, rcv = RxC, xmt = BRG */ 3057 clksubmode = 1; 3058 } 3059 3060 /* MODE 3061 * 3062 * 07..06 MDS[1..0] 10 = transparent HDLC mode 3063 * 05 ADM Address Mode, 0 = no addr recognition 3064 * 04 TMD Timer Mode, 0 = external 3065 * 03 RAC Receiver Active, 0 = inactive 3066 * 02 RTS 0=RTS active during xmit, 1=RTS always active 3067 * 01 TRS Timer Resolution, 1=512 3068 * 00 TLP Test Loop, 0 = no loop 3069 * 3070 * 1000 0010 3071 */ 3072 val = 0x82; 3073 if (info->params.loopback) 3074 val |= BIT0; 3075 3076 /* preserve RTS state */ 3077 if (info->serial_signals & SerialSignal_RTS) 3078 val |= BIT2; 3079 write_reg(info, CHA + MODE, val); 3080 3081 /* CCR0 3082 * 3083 * 07 PU Power Up, 1=active, 0=power down 3084 * 06 MCE Master Clock Enable, 1=enabled 3085 * 05 Reserved, 0 3086 * 04..02 SC[2..0] Encoding 3087 * 01..00 SM[1..0] Serial Mode, 00=HDLC 3088 * 3089 * 11000000 3090 */ 3091 val = 0xc0; 3092 switch (info->params.encoding) 3093 { 3094 case HDLC_ENCODING_NRZI: 3095 val |= BIT3; 3096 break; 3097 case HDLC_ENCODING_BIPHASE_SPACE: 3098 val |= BIT4; 3099 break; // FM0 3100 case HDLC_ENCODING_BIPHASE_MARK: 3101 val |= BIT4 + BIT2; 3102 break; // FM1 3103 case HDLC_ENCODING_BIPHASE_LEVEL: 3104 val |= BIT4 + BIT3; 3105 break; // Manchester 3106 } 3107 write_reg(info, CHA + CCR0, val); 3108 3109 /* CCR1 3110 * 3111 * 07 SFLG Shared Flag, 0 = disable shared flags 3112 * 06 GALP Go Active On Loop, 0 = not used 3113 * 05 GLP Go On Loop, 0 = not used 3114 * 04 ODS Output Driver Select, 1=TxD is push-pull output 3115 * 03 ITF Interframe Time Fill, 0=mark, 1=flag 3116 * 02..00 CM[2..0] Clock Mode 3117 * 3118 * 0001 0000 3119 */ 3120 val = 0x10 + clkmode; 3121 write_reg(info, CHA + CCR1, val); 3122 3123 /* CCR2 3124 * 3125 * 07..06 BGR[9..8] Baud rate bits 9..8 3126 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value 3127 * 04 SSEL Clock source select, 1=submode b 3128 * 03 TOE 0=TxCLK is input, 0=TxCLK is input 3129 * 02 RWX Read/Write Exchange 0=disabled 3130 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32 3131 * 00 DIV, data inversion 0=disabled, 1=enabled 3132 * 3133 * 0000 0000 3134 */ 3135 val = 0x00; 3136 if (clkmode == 2 || clkmode == 3 || clkmode == 6 3137 || clkmode == 7 || (clkmode == 0 && clksubmode == 1)) 3138 val |= BIT5; 3139 if (clksubmode) 3140 val |= BIT4; 3141 if (info->params.crc_type == HDLC_CRC_32_CCITT) 3142 val |= BIT1; 3143 if (info->params.encoding == HDLC_ENCODING_NRZB) 3144 val |= BIT0; 3145 write_reg(info, CHA + CCR2, val); 3146 3147 /* CCR3 3148 * 3149 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8 3150 * 05 EPT Enable preamble transmission, 1=enabled 3151 * 04 RADD Receive address pushed to FIFO, 0=disabled 3152 * 03 CRL CRC Reset Level, 0=FFFF 3153 * 02 RCRC Rx CRC 0=On 1=Off 3154 * 01 TCRC Tx CRC 0=On 1=Off 3155 * 00 PSD DPLL Phase Shift Disable 3156 * 3157 * 0000 0000 3158 */ 3159 val = 0x00; 3160 if (info->params.crc_type == HDLC_CRC_NONE) 3161 val |= BIT2 + BIT1; 3162 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 3163 val |= BIT5; 3164 switch (info->params.preamble_length) 3165 { 3166 case HDLC_PREAMBLE_LENGTH_16BITS: 3167 val |= BIT6; 3168 break; 3169 case HDLC_PREAMBLE_LENGTH_32BITS: 3170 val |= BIT6; 3171 break; 3172 case HDLC_PREAMBLE_LENGTH_64BITS: 3173 val |= BIT7 + BIT6; 3174 break; 3175 } 3176 write_reg(info, CHA + CCR3, val); 3177 3178 /* PRE - Preamble pattern */ 3179 val = 0; 3180 switch (info->params.preamble) 3181 { 3182 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 3183 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break; 3184 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break; 3185 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 3186 } 3187 write_reg(info, CHA + PRE, val); 3188 3189 /* CCR4 3190 * 3191 * 07 MCK4 Master Clock Divide by 4, 1=enabled 3192 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled 3193 * 05 TST1 Test Pin, 0=normal operation 3194 * 04 ICD Ivert Carrier Detect, 1=enabled (active low) 3195 * 03..02 Reserved, must be 0 3196 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes 3197 * 3198 * 0101 0000 3199 */ 3200 val = 0x50; 3201 write_reg(info, CHA + CCR4, val); 3202 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 3203 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16); 3204 else 3205 mgslpc_set_rate(info, CHA, info->params.clock_speed); 3206 3207 /* RLCR Receive length check register 3208 * 3209 * 7 1=enable receive length check 3210 * 6..0 Max frame length = (RL + 1) * 32 3211 */ 3212 write_reg(info, CHA + RLCR, 0); 3213 3214 /* XBCH Transmit Byte Count High 3215 * 3216 * 07 DMA mode, 0 = interrupt driven 3217 * 06 NRM, 0=ABM (ignored) 3218 * 05 CAS Carrier Auto Start 3219 * 04 XC Transmit Continuously (ignored) 3220 * 03..00 XBC[10..8] Transmit byte count bits 10..8 3221 * 3222 * 0000 0000 3223 */ 3224 val = 0x00; 3225 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 3226 val |= BIT5; 3227 write_reg(info, CHA + XBCH, val); 3228 enable_auxclk(info); 3229 if (info->params.loopback || info->testing_irq) 3230 loopback_enable(info); 3231 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 3232 { 3233 irq_enable(info, CHB, IRQ_CTS); 3234 /* PVR[3] 1=AUTO CTS active */ 3235 set_reg_bits(info, CHA + PVR, BIT3); 3236 } else 3237 clear_reg_bits(info, CHA + PVR, BIT3); 3238 3239 irq_enable(info, CHA, 3240 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT + 3241 IRQ_UNDERRUN + IRQ_TXFIFO); 3242 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET); 3243 wait_command_complete(info, CHA); 3244 read_reg16(info, CHA + ISR); /* clear pending IRQs */ 3245 3246 /* Master clock mode enabled above to allow reset commands 3247 * to complete even if no data clocks are present. 3248 * 3249 * Disable master clock mode for normal communications because 3250 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent 3251 * IRQ when in master clock mode. 3252 * 3253 * Leave master clock mode enabled for IRQ test because the 3254 * timer IRQ used by the test can only happen in master clock mode. 3255 */ 3256 if (!info->testing_irq) 3257 clear_reg_bits(info, CHA + CCR0, BIT6); 3258 3259 tx_set_idle(info); 3260 3261 tx_stop(info); 3262 rx_stop(info); 3263} 3264 3265static void rx_stop(MGSLPC_INFO *info) 3266{ 3267 if (debug_level >= DEBUG_LEVEL_ISR) 3268 printk("%s(%d):rx_stop(%s)\n", 3269 __FILE__,__LINE__, info->device_name ); 3270 3271 /* MODE:03 RAC Receiver Active, 0=inactive */ 3272 clear_reg_bits(info, CHA + MODE, BIT3); 3273 3274 info->rx_enabled = false; 3275 info->rx_overflow = false; 3276} 3277 3278static void rx_start(MGSLPC_INFO *info) 3279{ 3280 if (debug_level >= DEBUG_LEVEL_ISR) 3281 printk("%s(%d):rx_start(%s)\n", 3282 __FILE__,__LINE__, info->device_name ); 3283 3284 rx_reset_buffers(info); 3285 info->rx_enabled = false; 3286 info->rx_overflow = false; 3287 3288 /* MODE:03 RAC Receiver Active, 1=active */ 3289 set_reg_bits(info, CHA + MODE, BIT3); 3290 3291 info->rx_enabled = true; 3292} 3293 3294static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty) 3295{ 3296 if (debug_level >= DEBUG_LEVEL_ISR) 3297 printk("%s(%d):tx_start(%s)\n", 3298 __FILE__,__LINE__, info->device_name ); 3299 3300 if (info->tx_count) { 3301 /* If auto RTS enabled and RTS is inactive, then assert */ 3302 /* RTS and set a flag indicating that the driver should */ 3303 /* negate RTS when the transmission completes. */ 3304 info->drop_rts_on_tx_done = false; 3305 3306 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 3307 get_signals(info); 3308 if (!(info->serial_signals & SerialSignal_RTS)) { 3309 info->serial_signals |= SerialSignal_RTS; 3310 set_signals(info); 3311 info->drop_rts_on_tx_done = true; 3312 } 3313 } 3314 3315 if (info->params.mode == MGSL_MODE_ASYNC) { 3316 if (!info->tx_active) { 3317 info->tx_active = true; 3318 tx_ready(info, tty); 3319 } 3320 } else { 3321 info->tx_active = true; 3322 tx_ready(info, tty); 3323 mod_timer(&info->tx_timer, jiffies + 3324 msecs_to_jiffies(5000)); 3325 } 3326 } 3327 3328 if (!info->tx_enabled) 3329 info->tx_enabled = true; 3330} 3331 3332static void tx_stop(MGSLPC_INFO *info) 3333{ 3334 if (debug_level >= DEBUG_LEVEL_ISR) 3335 printk("%s(%d):tx_stop(%s)\n", 3336 __FILE__,__LINE__, info->device_name ); 3337 3338 del_timer(&info->tx_timer); 3339 3340 info->tx_enabled = false; 3341 info->tx_active = false; 3342} 3343 3344/* Reset the adapter to a known state and prepare it for further use. 3345 */ 3346static void reset_device(MGSLPC_INFO *info) 3347{ 3348 /* power up both channels (set BIT7) */ 3349 write_reg(info, CHA + CCR0, 0x80); 3350 write_reg(info, CHB + CCR0, 0x80); 3351 write_reg(info, CHA + MODE, 0); 3352 write_reg(info, CHB + MODE, 0); 3353 3354 /* disable all interrupts */ 3355 irq_disable(info, CHA, 0xffff); 3356 irq_disable(info, CHB, 0xffff); 3357 port_irq_disable(info, 0xff); 3358 3359 /* PCR Port Configuration Register 3360 * 3361 * 07..04 DEC[3..0] Serial I/F select outputs 3362 * 03 output, 1=AUTO CTS control enabled 3363 * 02 RI Ring Indicator input 0=active 3364 * 01 DSR input 0=active 3365 * 00 DTR output 0=active 3366 * 3367 * 0000 0110 3368 */ 3369 write_reg(info, PCR, 0x06); 3370 3371 /* PVR Port Value Register 3372 * 3373 * 07..04 DEC[3..0] Serial I/F select (0000=disabled) 3374 * 03 AUTO CTS output 1=enabled 3375 * 02 RI Ring Indicator input 3376 * 01 DSR input 3377 * 00 DTR output (1=inactive) 3378 * 3379 * 0000 0001 3380 */ 3381// write_reg(info, PVR, PVR_DTR); 3382 3383 /* IPC Interrupt Port Configuration 3384 * 3385 * 07 VIS 1=Masked interrupts visible 3386 * 06..05 Reserved, 0 3387 * 04..03 SLA Slave address, 00 ignored 3388 * 02 CASM Cascading Mode, 1=daisy chain 3389 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low 3390 * 3391 * 0000 0101 3392 */ 3393 write_reg(info, IPC, 0x05); 3394} 3395 3396static void async_mode(MGSLPC_INFO *info) 3397{ 3398 unsigned char val; 3399 3400 /* disable all interrupts */ 3401 irq_disable(info, CHA, 0xffff); 3402 irq_disable(info, CHB, 0xffff); 3403 port_irq_disable(info, 0xff); 3404 3405 /* MODE 3406 * 3407 * 07 Reserved, 0 3408 * 06 FRTS RTS State, 0=active 3409 * 05 FCTS Flow Control on CTS 3410 * 04 FLON Flow Control Enable 3411 * 03 RAC Receiver Active, 0 = inactive 3412 * 02 RTS 0=Auto RTS, 1=manual RTS 3413 * 01 TRS Timer Resolution, 1=512 3414 * 00 TLP Test Loop, 0 = no loop 3415 * 3416 * 0000 0110 3417 */ 3418 val = 0x06; 3419 if (info->params.loopback) 3420 val |= BIT0; 3421 3422 /* preserve RTS state */ 3423 if (!(info->serial_signals & SerialSignal_RTS)) 3424 val |= BIT6; 3425 write_reg(info, CHA + MODE, val); 3426 3427 /* CCR0 3428 * 3429 * 07 PU Power Up, 1=active, 0=power down 3430 * 06 MCE Master Clock Enable, 1=enabled 3431 * 05 Reserved, 0 3432 * 04..02 SC[2..0] Encoding, 000=NRZ 3433 * 01..00 SM[1..0] Serial Mode, 11=Async 3434 * 3435 * 1000 0011 3436 */ 3437 write_reg(info, CHA + CCR0, 0x83); 3438 3439 /* CCR1 3440 * 3441 * 07..05 Reserved, 0 3442 * 04 ODS Output Driver Select, 1=TxD is push-pull output 3443 * 03 BCR Bit Clock Rate, 1=16x 3444 * 02..00 CM[2..0] Clock Mode, 111=BRG 3445 * 3446 * 0001 1111 3447 */ 3448 write_reg(info, CHA + CCR1, 0x1f); 3449 3450 /* CCR2 (channel A) 3451 * 3452 * 07..06 BGR[9..8] Baud rate bits 9..8 3453 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value 3454 * 04 SSEL Clock source select, 1=submode b 3455 * 03 TOE 0=TxCLK is input, 0=TxCLK is input 3456 * 02 RWX Read/Write Exchange 0=disabled 3457 * 01 Reserved, 0 3458 * 00 DIV, data inversion 0=disabled, 1=enabled 3459 * 3460 * 0001 0000 3461 */ 3462 write_reg(info, CHA + CCR2, 0x10); 3463 3464 /* CCR3 3465 * 3466 * 07..01 Reserved, 0 3467 * 00 PSD DPLL Phase Shift Disable 3468 * 3469 * 0000 0000 3470 */ 3471 write_reg(info, CHA + CCR3, 0); 3472 3473 /* CCR4 3474 * 3475 * 07 MCK4 Master Clock Divide by 4, 1=enabled 3476 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled 3477 * 05 TST1 Test Pin, 0=normal operation 3478 * 04 ICD Ivert Carrier Detect, 1=enabled (active low) 3479 * 03..00 Reserved, must be 0 3480 * 3481 * 0101 0000 3482 */ 3483 write_reg(info, CHA + CCR4, 0x50); 3484 mgslpc_set_rate(info, CHA, info->params.data_rate * 16); 3485 3486 /* DAFO Data Format 3487 * 3488 * 07 Reserved, 0 3489 * 06 XBRK transmit break, 0=normal operation 3490 * 05 Stop bits (0=1, 1=2) 3491 * 04..03 PAR[1..0] Parity (01=odd, 10=even) 3492 * 02 PAREN Parity Enable 3493 * 01..00 CHL[1..0] Character Length (00=8, 01=7) 3494 * 3495 */ 3496 val = 0x00; 3497 if (info->params.data_bits != 8) 3498 val |= BIT0; /* 7 bits */ 3499 if (info->params.stop_bits != 1) 3500 val |= BIT5; 3501 if (info->params.parity != ASYNC_PARITY_NONE) 3502 { 3503 val |= BIT2; /* Parity enable */ 3504 if (info->params.parity == ASYNC_PARITY_ODD) 3505 val |= BIT3; 3506 else 3507 val |= BIT4; 3508 } 3509 write_reg(info, CHA + DAFO, val); 3510 3511 /* RFC Rx FIFO Control 3512 * 3513 * 07 Reserved, 0 3514 * 06 DPS, 1=parity bit not stored in data byte 3515 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF) 3516 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO 3517 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte 3518 * 01 Reserved, 0 3519 * 00 TCDE Terminate Char Detect Enable, 0=disabled 3520 * 3521 * 0101 1100 3522 */ 3523 write_reg(info, CHA + RFC, 0x5c); 3524 3525 /* RLCR Receive length check register 3526 * 3527 * Max frame length = (RL + 1) * 32 3528 */ 3529 write_reg(info, CHA + RLCR, 0); 3530 3531 /* XBCH Transmit Byte Count High 3532 * 3533 * 07 DMA mode, 0 = interrupt driven 3534 * 06 NRM, 0=ABM (ignored) 3535 * 05 CAS Carrier Auto Start 3536 * 04 XC Transmit Continuously (ignored) 3537 * 03..00 XBC[10..8] Transmit byte count bits 10..8 3538 * 3539 * 0000 0000 3540 */ 3541 val = 0x00; 3542 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 3543 val |= BIT5; 3544 write_reg(info, CHA + XBCH, val); 3545 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 3546 irq_enable(info, CHA, IRQ_CTS); 3547 3548 /* MODE:03 RAC Receiver Active, 1=active */ 3549 set_reg_bits(info, CHA + MODE, BIT3); 3550 enable_auxclk(info); 3551 if (info->params.flags & HDLC_FLAG_AUTO_CTS) { 3552 irq_enable(info, CHB, IRQ_CTS); 3553 /* PVR[3] 1=AUTO CTS active */ 3554 set_reg_bits(info, CHA + PVR, BIT3); 3555 } else 3556 clear_reg_bits(info, CHA + PVR, BIT3); 3557 irq_enable(info, CHA, 3558 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME + 3559 IRQ_ALLSENT + IRQ_TXFIFO); 3560 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET); 3561 wait_command_complete(info, CHA); 3562 read_reg16(info, CHA + ISR); /* clear pending IRQs */ 3563} 3564 3565/* Set the HDLC idle mode for the transmitter. 3566 */ 3567static void tx_set_idle(MGSLPC_INFO *info) 3568{ 3569 /* Note: ESCC2 only supports flags and one idle modes */ 3570 if (info->idle_mode == HDLC_TXIDLE_FLAGS) 3571 set_reg_bits(info, CHA + CCR1, BIT3); 3572 else 3573 clear_reg_bits(info, CHA + CCR1, BIT3); 3574} 3575 3576/* get state of the V24 status (input) signals. 3577 */ 3578static void get_signals(MGSLPC_INFO *info) 3579{ 3580 unsigned char status = 0; 3581 3582 /* preserve DTR and RTS */ 3583 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS; 3584 3585 if (read_reg(info, CHB + VSTR) & BIT7) 3586 info->serial_signals |= SerialSignal_DCD; 3587 if (read_reg(info, CHB + STAR) & BIT1) 3588 info->serial_signals |= SerialSignal_CTS; 3589 3590 status = read_reg(info, CHA + PVR); 3591 if (!(status & PVR_RI)) 3592 info->serial_signals |= SerialSignal_RI; 3593 if (!(status & PVR_DSR)) 3594 info->serial_signals |= SerialSignal_DSR; 3595} 3596 3597/* Set the state of DTR and RTS based on contents of 3598 * serial_signals member of device extension. 3599 */ 3600static void set_signals(MGSLPC_INFO *info) 3601{ 3602 unsigned char val; 3603 3604 val = read_reg(info, CHA + MODE); 3605 if (info->params.mode == MGSL_MODE_ASYNC) { 3606 if (info->serial_signals & SerialSignal_RTS) 3607 val &= ~BIT6; 3608 else 3609 val |= BIT6; 3610 } else { 3611 if (info->serial_signals & SerialSignal_RTS) 3612 val |= BIT2; 3613 else 3614 val &= ~BIT2; 3615 } 3616 write_reg(info, CHA + MODE, val); 3617 3618 if (info->serial_signals & SerialSignal_DTR) 3619 clear_reg_bits(info, CHA + PVR, PVR_DTR); 3620 else 3621 set_reg_bits(info, CHA + PVR, PVR_DTR); 3622} 3623 3624static void rx_reset_buffers(MGSLPC_INFO *info) 3625{ 3626 RXBUF *buf; 3627 int i; 3628 3629 info->rx_put = 0; 3630 info->rx_get = 0; 3631 info->rx_frame_count = 0; 3632 for (i=0 ; i < info->rx_buf_count ; i++) { 3633 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size)); 3634 buf->status = buf->count = 0; 3635 } 3636} 3637 3638/* Attempt to return a received HDLC frame 3639 * Only frames received without errors are returned. 3640 * 3641 * Returns true if frame returned, otherwise false 3642 */ 3643static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty) 3644{ 3645 unsigned short status; 3646 RXBUF *buf; 3647 unsigned int framesize = 0; 3648 unsigned long flags; 3649 bool return_frame = false; 3650 3651 if (info->rx_frame_count == 0) 3652 return false; 3653 3654 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size)); 3655 3656 status = buf->status; 3657 3658 /* 07 VFR 1=valid frame 3659 * 06 RDO 1=data overrun 3660 * 05 CRC 1=OK, 0=error 3661 * 04 RAB 1=frame aborted 3662 */ 3663 if ((status & 0xf0) != 0xA0) { 3664 if (!(status & BIT7) || (status & BIT4)) 3665 info->icount.rxabort++; 3666 else if (status & BIT6) 3667 info->icount.rxover++; 3668 else if (!(status & BIT5)) { 3669 info->icount.rxcrc++; 3670 if (info->params.crc_type & HDLC_CRC_RETURN_EX) 3671 return_frame = true; 3672 } 3673 framesize = 0; 3674#if SYNCLINK_GENERIC_HDLC 3675 { 3676 info->netdev->stats.rx_errors++; 3677 info->netdev->stats.rx_frame_errors++; 3678 } 3679#endif 3680 } else 3681 return_frame = true; 3682 3683 if (return_frame) 3684 framesize = buf->count; 3685 3686 if (debug_level >= DEBUG_LEVEL_BH) 3687 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n", 3688 __FILE__,__LINE__,info->device_name,status,framesize); 3689 3690 if (debug_level >= DEBUG_LEVEL_DATA) 3691 trace_block(info, buf->data, framesize, 0); 3692 3693 if (framesize) { 3694 if ((info->params.crc_type & HDLC_CRC_RETURN_EX && 3695 framesize+1 > info->max_frame_size) || 3696 framesize > info->max_frame_size) 3697 info->icount.rxlong++; 3698 else { 3699 if (status & BIT5) 3700 info->icount.rxok++; 3701 3702 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 3703 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR; 3704 ++framesize; 3705 } 3706 3707#if SYNCLINK_GENERIC_HDLC 3708 if (info->netcount) 3709 hdlcdev_rx(info, buf->data, framesize); 3710 else 3711#endif 3712 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize); 3713 } 3714 } 3715 3716 spin_lock_irqsave(&info->lock,flags); 3717 buf->status = buf->count = 0; 3718 info->rx_frame_count--; 3719 info->rx_get++; 3720 if (info->rx_get >= info->rx_buf_count) 3721 info->rx_get = 0; 3722 spin_unlock_irqrestore(&info->lock,flags); 3723 3724 return true; 3725} 3726 3727static bool register_test(MGSLPC_INFO *info) 3728{ 3729 static unsigned char patterns[] = 3730 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f }; 3731 static unsigned int count = ARRAY_SIZE(patterns); 3732 unsigned int i; 3733 bool rc = true; 3734 unsigned long flags; 3735 3736 spin_lock_irqsave(&info->lock,flags); 3737 reset_device(info); 3738 3739 for (i = 0; i < count; i++) { 3740 write_reg(info, XAD1, patterns[i]); 3741 write_reg(info, XAD2, patterns[(i + 1) % count]); 3742 if ((read_reg(info, XAD1) != patterns[i]) || 3743 (read_reg(info, XAD2) != patterns[(i + 1) % count])) { 3744 rc = false; 3745 break; 3746 } 3747 } 3748 3749 spin_unlock_irqrestore(&info->lock,flags); 3750 return rc; 3751} 3752 3753static bool irq_test(MGSLPC_INFO *info) 3754{ 3755 unsigned long end_time; 3756 unsigned long flags; 3757 3758 spin_lock_irqsave(&info->lock,flags); 3759 reset_device(info); 3760 3761 info->testing_irq = true; 3762 hdlc_mode(info); 3763 3764 info->irq_occurred = false; 3765 3766 /* init hdlc mode */ 3767 3768 irq_enable(info, CHA, IRQ_TIMER); 3769 write_reg(info, CHA + TIMR, 0); /* 512 cycles */ 3770 issue_command(info, CHA, CMD_START_TIMER); 3771 3772 spin_unlock_irqrestore(&info->lock,flags); 3773 3774 end_time=100; 3775 while(end_time-- && !info->irq_occurred) { 3776 msleep_interruptible(10); 3777 } 3778 3779 info->testing_irq = false; 3780 3781 spin_lock_irqsave(&info->lock,flags); 3782 reset_device(info); 3783 spin_unlock_irqrestore(&info->lock,flags); 3784 3785 return info->irq_occurred; 3786} 3787 3788static int adapter_test(MGSLPC_INFO *info) 3789{ 3790 if (!register_test(info)) { 3791 info->init_error = DiagStatus_AddressFailure; 3792 printk( "%s(%d):Register test failure for device %s Addr=%04X\n", 3793 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) ); 3794 return -ENODEV; 3795 } 3796 3797 if (!irq_test(info)) { 3798 info->init_error = DiagStatus_IrqFailure; 3799 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", 3800 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); 3801 return -ENODEV; 3802 } 3803 3804 if (debug_level >= DEBUG_LEVEL_INFO) 3805 printk("%s(%d):device %s passed diagnostics\n", 3806 __FILE__,__LINE__,info->device_name); 3807 return 0; 3808} 3809 3810static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit) 3811{ 3812 int i; 3813 int linecount; 3814 if (xmit) 3815 printk("%s tx data:\n",info->device_name); 3816 else 3817 printk("%s rx data:\n",info->device_name); 3818 3819 while(count) { 3820 if (count > 16) 3821 linecount = 16; 3822 else 3823 linecount = count; 3824 3825 for(i=0;i<linecount;i++) 3826 printk("%02X ",(unsigned char)data[i]); 3827 for(;i<17;i++) 3828 printk(" "); 3829 for(i=0;i<linecount;i++) { 3830 if (data[i]>=040 && data[i]<=0176) 3831 printk("%c",data[i]); 3832 else 3833 printk("."); 3834 } 3835 printk("\n"); 3836 3837 data += linecount; 3838 count -= linecount; 3839 } 3840} 3841 3842/* HDLC frame time out 3843 * update stats and do tx completion processing 3844 */ 3845static void tx_timeout(unsigned long context) 3846{ 3847 MGSLPC_INFO *info = (MGSLPC_INFO*)context; 3848 unsigned long flags; 3849 3850 if ( debug_level >= DEBUG_LEVEL_INFO ) 3851 printk( "%s(%d):tx_timeout(%s)\n", 3852 __FILE__,__LINE__,info->device_name); 3853 if(info->tx_active && 3854 info->params.mode == MGSL_MODE_HDLC) { 3855 info->icount.txtimeout++; 3856 } 3857 spin_lock_irqsave(&info->lock,flags); 3858 info->tx_active = false; 3859 info->tx_count = info->tx_put = info->tx_get = 0; 3860 3861 spin_unlock_irqrestore(&info->lock,flags); 3862 3863#if SYNCLINK_GENERIC_HDLC 3864 if (info->netcount) 3865 hdlcdev_tx_done(info); 3866 else 3867#endif 3868 { 3869 struct tty_struct *tty = tty_port_tty_get(&info->port); 3870 bh_transmit(info, tty); 3871 tty_kref_put(tty); 3872 } 3873} 3874 3875#if SYNCLINK_GENERIC_HDLC 3876 3877/** 3878 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 3879 * set encoding and frame check sequence (FCS) options 3880 * 3881 * dev pointer to network device structure 3882 * encoding serial encoding setting 3883 * parity FCS setting 3884 * 3885 * returns 0 if success, otherwise error code 3886 */ 3887static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 3888 unsigned short parity) 3889{ 3890 MGSLPC_INFO *info = dev_to_port(dev); 3891 struct tty_struct *tty; 3892 unsigned char new_encoding; 3893 unsigned short new_crctype; 3894 3895 /* return error if TTY interface open */ 3896 if (info->port.count) 3897 return -EBUSY; 3898 3899 switch (encoding) 3900 { 3901 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 3902 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 3903 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 3904 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 3905 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 3906 default: return -EINVAL; 3907 } 3908 3909 switch (parity) 3910 { 3911 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 3912 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 3913 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 3914 default: return -EINVAL; 3915 } 3916 3917 info->params.encoding = new_encoding; 3918 info->params.crc_type = new_crctype; 3919 3920 /* if network interface up, reprogram hardware */ 3921 if (info->netcount) { 3922 tty = tty_port_tty_get(&info->port); 3923 mgslpc_program_hw(info, tty); 3924 tty_kref_put(tty); 3925 } 3926 3927 return 0; 3928} 3929 3930/** 3931 * called by generic HDLC layer to send frame 3932 * 3933 * skb socket buffer containing HDLC frame 3934 * dev pointer to network device structure 3935 */ 3936static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 3937 struct net_device *dev) 3938{ 3939 MGSLPC_INFO *info = dev_to_port(dev); 3940 unsigned long flags; 3941 3942 if (debug_level >= DEBUG_LEVEL_INFO) 3943 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); 3944 3945 /* stop sending until this frame completes */ 3946 netif_stop_queue(dev); 3947 3948 /* copy data to device buffers */ 3949 skb_copy_from_linear_data(skb, info->tx_buf, skb->len); 3950 info->tx_get = 0; 3951 info->tx_put = info->tx_count = skb->len; 3952 3953 /* update network statistics */ 3954 dev->stats.tx_packets++; 3955 dev->stats.tx_bytes += skb->len; 3956 3957 /* done with socket buffer, so free it */ 3958 dev_kfree_skb(skb); 3959 3960 /* save start time for transmit timeout detection */ 3961 dev->trans_start = jiffies; 3962 3963 /* start hardware transmitter if necessary */ 3964 spin_lock_irqsave(&info->lock,flags); 3965 if (!info->tx_active) { 3966 struct tty_struct *tty = tty_port_tty_get(&info->port); 3967 tx_start(info, tty); 3968 tty_kref_put(tty); 3969 } 3970 spin_unlock_irqrestore(&info->lock,flags); 3971 3972 return NETDEV_TX_OK; 3973} 3974 3975/** 3976 * called by network layer when interface enabled 3977 * claim resources and initialize hardware 3978 * 3979 * dev pointer to network device structure 3980 * 3981 * returns 0 if success, otherwise error code 3982 */ 3983static int hdlcdev_open(struct net_device *dev) 3984{ 3985 MGSLPC_INFO *info = dev_to_port(dev); 3986 struct tty_struct *tty; 3987 int rc; 3988 unsigned long flags; 3989 3990 if (debug_level >= DEBUG_LEVEL_INFO) 3991 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); 3992 3993 /* generic HDLC layer open processing */ 3994 if ((rc = hdlc_open(dev))) 3995 return rc; 3996 3997 /* arbitrate between network and tty opens */ 3998 spin_lock_irqsave(&info->netlock, flags); 3999 if (info->port.count != 0 || info->netcount != 0) { 4000 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); 4001 spin_unlock_irqrestore(&info->netlock, flags); 4002 return -EBUSY; 4003 } 4004 info->netcount=1; 4005 spin_unlock_irqrestore(&info->netlock, flags); 4006 4007 tty = tty_port_tty_get(&info->port); 4008 /* claim resources and init adapter */ 4009 if ((rc = startup(info, tty)) != 0) { 4010 tty_kref_put(tty); 4011 spin_lock_irqsave(&info->netlock, flags); 4012 info->netcount=0; 4013 spin_unlock_irqrestore(&info->netlock, flags); 4014 return rc; 4015 } 4016 /* assert DTR and RTS, apply hardware settings */ 4017 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 4018 mgslpc_program_hw(info, tty); 4019 tty_kref_put(tty); 4020 4021 /* enable network layer transmit */ 4022 dev->trans_start = jiffies; 4023 netif_start_queue(dev); 4024 4025 /* inform generic HDLC layer of current DCD status */ 4026 spin_lock_irqsave(&info->lock, flags); 4027 get_signals(info); 4028 spin_unlock_irqrestore(&info->lock, flags); 4029 if (info->serial_signals & SerialSignal_DCD) 4030 netif_carrier_on(dev); 4031 else 4032 netif_carrier_off(dev); 4033 return 0; 4034} 4035 4036/** 4037 * called by network layer when interface is disabled 4038 * shutdown hardware and release resources 4039 * 4040 * dev pointer to network device structure 4041 * 4042 * returns 0 if success, otherwise error code 4043 */ 4044static int hdlcdev_close(struct net_device *dev) 4045{ 4046 MGSLPC_INFO *info = dev_to_port(dev); 4047 struct tty_struct *tty = tty_port_tty_get(&info->port); 4048 unsigned long flags; 4049 4050 if (debug_level >= DEBUG_LEVEL_INFO) 4051 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); 4052 4053 netif_stop_queue(dev); 4054 4055 /* shutdown adapter and release resources */ 4056 shutdown(info, tty); 4057 tty_kref_put(tty); 4058 hdlc_close(dev); 4059 4060 spin_lock_irqsave(&info->netlock, flags); 4061 info->netcount=0; 4062 spin_unlock_irqrestore(&info->netlock, flags); 4063 4064 return 0; 4065} 4066 4067/** 4068 * called by network layer to process IOCTL call to network device 4069 * 4070 * dev pointer to network device structure 4071 * ifr pointer to network interface request structure 4072 * cmd IOCTL command code 4073 * 4074 * returns 0 if success, otherwise error code 4075 */ 4076static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4077{ 4078 const size_t size = sizeof(sync_serial_settings); 4079 sync_serial_settings new_line; 4080 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 4081 MGSLPC_INFO *info = dev_to_port(dev); 4082 unsigned int flags; 4083 4084 if (debug_level >= DEBUG_LEVEL_INFO) 4085 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); 4086 4087 /* return error if TTY interface open */ 4088 if (info->port.count) 4089 return -EBUSY; 4090 4091 if (cmd != SIOCWANDEV) 4092 return hdlc_ioctl(dev, ifr, cmd); 4093 4094 memset(&new_line, 0, size); 4095 4096 switch(ifr->ifr_settings.type) { 4097 case IF_GET_IFACE: /* return current sync_serial_settings */ 4098 4099 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 4100 if (ifr->ifr_settings.size < size) { 4101 ifr->ifr_settings.size = size; /* data size wanted */ 4102 return -ENOBUFS; 4103 } 4104 4105 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 4106 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 4107 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 4108 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 4109 4110 switch (flags){ 4111 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 4112 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 4113 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 4114 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 4115 default: new_line.clock_type = CLOCK_DEFAULT; 4116 } 4117 4118 new_line.clock_rate = info->params.clock_speed; 4119 new_line.loopback = info->params.loopback ? 1:0; 4120 4121 if (copy_to_user(line, &new_line, size)) 4122 return -EFAULT; 4123 return 0; 4124 4125 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 4126 4127 if(!capable(CAP_NET_ADMIN)) 4128 return -EPERM; 4129 if (copy_from_user(&new_line, line, size)) 4130 return -EFAULT; 4131 4132 switch (new_line.clock_type) 4133 { 4134 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 4135 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 4136 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 4137 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 4138 case CLOCK_DEFAULT: flags = info->params.flags & 4139 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 4140 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 4141 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 4142 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 4143 default: return -EINVAL; 4144 } 4145 4146 if (new_line.loopback != 0 && new_line.loopback != 1) 4147 return -EINVAL; 4148 4149 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 4150 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 4151 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 4152 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 4153 info->params.flags |= flags; 4154 4155 info->params.loopback = new_line.loopback; 4156 4157 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 4158 info->params.clock_speed = new_line.clock_rate; 4159 else 4160 info->params.clock_speed = 0; 4161 4162 /* if network interface up, reprogram hardware */ 4163 if (info->netcount) { 4164 struct tty_struct *tty = tty_port_tty_get(&info->port); 4165 mgslpc_program_hw(info, tty); 4166 tty_kref_put(tty); 4167 } 4168 return 0; 4169 4170 default: 4171 return hdlc_ioctl(dev, ifr, cmd); 4172 } 4173} 4174 4175/** 4176 * called by network layer when transmit timeout is detected 4177 * 4178 * dev pointer to network device structure 4179 */ 4180static void hdlcdev_tx_timeout(struct net_device *dev) 4181{ 4182 MGSLPC_INFO *info = dev_to_port(dev); 4183 unsigned long flags; 4184 4185 if (debug_level >= DEBUG_LEVEL_INFO) 4186 printk("hdlcdev_tx_timeout(%s)\n",dev->name); 4187 4188 dev->stats.tx_errors++; 4189 dev->stats.tx_aborted_errors++; 4190 4191 spin_lock_irqsave(&info->lock,flags); 4192 tx_stop(info); 4193 spin_unlock_irqrestore(&info->lock,flags); 4194 4195 netif_wake_queue(dev); 4196} 4197 4198/** 4199 * called by device driver when transmit completes 4200 * reenable network layer transmit if stopped 4201 * 4202 * info pointer to device instance information 4203 */ 4204static void hdlcdev_tx_done(MGSLPC_INFO *info) 4205{ 4206 if (netif_queue_stopped(info->netdev)) 4207 netif_wake_queue(info->netdev); 4208} 4209 4210/** 4211 * called by device driver when frame received 4212 * pass frame to network layer 4213 * 4214 * info pointer to device instance information 4215 * buf pointer to buffer contianing frame data 4216 * size count of data bytes in buf 4217 */ 4218static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size) 4219{ 4220 struct sk_buff *skb = dev_alloc_skb(size); 4221 struct net_device *dev = info->netdev; 4222 4223 if (debug_level >= DEBUG_LEVEL_INFO) 4224 printk("hdlcdev_rx(%s)\n",dev->name); 4225 4226 if (skb == NULL) { 4227 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name); 4228 dev->stats.rx_dropped++; 4229 return; 4230 } 4231 4232 memcpy(skb_put(skb, size), buf, size); 4233 4234 skb->protocol = hdlc_type_trans(skb, dev); 4235 4236 dev->stats.rx_packets++; 4237 dev->stats.rx_bytes += size; 4238 4239 netif_rx(skb); 4240} 4241 4242static const struct net_device_ops hdlcdev_ops = { 4243 .ndo_open = hdlcdev_open, 4244 .ndo_stop = hdlcdev_close, 4245 .ndo_change_mtu = hdlc_change_mtu, 4246 .ndo_start_xmit = hdlc_start_xmit, 4247 .ndo_do_ioctl = hdlcdev_ioctl, 4248 .ndo_tx_timeout = hdlcdev_tx_timeout, 4249}; 4250 4251/** 4252 * called by device driver when adding device instance 4253 * do generic HDLC initialization 4254 * 4255 * info pointer to device instance information 4256 * 4257 * returns 0 if success, otherwise error code 4258 */ 4259static int hdlcdev_init(MGSLPC_INFO *info) 4260{ 4261 int rc; 4262 struct net_device *dev; 4263 hdlc_device *hdlc; 4264 4265 /* allocate and initialize network and HDLC layer objects */ 4266 4267 if (!(dev = alloc_hdlcdev(info))) { 4268 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); 4269 return -ENOMEM; 4270 } 4271 4272 /* for network layer reporting purposes only */ 4273 dev->base_addr = info->io_base; 4274 dev->irq = info->irq_level; 4275 4276 /* network layer callbacks and settings */ 4277 dev->netdev_ops = &hdlcdev_ops; 4278 dev->watchdog_timeo = 10 * HZ; 4279 dev->tx_queue_len = 50; 4280 4281 /* generic HDLC layer callbacks and settings */ 4282 hdlc = dev_to_hdlc(dev); 4283 hdlc->attach = hdlcdev_attach; 4284 hdlc->xmit = hdlcdev_xmit; 4285 4286 /* register objects with HDLC layer */ 4287 if ((rc = register_hdlc_device(dev))) { 4288 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 4289 free_netdev(dev); 4290 return rc; 4291 } 4292 4293 info->netdev = dev; 4294 return 0; 4295} 4296 4297/** 4298 * called by device driver when removing device instance 4299 * do generic HDLC cleanup 4300 * 4301 * info pointer to device instance information 4302 */ 4303static void hdlcdev_exit(MGSLPC_INFO *info) 4304{ 4305 unregister_hdlc_device(info->netdev); 4306 free_netdev(info->netdev); 4307 info->netdev = NULL; 4308} 4309 4310#endif /* CONFIG_HDLC */ 4311 4312