tpm_tis.c revision a6f97b293b08877d945ea3f28926aa446dd7ca2e
1/* 2 * Copyright (C) 2005, 2006 IBM Corporation 3 * 4 * Authors: 5 * Leendert van Doorn <leendert@watson.ibm.com> 6 * Kylene Hall <kjhall@us.ibm.com> 7 * 8 * Maintained by: <tpmdd-devel@lists.sourceforge.net> 9 * 10 * Device driver for TCG/TCPA TPM (trusted platform module). 11 * Specifications at www.trustedcomputinggroup.org 12 * 13 * This device driver implements the TPM interface as defined in 14 * the TCG TPM Interface Spec version 1.2, revision 1.0. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation, version 2 of the 19 * License. 20 */ 21#include <linux/init.h> 22#include <linux/module.h> 23#include <linux/moduleparam.h> 24#include <linux/pnp.h> 25#include <linux/interrupt.h> 26#include <linux/wait.h> 27#include "tpm.h" 28 29#define TPM_HEADER_SIZE 10 30 31enum tis_access { 32 TPM_ACCESS_VALID = 0x80, 33 TPM_ACCESS_ACTIVE_LOCALITY = 0x20, 34 TPM_ACCESS_REQUEST_PENDING = 0x04, 35 TPM_ACCESS_REQUEST_USE = 0x02, 36}; 37 38enum tis_status { 39 TPM_STS_VALID = 0x80, 40 TPM_STS_COMMAND_READY = 0x40, 41 TPM_STS_GO = 0x20, 42 TPM_STS_DATA_AVAIL = 0x10, 43 TPM_STS_DATA_EXPECT = 0x08, 44}; 45 46enum tis_int_flags { 47 TPM_GLOBAL_INT_ENABLE = 0x80000000, 48 TPM_INTF_BURST_COUNT_STATIC = 0x100, 49 TPM_INTF_CMD_READY_INT = 0x080, 50 TPM_INTF_INT_EDGE_FALLING = 0x040, 51 TPM_INTF_INT_EDGE_RISING = 0x020, 52 TPM_INTF_INT_LEVEL_LOW = 0x010, 53 TPM_INTF_INT_LEVEL_HIGH = 0x008, 54 TPM_INTF_LOCALITY_CHANGE_INT = 0x004, 55 TPM_INTF_STS_VALID_INT = 0x002, 56 TPM_INTF_DATA_AVAIL_INT = 0x001, 57}; 58 59enum tis_defaults { 60 TIS_MEM_BASE = 0xFED40000, 61 TIS_MEM_LEN = 0x5000, 62 TIS_SHORT_TIMEOUT = 750, /* ms */ 63 TIS_LONG_TIMEOUT = 2000, /* 2 sec */ 64}; 65 66#define TPM_ACCESS(l) (0x0000 | ((l) << 12)) 67#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) 68#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) 69#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) 70#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) 71#define TPM_STS(l) (0x0018 | ((l) << 12)) 72#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) 73 74#define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) 75#define TPM_RID(l) (0x0F04 | ((l) << 12)) 76 77static LIST_HEAD(tis_chips); 78static DEFINE_SPINLOCK(tis_lock); 79 80static int check_locality(struct tpm_chip *chip, int l) 81{ 82 if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & 83 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == 84 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) 85 return chip->vendor.locality = l; 86 87 return -1; 88} 89 90static void release_locality(struct tpm_chip *chip, int l, int force) 91{ 92 if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & 93 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) == 94 (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) 95 iowrite8(TPM_ACCESS_ACTIVE_LOCALITY, 96 chip->vendor.iobase + TPM_ACCESS(l)); 97} 98 99static int request_locality(struct tpm_chip *chip, int l) 100{ 101 unsigned long stop; 102 long rc; 103 104 if (check_locality(chip, l) >= 0) 105 return l; 106 107 iowrite8(TPM_ACCESS_REQUEST_USE, 108 chip->vendor.iobase + TPM_ACCESS(l)); 109 110 if (chip->vendor.irq) { 111 rc = wait_event_interruptible_timeout(chip->vendor.int_queue, 112 (check_locality 113 (chip, l) >= 0), 114 chip->vendor.timeout_a); 115 if (rc > 0) 116 return l; 117 118 } else { 119 /* wait for burstcount */ 120 stop = jiffies + chip->vendor.timeout_a; 121 do { 122 if (check_locality(chip, l) >= 0) 123 return l; 124 msleep(TPM_TIMEOUT); 125 } 126 while (time_before(jiffies, stop)); 127 } 128 return -1; 129} 130 131static u8 tpm_tis_status(struct tpm_chip *chip) 132{ 133 return ioread8(chip->vendor.iobase + 134 TPM_STS(chip->vendor.locality)); 135} 136 137static void tpm_tis_ready(struct tpm_chip *chip) 138{ 139 /* this causes the current command to be aborted */ 140 iowrite8(TPM_STS_COMMAND_READY, 141 chip->vendor.iobase + TPM_STS(chip->vendor.locality)); 142} 143 144static int get_burstcount(struct tpm_chip *chip) 145{ 146 unsigned long stop; 147 int burstcnt; 148 149 /* wait for burstcount */ 150 /* which timeout value, spec has 2 answers (c & d) */ 151 stop = jiffies + chip->vendor.timeout_d; 152 do { 153 burstcnt = ioread8(chip->vendor.iobase + 154 TPM_STS(chip->vendor.locality) + 1); 155 burstcnt += ioread8(chip->vendor.iobase + 156 TPM_STS(chip->vendor.locality) + 157 2) << 8; 158 if (burstcnt) 159 return burstcnt; 160 msleep(TPM_TIMEOUT); 161 } while (time_before(jiffies, stop)); 162 return -EBUSY; 163} 164 165static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout, 166 wait_queue_head_t *queue) 167{ 168 unsigned long stop; 169 long rc; 170 u8 status; 171 172 /* check current status */ 173 status = tpm_tis_status(chip); 174 if ((status & mask) == mask) 175 return 0; 176 177 if (chip->vendor.irq) { 178 rc = wait_event_interruptible_timeout(*queue, 179 ((tpm_tis_status 180 (chip) & mask) == 181 mask), timeout); 182 if (rc > 0) 183 return 0; 184 } else { 185 stop = jiffies + timeout; 186 do { 187 msleep(TPM_TIMEOUT); 188 status = tpm_tis_status(chip); 189 if ((status & mask) == mask) 190 return 0; 191 } while (time_before(jiffies, stop)); 192 } 193 return -ETIME; 194} 195 196static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) 197{ 198 int size = 0, burstcnt; 199 while (size < count && 200 wait_for_stat(chip, 201 TPM_STS_DATA_AVAIL | TPM_STS_VALID, 202 chip->vendor.timeout_c, 203 &chip->vendor.read_queue) 204 == 0) { 205 burstcnt = get_burstcount(chip); 206 for (; burstcnt > 0 && size < count; burstcnt--) 207 buf[size++] = ioread8(chip->vendor.iobase + 208 TPM_DATA_FIFO(chip->vendor. 209 locality)); 210 } 211 return size; 212} 213 214static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) 215{ 216 int size = 0; 217 int expected, status; 218 219 if (count < TPM_HEADER_SIZE) { 220 size = -EIO; 221 goto out; 222 } 223 224 /* read first 10 bytes, including tag, paramsize, and result */ 225 if ((size = 226 recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) { 227 dev_err(chip->dev, "Unable to read header\n"); 228 goto out; 229 } 230 231 expected = be32_to_cpu(*(__be32 *) (buf + 2)); 232 if (expected > count) { 233 size = -EIO; 234 goto out; 235 } 236 237 if ((size += 238 recv_data(chip, &buf[TPM_HEADER_SIZE], 239 expected - TPM_HEADER_SIZE)) < expected) { 240 dev_err(chip->dev, "Unable to read remainder of result\n"); 241 size = -ETIME; 242 goto out; 243 } 244 245 wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, 246 &chip->vendor.int_queue); 247 status = tpm_tis_status(chip); 248 if (status & TPM_STS_DATA_AVAIL) { /* retry? */ 249 dev_err(chip->dev, "Error left over data\n"); 250 size = -EIO; 251 goto out; 252 } 253 254out: 255 tpm_tis_ready(chip); 256 release_locality(chip, chip->vendor.locality, 0); 257 return size; 258} 259 260/* 261 * If interrupts are used (signaled by an irq set in the vendor structure) 262 * tpm.c can skip polling for the data to be available as the interrupt is 263 * waited for here 264 */ 265static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len) 266{ 267 int rc, status, burstcnt; 268 size_t count = 0; 269 u32 ordinal; 270 271 if (request_locality(chip, 0) < 0) 272 return -EBUSY; 273 274 status = tpm_tis_status(chip); 275 if ((status & TPM_STS_COMMAND_READY) == 0) { 276 tpm_tis_ready(chip); 277 if (wait_for_stat 278 (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b, 279 &chip->vendor.int_queue) < 0) { 280 rc = -ETIME; 281 goto out_err; 282 } 283 } 284 285 while (count < len - 1) { 286 burstcnt = get_burstcount(chip); 287 for (; burstcnt > 0 && count < len - 1; burstcnt--) { 288 iowrite8(buf[count], chip->vendor.iobase + 289 TPM_DATA_FIFO(chip->vendor.locality)); 290 count++; 291 } 292 293 wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, 294 &chip->vendor.int_queue); 295 status = tpm_tis_status(chip); 296 if ((status & TPM_STS_DATA_EXPECT) == 0) { 297 rc = -EIO; 298 goto out_err; 299 } 300 } 301 302 /* write last byte */ 303 iowrite8(buf[count], 304 chip->vendor.iobase + 305 TPM_DATA_FIFO(chip->vendor.locality)); 306 wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, 307 &chip->vendor.int_queue); 308 status = tpm_tis_status(chip); 309 if ((status & TPM_STS_DATA_EXPECT) != 0) { 310 rc = -EIO; 311 goto out_err; 312 } 313 314 /* go and do it */ 315 iowrite8(TPM_STS_GO, 316 chip->vendor.iobase + TPM_STS(chip->vendor.locality)); 317 318 if (chip->vendor.irq) { 319 ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); 320 if (wait_for_stat 321 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, 322 tpm_calc_ordinal_duration(chip, ordinal), 323 &chip->vendor.read_queue) < 0) { 324 rc = -ETIME; 325 goto out_err; 326 } 327 } 328 return len; 329out_err: 330 tpm_tis_ready(chip); 331 release_locality(chip, chip->vendor.locality, 0); 332 return rc; 333} 334 335static const struct file_operations tis_ops = { 336 .owner = THIS_MODULE, 337 .llseek = no_llseek, 338 .open = tpm_open, 339 .read = tpm_read, 340 .write = tpm_write, 341 .release = tpm_release, 342}; 343 344static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL); 345static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL); 346static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL); 347static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL); 348static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL); 349static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated, 350 NULL); 351static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL); 352static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel); 353 354static struct attribute *tis_attrs[] = { 355 &dev_attr_pubek.attr, 356 &dev_attr_pcrs.attr, 357 &dev_attr_enabled.attr, 358 &dev_attr_active.attr, 359 &dev_attr_owned.attr, 360 &dev_attr_temp_deactivated.attr, 361 &dev_attr_caps.attr, 362 &dev_attr_cancel.attr, NULL, 363}; 364 365static struct attribute_group tis_attr_grp = { 366 .attrs = tis_attrs 367}; 368 369static struct tpm_vendor_specific tpm_tis = { 370 .status = tpm_tis_status, 371 .recv = tpm_tis_recv, 372 .send = tpm_tis_send, 373 .cancel = tpm_tis_ready, 374 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, 375 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, 376 .req_canceled = TPM_STS_COMMAND_READY, 377 .attr_group = &tis_attr_grp, 378 .miscdev = { 379 .fops = &tis_ops,}, 380}; 381 382static irqreturn_t tis_int_probe(int irq, void *dev_id) 383{ 384 struct tpm_chip *chip = dev_id; 385 u32 interrupt; 386 387 interrupt = ioread32(chip->vendor.iobase + 388 TPM_INT_STATUS(chip->vendor.locality)); 389 390 if (interrupt == 0) 391 return IRQ_NONE; 392 393 chip->vendor.irq = irq; 394 395 /* Clear interrupts handled with TPM_EOI */ 396 iowrite32(interrupt, 397 chip->vendor.iobase + 398 TPM_INT_STATUS(chip->vendor.locality)); 399 return IRQ_HANDLED; 400} 401 402static irqreturn_t tis_int_handler(int dummy, void *dev_id) 403{ 404 struct tpm_chip *chip = dev_id; 405 u32 interrupt; 406 int i; 407 408 interrupt = ioread32(chip->vendor.iobase + 409 TPM_INT_STATUS(chip->vendor.locality)); 410 411 if (interrupt == 0) 412 return IRQ_NONE; 413 414 if (interrupt & TPM_INTF_DATA_AVAIL_INT) 415 wake_up_interruptible(&chip->vendor.read_queue); 416 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT) 417 for (i = 0; i < 5; i++) 418 if (check_locality(chip, i) >= 0) 419 break; 420 if (interrupt & 421 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT | 422 TPM_INTF_CMD_READY_INT)) 423 wake_up_interruptible(&chip->vendor.int_queue); 424 425 /* Clear interrupts handled with TPM_EOI */ 426 iowrite32(interrupt, 427 chip->vendor.iobase + 428 TPM_INT_STATUS(chip->vendor.locality)); 429 ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); 430 return IRQ_HANDLED; 431} 432 433static int interrupts = 1; 434module_param(interrupts, bool, 0444); 435MODULE_PARM_DESC(interrupts, "Enable interrupts"); 436 437static int tpm_tis_init(struct device *dev, resource_size_t start, 438 resource_size_t len, unsigned int irq) 439{ 440 u32 vendor, intfcaps, intmask; 441 int rc, i; 442 struct tpm_chip *chip; 443 444 if (!(chip = tpm_register_hardware(dev, &tpm_tis))) 445 return -ENODEV; 446 447 chip->vendor.iobase = ioremap(start, len); 448 if (!chip->vendor.iobase) { 449 rc = -EIO; 450 goto out_err; 451 } 452 453 if (request_locality(chip, 0) != 0) { 454 rc = -ENODEV; 455 goto out_err; 456 } 457 458 vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); 459 460 /* Default timeouts */ 461 chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT); 462 chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT); 463 chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT); 464 chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT); 465 466 dev_info(dev, 467 "1.2 TPM (device-id 0x%X, rev-id %d)\n", 468 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0))); 469 470 /* Figure out the capabilities */ 471 intfcaps = 472 ioread32(chip->vendor.iobase + 473 TPM_INTF_CAPS(chip->vendor.locality)); 474 dev_dbg(dev, "TPM interface capabilities (0x%x):\n", 475 intfcaps); 476 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC) 477 dev_dbg(dev, "\tBurst Count Static\n"); 478 if (intfcaps & TPM_INTF_CMD_READY_INT) 479 dev_dbg(dev, "\tCommand Ready Int Support\n"); 480 if (intfcaps & TPM_INTF_INT_EDGE_FALLING) 481 dev_dbg(dev, "\tInterrupt Edge Falling\n"); 482 if (intfcaps & TPM_INTF_INT_EDGE_RISING) 483 dev_dbg(dev, "\tInterrupt Edge Rising\n"); 484 if (intfcaps & TPM_INTF_INT_LEVEL_LOW) 485 dev_dbg(dev, "\tInterrupt Level Low\n"); 486 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH) 487 dev_dbg(dev, "\tInterrupt Level High\n"); 488 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT) 489 dev_dbg(dev, "\tLocality Change Int Support\n"); 490 if (intfcaps & TPM_INTF_STS_VALID_INT) 491 dev_dbg(dev, "\tSts Valid Int Support\n"); 492 if (intfcaps & TPM_INTF_DATA_AVAIL_INT) 493 dev_dbg(dev, "\tData Avail Int Support\n"); 494 495 /* INTERRUPT Setup */ 496 init_waitqueue_head(&chip->vendor.read_queue); 497 init_waitqueue_head(&chip->vendor.int_queue); 498 499 intmask = 500 ioread32(chip->vendor.iobase + 501 TPM_INT_ENABLE(chip->vendor.locality)); 502 503 intmask |= TPM_INTF_CMD_READY_INT 504 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT 505 | TPM_INTF_STS_VALID_INT; 506 507 iowrite32(intmask, 508 chip->vendor.iobase + 509 TPM_INT_ENABLE(chip->vendor.locality)); 510 if (interrupts) 511 chip->vendor.irq = irq; 512 if (interrupts && !chip->vendor.irq) { 513 chip->vendor.irq = 514 ioread8(chip->vendor.iobase + 515 TPM_INT_VECTOR(chip->vendor.locality)); 516 517 for (i = 3; i < 16 && chip->vendor.irq == 0; i++) { 518 iowrite8(i, chip->vendor.iobase + 519 TPM_INT_VECTOR(chip->vendor.locality)); 520 if (request_irq 521 (i, tis_int_probe, IRQF_SHARED, 522 chip->vendor.miscdev.name, chip) != 0) { 523 dev_info(chip->dev, 524 "Unable to request irq: %d for probe\n", 525 i); 526 continue; 527 } 528 529 /* Clear all existing */ 530 iowrite32(ioread32 531 (chip->vendor.iobase + 532 TPM_INT_STATUS(chip->vendor.locality)), 533 chip->vendor.iobase + 534 TPM_INT_STATUS(chip->vendor.locality)); 535 536 /* Turn on */ 537 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, 538 chip->vendor.iobase + 539 TPM_INT_ENABLE(chip->vendor.locality)); 540 541 /* Generate Interrupts */ 542 tpm_gen_interrupt(chip); 543 544 /* Turn off */ 545 iowrite32(intmask, 546 chip->vendor.iobase + 547 TPM_INT_ENABLE(chip->vendor.locality)); 548 free_irq(i, chip); 549 } 550 } 551 if (chip->vendor.irq) { 552 iowrite8(chip->vendor.irq, 553 chip->vendor.iobase + 554 TPM_INT_VECTOR(chip->vendor.locality)); 555 if (request_irq 556 (chip->vendor.irq, tis_int_handler, IRQF_SHARED, 557 chip->vendor.miscdev.name, chip) != 0) { 558 dev_info(chip->dev, 559 "Unable to request irq: %d for use\n", 560 chip->vendor.irq); 561 chip->vendor.irq = 0; 562 } else { 563 /* Clear all existing */ 564 iowrite32(ioread32 565 (chip->vendor.iobase + 566 TPM_INT_STATUS(chip->vendor.locality)), 567 chip->vendor.iobase + 568 TPM_INT_STATUS(chip->vendor.locality)); 569 570 /* Turn on */ 571 iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, 572 chip->vendor.iobase + 573 TPM_INT_ENABLE(chip->vendor.locality)); 574 } 575 } 576 577 INIT_LIST_HEAD(&chip->vendor.list); 578 spin_lock(&tis_lock); 579 list_add(&chip->vendor.list, &tis_chips); 580 spin_unlock(&tis_lock); 581 582 tpm_get_timeouts(chip); 583 tpm_continue_selftest(chip); 584 585 return 0; 586out_err: 587 if (chip->vendor.iobase) 588 iounmap(chip->vendor.iobase); 589 tpm_remove_hardware(chip->dev); 590 return rc; 591} 592 593static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev, 594 const struct pnp_device_id *pnp_id) 595{ 596 resource_size_t start, len; 597 unsigned int irq = 0; 598 599 start = pnp_mem_start(pnp_dev, 0); 600 len = pnp_mem_len(pnp_dev, 0); 601 602 if (pnp_irq_valid(pnp_dev, 0)) 603 irq = pnp_irq(pnp_dev, 0); 604 else 605 interrupts = 0; 606 607 return tpm_tis_init(&pnp_dev->dev, start, len, irq); 608} 609 610static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg) 611{ 612 return tpm_pm_suspend(&dev->dev, msg); 613} 614 615static int tpm_tis_pnp_resume(struct pnp_dev *dev) 616{ 617 return tpm_pm_resume(&dev->dev); 618} 619 620static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = { 621 {"PNP0C31", 0}, /* TPM */ 622 {"ATM1200", 0}, /* Atmel */ 623 {"IFX0102", 0}, /* Infineon */ 624 {"BCM0101", 0}, /* Broadcom */ 625 {"NSC1200", 0}, /* National */ 626 /* Add new here */ 627 {"", 0}, /* User Specified */ 628 {"", 0} /* Terminator */ 629}; 630 631static struct pnp_driver tis_pnp_driver = { 632 .name = "tpm_tis", 633 .id_table = tpm_pnp_tbl, 634 .probe = tpm_tis_pnp_init, 635 .suspend = tpm_tis_pnp_suspend, 636 .resume = tpm_tis_pnp_resume, 637}; 638 639#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2 640module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id, 641 sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444); 642MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe"); 643 644static struct device_driver tis_drv = { 645 .name = "tpm_tis", 646 .bus = &platform_bus_type, 647 .owner = THIS_MODULE, 648 .suspend = tpm_pm_suspend, 649 .resume = tpm_pm_resume, 650}; 651 652static struct platform_device *pdev; 653 654static int force; 655module_param(force, bool, 0444); 656MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry"); 657static int __init init_tis(void) 658{ 659 int rc; 660 661 if (force) { 662 rc = driver_register(&tis_drv); 663 if (rc < 0) 664 return rc; 665 if (IS_ERR(pdev=platform_device_register_simple("tpm_tis", -1, NULL, 0))) 666 return PTR_ERR(pdev); 667 if((rc=tpm_tis_init(&pdev->dev, TIS_MEM_BASE, TIS_MEM_LEN, 0)) != 0) { 668 platform_device_unregister(pdev); 669 driver_unregister(&tis_drv); 670 } 671 return rc; 672 } 673 674 return pnp_register_driver(&tis_pnp_driver); 675} 676 677static void __exit cleanup_tis(void) 678{ 679 struct tpm_vendor_specific *i, *j; 680 struct tpm_chip *chip; 681 spin_lock(&tis_lock); 682 list_for_each_entry_safe(i, j, &tis_chips, list) { 683 chip = to_tpm_chip(i); 684 iowrite32(~TPM_GLOBAL_INT_ENABLE & 685 ioread32(chip->vendor.iobase + 686 TPM_INT_ENABLE(chip->vendor. 687 locality)), 688 chip->vendor.iobase + 689 TPM_INT_ENABLE(chip->vendor.locality)); 690 release_locality(chip, chip->vendor.locality, 1); 691 if (chip->vendor.irq) 692 free_irq(chip->vendor.irq, chip); 693 iounmap(i->iobase); 694 list_del(&i->list); 695 tpm_remove_hardware(chip->dev); 696 } 697 spin_unlock(&tis_lock); 698 if (force) { 699 platform_device_unregister(pdev); 700 driver_unregister(&tis_drv); 701 } else 702 pnp_unregister_driver(&tis_pnp_driver); 703} 704 705module_init(init_tis); 706module_exit(cleanup_tis); 707MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); 708MODULE_DESCRIPTION("TPM Driver"); 709MODULE_VERSION("2.0"); 710MODULE_LICENSE("GPL"); 711