fsldma.c revision 0793448187643b50af89d36b08470baf45a3cab4
1173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/* 2173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 4173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 6173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Author: 7173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 10173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Description: 11173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 15a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * This driver instructs the DMA controller to issue the PCI Read Multiple 16a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * command for PCI read operations, instead of using the default PCI Read Line 17a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * command. Please be aware that this setting may result in read pre-fetching 18a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * on some platforms. 19a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * 20173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * This is free software; you can redistribute it and/or modify 21173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * it under the terms of the GNU General Public License as published by 22173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * the Free Software Foundation; either version 2 of the License, or 23173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * (at your option) any later version. 24173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 25173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 26173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 27173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/init.h> 28173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/module.h> 29173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/pci.h> 30173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/interrupt.h> 31173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/dmaengine.h> 32173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/delay.h> 33173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/dma-mapping.h> 34173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/dmapool.h> 35173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include <linux/of_platform.h> 36173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 37bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder#include <asm/fsldma.h> 38173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#include "fsldma.h" 39173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 40a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void dma_init(struct fsldma_chan *chan) 41173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 42173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Reset the channel */ 43a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, 0, 32); 44173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 45a1c03319018061304be28d131073ac13a5cb86fbIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 46173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case FSL_DMA_IP_85XX: 47173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Set the channel to below modes: 48173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * EIE - Error interrupt enable 49173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * EOSIE - End of segments interrupt enable (basic mode) 50173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * EOLNIE - End of links interrupt enable 51173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 52a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE 53173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 54173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 55173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case FSL_DMA_IP_83XX: 56173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Set the channel to below modes: 57173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * EOTIE - End-of-transfer interrupt enable 58a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder * PRC_RM - PCI read multiple 59173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 60a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE 61a7aea373b4ca428f1be2c1fedd2f26c8e3f2864dIra W. Snyder | FSL_DMA_MR_PRC_RM, 32); 62173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 63173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 64173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 65173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 66a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_sr(struct fsldma_chan *chan, u32 val) 67173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 68a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->sr, val, 32); 69173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 70173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 71a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic u32 get_sr(struct fsldma_chan *chan) 72173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 73a1c03319018061304be28d131073ac13a5cb86fbIra Snyder return DMA_IN(chan, &chan->regs->sr, 32); 74173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 75173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 76a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_desc_cnt(struct fsldma_chan *chan, 77173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_dma_ld_hw *hw, u32 count) 78173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 79a1c03319018061304be28d131073ac13a5cb86fbIra Snyder hw->count = CPU_TO_DMA(chan, count, 32); 80173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 81173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 82a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_desc_src(struct fsldma_chan *chan, 83173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 84173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 85173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei u64 snoop_bits; 86173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 87a1c03319018061304be28d131073ac13a5cb86fbIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 88173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 89a1c03319018061304be28d131073ac13a5cb86fbIra Snyder hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); 90173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 91173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 92a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_desc_dst(struct fsldma_chan *chan, 93738f5f7e1ae876448cb7d9c82bea258b69386647Ira Snyder struct fsl_dma_ld_hw *hw, dma_addr_t dst) 94173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 95173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei u64 snoop_bits; 96173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 97a1c03319018061304be28d131073ac13a5cb86fbIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 98173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 99a1c03319018061304be28d131073ac13a5cb86fbIra Snyder hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); 100173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 101173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 102a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_desc_next(struct fsldma_chan *chan, 103173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 104173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 105173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei u64 snoop_bits; 106173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 107a1c03319018061304be28d131073ac13a5cb86fbIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 108173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei ? FSL_DMA_SNEN : 0; 109a1c03319018061304be28d131073ac13a5cb86fbIra Snyder hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 110173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 111173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 112a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) 113173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 114a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); 115173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 116173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 117a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic dma_addr_t get_cdar(struct fsldma_chan *chan) 118173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 119a1c03319018061304be28d131073ac13a5cb86fbIra Snyder return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; 120173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 121173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 122a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic dma_addr_t get_ndar(struct fsldma_chan *chan) 123173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 124a1c03319018061304be28d131073ac13a5cb86fbIra Snyder return DMA_IN(chan, &chan->regs->ndar, 64); 125173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 126173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 127a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic u32 get_bcr(struct fsldma_chan *chan) 128f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei{ 129a1c03319018061304be28d131073ac13a5cb86fbIra Snyder return DMA_IN(chan, &chan->regs->bcr, 32); 130f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei} 131f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei 132a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic int dma_is_idle(struct fsldma_chan *chan) 133173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 134a1c03319018061304be28d131073ac13a5cb86fbIra Snyder u32 sr = get_sr(chan); 135173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 136173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 137173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 138a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void dma_start(struct fsldma_chan *chan) 139173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 140272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder u32 mode; 141272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 142a1c03319018061304be28d131073ac13a5cb86fbIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 143272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 144a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 145a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 146a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->bcr, 0, 32); 147272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_EMP_EN; 148272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder } else { 149272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode &= ~FSL_DMA_MR_EMP_EN; 150272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder } 15143a1a3ed6bf5a1b9ae197b4f5f20033baf19db61Ira Snyder } 152173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 153a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->feature & FSL_DMA_CHAN_START_EXT) 154272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_EMS_EN; 155173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei else 156272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_CS; 157173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 158a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 159173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 160173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 161a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void dma_halt(struct fsldma_chan *chan) 162173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 163272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder u32 mode; 164900325a6ce33995688b7a680a34e7698f16f4d72Dan Williams int i; 165900325a6ce33995688b7a680a34e7698f16f4d72Dan Williams 166a1c03319018061304be28d131073ac13a5cb86fbIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 167272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_CA; 168a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 169272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 170272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); 171a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 172173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 173900325a6ce33995688b7a680a34e7698f16f4d72Dan Williams for (i = 0; i < 100; i++) { 174a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (dma_is_idle(chan)) 1759c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder return; 1769c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 177173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei udelay(10); 178900325a6ce33995688b7a680a34e7698f16f4d72Dan Williams } 179272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 1809c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (!dma_is_idle(chan)) 181a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_err(chan->dev, "DMA halt timeout!\n"); 182173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 183173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 184a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void set_ld_eol(struct fsldma_chan *chan, 185173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_desc_sw *desc) 186173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 187776c8943f2766f2819fafd88fdfbaf418ecd6e41Ira Snyder u64 snoop_bits; 188776c8943f2766f2819fafd88fdfbaf418ecd6e41Ira Snyder 189a1c03319018061304be28d131073ac13a5cb86fbIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 190776c8943f2766f2819fafd88fdfbaf418ecd6e41Ira Snyder ? FSL_DMA_SNEN : 0; 191776c8943f2766f2819fafd88fdfbaf418ecd6e41Ira Snyder 192a1c03319018061304be28d131073ac13a5cb86fbIra Snyder desc->hw.next_ln_addr = CPU_TO_DMA(chan, 193a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 194776c8943f2766f2819fafd88fdfbaf418ecd6e41Ira Snyder | snoop_bits, 64); 195173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 196173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 197173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 198173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 199a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 200173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * @size : Address loop size, 0 for disable loop 201173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 202173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * The set source address hold transfer size. The source 203173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * address hold or loop transfer size is when the DMA transfer 204173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * data from source address (SA), if the loop size is 4, the DMA will 205173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 206173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * SA + 1 ... and so on. 207173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 208a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) 209173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 210272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder u32 mode; 211272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 212a1c03319018061304be28d131073ac13a5cb86fbIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 213272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 214173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei switch (size) { 215173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 0: 216272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode &= ~FSL_DMA_MR_SAHE; 217173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 218173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 1: 219173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 2: 220173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 4: 221173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 8: 222272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); 223173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 224173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 225272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 226a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 227173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 228173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 229173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 230738f5f7e1ae876448cb7d9c82bea258b69386647Ira Snyder * fsl_chan_set_dst_loop_size - Set destination address hold transfer size 231a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 232173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * @size : Address loop size, 0 for disable loop 233173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 234173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * The set destination address hold transfer size. The destination 235173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * address hold or loop transfer size is when the DMA transfer 236173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 237173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 238173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * TA + 1 ... and so on. 239173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 240a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) 241173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 242272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder u32 mode; 243272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 244a1c03319018061304be28d131073ac13a5cb86fbIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 245272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 246173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei switch (size) { 247173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 0: 248272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode &= ~FSL_DMA_MR_DAHE; 249173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 250173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 1: 251173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 2: 252173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 4: 253173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case 8: 254272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); 255173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 256173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 257272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 258a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 259173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 260173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 261173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 262e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * fsl_chan_set_request_count - Set DMA Request Count for external control 263a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 264e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * @size : Number of bytes to transfer in a single request 265e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * 266e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 267e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * The DMA request count is how many bytes are allowed to transfer before 268e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * pausing the channel, after which a new assertion of DREQ# resumes channel 269e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * operation. 270173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 271e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * A size of 0 disables external pause control. The maximum size is 1024. 272173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 273a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) 274173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 275272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder u32 mode; 276272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 277e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder BUG_ON(size > 1024); 278272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 279a1c03319018061304be28d131073ac13a5cb86fbIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 280272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder mode |= (__ilog2(size) << 24) & 0x0f000000; 281272ca655090978bdaa2630fc44fb2c03da5576fdIra Snyder 282a1c03319018061304be28d131073ac13a5cb86fbIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 283e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder} 284173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 285e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder/** 286e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * fsl_chan_toggle_ext_pause - Toggle channel external pause status 287a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 288e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * @enable : 0 is disabled, 1 is enabled. 289e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * 290e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 291e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * The DMA Request Count feature should be used in addition to this feature 292e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder * to set the number of bytes to transfer before pausing the channel. 293e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder */ 294a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) 295e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder{ 296e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder if (enable) 297a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 298e6c7ecb64e08ef346cb7062b4a5421f00bc602bdIra Snyder else 299a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 300173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 301173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 302173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 303173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 304a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 305173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * @enable : 0 is disabled, 1 is enabled. 306173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 307173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * If enable the external start, the channel can be started by an 308173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * external DMA start pin. So the dma_start() does not start the 309173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * transfer immediately. The DMA channel will wait for the 310173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * control pin asserted. 311173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 312a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) 313173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 314173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (enable) 315a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->feature |= FSL_DMA_CHAN_START_EXT; 316173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei else 317a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->feature &= ~FSL_DMA_CHAN_START_EXT; 318173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 319173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 3209c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderstatic void append_ld_queue(struct fsldma_chan *chan, 3219c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc) 3229c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder{ 3239c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); 3249c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 3259c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (list_empty(&chan->ld_pending)) 3269c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder goto out_splice; 3279c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 3289c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 3299c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * Add the hardware descriptor to the chain of hardware descriptors 3309c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * that already exists in memory. 3319c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * 3329c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * This will un-set the EOL bit of the existing transaction, and the 3339c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * last link in this transaction will become the EOL descriptor. 3349c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 3359c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder set_desc_next(chan, &tail->hw, desc->async_tx.phys); 3369c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 3379c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 3389c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * Add the software descriptor and all children to the list 3399c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * of pending transactions 3409c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 3419c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderout_splice: 3429c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 3439c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder} 3449c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 345173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 346173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 347a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = to_fsl_chan(tx->chan); 348eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 349eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams struct fsl_desc_sw *child; 350173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei unsigned long flags; 351173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cookie_t cookie; 352173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 353a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 354173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 3559c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 3569c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * assign cookies to all of the software descriptors 3579c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * that make up this transaction 3589c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 359a1c03319018061304be28d131073ac13a5cb86fbIra Snyder cookie = chan->common.cookie; 360eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams list_for_each_entry(child, &desc->tx_list, node) { 361bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder cookie++; 362bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder if (cookie < 0) 363bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder cookie = 1; 364bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder 3656ca3a7a96e91b1aa8c704153c992b191d35b5747Steven J. Magnani child->async_tx.cookie = cookie; 366bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder } 367bcfb7465c03a8c62c89da374677df56f6b894d44Ira Snyder 368a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->common.cookie = cookie; 3699c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 3709c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* put this transaction onto the tail of the pending queue */ 371a1c03319018061304be28d131073ac13a5cb86fbIra Snyder append_ld_queue(chan, desc); 372173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 373a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 374173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 375173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return cookie; 376173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 377173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 378173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 379173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 380a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 381173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 382173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Return - The descriptor allocated. NULL for failed. 383173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 384173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic struct fsl_desc_sw *fsl_dma_alloc_descriptor( 385a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan) 386173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 3879c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc; 388173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_addr_t pdesc; 3899c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 3909c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); 3919c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (!desc) { 3929c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "out of memory for link desc\n"); 3939c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder return NULL; 394173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 395173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 3969c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder memset(desc, 0, sizeof(*desc)); 3979c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder INIT_LIST_HEAD(&desc->tx_list); 3989c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 3999c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder desc->async_tx.tx_submit = fsl_dma_tx_submit; 4009c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder desc->async_tx.phys = pdesc; 4019c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 4029c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder return desc; 403173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 404173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 405173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 406173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 407173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 408a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 409173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 410173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * This function will create a dma pool for descriptor allocation. 411173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 412173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * Return - The number of descriptors allocated. 413173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 414a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) 415173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 416a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 41777cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 41877cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi /* Has this channel already been allocated? */ 419a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->desc_pool) 42077cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi return 1; 421173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 4229c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 4239c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * We need the descriptor to be aligned to 32bytes 424173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * for meeting FSL DMA specification requirement. 425173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 426a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 4279c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder chan->dev, 4289c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder sizeof(struct fsl_desc_sw), 4299c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder __alignof__(struct fsl_desc_sw), 0); 430a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!chan->desc_pool) { 4319c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_err(chan->dev, "unable to allocate channel %d " 4329c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder "descriptor pool\n", chan->id); 4339c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder return -ENOMEM; 434173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 435173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 4369c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* there is at least one descriptor free to be allocated */ 437173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return 1; 438173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 439173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 440173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 4419c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * fsldma_free_desc_list - Free all descriptors in a queue 4429c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * @chan: Freescae DMA channel 4439c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * @list: the list to free 4449c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * 4459c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * LOCKING: must hold chan->desc_lock 4469c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 4479c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderstatic void fsldma_free_desc_list(struct fsldma_chan *chan, 4489c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct list_head *list) 4499c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder{ 4509c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc, *_desc; 4519c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 4529c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_for_each_entry_safe(desc, _desc, list, node) { 4539c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_del(&desc->node); 4549c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 4559c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder } 4569c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder} 4579c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 4589c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderstatic void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, 4599c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct list_head *list) 4609c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder{ 4619c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc, *_desc; 4629c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 4639c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_for_each_entry_safe_reverse(desc, _desc, list, node) { 4649c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_del(&desc->node); 4659c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 4669c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder } 4679c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder} 4689c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 4699c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder/** 470173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 471a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 472173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 473a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_dma_free_chan_resources(struct dma_chan *dchan) 474173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 475a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 476173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei unsigned long flags; 477173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 478a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_dbg(chan->dev, "Free all channel resources.\n"); 479a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 4809c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 4819c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list(chan, &chan->ld_running); 482a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 48377cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 4849c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_pool_destroy(chan->desc_pool); 485a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->desc_pool = NULL; 486173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 487173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 4882187c269ad29510f1d65ec684133d1d3426d0eedZhang Weistatic struct dma_async_tx_descriptor * 489a1c03319018061304be28d131073ac13a5cb86fbIra Snyderfsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) 4902187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei{ 491a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan; 4922187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei struct fsl_desc_sw *new; 4932187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 494a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!dchan) 4952187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei return NULL; 4962187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 497a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan = to_fsl_chan(dchan); 4982187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 499a1c03319018061304be28d131073ac13a5cb86fbIra Snyder new = fsl_dma_alloc_descriptor(chan); 5002187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei if (!new) { 501a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_err(chan->dev, "No free memory for link descriptor\n"); 5022187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei return NULL; 5032187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei } 5042187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 5052187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei new->async_tx.cookie = -EBUSY; 506636bdeaa1243327501edfd2a597ed7443eb4239aDan Williams new->async_tx.flags = flags; 5072187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 508f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei /* Insert the link descriptor to the LD ring */ 509eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams list_add_tail(&new->node, &new->tx_list); 510f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei 5112187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 512a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_ld_eol(chan, new); 5132187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 5142187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei return &new->async_tx; 5152187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei} 5162187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei 517173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Weistatic struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 518a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, 519173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei size_t len, unsigned long flags) 520173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 521a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan; 522173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 523173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei size_t copy; 524173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 525a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!dchan) 526173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return NULL; 527173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 528173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!len) 529173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return NULL; 530173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 531a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan = to_fsl_chan(dchan); 532173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 533173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei do { 534173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 535173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Allocate the link descriptor from DMA pool */ 536a1c03319018061304be28d131073ac13a5cb86fbIra Snyder new = fsl_dma_alloc_descriptor(chan); 537173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!new) { 538a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_err(chan->dev, 539173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei "No free memory for link descriptor\n"); 5402e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder goto fail; 541173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 542173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#ifdef FSL_DMA_LD_DEBUG 543a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_dbg(chan->dev, "new link desc alloc %p\n", new); 544173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei#endif 545173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 54656822843ff99c88c778a614851328fcbb1503d10Zhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 547173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 548a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_cnt(chan, &new->hw, copy); 549a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_src(chan, &new->hw, dma_src); 550a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_dst(chan, &new->hw, dma_dst); 551173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 552173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!first) 553173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei first = new; 554173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei else 555a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_next(chan, &prev->hw, new->async_tx.phys); 556173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 557173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei new->async_tx.cookie = 0; 558636bdeaa1243327501edfd2a597ed7443eb4239aDan Williams async_tx_ack(&new->async_tx); 559173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 560173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei prev = new; 561173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei len -= copy; 562173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_src += copy; 563738f5f7e1ae876448cb7d9c82bea258b69386647Ira Snyder dma_dst += copy; 564173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 565173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Insert the link descriptor to the LD ring */ 566eda34234578fd822c950fd06b5c5ff7ac08b3001Dan Williams list_add_tail(&new->node, &first->tx_list); 567173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } while (len); 568173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 569636bdeaa1243327501edfd2a597ed7443eb4239aDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 570173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei new->async_tx.cookie = -EBUSY; 571173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 572173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Set End-of-link to the last link descriptor of new list*/ 573a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_ld_eol(chan, new); 574173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 5752e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder return &first->async_tx; 5762e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder 5772e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyderfail: 5782e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder if (!first) 5792e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder return NULL; 5802e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder 5819c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 5822e077f8e8337e52eef3c39c24c31e103b11a0326Ira Snyder return NULL; 583173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 584173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 585173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 586bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 587bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * @chan: DMA channel 588bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * @sgl: scatterlist to transfer to/from 589bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * @sg_len: number of entries in @scatterlist 590bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * @direction: DMA direction 591bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * @flags: DMAEngine flags 592bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 593bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the 594bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * DMA_SLAVE API, this gets the device-specific information from the 595bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * chan->private variable. 596bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 597bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyderstatic struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 598a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 599bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder enum dma_data_direction direction, unsigned long flags) 600bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder{ 601a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan; 602bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; 603bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder struct fsl_dma_slave *slave; 604bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder size_t copy; 605bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 606bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder int i; 607bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder struct scatterlist *sg; 608bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder size_t sg_used; 609bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder size_t hw_used; 610bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder struct fsl_dma_hw_addr *hw; 611bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_addr_t dma_dst, dma_src; 612bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 613a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!dchan) 614bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 615bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 616a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!dchan->private) 617bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 618bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 619a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan = to_fsl_chan(dchan); 620a1c03319018061304be28d131073ac13a5cb86fbIra Snyder slave = dchan->private; 621bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 622bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (list_empty(&slave->addresses)) 623bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 624bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 625bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); 626bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw_used = 0; 627bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 628bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 629bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * Build the hardware transaction to copy from the scatterlist to 630bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * the hardware, or from the hardware to the scatterlist 631bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 632bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * If you are copying from the hardware to the scatterlist and it 633bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * takes two hardware entries to fill an entire page, then both 634bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * hardware entries will be coalesced into the same page 635bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 636bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * If you are copying from the scatterlist to the hardware and a 637bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * single page can fill two hardware entries, then the data will 638bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * be read out of the page into the first hardware entry, and so on 639bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 640bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder for_each_sg(sgl, sg, sg_len, i) { 641bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder sg_used = 0; 642bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 643bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Loop until the entire scatterlist entry is used */ 644bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder while (sg_used < sg_dma_len(sg)) { 645bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 646bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 647bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * If we've used up the current hardware address/length 648bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * pair, we need to load a new one 649bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 650bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * This is done in a while loop so that descriptors with 651bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * length == 0 will be skipped 652bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 653bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder while (hw_used >= hw->length) { 654bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 655bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 656bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * If the current hardware entry is the last 657bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * entry in the list, we're finished 658bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 659bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (list_is_last(&hw->entry, &slave->addresses)) 660bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder goto finished; 661bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 662bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Get the next hardware address/length pair */ 663bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw = list_entry(hw->entry.next, 664bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder struct fsl_dma_hw_addr, entry); 665bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw_used = 0; 666bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 667bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 668bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Allocate the link descriptor from DMA pool */ 669a1c03319018061304be28d131073ac13a5cb86fbIra Snyder new = fsl_dma_alloc_descriptor(chan); 670bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (!new) { 671a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_err(chan->dev, "No free memory for " 672bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder "link descriptor\n"); 673bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder goto fail; 674bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 675bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder#ifdef FSL_DMA_LD_DEBUG 676a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_dbg(chan->dev, "new link desc alloc %p\n", new); 677bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder#endif 678bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 679bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 680bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * Calculate the maximum number of bytes to transfer, 681bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * making sure it is less than the DMA controller limit 682bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 683bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder copy = min_t(size_t, sg_dma_len(sg) - sg_used, 684bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw->length - hw_used); 685bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); 686bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 687bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 688bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * DMA_FROM_DEVICE 689bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * from the hardware to the scatterlist 690bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 691bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * DMA_TO_DEVICE 692bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * from the scatterlist to the hardware 693bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 694bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (direction == DMA_FROM_DEVICE) { 695bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_src = hw->address + hw_used; 696bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_dst = sg_dma_address(sg) + sg_used; 697bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } else { 698bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_src = sg_dma_address(sg) + sg_used; 699bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_dst = hw->address + hw_used; 700bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 701bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 702bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Fill in the descriptor */ 703a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_cnt(chan, &new->hw, copy); 704a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_src(chan, &new->hw, dma_src); 705a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_dst(chan, &new->hw, dma_dst); 706bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 707bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 708bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * If this is not the first descriptor, chain the 709bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * current descriptor after the previous descriptor 710bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 711bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (!first) { 712bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder first = new; 713bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } else { 714a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_desc_next(chan, &prev->hw, 715bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder new->async_tx.phys); 716bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 717bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 718bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder new->async_tx.cookie = 0; 719bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder async_tx_ack(&new->async_tx); 720bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 721bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder prev = new; 722bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder sg_used += copy; 723bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder hw_used += copy; 724bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 725bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Insert the link descriptor into the LD ring */ 726bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder list_add_tail(&new->node, &first->tx_list); 727bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 728bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder } 729bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 730bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyderfinished: 731bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 732bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* All of the hardware address/length pairs had length == 0 */ 733bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (!first || !new) 734bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 735bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 736bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder new->async_tx.flags = flags; 737bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder new->async_tx.cookie = -EBUSY; 738bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 739bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Set End-of-link to the last link descriptor of new list */ 740a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_ld_eol(chan, new); 741bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 742bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Enable extra controller features */ 743a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->set_src_loop_size) 744a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_src_loop_size(chan, slave->src_loop_size); 745bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 746a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->set_dst_loop_size) 747a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_dst_loop_size(chan, slave->dst_loop_size); 748bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 749a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->toggle_ext_start) 750a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->toggle_ext_start(chan, slave->external_start); 751bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 752a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->toggle_ext_pause) 753a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->toggle_ext_pause(chan, slave->external_pause); 754bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 755a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->set_request_count) 756a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_request_count(chan, slave->request_count); 757bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 758bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return &first->async_tx; 759bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 760bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyderfail: 761bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* If first was not set, then we failed to allocate the very first 762bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * descriptor, and we're done */ 763bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder if (!first) 764bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 765bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 766bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* 767bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * First is set, so all of the descriptors we allocated have been added 768bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * to first->tx_list, INCLUDING "first" itself. Therefore we 769bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * must traverse the list backwards freeing each descriptor in turn 770bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * 771bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder * We're re-using variables for the loop, oh well 772bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder */ 7739c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 774bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder return NULL; 775bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder} 776bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 777c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleijstatic int fsl_dma_device_control(struct dma_chan *dchan, 778c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij enum dma_ctrl_cmd cmd) 779bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder{ 780a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan; 781bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder unsigned long flags; 782bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 783c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij /* Only supports DMA_TERMINATE_ALL */ 784c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij if (cmd != DMA_TERMINATE_ALL) 785c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij return -ENXIO; 786c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij 787a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!dchan) 788c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij return -EINVAL; 789bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 790a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan = to_fsl_chan(dchan); 791bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 792bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Halt the DMA engine */ 793a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dma_halt(chan); 794bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 795a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 796bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 797bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder /* Remove and free all of the descriptors in the LD queue */ 7989c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 7999c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder fsldma_free_desc_list(chan, &chan->ld_running); 800bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 801a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 802c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij 803c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij return 0; 804bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder} 805bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder 806bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder/** 807173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 808a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 8099c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * 8109c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * CONTEXT: hardirq 811173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 812a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) 813173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 8149c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc; 8159c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder unsigned long flags; 8169c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_cookie_t cookie; 817173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 8189c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder spin_lock_irqsave(&chan->desc_lock, flags); 819173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 8209c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (list_empty(&chan->ld_running)) { 8219c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "no running descriptors\n"); 8229c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder goto out_unlock; 823173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 8249c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 8259c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* Get the last descriptor, update the cookie to that */ 8269c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder desc = to_fsl_desc(chan->ld_running.prev); 8279c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (dma_is_idle(chan)) 8289c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder cookie = desc->async_tx.cookie; 82976bd061f5c7b7550cdaed68ad6219ea7cee288fcSteven J. Magnani else { 8309c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder cookie = desc->async_tx.cookie - 1; 83176bd061f5c7b7550cdaed68ad6219ea7cee288fcSteven J. Magnani if (unlikely(cookie < DMA_MIN_COOKIE)) 83276bd061f5c7b7550cdaed68ad6219ea7cee288fcSteven J. Magnani cookie = DMA_MAX_COOKIE; 83376bd061f5c7b7550cdaed68ad6219ea7cee288fcSteven J. Magnani } 8349c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 8359c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder chan->completed_cookie = cookie; 8369c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 8379c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderout_unlock: 8389c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 8399c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder} 8409c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 8419c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder/** 8429c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * fsldma_desc_status - Check the status of a descriptor 8439c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * @chan: Freescale DMA channel 8449c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * @desc: DMA SW descriptor 8459c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * 8469c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * This function will return the status of the given descriptor 8479c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 8489c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyderstatic enum dma_status fsldma_desc_status(struct fsldma_chan *chan, 8499c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc) 8509c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder{ 8519c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder return dma_async_is_complete(desc->async_tx.cookie, 8529c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder chan->completed_cookie, 8539c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder chan->common.cookie); 854173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 855173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 856173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 857173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 858a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 859173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * 860173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * This function clean up the ld_queue of DMA channel. 861173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 862a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_ld_cleanup(struct fsldma_chan *chan) 863173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 864173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei struct fsl_desc_sw *desc, *_desc; 865173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei unsigned long flags; 866173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 867a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 868173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 8699c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); 8709c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { 871173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_async_tx_callback callback; 872173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei void *callback_param; 873173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 8749c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) 875173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei break; 876173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 8779c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* Remove from the list of running transactions */ 878173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei list_del(&desc->node); 879173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 880173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Run the link descriptor callback function */ 8819c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder callback = desc->async_tx.callback; 8829c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder callback_param = desc->async_tx.callback_param; 883173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (callback) { 884a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 8859c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "LD %p callback\n", desc); 886173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei callback(callback_param); 887a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 888173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 8899c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 8909c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* Run any dependencies, then free the descriptor */ 8919c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_run_dependencies(&desc->async_tx); 8929c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 893173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 8949c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 895a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 896173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 897173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 898173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 8999c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * fsl_chan_xfer_ld_queue - transfer any pending transactions 900a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 9019c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * 9029c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * This will make sure that any pending transactions will be run. 9039c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * If the DMA controller is idle, it will be started. Otherwise, 9049c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * the DMA controller's interrupt handler will start any pending 9059c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * transactions when it becomes idle. 906173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 907a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) 908173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 9099c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder struct fsl_desc_sw *desc; 910173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei unsigned long flags; 911173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 912a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 913138ef0185177a6d221d24b6aa8f12d867fbbef90Ira Snyder 9149c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9159c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * If the list of pending descriptors is empty, then we 9169c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * don't need to do any work at all 9179c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 9189c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (list_empty(&chan->ld_pending)) { 9199c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "no pending LDs\n"); 920138ef0185177a6d221d24b6aa8f12d867fbbef90Ira Snyder goto out_unlock; 9219c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder } 922173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 9239c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9249c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * The DMA controller is not idle, which means the interrupt 9259c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * handler will start any queued transactions when it runs 9269c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * at the end of the current transaction 9279c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 9289c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder if (!dma_is_idle(chan)) { 9299c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "DMA controller still busy\n"); 9309c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder goto out_unlock; 9319c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder } 9329c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 9339c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9349c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * TODO: 9359c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * make sure the dma_halt() function really un-wedges the 9369c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * controller as much as possible 9379c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 938a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dma_halt(chan); 939173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 9409c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9419c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * If there are some link descriptors which have not been 9429c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * transferred, we need to start the controller 943173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 944173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 9459c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9469c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * Move all elements from the queue of pending transactions 9479c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * onto the list of running transactions 9489c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 9499c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); 9509c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder list_splice_tail_init(&chan->ld_pending, &chan->ld_running); 9519c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder 9529c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 9539c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * Program the descriptor's address into the DMA controller, 9549c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * then start the DMA transaction 9559c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder */ 9569c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder set_cdar(chan, desc->async_tx.phys); 9579c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dma_start(chan); 958138ef0185177a6d221d24b6aa8f12d867fbbef90Ira Snyder 959138ef0185177a6d221d24b6aa8f12d867fbbef90Ira Snyderout_unlock: 960a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 961173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 962173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 963173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 964173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 965a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 966173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 967a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) 968173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 969a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 970a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fsl_chan_xfer_ld_queue(chan); 971173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 972173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 973173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei/** 9740793448187643b50af89d36b08470baf45a3cab4Linus Walleij * fsl_tx_status - Determine the DMA status 975a1c03319018061304be28d131073ac13a5cb86fbIra Snyder * @chan : Freescale DMA channel 976173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 9770793448187643b50af89d36b08470baf45a3cab4Linus Walleijstatic enum dma_status fsl_tx_status(struct dma_chan *dchan, 978173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cookie_t cookie, 9790793448187643b50af89d36b08470baf45a3cab4Linus Walleij struct dma_tx_state *txstate) 980173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 981a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 982173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cookie_t last_used; 983173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cookie_t last_complete; 984173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 985a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fsl_chan_ld_cleanup(chan); 986173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 987a1c03319018061304be28d131073ac13a5cb86fbIra Snyder last_used = dchan->cookie; 988a1c03319018061304be28d131073ac13a5cb86fbIra Snyder last_complete = chan->completed_cookie; 989173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 9900793448187643b50af89d36b08470baf45a3cab4Linus Walleij if (txstate) { 9910793448187643b50af89d36b08470baf45a3cab4Linus Walleij txstate->last = last_complete; 9920793448187643b50af89d36b08470baf45a3cab4Linus Walleij txstate->used = last_used; 9930793448187643b50af89d36b08470baf45a3cab4Linus Walleij txstate->residue = 0; 9940793448187643b50af89d36b08470baf45a3cab4Linus Walleij } 995173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 996173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 997173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 998173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 999d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder/*----------------------------------------------------------------------------*/ 1000d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder/* Interrupt Handling */ 1001d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder/*----------------------------------------------------------------------------*/ 1002d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1003e7a29151de1bd52081f27f149b68074fac0323beIra Snyderstatic irqreturn_t fsldma_chan_irq(int irq, void *data) 1004173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1005a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = data; 10061c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei int update_cookie = 0; 10071c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei int xfer_ld_q = 0; 1008a1c03319018061304be28d131073ac13a5cb86fbIra Snyder u32 stat; 1009173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 10109c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* save and clear the status register */ 1011a1c03319018061304be28d131073ac13a5cb86fbIra Snyder stat = get_sr(chan); 10129c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder set_sr(chan, stat); 10139c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); 1014173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1015173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 1016173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!stat) 1017173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return IRQ_NONE; 1018173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1019173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (stat & FSL_DMA_SR_TE) 1020a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_err(chan->dev, "Transfer Error!\n"); 1021173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 10229c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 10239c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * Programming Error 1024f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 1025f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei * triger a PE interrupt. 1026f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei */ 1027f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei if (stat & FSL_DMA_SR_PE) { 10289c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: Programming Error INT\n"); 1029a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (get_bcr(chan) == 0) { 1030f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 1031f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei * Now, update the completed cookie, and continue the 1032f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei * next uncompleted transfer. 1033f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei */ 10341c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei update_cookie = 1; 10351c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei xfer_ld_q = 1; 1036f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei } 1037f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei stat &= ~FSL_DMA_SR_PE; 1038f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei } 1039f79abb627f033c85a6088231f20c85bc4a9bd757Zhang Wei 10409c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 10419c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * If the link descriptor segment transfer finishes, 1042173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * we will recycle the used descriptor. 1043173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 1044173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (stat & FSL_DMA_SR_EOSI) { 10459c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: End-of-segments INT\n"); 10469c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", 1047a1c03319018061304be28d131073ac13a5cb86fbIra Snyder (unsigned long long)get_cdar(chan), 1048a1c03319018061304be28d131073ac13a5cb86fbIra Snyder (unsigned long long)get_ndar(chan)); 1049173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei stat &= ~FSL_DMA_SR_EOSI; 10501c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei update_cookie = 1; 10511c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei } 10521c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei 10539c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 10549c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * For MPC8349, EOCDI event need to update cookie 10551c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei * and start the next transfer if it exist. 10561c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei */ 10571c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei if (stat & FSL_DMA_SR_EOCDI) { 10589c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); 10591c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei stat &= ~FSL_DMA_SR_EOCDI; 10601c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei update_cookie = 1; 10611c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei xfer_ld_q = 1; 1062173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1063173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 10649c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder /* 10659c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder * If it current transfer is the end-of-transfer, 1066173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * we should clear the Channel Start bit for 1067173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei * prepare next transfer. 1068173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 10691c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei if (stat & FSL_DMA_SR_EOLNI) { 10709c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: End-of-link INT\n"); 1071173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei stat &= ~FSL_DMA_SR_EOLNI; 10721c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei xfer_ld_q = 1; 1073173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1074173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 10751c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei if (update_cookie) 1076a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fsl_dma_update_completed_cookie(chan); 10771c62979ed29a8e2bf9fbe1db101c81a0089676f8Zhang Wei if (xfer_ld_q) 1078a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fsl_chan_xfer_ld_queue(chan); 1079173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (stat) 10809c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); 1081173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 10829c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder dev_dbg(chan->dev, "irq: Exit\n"); 1083a1c03319018061304be28d131073ac13a5cb86fbIra Snyder tasklet_schedule(&chan->tasklet); 1084173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return IRQ_HANDLED; 1085173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1086173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1087d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyderstatic void dma_do_tasklet(unsigned long data) 1088d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder{ 1089a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan = (struct fsldma_chan *)data; 1090a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fsl_chan_ld_cleanup(chan); 1091d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder} 1092d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1093d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyderstatic irqreturn_t fsldma_ctrl_irq(int irq, void *data) 1094173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1095a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder struct fsldma_device *fdev = data; 1096d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder struct fsldma_chan *chan; 1097d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder unsigned int handled = 0; 1098d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder u32 gsr, mask; 1099d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder int i; 1100173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1101e7a29151de1bd52081f27f149b68074fac0323beIra Snyder gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) 1102d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder : in_le32(fdev->regs); 1103d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder mask = 0xff000000; 1104d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); 1105173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1106d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1107d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder chan = fdev->chan[i]; 1108d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (!chan) 1109d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder continue; 1110d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1111d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (gsr & mask) { 1112d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); 1113d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder fsldma_chan_irq(irq, chan); 1114d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder handled++; 1115d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1116d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1117d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder gsr &= ~mask; 1118d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder mask >>= 8; 1119d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1120d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1121d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder return IRQ_RETVAL(handled); 1122173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1123173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1124d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyderstatic void fsldma_free_irqs(struct fsldma_device *fdev) 1125173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1126d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder struct fsldma_chan *chan; 1127d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder int i; 1128d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1129d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (fdev->irq != NO_IRQ) { 1130d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "free per-controller IRQ\n"); 1131d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder free_irq(fdev->irq, fdev); 1132d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder return; 1133d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1134d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1135d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1136d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder chan = fdev->chan[i]; 1137d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (chan && chan->irq != NO_IRQ) { 1138d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); 1139d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder free_irq(chan->irq, chan); 1140d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1141d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1142d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder} 1143d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1144d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyderstatic int fsldma_request_irqs(struct fsldma_device *fdev) 1145d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder{ 1146d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder struct fsldma_chan *chan; 1147d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder int ret; 1148d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder int i; 1149d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1150d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder /* if we have a per-controller IRQ, use that */ 1151d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (fdev->irq != NO_IRQ) { 1152d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "request per-controller IRQ\n"); 1153d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, 1154d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder "fsldma-controller", fdev); 1155d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder return ret; 1156d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1157d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1158d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder /* no per-controller IRQ, use the per-channel IRQs */ 1159d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1160d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder chan = fdev->chan[i]; 1161d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (!chan) 1162d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder continue; 1163d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1164d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (chan->irq == NO_IRQ) { 1165d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_err(fdev->dev, "no interrupts property defined for " 1166d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder "DMA channel %d. Please fix your " 1167d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder "device tree\n", chan->id); 1168d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder ret = -ENODEV; 1169d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder goto out_unwind; 1170d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1171d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1172d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); 1173d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, 1174d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder "fsldma-chan", chan); 1175d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (ret) { 1176d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_err(fdev->dev, "unable to request IRQ for DMA " 1177d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder "channel %d\n", chan->id); 1178d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder goto out_unwind; 1179d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1180d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1181d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1182d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder return 0; 1183d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1184d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyderout_unwind: 1185d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder for (/* none */; i >= 0; i--) { 1186d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder chan = fdev->chan[i]; 1187d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (!chan) 1188d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder continue; 1189d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1190d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (chan->irq == NO_IRQ) 1191d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder continue; 1192d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1193d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder free_irq(chan->irq, chan); 1194d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1195d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1196d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder return ret; 1197173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1198173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1199a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/*----------------------------------------------------------------------------*/ 1200a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/* OpenFirmware Subsystem */ 1201a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/*----------------------------------------------------------------------------*/ 1202a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder 1203a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstatic int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, 120477cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi struct device_node *node, u32 feature, const char *compatible) 1205173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1206a1c03319018061304be28d131073ac13a5cb86fbIra Snyder struct fsldma_chan *chan; 12074ce0e953f6286777452bf07c83056342d6b9b257Ira Snyder struct resource res; 1208173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei int err; 1209173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1210173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* alloc channel */ 1211a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan = kzalloc(sizeof(*chan), GFP_KERNEL); 1212a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!chan) { 1213e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(fdev->dev, "no free memory for DMA channels!\n"); 1214e7a29151de1bd52081f27f149b68074fac0323beIra Snyder err = -ENOMEM; 1215e7a29151de1bd52081f27f149b68074fac0323beIra Snyder goto out_return; 1216e7a29151de1bd52081f27f149b68074fac0323beIra Snyder } 1217e7a29151de1bd52081f27f149b68074fac0323beIra Snyder 1218e7a29151de1bd52081f27f149b68074fac0323beIra Snyder /* ioremap registers for use */ 1219a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->regs = of_iomap(node, 0); 1220a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (!chan->regs) { 1221e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(fdev->dev, "unable to ioremap registers\n"); 1222e7a29151de1bd52081f27f149b68074fac0323beIra Snyder err = -ENOMEM; 1223a1c03319018061304be28d131073ac13a5cb86fbIra Snyder goto out_free_chan; 1224173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1225173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 12264ce0e953f6286777452bf07c83056342d6b9b257Ira Snyder err = of_address_to_resource(node, 0, &res); 1227173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (err) { 1228e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(fdev->dev, "unable to find 'reg' property\n"); 1229e7a29151de1bd52081f27f149b68074fac0323beIra Snyder goto out_iounmap_regs; 1230173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1231173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1232a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->feature = feature; 1233173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!fdev->feature) 1234a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fdev->feature = chan->feature; 1235173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1236e7a29151de1bd52081f27f149b68074fac0323beIra Snyder /* 1237e7a29151de1bd52081f27f149b68074fac0323beIra Snyder * If the DMA device's feature is different than the feature 1238e7a29151de1bd52081f27f149b68074fac0323beIra Snyder * of its channels, report the bug 1239173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei */ 1240a1c03319018061304be28d131073ac13a5cb86fbIra Snyder WARN_ON(fdev->feature != chan->feature); 1241e7a29151de1bd52081f27f149b68074fac0323beIra Snyder 1242a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->dev = fdev->dev; 1243a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->id = ((res.start - 0x100) & 0xfff) >> 7; 1244a1c03319018061304be28d131073ac13a5cb86fbIra Snyder if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 1245e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(fdev->dev, "too many channels for device\n"); 1246173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei err = -EINVAL; 1247e7a29151de1bd52081f27f149b68074fac0323beIra Snyder goto out_iounmap_regs; 1248173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1249173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1250a1c03319018061304be28d131073ac13a5cb86fbIra Snyder fdev->chan[chan->id] = chan; 1251a1c03319018061304be28d131073ac13a5cb86fbIra Snyder tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); 1252e7a29151de1bd52081f27f149b68074fac0323beIra Snyder 1253e7a29151de1bd52081f27f149b68074fac0323beIra Snyder /* Initialize the channel */ 1254a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dma_init(chan); 1255173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1256173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Clear cdar registers */ 1257a1c03319018061304be28d131073ac13a5cb86fbIra Snyder set_cdar(chan, 0); 1258173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1259a1c03319018061304be28d131073ac13a5cb86fbIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 1260173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case FSL_DMA_IP_85XX: 1261a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 1262173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei case FSL_DMA_IP_83XX: 1263a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->toggle_ext_start = fsl_chan_toggle_ext_start; 1264a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_src_loop_size = fsl_chan_set_src_loop_size; 1265a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; 1266a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->set_request_count = fsl_chan_set_request_count; 1267173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1268173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1269a1c03319018061304be28d131073ac13a5cb86fbIra Snyder spin_lock_init(&chan->desc_lock); 12709c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder INIT_LIST_HEAD(&chan->ld_pending); 12719c3a50b7d7ec45da34e73cac66cde12dd6092dd8Ira Snyder INIT_LIST_HEAD(&chan->ld_running); 1272173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1273a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->common.device = &fdev->common; 1274173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1275d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder /* find the IRQ line, if it exists in the device tree */ 1276a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->irq = irq_of_parse_and_map(node, 0); 1277d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1278173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei /* Add the channel to DMA device channel list */ 1279a1c03319018061304be28d131073ac13a5cb86fbIra Snyder list_add_tail(&chan->common.device_node, &fdev->common.channels); 1280173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei fdev->common.chancnt++; 1281173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1282a1c03319018061304be28d131073ac13a5cb86fbIra Snyder dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, 1283a1c03319018061304be28d131073ac13a5cb86fbIra Snyder chan->irq != NO_IRQ ? chan->irq : fdev->irq); 1284173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1285173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return 0; 128651ee87f27a1d2c0e08492924f2fb0223c4c704d9Li Yang 1287e7a29151de1bd52081f27f149b68074fac0323beIra Snyderout_iounmap_regs: 1288a1c03319018061304be28d131073ac13a5cb86fbIra Snyder iounmap(chan->regs); 1289a1c03319018061304be28d131073ac13a5cb86fbIra Snyderout_free_chan: 1290a1c03319018061304be28d131073ac13a5cb86fbIra Snyder kfree(chan); 1291e7a29151de1bd52081f27f149b68074fac0323beIra Snyderout_return: 1292173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return err; 1293173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1294173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1295a1c03319018061304be28d131073ac13a5cb86fbIra Snyderstatic void fsl_dma_chan_remove(struct fsldma_chan *chan) 1296173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1297a1c03319018061304be28d131073ac13a5cb86fbIra Snyder irq_dispose_mapping(chan->irq); 1298a1c03319018061304be28d131073ac13a5cb86fbIra Snyder list_del(&chan->common.device_node); 1299a1c03319018061304be28d131073ac13a5cb86fbIra Snyder iounmap(chan->regs); 1300a1c03319018061304be28d131073ac13a5cb86fbIra Snyder kfree(chan); 1301173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1302173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1303e7a29151de1bd52081f27f149b68074fac0323beIra Snyderstatic int __devinit fsldma_of_probe(struct of_device *op, 1304173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei const struct of_device_id *match) 1305173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 1306a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder struct fsldma_device *fdev; 130777cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi struct device_node *child; 1308e7a29151de1bd52081f27f149b68074fac0323beIra Snyder int err; 1309173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1310a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); 1311173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei if (!fdev) { 1312e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(&op->dev, "No enough memory for 'priv'\n"); 1313e7a29151de1bd52081f27f149b68074fac0323beIra Snyder err = -ENOMEM; 1314e7a29151de1bd52081f27f149b68074fac0323beIra Snyder goto out_return; 1315173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1316e7a29151de1bd52081f27f149b68074fac0323beIra Snyder 1317e7a29151de1bd52081f27f149b68074fac0323beIra Snyder fdev->dev = &op->dev; 1318173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei INIT_LIST_HEAD(&fdev->common.channels); 1319173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1320e7a29151de1bd52081f27f149b68074fac0323beIra Snyder /* ioremap the registers for use */ 1321e7a29151de1bd52081f27f149b68074fac0323beIra Snyder fdev->regs = of_iomap(op->node, 0); 1322e7a29151de1bd52081f27f149b68074fac0323beIra Snyder if (!fdev->regs) { 1323e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_err(&op->dev, "unable to ioremap registers\n"); 1324e7a29151de1bd52081f27f149b68074fac0323beIra Snyder err = -ENOMEM; 1325e7a29151de1bd52081f27f149b68074fac0323beIra Snyder goto out_free_fdev; 1326173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei } 1327173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1328d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder /* map the channel IRQ if it exists, but don't hookup the handler yet */ 1329d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder fdev->irq = irq_of_parse_and_map(op->node, 0); 1330d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1331173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1332173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1333bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); 1334173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1335173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 13362187c269ad29510f1d65ec684133d1d3426d0eedZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1337173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 13380793448187643b50af89d36b08470baf45a3cab4Linus Walleij fdev->common.device_tx_status = fsl_tx_status; 1339173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1340bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7dIra Snyder fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; 1341c3635c78e500a52c9fcd55de381a72928d9e054dLinus Walleij fdev->common.device_control = fsl_dma_device_control; 1342e7a29151de1bd52081f27f149b68074fac0323beIra Snyder fdev->common.dev = &op->dev; 1343173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1344e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_set_drvdata(&op->dev, fdev); 134577cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1346e7a29151de1bd52081f27f149b68074fac0323beIra Snyder /* 1347e7a29151de1bd52081f27f149b68074fac0323beIra Snyder * We cannot use of_platform_bus_probe() because there is no 1348e7a29151de1bd52081f27f149b68074fac0323beIra Snyder * of_platform_bus_remove(). Instead, we manually instantiate every DMA 134977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi * channel object. 135077cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi */ 1351e7a29151de1bd52081f27f149b68074fac0323beIra Snyder for_each_child_of_node(op->node, child) { 1352e7a29151de1bd52081f27f149b68074fac0323beIra Snyder if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { 135377cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi fsl_dma_chan_probe(fdev, child, 135477cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 135577cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi "fsl,eloplus-dma-channel"); 1356e7a29151de1bd52081f27f149b68074fac0323beIra Snyder } 1357e7a29151de1bd52081f27f149b68074fac0323beIra Snyder 1358e7a29151de1bd52081f27f149b68074fac0323beIra Snyder if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { 135977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi fsl_dma_chan_probe(fdev, child, 136077cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 136177cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi "fsl,elo-dma-channel"); 1362e7a29151de1bd52081f27f149b68074fac0323beIra Snyder } 136377cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi } 1364173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1365d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder /* 1366d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder * Hookup the IRQ handler(s) 1367d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder * 1368d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder * If we have a per-controller interrupt, we prefer that to the 1369d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder * per-channel interrupts to reduce the number of shared interrupt 1370d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder * handlers on the same IRQ line 1371d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder */ 1372d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder err = fsldma_request_irqs(fdev); 1373d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder if (err) { 1374d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder dev_err(fdev->dev, "unable to request IRQs\n"); 1375d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder goto out_free_fdev; 1376d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder } 1377d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1378173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei dma_async_device_register(&fdev->common); 1379173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return 0; 1380173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1381e7a29151de1bd52081f27f149b68074fac0323beIra Snyderout_free_fdev: 1382d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder irq_dispose_mapping(fdev->irq); 1383173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei kfree(fdev); 1384e7a29151de1bd52081f27f149b68074fac0323beIra Snyderout_return: 1385173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei return err; 1386173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1387173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1388e7a29151de1bd52081f27f149b68074fac0323beIra Snyderstatic int fsldma_of_remove(struct of_device *op) 138977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi{ 1390a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder struct fsldma_device *fdev; 139177cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi unsigned int i; 139277cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1393e7a29151de1bd52081f27f149b68074fac0323beIra Snyder fdev = dev_get_drvdata(&op->dev); 139477cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi dma_async_device_unregister(&fdev->common); 139577cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1396d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder fsldma_free_irqs(fdev); 1397d3f620b2c4fecdc8e060b70e8d92d29fc01c6126Ira Snyder 1398e7a29151de1bd52081f27f149b68074fac0323beIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 139977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi if (fdev->chan[i]) 140077cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 1401e7a29151de1bd52081f27f149b68074fac0323beIra Snyder } 140277cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1403e7a29151de1bd52081f27f149b68074fac0323beIra Snyder iounmap(fdev->regs); 1404e7a29151de1bd52081f27f149b68074fac0323beIra Snyder dev_set_drvdata(&op->dev, NULL); 140577cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi kfree(fdev); 140677cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 140777cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi return 0; 140877cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi} 140977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 14104b1cf1facca31b7db2a61d8aa2ba40d5a93a0957Márton Némethstatic const struct of_device_id fsldma_of_ids[] = { 1411049c9d45531d9825bf737891163a794fca1421c5Kumar Gala { .compatible = "fsl,eloplus-dma", }, 1412049c9d45531d9825bf737891163a794fca1421c5Kumar Gala { .compatible = "fsl,elo-dma", }, 1413173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei {} 1414173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei}; 1415173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1416a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstatic struct of_platform_driver fsldma_of_driver = { 1417a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder .name = "fsl-elo-dma", 1418a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder .match_table = fsldma_of_ids, 1419a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder .probe = fsldma_of_probe, 1420a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder .remove = fsldma_of_remove, 1421173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei}; 1422173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1423a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/*----------------------------------------------------------------------------*/ 1424a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/* Module Init / Exit */ 1425a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder/*----------------------------------------------------------------------------*/ 1426a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder 1427a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstatic __init int fsldma_init(void) 1428173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei{ 142977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi int ret; 143077cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 143177cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 143277cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1433a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder ret = of_register_platform_driver(&fsldma_of_driver); 143477cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi if (ret) 143577cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi pr_err("fsldma: failed to register platform driver\n"); 143677cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 143777cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi return ret; 143877cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi} 143977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 1440a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyderstatic void __exit fsldma_exit(void) 144177cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi{ 1442a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snyder of_unregister_platform_driver(&fsldma_of_driver); 1443173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei} 1444173acc7ce8538f1f3040791dc622a92aadc12cf4Zhang Wei 1445a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snydersubsys_initcall(fsldma_init); 1446a4f56d4b103d4e5d1a59a9118db0185a6bd1a83bIra Snydermodule_exit(fsldma_exit); 144777cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur Tabi 144877cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur TabiMODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 144977cd62e8082b9743b59ee1946a4c3ee2e3cd2bceTimur TabiMODULE_LICENSE("GPL"); 1450