fsldma.c revision 272ca655090978bdaa2630fc44fb2c03da5576fd
1/* 2 * Freescale MPC85xx, MPC83xx DMA Engine support 3 * 4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: 7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9 * 10 * Description: 11 * DMA engine driver for Freescale MPC8540 DMA controller, which is 12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13 * The support for MPC8349 DMA contorller is also added. 14 * 15 * This driver instructs the DMA controller to issue the PCI Read Multiple 16 * command for PCI read operations, instead of using the default PCI Read Line 17 * command. Please be aware that this setting may result in read pre-fetching 18 * on some platforms. 19 * 20 * This is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2 of the License, or 23 * (at your option) any later version. 24 * 25 */ 26 27#include <linux/init.h> 28#include <linux/module.h> 29#include <linux/pci.h> 30#include <linux/interrupt.h> 31#include <linux/dmaengine.h> 32#include <linux/delay.h> 33#include <linux/dma-mapping.h> 34#include <linux/dmapool.h> 35#include <linux/of_platform.h> 36 37#include <asm/fsldma.h> 38#include "fsldma.h" 39 40static void dma_init(struct fsl_dma_chan *fsl_chan) 41{ 42 /* Reset the channel */ 43 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); 44 45 switch (fsl_chan->feature & FSL_DMA_IP_MASK) { 46 case FSL_DMA_IP_85XX: 47 /* Set the channel to below modes: 48 * EIE - Error interrupt enable 49 * EOSIE - End of segments interrupt enable (basic mode) 50 * EOLNIE - End of links interrupt enable 51 */ 52 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE 53 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 54 break; 55 case FSL_DMA_IP_83XX: 56 /* Set the channel to below modes: 57 * EOTIE - End-of-transfer interrupt enable 58 * PRC_RM - PCI read multiple 59 */ 60 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE 61 | FSL_DMA_MR_PRC_RM, 32); 62 break; 63 } 64 65} 66 67static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) 68{ 69 DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); 70} 71 72static u32 get_sr(struct fsl_dma_chan *fsl_chan) 73{ 74 return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); 75} 76 77static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, 78 struct fsl_dma_ld_hw *hw, u32 count) 79{ 80 hw->count = CPU_TO_DMA(fsl_chan, count, 32); 81} 82 83static void set_desc_src(struct fsl_dma_chan *fsl_chan, 84 struct fsl_dma_ld_hw *hw, dma_addr_t src) 85{ 86 u64 snoop_bits; 87 88 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 89 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 90 hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); 91} 92 93static void set_desc_dest(struct fsl_dma_chan *fsl_chan, 94 struct fsl_dma_ld_hw *hw, dma_addr_t dest) 95{ 96 u64 snoop_bits; 97 98 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 99 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 100 hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); 101} 102 103static void set_desc_next(struct fsl_dma_chan *fsl_chan, 104 struct fsl_dma_ld_hw *hw, dma_addr_t next) 105{ 106 u64 snoop_bits; 107 108 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 109 ? FSL_DMA_SNEN : 0; 110 hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); 111} 112 113static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 114{ 115 DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); 116} 117 118static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) 119{ 120 return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; 121} 122 123static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 124{ 125 DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); 126} 127 128static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) 129{ 130 return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); 131} 132 133static u32 get_bcr(struct fsl_dma_chan *fsl_chan) 134{ 135 return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); 136} 137 138static int dma_is_idle(struct fsl_dma_chan *fsl_chan) 139{ 140 u32 sr = get_sr(fsl_chan); 141 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 142} 143 144static void dma_start(struct fsl_dma_chan *fsl_chan) 145{ 146 u32 mode; 147 148 mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); 149 150 if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 151 if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 152 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); 153 mode |= FSL_DMA_MR_EMP_EN; 154 } else { 155 mode &= ~FSL_DMA_MR_EMP_EN; 156 } 157 } 158 159 if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) 160 mode |= FSL_DMA_MR_EMS_EN; 161 else 162 mode |= FSL_DMA_MR_CS; 163 164 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 165} 166 167static void dma_halt(struct fsl_dma_chan *fsl_chan) 168{ 169 u32 mode; 170 int i; 171 172 mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); 173 mode |= FSL_DMA_MR_CA; 174 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 175 176 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); 177 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 178 179 for (i = 0; i < 100; i++) { 180 if (dma_is_idle(fsl_chan)) 181 break; 182 udelay(10); 183 } 184 185 if (i >= 100 && !dma_is_idle(fsl_chan)) 186 dev_err(fsl_chan->dev, "DMA halt timeout!\n"); 187} 188 189static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 190 struct fsl_desc_sw *desc) 191{ 192 u64 snoop_bits; 193 194 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 195 ? FSL_DMA_SNEN : 0; 196 197 desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 198 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 199 | snoop_bits, 64); 200} 201 202static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 203 struct fsl_desc_sw *new_desc) 204{ 205 struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); 206 207 if (list_empty(&fsl_chan->ld_queue)) 208 return; 209 210 /* Link to the new descriptor physical address and 211 * Enable End-of-segment interrupt for 212 * the last link descriptor. 213 * (the previous node's next link descriptor) 214 * 215 * For FSL_DMA_IP_83xx, the snoop enable bit need be set. 216 */ 217 queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 218 new_desc->async_tx.phys | FSL_DMA_EOSIE | 219 (((fsl_chan->feature & FSL_DMA_IP_MASK) 220 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); 221} 222 223/** 224 * fsl_chan_set_src_loop_size - Set source address hold transfer size 225 * @fsl_chan : Freescale DMA channel 226 * @size : Address loop size, 0 for disable loop 227 * 228 * The set source address hold transfer size. The source 229 * address hold or loop transfer size is when the DMA transfer 230 * data from source address (SA), if the loop size is 4, the DMA will 231 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 232 * SA + 1 ... and so on. 233 */ 234static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) 235{ 236 u32 mode; 237 238 mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); 239 240 switch (size) { 241 case 0: 242 mode &= ~FSL_DMA_MR_SAHE; 243 break; 244 case 1: 245 case 2: 246 case 4: 247 case 8: 248 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); 249 break; 250 } 251 252 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 253} 254 255/** 256 * fsl_chan_set_dest_loop_size - Set destination address hold transfer size 257 * @fsl_chan : Freescale DMA channel 258 * @size : Address loop size, 0 for disable loop 259 * 260 * The set destination address hold transfer size. The destination 261 * address hold or loop transfer size is when the DMA transfer 262 * data to destination address (TA), if the loop size is 4, the DMA will 263 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 264 * TA + 1 ... and so on. 265 */ 266static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) 267{ 268 u32 mode; 269 270 mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); 271 272 switch (size) { 273 case 0: 274 mode &= ~FSL_DMA_MR_DAHE; 275 break; 276 case 1: 277 case 2: 278 case 4: 279 case 8: 280 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); 281 break; 282 } 283 284 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 285} 286 287/** 288 * fsl_chan_set_request_count - Set DMA Request Count for external control 289 * @fsl_chan : Freescale DMA channel 290 * @size : Number of bytes to transfer in a single request 291 * 292 * The Freescale DMA channel can be controlled by the external signal DREQ#. 293 * The DMA request count is how many bytes are allowed to transfer before 294 * pausing the channel, after which a new assertion of DREQ# resumes channel 295 * operation. 296 * 297 * A size of 0 disables external pause control. The maximum size is 1024. 298 */ 299static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size) 300{ 301 u32 mode; 302 303 BUG_ON(size > 1024); 304 305 mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); 306 mode |= (__ilog2(size) << 24) & 0x0f000000; 307 308 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); 309} 310 311/** 312 * fsl_chan_toggle_ext_pause - Toggle channel external pause status 313 * @fsl_chan : Freescale DMA channel 314 * @enable : 0 is disabled, 1 is enabled. 315 * 316 * The Freescale DMA channel can be controlled by the external signal DREQ#. 317 * The DMA Request Count feature should be used in addition to this feature 318 * to set the number of bytes to transfer before pausing the channel. 319 */ 320static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable) 321{ 322 if (enable) 323 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 324 else 325 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 326} 327 328/** 329 * fsl_chan_toggle_ext_start - Toggle channel external start status 330 * @fsl_chan : Freescale DMA channel 331 * @enable : 0 is disabled, 1 is enabled. 332 * 333 * If enable the external start, the channel can be started by an 334 * external DMA start pin. So the dma_start() does not start the 335 * transfer immediately. The DMA channel will wait for the 336 * control pin asserted. 337 */ 338static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) 339{ 340 if (enable) 341 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; 342 else 343 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; 344} 345 346static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 347{ 348 struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); 349 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 350 struct fsl_desc_sw *child; 351 unsigned long flags; 352 dma_cookie_t cookie; 353 354 /* cookie increment and adding to ld_queue must be atomic */ 355 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 356 357 cookie = fsl_chan->common.cookie; 358 list_for_each_entry(child, &desc->tx_list, node) { 359 cookie++; 360 if (cookie < 0) 361 cookie = 1; 362 363 desc->async_tx.cookie = cookie; 364 } 365 366 fsl_chan->common.cookie = cookie; 367 append_ld_queue(fsl_chan, desc); 368 list_splice_init(&desc->tx_list, fsl_chan->ld_queue.prev); 369 370 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 371 372 return cookie; 373} 374 375/** 376 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 377 * @fsl_chan : Freescale DMA channel 378 * 379 * Return - The descriptor allocated. NULL for failed. 380 */ 381static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 382 struct fsl_dma_chan *fsl_chan) 383{ 384 dma_addr_t pdesc; 385 struct fsl_desc_sw *desc_sw; 386 387 desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); 388 if (desc_sw) { 389 memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); 390 INIT_LIST_HEAD(&desc_sw->tx_list); 391 dma_async_tx_descriptor_init(&desc_sw->async_tx, 392 &fsl_chan->common); 393 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; 394 desc_sw->async_tx.phys = pdesc; 395 } 396 397 return desc_sw; 398} 399 400 401/** 402 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 403 * @fsl_chan : Freescale DMA channel 404 * 405 * This function will create a dma pool for descriptor allocation. 406 * 407 * Return - The number of descriptors allocated. 408 */ 409static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) 410{ 411 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 412 413 /* Has this channel already been allocated? */ 414 if (fsl_chan->desc_pool) 415 return 1; 416 417 /* We need the descriptor to be aligned to 32bytes 418 * for meeting FSL DMA specification requirement. 419 */ 420 fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 421 fsl_chan->dev, sizeof(struct fsl_desc_sw), 422 32, 0); 423 if (!fsl_chan->desc_pool) { 424 dev_err(fsl_chan->dev, "No memory for channel %d " 425 "descriptor dma pool.\n", fsl_chan->id); 426 return 0; 427 } 428 429 return 1; 430} 431 432/** 433 * fsl_dma_free_chan_resources - Free all resources of the channel. 434 * @fsl_chan : Freescale DMA channel 435 */ 436static void fsl_dma_free_chan_resources(struct dma_chan *chan) 437{ 438 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 439 struct fsl_desc_sw *desc, *_desc; 440 unsigned long flags; 441 442 dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); 443 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 444 list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 445#ifdef FSL_DMA_LD_DEBUG 446 dev_dbg(fsl_chan->dev, 447 "LD %p will be released.\n", desc); 448#endif 449 list_del(&desc->node); 450 /* free link descriptor */ 451 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 452 } 453 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 454 dma_pool_destroy(fsl_chan->desc_pool); 455 456 fsl_chan->desc_pool = NULL; 457} 458 459static struct dma_async_tx_descriptor * 460fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) 461{ 462 struct fsl_dma_chan *fsl_chan; 463 struct fsl_desc_sw *new; 464 465 if (!chan) 466 return NULL; 467 468 fsl_chan = to_fsl_chan(chan); 469 470 new = fsl_dma_alloc_descriptor(fsl_chan); 471 if (!new) { 472 dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); 473 return NULL; 474 } 475 476 new->async_tx.cookie = -EBUSY; 477 new->async_tx.flags = flags; 478 479 /* Insert the link descriptor to the LD ring */ 480 list_add_tail(&new->node, &new->tx_list); 481 482 /* Set End-of-link to the last link descriptor of new list*/ 483 set_ld_eol(fsl_chan, new); 484 485 return &new->async_tx; 486} 487 488static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 489 struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, 490 size_t len, unsigned long flags) 491{ 492 struct fsl_dma_chan *fsl_chan; 493 struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 494 struct list_head *list; 495 size_t copy; 496 497 if (!chan) 498 return NULL; 499 500 if (!len) 501 return NULL; 502 503 fsl_chan = to_fsl_chan(chan); 504 505 do { 506 507 /* Allocate the link descriptor from DMA pool */ 508 new = fsl_dma_alloc_descriptor(fsl_chan); 509 if (!new) { 510 dev_err(fsl_chan->dev, 511 "No free memory for link descriptor\n"); 512 goto fail; 513 } 514#ifdef FSL_DMA_LD_DEBUG 515 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 516#endif 517 518 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 519 520 set_desc_cnt(fsl_chan, &new->hw, copy); 521 set_desc_src(fsl_chan, &new->hw, dma_src); 522 set_desc_dest(fsl_chan, &new->hw, dma_dest); 523 524 if (!first) 525 first = new; 526 else 527 set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); 528 529 new->async_tx.cookie = 0; 530 async_tx_ack(&new->async_tx); 531 532 prev = new; 533 len -= copy; 534 dma_src += copy; 535 dma_dest += copy; 536 537 /* Insert the link descriptor to the LD ring */ 538 list_add_tail(&new->node, &first->tx_list); 539 } while (len); 540 541 new->async_tx.flags = flags; /* client is in control of this ack */ 542 new->async_tx.cookie = -EBUSY; 543 544 /* Set End-of-link to the last link descriptor of new list*/ 545 set_ld_eol(fsl_chan, new); 546 547 return &first->async_tx; 548 549fail: 550 if (!first) 551 return NULL; 552 553 list = &first->tx_list; 554 list_for_each_entry_safe_reverse(new, prev, list, node) { 555 list_del(&new->node); 556 dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); 557 } 558 559 return NULL; 560} 561 562/** 563 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 564 * @chan: DMA channel 565 * @sgl: scatterlist to transfer to/from 566 * @sg_len: number of entries in @scatterlist 567 * @direction: DMA direction 568 * @flags: DMAEngine flags 569 * 570 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the 571 * DMA_SLAVE API, this gets the device-specific information from the 572 * chan->private variable. 573 */ 574static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 575 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 576 enum dma_data_direction direction, unsigned long flags) 577{ 578 struct fsl_dma_chan *fsl_chan; 579 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; 580 struct fsl_dma_slave *slave; 581 struct list_head *tx_list; 582 size_t copy; 583 584 int i; 585 struct scatterlist *sg; 586 size_t sg_used; 587 size_t hw_used; 588 struct fsl_dma_hw_addr *hw; 589 dma_addr_t dma_dst, dma_src; 590 591 if (!chan) 592 return NULL; 593 594 if (!chan->private) 595 return NULL; 596 597 fsl_chan = to_fsl_chan(chan); 598 slave = chan->private; 599 600 if (list_empty(&slave->addresses)) 601 return NULL; 602 603 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); 604 hw_used = 0; 605 606 /* 607 * Build the hardware transaction to copy from the scatterlist to 608 * the hardware, or from the hardware to the scatterlist 609 * 610 * If you are copying from the hardware to the scatterlist and it 611 * takes two hardware entries to fill an entire page, then both 612 * hardware entries will be coalesced into the same page 613 * 614 * If you are copying from the scatterlist to the hardware and a 615 * single page can fill two hardware entries, then the data will 616 * be read out of the page into the first hardware entry, and so on 617 */ 618 for_each_sg(sgl, sg, sg_len, i) { 619 sg_used = 0; 620 621 /* Loop until the entire scatterlist entry is used */ 622 while (sg_used < sg_dma_len(sg)) { 623 624 /* 625 * If we've used up the current hardware address/length 626 * pair, we need to load a new one 627 * 628 * This is done in a while loop so that descriptors with 629 * length == 0 will be skipped 630 */ 631 while (hw_used >= hw->length) { 632 633 /* 634 * If the current hardware entry is the last 635 * entry in the list, we're finished 636 */ 637 if (list_is_last(&hw->entry, &slave->addresses)) 638 goto finished; 639 640 /* Get the next hardware address/length pair */ 641 hw = list_entry(hw->entry.next, 642 struct fsl_dma_hw_addr, entry); 643 hw_used = 0; 644 } 645 646 /* Allocate the link descriptor from DMA pool */ 647 new = fsl_dma_alloc_descriptor(fsl_chan); 648 if (!new) { 649 dev_err(fsl_chan->dev, "No free memory for " 650 "link descriptor\n"); 651 goto fail; 652 } 653#ifdef FSL_DMA_LD_DEBUG 654 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 655#endif 656 657 /* 658 * Calculate the maximum number of bytes to transfer, 659 * making sure it is less than the DMA controller limit 660 */ 661 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 662 hw->length - hw_used); 663 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); 664 665 /* 666 * DMA_FROM_DEVICE 667 * from the hardware to the scatterlist 668 * 669 * DMA_TO_DEVICE 670 * from the scatterlist to the hardware 671 */ 672 if (direction == DMA_FROM_DEVICE) { 673 dma_src = hw->address + hw_used; 674 dma_dst = sg_dma_address(sg) + sg_used; 675 } else { 676 dma_src = sg_dma_address(sg) + sg_used; 677 dma_dst = hw->address + hw_used; 678 } 679 680 /* Fill in the descriptor */ 681 set_desc_cnt(fsl_chan, &new->hw, copy); 682 set_desc_src(fsl_chan, &new->hw, dma_src); 683 set_desc_dest(fsl_chan, &new->hw, dma_dst); 684 685 /* 686 * If this is not the first descriptor, chain the 687 * current descriptor after the previous descriptor 688 */ 689 if (!first) { 690 first = new; 691 } else { 692 set_desc_next(fsl_chan, &prev->hw, 693 new->async_tx.phys); 694 } 695 696 new->async_tx.cookie = 0; 697 async_tx_ack(&new->async_tx); 698 699 prev = new; 700 sg_used += copy; 701 hw_used += copy; 702 703 /* Insert the link descriptor into the LD ring */ 704 list_add_tail(&new->node, &first->tx_list); 705 } 706 } 707 708finished: 709 710 /* All of the hardware address/length pairs had length == 0 */ 711 if (!first || !new) 712 return NULL; 713 714 new->async_tx.flags = flags; 715 new->async_tx.cookie = -EBUSY; 716 717 /* Set End-of-link to the last link descriptor of new list */ 718 set_ld_eol(fsl_chan, new); 719 720 /* Enable extra controller features */ 721 if (fsl_chan->set_src_loop_size) 722 fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size); 723 724 if (fsl_chan->set_dest_loop_size) 725 fsl_chan->set_dest_loop_size(fsl_chan, slave->dst_loop_size); 726 727 if (fsl_chan->toggle_ext_start) 728 fsl_chan->toggle_ext_start(fsl_chan, slave->external_start); 729 730 if (fsl_chan->toggle_ext_pause) 731 fsl_chan->toggle_ext_pause(fsl_chan, slave->external_pause); 732 733 if (fsl_chan->set_request_count) 734 fsl_chan->set_request_count(fsl_chan, slave->request_count); 735 736 return &first->async_tx; 737 738fail: 739 /* If first was not set, then we failed to allocate the very first 740 * descriptor, and we're done */ 741 if (!first) 742 return NULL; 743 744 /* 745 * First is set, so all of the descriptors we allocated have been added 746 * to first->tx_list, INCLUDING "first" itself. Therefore we 747 * must traverse the list backwards freeing each descriptor in turn 748 * 749 * We're re-using variables for the loop, oh well 750 */ 751 tx_list = &first->tx_list; 752 list_for_each_entry_safe_reverse(new, prev, tx_list, node) { 753 list_del_init(&new->node); 754 dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); 755 } 756 757 return NULL; 758} 759 760static void fsl_dma_device_terminate_all(struct dma_chan *chan) 761{ 762 struct fsl_dma_chan *fsl_chan; 763 struct fsl_desc_sw *desc, *tmp; 764 unsigned long flags; 765 766 if (!chan) 767 return; 768 769 fsl_chan = to_fsl_chan(chan); 770 771 /* Halt the DMA engine */ 772 dma_halt(fsl_chan); 773 774 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 775 776 /* Remove and free all of the descriptors in the LD queue */ 777 list_for_each_entry_safe(desc, tmp, &fsl_chan->ld_queue, node) { 778 list_del(&desc->node); 779 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 780 } 781 782 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 783} 784 785/** 786 * fsl_dma_update_completed_cookie - Update the completed cookie. 787 * @fsl_chan : Freescale DMA channel 788 */ 789static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) 790{ 791 struct fsl_desc_sw *cur_desc, *desc; 792 dma_addr_t ld_phy; 793 794 ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; 795 796 if (ld_phy) { 797 cur_desc = NULL; 798 list_for_each_entry(desc, &fsl_chan->ld_queue, node) 799 if (desc->async_tx.phys == ld_phy) { 800 cur_desc = desc; 801 break; 802 } 803 804 if (cur_desc && cur_desc->async_tx.cookie) { 805 if (dma_is_idle(fsl_chan)) 806 fsl_chan->completed_cookie = 807 cur_desc->async_tx.cookie; 808 else 809 fsl_chan->completed_cookie = 810 cur_desc->async_tx.cookie - 1; 811 } 812 } 813} 814 815/** 816 * fsl_chan_ld_cleanup - Clean up link descriptors 817 * @fsl_chan : Freescale DMA channel 818 * 819 * This function clean up the ld_queue of DMA channel. 820 * If 'in_intr' is set, the function will move the link descriptor to 821 * the recycle list. Otherwise, free it directly. 822 */ 823static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) 824{ 825 struct fsl_desc_sw *desc, *_desc; 826 unsigned long flags; 827 828 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 829 830 dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", 831 fsl_chan->completed_cookie); 832 list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 833 dma_async_tx_callback callback; 834 void *callback_param; 835 836 if (dma_async_is_complete(desc->async_tx.cookie, 837 fsl_chan->completed_cookie, fsl_chan->common.cookie) 838 == DMA_IN_PROGRESS) 839 break; 840 841 callback = desc->async_tx.callback; 842 callback_param = desc->async_tx.callback_param; 843 844 /* Remove from ld_queue list */ 845 list_del(&desc->node); 846 847 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", 848 desc); 849 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 850 851 /* Run the link descriptor callback function */ 852 if (callback) { 853 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 854 dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", 855 desc); 856 callback(callback_param); 857 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 858 } 859 } 860 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 861} 862 863/** 864 * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. 865 * @fsl_chan : Freescale DMA channel 866 */ 867static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) 868{ 869 struct list_head *ld_node; 870 dma_addr_t next_dest_addr; 871 unsigned long flags; 872 873 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 874 875 if (!dma_is_idle(fsl_chan)) 876 goto out_unlock; 877 878 dma_halt(fsl_chan); 879 880 /* If there are some link descriptors 881 * not transfered in queue. We need to start it. 882 */ 883 884 /* Find the first un-transfer desciptor */ 885 for (ld_node = fsl_chan->ld_queue.next; 886 (ld_node != &fsl_chan->ld_queue) 887 && (dma_async_is_complete( 888 to_fsl_desc(ld_node)->async_tx.cookie, 889 fsl_chan->completed_cookie, 890 fsl_chan->common.cookie) == DMA_SUCCESS); 891 ld_node = ld_node->next); 892 893 if (ld_node != &fsl_chan->ld_queue) { 894 /* Get the ld start address from ld_queue */ 895 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; 896 dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n", 897 (unsigned long long)next_dest_addr); 898 set_cdar(fsl_chan, next_dest_addr); 899 dma_start(fsl_chan); 900 } else { 901 set_cdar(fsl_chan, 0); 902 set_ndar(fsl_chan, 0); 903 } 904 905out_unlock: 906 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 907} 908 909/** 910 * fsl_dma_memcpy_issue_pending - Issue the DMA start command 911 * @fsl_chan : Freescale DMA channel 912 */ 913static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) 914{ 915 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 916 917#ifdef FSL_DMA_LD_DEBUG 918 struct fsl_desc_sw *ld; 919 unsigned long flags; 920 921 spin_lock_irqsave(&fsl_chan->desc_lock, flags); 922 if (list_empty(&fsl_chan->ld_queue)) { 923 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 924 return; 925 } 926 927 dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); 928 list_for_each_entry(ld, &fsl_chan->ld_queue, node) { 929 int i; 930 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", 931 fsl_chan->id, ld->async_tx.phys); 932 for (i = 0; i < 8; i++) 933 dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", 934 i, *(((u32 *)&ld->hw) + i)); 935 } 936 dev_dbg(fsl_chan->dev, "----------------\n"); 937 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 938#endif 939 940 fsl_chan_xfer_ld_queue(fsl_chan); 941} 942 943/** 944 * fsl_dma_is_complete - Determine the DMA status 945 * @fsl_chan : Freescale DMA channel 946 */ 947static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, 948 dma_cookie_t cookie, 949 dma_cookie_t *done, 950 dma_cookie_t *used) 951{ 952 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 953 dma_cookie_t last_used; 954 dma_cookie_t last_complete; 955 956 fsl_chan_ld_cleanup(fsl_chan); 957 958 last_used = chan->cookie; 959 last_complete = fsl_chan->completed_cookie; 960 961 if (done) 962 *done = last_complete; 963 964 if (used) 965 *used = last_used; 966 967 return dma_async_is_complete(cookie, last_complete, last_used); 968} 969 970static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) 971{ 972 struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 973 u32 stat; 974 int update_cookie = 0; 975 int xfer_ld_q = 0; 976 977 stat = get_sr(fsl_chan); 978 dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", 979 fsl_chan->id, stat); 980 set_sr(fsl_chan, stat); /* Clear the event register */ 981 982 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 983 if (!stat) 984 return IRQ_NONE; 985 986 if (stat & FSL_DMA_SR_TE) 987 dev_err(fsl_chan->dev, "Transfer Error!\n"); 988 989 /* Programming Error 990 * The DMA_INTERRUPT async_tx is a NULL transfer, which will 991 * triger a PE interrupt. 992 */ 993 if (stat & FSL_DMA_SR_PE) { 994 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); 995 if (get_bcr(fsl_chan) == 0) { 996 /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 997 * Now, update the completed cookie, and continue the 998 * next uncompleted transfer. 999 */ 1000 update_cookie = 1; 1001 xfer_ld_q = 1; 1002 } 1003 stat &= ~FSL_DMA_SR_PE; 1004 } 1005 1006 /* If the link descriptor segment transfer finishes, 1007 * we will recycle the used descriptor. 1008 */ 1009 if (stat & FSL_DMA_SR_EOSI) { 1010 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); 1011 dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", 1012 (unsigned long long)get_cdar(fsl_chan), 1013 (unsigned long long)get_ndar(fsl_chan)); 1014 stat &= ~FSL_DMA_SR_EOSI; 1015 update_cookie = 1; 1016 } 1017 1018 /* For MPC8349, EOCDI event need to update cookie 1019 * and start the next transfer if it exist. 1020 */ 1021 if (stat & FSL_DMA_SR_EOCDI) { 1022 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); 1023 stat &= ~FSL_DMA_SR_EOCDI; 1024 update_cookie = 1; 1025 xfer_ld_q = 1; 1026 } 1027 1028 /* If it current transfer is the end-of-transfer, 1029 * we should clear the Channel Start bit for 1030 * prepare next transfer. 1031 */ 1032 if (stat & FSL_DMA_SR_EOLNI) { 1033 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); 1034 stat &= ~FSL_DMA_SR_EOLNI; 1035 xfer_ld_q = 1; 1036 } 1037 1038 if (update_cookie) 1039 fsl_dma_update_completed_cookie(fsl_chan); 1040 if (xfer_ld_q) 1041 fsl_chan_xfer_ld_queue(fsl_chan); 1042 if (stat) 1043 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", 1044 stat); 1045 1046 dev_dbg(fsl_chan->dev, "event: Exit\n"); 1047 tasklet_schedule(&fsl_chan->tasklet); 1048 return IRQ_HANDLED; 1049} 1050 1051static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) 1052{ 1053 struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; 1054 u32 gsr; 1055 int ch_nr; 1056 1057 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) 1058 : in_le32(fdev->reg_base); 1059 ch_nr = (32 - ffs(gsr)) / 8; 1060 1061 return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, 1062 fdev->chan[ch_nr]) : IRQ_NONE; 1063} 1064 1065static void dma_do_tasklet(unsigned long data) 1066{ 1067 struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 1068 fsl_chan_ld_cleanup(fsl_chan); 1069} 1070 1071static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, 1072 struct device_node *node, u32 feature, const char *compatible) 1073{ 1074 struct fsl_dma_chan *new_fsl_chan; 1075 int err; 1076 1077 /* alloc channel */ 1078 new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); 1079 if (!new_fsl_chan) { 1080 dev_err(fdev->dev, "No free memory for allocating " 1081 "dma channels!\n"); 1082 return -ENOMEM; 1083 } 1084 1085 /* get dma channel register base */ 1086 err = of_address_to_resource(node, 0, &new_fsl_chan->reg); 1087 if (err) { 1088 dev_err(fdev->dev, "Can't get %s property 'reg'\n", 1089 node->full_name); 1090 goto err_no_reg; 1091 } 1092 1093 new_fsl_chan->feature = feature; 1094 1095 if (!fdev->feature) 1096 fdev->feature = new_fsl_chan->feature; 1097 1098 /* If the DMA device's feature is different than its channels', 1099 * report the bug. 1100 */ 1101 WARN_ON(fdev->feature != new_fsl_chan->feature); 1102 1103 new_fsl_chan->dev = fdev->dev; 1104 new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, 1105 new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); 1106 1107 new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; 1108 if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 1109 dev_err(fdev->dev, "There is no %d channel!\n", 1110 new_fsl_chan->id); 1111 err = -EINVAL; 1112 goto err_no_chan; 1113 } 1114 fdev->chan[new_fsl_chan->id] = new_fsl_chan; 1115 tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, 1116 (unsigned long)new_fsl_chan); 1117 1118 /* Init the channel */ 1119 dma_init(new_fsl_chan); 1120 1121 /* Clear cdar registers */ 1122 set_cdar(new_fsl_chan, 0); 1123 1124 switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { 1125 case FSL_DMA_IP_85XX: 1126 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 1127 case FSL_DMA_IP_83XX: 1128 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; 1129 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; 1130 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; 1131 new_fsl_chan->set_request_count = fsl_chan_set_request_count; 1132 } 1133 1134 spin_lock_init(&new_fsl_chan->desc_lock); 1135 INIT_LIST_HEAD(&new_fsl_chan->ld_queue); 1136 1137 new_fsl_chan->common.device = &fdev->common; 1138 1139 /* Add the channel to DMA device channel list */ 1140 list_add_tail(&new_fsl_chan->common.device_node, 1141 &fdev->common.channels); 1142 fdev->common.chancnt++; 1143 1144 new_fsl_chan->irq = irq_of_parse_and_map(node, 0); 1145 if (new_fsl_chan->irq != NO_IRQ) { 1146 err = request_irq(new_fsl_chan->irq, 1147 &fsl_dma_chan_do_interrupt, IRQF_SHARED, 1148 "fsldma-channel", new_fsl_chan); 1149 if (err) { 1150 dev_err(fdev->dev, "DMA channel %s request_irq error " 1151 "with return %d\n", node->full_name, err); 1152 goto err_no_irq; 1153 } 1154 } 1155 1156 dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, 1157 compatible, 1158 new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); 1159 1160 return 0; 1161 1162err_no_irq: 1163 list_del(&new_fsl_chan->common.device_node); 1164err_no_chan: 1165 iounmap(new_fsl_chan->reg_base); 1166err_no_reg: 1167 kfree(new_fsl_chan); 1168 return err; 1169} 1170 1171static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) 1172{ 1173 if (fchan->irq != NO_IRQ) 1174 free_irq(fchan->irq, fchan); 1175 list_del(&fchan->common.device_node); 1176 iounmap(fchan->reg_base); 1177 kfree(fchan); 1178} 1179 1180static int __devinit of_fsl_dma_probe(struct of_device *dev, 1181 const struct of_device_id *match) 1182{ 1183 int err; 1184 struct fsl_dma_device *fdev; 1185 struct device_node *child; 1186 1187 fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); 1188 if (!fdev) { 1189 dev_err(&dev->dev, "No enough memory for 'priv'\n"); 1190 return -ENOMEM; 1191 } 1192 fdev->dev = &dev->dev; 1193 INIT_LIST_HEAD(&fdev->common.channels); 1194 1195 /* get DMA controller register base */ 1196 err = of_address_to_resource(dev->node, 0, &fdev->reg); 1197 if (err) { 1198 dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1199 dev->node->full_name); 1200 goto err_no_reg; 1201 } 1202 1203 dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " 1204 "controller at 0x%llx...\n", 1205 match->compatible, (unsigned long long)fdev->reg.start); 1206 fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end 1207 - fdev->reg.start + 1); 1208 1209 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1210 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1211 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); 1212 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1213 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 1214 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1215 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 1216 fdev->common.device_is_tx_complete = fsl_dma_is_complete; 1217 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1218 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; 1219 fdev->common.device_terminate_all = fsl_dma_device_terminate_all; 1220 fdev->common.dev = &dev->dev; 1221 1222 fdev->irq = irq_of_parse_and_map(dev->node, 0); 1223 if (fdev->irq != NO_IRQ) { 1224 err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, 1225 "fsldma-device", fdev); 1226 if (err) { 1227 dev_err(&dev->dev, "DMA device request_irq error " 1228 "with return %d\n", err); 1229 goto err; 1230 } 1231 } 1232 1233 dev_set_drvdata(&(dev->dev), fdev); 1234 1235 /* We cannot use of_platform_bus_probe() because there is no 1236 * of_platform_bus_remove. Instead, we manually instantiate every DMA 1237 * channel object. 1238 */ 1239 for_each_child_of_node(dev->node, child) { 1240 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) 1241 fsl_dma_chan_probe(fdev, child, 1242 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 1243 "fsl,eloplus-dma-channel"); 1244 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) 1245 fsl_dma_chan_probe(fdev, child, 1246 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 1247 "fsl,elo-dma-channel"); 1248 } 1249 1250 dma_async_device_register(&fdev->common); 1251 return 0; 1252 1253err: 1254 iounmap(fdev->reg_base); 1255err_no_reg: 1256 kfree(fdev); 1257 return err; 1258} 1259 1260static int of_fsl_dma_remove(struct of_device *of_dev) 1261{ 1262 struct fsl_dma_device *fdev; 1263 unsigned int i; 1264 1265 fdev = dev_get_drvdata(&of_dev->dev); 1266 1267 dma_async_device_unregister(&fdev->common); 1268 1269 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) 1270 if (fdev->chan[i]) 1271 fsl_dma_chan_remove(fdev->chan[i]); 1272 1273 if (fdev->irq != NO_IRQ) 1274 free_irq(fdev->irq, fdev); 1275 1276 iounmap(fdev->reg_base); 1277 1278 kfree(fdev); 1279 dev_set_drvdata(&of_dev->dev, NULL); 1280 1281 return 0; 1282} 1283 1284static struct of_device_id of_fsl_dma_ids[] = { 1285 { .compatible = "fsl,eloplus-dma", }, 1286 { .compatible = "fsl,elo-dma", }, 1287 {} 1288}; 1289 1290static struct of_platform_driver of_fsl_dma_driver = { 1291 .name = "fsl-elo-dma", 1292 .match_table = of_fsl_dma_ids, 1293 .probe = of_fsl_dma_probe, 1294 .remove = of_fsl_dma_remove, 1295}; 1296 1297static __init int of_fsl_dma_init(void) 1298{ 1299 int ret; 1300 1301 pr_info("Freescale Elo / Elo Plus DMA driver\n"); 1302 1303 ret = of_register_platform_driver(&of_fsl_dma_driver); 1304 if (ret) 1305 pr_err("fsldma: failed to register platform driver\n"); 1306 1307 return ret; 1308} 1309 1310static void __exit of_fsl_dma_exit(void) 1311{ 1312 of_unregister_platform_driver(&of_fsl_dma_driver); 1313} 1314 1315subsys_initcall(of_fsl_dma_init); 1316module_exit(of_fsl_dma_exit); 1317 1318MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 1319MODULE_LICENSE("GPL"); 1320