imx-dma.c revision 6c05f09155f40368c51ce00b8291401858e49bcb
1/* 2 * drivers/dma/imx-dma.c 3 * 4 * This file contains a driver for the Freescale i.MX DMA engine 5 * found on i.MX1/21/27 6 * 7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/types.h> 19#include <linux/mm.h> 20#include <linux/interrupt.h> 21#include <linux/spinlock.h> 22#include <linux/device.h> 23#include <linux/dma-mapping.h> 24#include <linux/slab.h> 25#include <linux/platform_device.h> 26#include <linux/dmaengine.h> 27 28#include <asm/irq.h> 29#include <mach/dma-v1.h> 30#include <mach/hardware.h> 31 32struct imxdma_channel { 33 struct imxdma_engine *imxdma; 34 unsigned int channel; 35 unsigned int imxdma_channel; 36 37 enum dma_slave_buswidth word_size; 38 dma_addr_t per_address; 39 u32 watermark_level; 40 struct dma_chan chan; 41 spinlock_t lock; 42 struct dma_async_tx_descriptor desc; 43 dma_cookie_t last_completed; 44 enum dma_status status; 45 int dma_request; 46 struct scatterlist *sg_list; 47}; 48 49#define MAX_DMA_CHANNELS 8 50 51struct imxdma_engine { 52 struct device *dev; 53 struct device_dma_parameters dma_parms; 54 struct dma_device dma_device; 55 struct imxdma_channel channel[MAX_DMA_CHANNELS]; 56}; 57 58static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) 59{ 60 return container_of(chan, struct imxdma_channel, chan); 61} 62 63static void imxdma_handle(struct imxdma_channel *imxdmac) 64{ 65 if (imxdmac->desc.callback) 66 imxdmac->desc.callback(imxdmac->desc.callback_param); 67 imxdmac->last_completed = imxdmac->desc.cookie; 68} 69 70static void imxdma_irq_handler(int channel, void *data) 71{ 72 struct imxdma_channel *imxdmac = data; 73 74 imxdmac->status = DMA_SUCCESS; 75 imxdma_handle(imxdmac); 76} 77 78static void imxdma_err_handler(int channel, void *data, int error) 79{ 80 struct imxdma_channel *imxdmac = data; 81 82 imxdmac->status = DMA_ERROR; 83 imxdma_handle(imxdmac); 84} 85 86static void imxdma_progression(int channel, void *data, 87 struct scatterlist *sg) 88{ 89 struct imxdma_channel *imxdmac = data; 90 91 imxdmac->status = DMA_SUCCESS; 92 imxdma_handle(imxdmac); 93} 94 95static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 96 unsigned long arg) 97{ 98 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 99 struct dma_slave_config *dmaengine_cfg = (void *)arg; 100 int ret; 101 unsigned int mode = 0; 102 103 switch (cmd) { 104 case DMA_TERMINATE_ALL: 105 imxdmac->status = DMA_ERROR; 106 imx_dma_disable(imxdmac->imxdma_channel); 107 return 0; 108 case DMA_SLAVE_CONFIG: 109 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { 110 imxdmac->per_address = dmaengine_cfg->src_addr; 111 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 112 imxdmac->word_size = dmaengine_cfg->src_addr_width; 113 } else { 114 imxdmac->per_address = dmaengine_cfg->dst_addr; 115 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; 116 imxdmac->word_size = dmaengine_cfg->dst_addr_width; 117 } 118 119 switch (imxdmac->word_size) { 120 case DMA_SLAVE_BUSWIDTH_1_BYTE: 121 mode = IMX_DMA_MEMSIZE_8; 122 break; 123 case DMA_SLAVE_BUSWIDTH_2_BYTES: 124 mode = IMX_DMA_MEMSIZE_16; 125 break; 126 default: 127 case DMA_SLAVE_BUSWIDTH_4_BYTES: 128 mode = IMX_DMA_MEMSIZE_32; 129 break; 130 } 131 ret = imx_dma_config_channel(imxdmac->imxdma_channel, 132 mode | IMX_DMA_TYPE_FIFO, 133 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 134 imxdmac->dma_request, 1); 135 136 if (ret) 137 return ret; 138 139 imx_dma_config_burstlen(imxdmac->imxdma_channel, 140 imxdmac->watermark_level * imxdmac->word_size); 141 142 return 0; 143 default: 144 return -ENOSYS; 145 } 146 147 return -EINVAL; 148} 149 150static enum dma_status imxdma_tx_status(struct dma_chan *chan, 151 dma_cookie_t cookie, 152 struct dma_tx_state *txstate) 153{ 154 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 155 dma_cookie_t last_used; 156 enum dma_status ret; 157 158 last_used = chan->cookie; 159 160 ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used); 161 dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0); 162 163 return ret; 164} 165 166static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma) 167{ 168 dma_cookie_t cookie = imxdma->chan.cookie; 169 170 if (++cookie < 0) 171 cookie = 1; 172 173 imxdma->chan.cookie = cookie; 174 imxdma->desc.cookie = cookie; 175 176 return cookie; 177} 178 179static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) 180{ 181 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); 182 dma_cookie_t cookie; 183 184 spin_lock_irq(&imxdmac->lock); 185 186 cookie = imxdma_assign_cookie(imxdmac); 187 188 spin_unlock_irq(&imxdmac->lock); 189 190 return cookie; 191} 192 193static int imxdma_alloc_chan_resources(struct dma_chan *chan) 194{ 195 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 196 struct imx_dma_data *data = chan->private; 197 198 if (data != NULL) 199 imxdmac->dma_request = data->dma_request; 200 201 dma_async_tx_descriptor_init(&imxdmac->desc, chan); 202 imxdmac->desc.tx_submit = imxdma_tx_submit; 203 /* txd.flags will be overwritten in prep funcs */ 204 imxdmac->desc.flags = DMA_CTRL_ACK; 205 206 imxdmac->status = DMA_SUCCESS; 207 208 return 0; 209} 210 211static void imxdma_free_chan_resources(struct dma_chan *chan) 212{ 213 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 214 215 imx_dma_disable(imxdmac->imxdma_channel); 216 217 if (imxdmac->sg_list) { 218 kfree(imxdmac->sg_list); 219 imxdmac->sg_list = NULL; 220 } 221} 222 223static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 224 struct dma_chan *chan, struct scatterlist *sgl, 225 unsigned int sg_len, enum dma_transfer_direction direction, 226 unsigned long flags) 227{ 228 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 229 struct scatterlist *sg; 230 int i, ret, dma_length = 0; 231 unsigned int dmamode; 232 233 if (imxdmac->status == DMA_IN_PROGRESS) 234 return NULL; 235 236 imxdmac->status = DMA_IN_PROGRESS; 237 238 for_each_sg(sgl, sg, sg_len, i) { 239 dma_length += sg->length; 240 } 241 242 if (direction == DMA_DEV_TO_MEM) 243 dmamode = DMA_MODE_READ; 244 else 245 dmamode = DMA_MODE_WRITE; 246 247 switch (imxdmac->word_size) { 248 case DMA_SLAVE_BUSWIDTH_4_BYTES: 249 if (sgl->length & 3 || sgl->dma_address & 3) 250 return NULL; 251 break; 252 case DMA_SLAVE_BUSWIDTH_2_BYTES: 253 if (sgl->length & 1 || sgl->dma_address & 1) 254 return NULL; 255 break; 256 case DMA_SLAVE_BUSWIDTH_1_BYTE: 257 break; 258 default: 259 return NULL; 260 } 261 262 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len, 263 dma_length, imxdmac->per_address, dmamode); 264 if (ret) 265 return NULL; 266 267 return &imxdmac->desc; 268} 269 270static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 271 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 272 size_t period_len, enum dma_transfer_direction direction) 273{ 274 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 275 struct imxdma_engine *imxdma = imxdmac->imxdma; 276 int i, ret; 277 unsigned int periods = buf_len / period_len; 278 unsigned int dmamode; 279 280 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", 281 __func__, imxdmac->channel, buf_len, period_len); 282 283 if (imxdmac->status == DMA_IN_PROGRESS) 284 return NULL; 285 imxdmac->status = DMA_IN_PROGRESS; 286 287 ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel, 288 imxdma_progression); 289 if (ret) { 290 dev_err(imxdma->dev, "Failed to setup the DMA handler\n"); 291 return NULL; 292 } 293 294 if (imxdmac->sg_list) 295 kfree(imxdmac->sg_list); 296 297 imxdmac->sg_list = kcalloc(periods + 1, 298 sizeof(struct scatterlist), GFP_KERNEL); 299 if (!imxdmac->sg_list) 300 return NULL; 301 302 sg_init_table(imxdmac->sg_list, periods); 303 304 for (i = 0; i < periods; i++) { 305 imxdmac->sg_list[i].page_link = 0; 306 imxdmac->sg_list[i].offset = 0; 307 imxdmac->sg_list[i].dma_address = dma_addr; 308 imxdmac->sg_list[i].length = period_len; 309 dma_addr += period_len; 310 } 311 312 /* close the loop */ 313 imxdmac->sg_list[periods].offset = 0; 314 imxdmac->sg_list[periods].length = 0; 315 imxdmac->sg_list[periods].page_link = 316 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 317 318 if (direction == DMA_DEV_TO_MEM) 319 dmamode = DMA_MODE_READ; 320 else 321 dmamode = DMA_MODE_WRITE; 322 323 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods, 324 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode); 325 if (ret) 326 return NULL; 327 328 return &imxdmac->desc; 329} 330 331static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( 332 struct dma_chan *chan, dma_addr_t dest, 333 dma_addr_t src, size_t len, unsigned long flags) 334{ 335 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 336 struct imxdma_engine *imxdma = imxdmac->imxdma; 337 int ret; 338 339 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", 340 __func__, imxdmac->channel, src, dest, len); 341 342 if (imxdmac->status == DMA_IN_PROGRESS) 343 return NULL; 344 imxdmac->status = DMA_IN_PROGRESS; 345 346 ret = imx_dma_config_channel(imxdmac->imxdma_channel, 347 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 348 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 349 0, 0); 350 if (ret) 351 return NULL; 352 353 ret = imx_dma_setup_single(imxdmac->imxdma_channel, src, len, 354 dest, DMA_MODE_WRITE); 355 if (ret) 356 return NULL; 357 358 return &imxdmac->desc; 359} 360 361static void imxdma_issue_pending(struct dma_chan *chan) 362{ 363 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 364 365 if (imxdmac->status == DMA_IN_PROGRESS) 366 imx_dma_enable(imxdmac->imxdma_channel); 367} 368 369static int __init imxdma_probe(struct platform_device *pdev) 370{ 371 struct imxdma_engine *imxdma; 372 int ret, i; 373 374 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); 375 if (!imxdma) 376 return -ENOMEM; 377 378 INIT_LIST_HEAD(&imxdma->dma_device.channels); 379 380 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); 381 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); 382 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); 383 384 /* Initialize channel parameters */ 385 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 386 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 387 388 imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine", 389 DMA_PRIO_MEDIUM); 390 if ((int)imxdmac->channel < 0) { 391 ret = -ENODEV; 392 goto err_init; 393 } 394 395 imx_dma_setup_handlers(imxdmac->imxdma_channel, 396 imxdma_irq_handler, imxdma_err_handler, imxdmac); 397 398 imxdmac->imxdma = imxdma; 399 spin_lock_init(&imxdmac->lock); 400 401 imxdmac->chan.device = &imxdma->dma_device; 402 imxdmac->channel = i; 403 404 /* Add the channel to the DMAC list */ 405 list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels); 406 } 407 408 imxdma->dev = &pdev->dev; 409 imxdma->dma_device.dev = &pdev->dev; 410 411 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; 412 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; 413 imxdma->dma_device.device_tx_status = imxdma_tx_status; 414 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; 415 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; 416 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; 417 imxdma->dma_device.device_control = imxdma_control; 418 imxdma->dma_device.device_issue_pending = imxdma_issue_pending; 419 420 platform_set_drvdata(pdev, imxdma); 421 422 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ 423 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; 424 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); 425 426 ret = dma_async_device_register(&imxdma->dma_device); 427 if (ret) { 428 dev_err(&pdev->dev, "unable to register\n"); 429 goto err_init; 430 } 431 432 return 0; 433 434err_init: 435 while (--i >= 0) { 436 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 437 imx_dma_free(imxdmac->imxdma_channel); 438 } 439 440 kfree(imxdma); 441 return ret; 442} 443 444static int __exit imxdma_remove(struct platform_device *pdev) 445{ 446 struct imxdma_engine *imxdma = platform_get_drvdata(pdev); 447 int i; 448 449 dma_async_device_unregister(&imxdma->dma_device); 450 451 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 452 struct imxdma_channel *imxdmac = &imxdma->channel[i]; 453 454 imx_dma_free(imxdmac->imxdma_channel); 455 } 456 457 kfree(imxdma); 458 459 return 0; 460} 461 462static struct platform_driver imxdma_driver = { 463 .driver = { 464 .name = "imx-dma", 465 }, 466 .remove = __exit_p(imxdma_remove), 467}; 468 469static int __init imxdma_module_init(void) 470{ 471 return platform_driver_probe(&imxdma_driver, imxdma_probe); 472} 473subsys_initcall(imxdma_module_init); 474 475MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); 476MODULE_DESCRIPTION("i.MX dma driver"); 477MODULE_LICENSE("GPL"); 478