1ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/* 2ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip 3ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * 4ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Copyright (c) 2008 Wind River Systems, Inc. 5ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * 6ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Authors: Cao Qingtao <qingtao.cao@windriver.com> 7ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Benjamin Walsh <benjamin.walsh@windriver.com> 8ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Hu Yongqi <yongqi.hu@windriver.com> 9ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * 10ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * This program is free software; you can redistribute it and/or modify 11ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * it under the terms of the GNU General Public License version 2 as 12ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * published by the Free Software Foundation. 13ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * 14ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * This program is distributed in the hope that it will be useful, 15ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * but WITHOUT ANY WARRANTY; without even the implied warranty of 16ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * See the GNU General Public License for more details. 18ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * 19ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * You should have received a copy of the GNU General Public License 20ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * along with this program; if not, write to the Free Software 21ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao */ 23ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 24ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#ifndef _AMD8111_EDAC_H_ 25ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define _AMD8111_EDAC_H_ 26ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 27ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 28ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * PCI Bridge Status and Command Register, DevA:0x04 29ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 30ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_PCI_STSCMD 0x04 31ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum pci_stscmd_bits { 32ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_SSE = BIT(30), 33ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_RMA = BIT(29), 34ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_RTA = BIT(28), 35ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_SERREN = BIT(8), 36ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_CLEAR_MASK = (PCI_STSCMD_SSE | 37ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_RMA | 38ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_STSCMD_RTA) 39ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 40ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 41ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 42ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * PCI Bridge Memory Base-Limit Register, DevA:0x1c 43ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 44ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_MEM_LIM 0x1c 45ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum mem_limit_bits { 46ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_DPE = BIT(31), 47ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RSE = BIT(30), 48ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RMA = BIT(29), 49ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RTA = BIT(28), 50ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_STA = BIT(27), 51ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_MDPE = BIT(24), 52ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_CLEAR_MASK = (MEM_LIMIT_DPE | 53ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RSE | 54ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RMA | 55ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_RTA | 56ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_STA | 57ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao MEM_LIMIT_MDPE) 58ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 59ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 60ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 61ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * HyperTransport Link Control Register, DevA:0xc4 62ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 63ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_HT_LINK 0xc4 64ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum ht_link_bits { 65ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao HT_LINK_LKFAIL = BIT(4), 66ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao HT_LINK_CRCFEN = BIT(1), 67ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL) 68ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 69ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 70ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 71ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * PCI Bridge Interrupt and Bridge Control, DevA:0x3c 72ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 73ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_PCI_INTBRG_CTRL 0x3c 74ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum pci_intbrg_ctrl_bits { 75ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_DTSERREN = BIT(27), 76ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_DTSTAT = BIT(26), 77ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_MARSP = BIT(21), 78ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_SERREN = BIT(17), 79ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_PEREN = BIT(16), 80ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_CLEAR_MASK = (PCI_INTBRG_CTRL_DTSTAT), 81ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_POLL_MASK = (PCI_INTBRG_CTRL_DTSERREN | 82ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_MARSP | 83ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao PCI_INTBRG_CTRL_SERREN) 84ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 85ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 86ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 87ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * I/O Control 1 Register, DevB:0x40 88ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 89ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_IO_CTRL_1 0x40 90ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum io_ctrl_1_bits { 91ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao IO_CTRL_1_NMIONERR = BIT(7), 92ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao IO_CTRL_1_LPC_ERR = BIT(6), 93ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao IO_CTRL_1_PW2LPC = BIT(1), 94ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao IO_CTRL_1_CLEAR_MASK = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC) 95ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 96ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 97ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao/************************************************************ 98ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao * Legacy I/O Space Registers 99ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao ************************************************************/ 100ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#define REG_AT_COMPAT 0x61 101ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaoenum at_compat_bits { 102ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao AT_COMPAT_SERR = BIT(7), 103ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao AT_COMPAT_IOCHK = BIT(6), 104ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao AT_COMPAT_CLRIOCHK = BIT(3), 105ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao AT_COMPAT_CLRSERR = BIT(2), 106ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 107ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 108ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaostruct amd8111_dev_info { 109ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao u16 err_dev; /* PCI Device ID */ 110ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao struct pci_dev *dev; 111ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao int edac_idx; /* device index */ 112ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao char *ctl_name; 113ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao struct edac_device_ctl_info *edac_dev; 114ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*init)(struct amd8111_dev_info *dev_info); 115ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*exit)(struct amd8111_dev_info *dev_info); 116ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*check)(struct edac_device_ctl_info *edac_dev); 117ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 118ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 119ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciaostruct amd8111_pci_info { 120ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao u16 err_dev; /* PCI Device ID */ 121ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao struct pci_dev *dev; 122ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao int edac_idx; /* pci index */ 123ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao const char *ctl_name; 124ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao struct edac_pci_ctl_info *edac_dev; 125ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*init)(struct amd8111_pci_info *dev_info); 126ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*exit)(struct amd8111_pci_info *dev_info); 127ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao void (*check)(struct edac_pci_ctl_info *edac_dev); 128ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao}; 129ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao 130ec2cf2e2726546e8a2cae7cdaf3e9f7954c336b1Harry Ciao#endif /* _AMD8111_EDAC_H_ */ 131