14f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* 24f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * EDAC defs for Marvell MV64x60 bridge chip 34f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * 44f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * Author: Dave Jiang <djiang@mvista.com> 54f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * 64f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * 2007 (c) MontaVista Software, Inc. This file is licensed under 74f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * the terms of the GNU General Public License version 2. This program 84f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * is licensed "as is" without any warranty of any kind, whether express 94f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * or implied. 104f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * 114f4aeeabc061826376c9a72b4714d062664999eaDave Jiang */ 124f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#ifndef _MV64X60_EDAC_H_ 134f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define _MV64X60_EDAC_H_ 144f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 15152ba3942276c2a240703669ae4a3099e0a79451Michal Marek#define MV64x60_REVISION " Ver: 2.0.0" 164f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define EDAC_MOD_STR "MV64x60_edac" 174f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 184f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define mv64x60_printk(level, fmt, arg...) \ 194f4aeeabc061826376c9a72b4714d062664999eaDave Jiang edac_printk(level, "MV64x60", fmt, ##arg) 204f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 214f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define mv64x60_mc_printk(mci, level, fmt, arg...) \ 224f4aeeabc061826376c9a72b4714d062664999eaDave Jiang edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg) 234f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 244f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* CPU Error Report Registers */ 254f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */ 264f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */ 274f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */ 284f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */ 294f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */ 304f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */ 314f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */ 324f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 334f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64x60_CPU_CAUSE_MASK 0x07ffffff 344f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 354f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* SRAM Error Report Registers */ 364f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */ 374f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */ 384f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */ 394f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */ 404f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */ 414f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */ 424f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 434f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* SDRAM Controller Registers */ 444f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */ 454f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */ 464f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */ 474f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */ 484f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */ 494f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */ 504f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */ 514f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */ 524f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 534f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_REGISTERED 0x20000 544f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_SDRAM_ECC 0x40000 554f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 564f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#ifdef CONFIG_PCI 574f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* 584f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of 594f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as 604f4aeeabc061826376c9a72b4714d062664999eaDave Jiang * well. IOW, don't set bit 0. 614f4aeeabc061826376c9a72b4714d062664999eaDave Jiang */ 624f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24 634f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 644f4aeeabc061826376c9a72b4714d062664999eaDave Jiang/* Register offsets from PCIx error address low register */ 654f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_ADDR_LO 0x00 664f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_ADDR_HI 0x04 674f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_ATTR 0x08 684f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_CMD 0x10 694f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_CAUSE 0x18 704f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERROR_MASK 0x1c 714f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 724f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERR_SWrPerr 0x0002 734f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERR_SRdPerr 0x0004 744f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERR_MWrPerr 0x0020 754f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_ERR_MRdPerr 0x0040 764f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 774f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \ 784f4aeeabc061826376c9a72b4714d062664999eaDave Jiang MV64X60_PCI_ERR_SRdPerr | \ 794f4aeeabc061826376c9a72b4714d062664999eaDave Jiang MV64X60_PCI_ERR_MWrPerr | \ 804f4aeeabc061826376c9a72b4714d062664999eaDave Jiang MV64X60_PCI_ERR_MRdPerr) 814f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 824f4aeeabc061826376c9a72b4714d062664999eaDave Jiangstruct mv64x60_pci_pdata { 834f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int pci_hose; 844f4aeeabc061826376c9a72b4714d062664999eaDave Jiang void __iomem *pci_vbase; 854f4aeeabc061826376c9a72b4714d062664999eaDave Jiang char *name; 864f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int irq; 874f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int edac_idx; 884f4aeeabc061826376c9a72b4714d062664999eaDave Jiang}; 894f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 904f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#endif /* CONFIG_PCI */ 914f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 924f4aeeabc061826376c9a72b4714d062664999eaDave Jiangstruct mv64x60_mc_pdata { 934f4aeeabc061826376c9a72b4714d062664999eaDave Jiang void __iomem *mc_vbase; 944f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int total_mem; 954f4aeeabc061826376c9a72b4714d062664999eaDave Jiang char *name; 964f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int irq; 974f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int edac_idx; 984f4aeeabc061826376c9a72b4714d062664999eaDave Jiang}; 994f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 1004f4aeeabc061826376c9a72b4714d062664999eaDave Jiangstruct mv64x60_cpu_pdata { 1014f4aeeabc061826376c9a72b4714d062664999eaDave Jiang void __iomem *cpu_vbase[2]; 1024f4aeeabc061826376c9a72b4714d062664999eaDave Jiang char *name; 1034f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int irq; 1044f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int edac_idx; 1054f4aeeabc061826376c9a72b4714d062664999eaDave Jiang}; 1064f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 1074f4aeeabc061826376c9a72b4714d062664999eaDave Jiangstruct mv64x60_sram_pdata { 1084f4aeeabc061826376c9a72b4714d062664999eaDave Jiang void __iomem *sram_vbase; 1094f4aeeabc061826376c9a72b4714d062664999eaDave Jiang char *name; 1104f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int irq; 1114f4aeeabc061826376c9a72b4714d062664999eaDave Jiang int edac_idx; 1124f4aeeabc061826376c9a72b4714d062664999eaDave Jiang}; 1134f4aeeabc061826376c9a72b4714d062664999eaDave Jiang 1144f4aeeabc061826376c9a72b4714d062664999eaDave Jiang#endif 115