1df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake/* 2df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * Intel X38 Memory Controller kernel module 3df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * Copyright (C) 2008 Cluster Computing, Inc. 4df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 5df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * This file may be distributed under the terms of the 6df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * GNU General Public License. 7df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 8df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * This file is based on i3200_edac.c 9df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 10df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 11df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 12df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include <linux/module.h> 13df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include <linux/init.h> 14df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include <linux/pci.h> 15df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include <linux/pci_ids.h> 16df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include <linux/edac.h> 17df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#include "edac_core.h" 18df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 19df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_REVISION "1.1" 20df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 21df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define EDAC_MOD_STR "x38_edac" 22df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 23df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define PCI_DEVICE_ID_INTEL_X38_HB 0x29e0 24df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 25df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_RANKS 8 26df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_RANKS_PER_CHANNEL 4 27df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_CHANNELS 2 28df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 29df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */ 30df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 31df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */ 323d768213a6c34a27fac1804143da8cf18b8b175fLu Zhihe#define X38_MCHBAR_HIGH 0x4c 33df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */ 34df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_MMR_WINDOW_SIZE 16384 35df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 36df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_TOM 0xa0 /* Top of Memory (16b) 37df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 38df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 15:10 reserved 39df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 9:0 total populated physical memory 40df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 41df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_TOM_MASK 0x3ff /* bits 9:0 */ 42df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_TOM_SHIFT 26 /* 64MiB grain */ 43df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 44df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ERRSTS 0xc8 /* Error Status Register (16b) 45df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 46df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 15 reserved 47df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 14 Isochronous TBWRR Run Behind FIFO Full 48df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * (ITCV) 49df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 13 Isochronous TBWRR Run Behind FIFO Put 50df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * (ITSTV) 51df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 12 reserved 52df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 11 MCH Thermal Sensor Event 53df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * for SMI/SCI/SERR (GTSE) 54df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 10 reserved 55df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 9 LOCK to non-DRAM Memory Flag (LCKF) 56df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 8 reserved 57df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 7 DRAM Throttle Flag (DTF) 58df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 6:2 reserved 59df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 1 Multi-bit DRAM ECC Error Flag (DMERR) 60df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 0 Single-bit DRAM ECC Error Flag (DSERR) 61df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 62df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ERRSTS_UE 0x0002 63df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ERRSTS_CE 0x0001 64df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE) 65df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 66df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 67df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake/* Intel MMIO register space - device 0 function 0 - MMR space */ 68df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 69df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4) 70df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 71df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 15:10 reserved 72df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 9:0 Channel 0 DRAM Rank Boundary Address 73df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 74df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */ 75df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_DRB_MASK 0x3ff /* bits 9:0 */ 76df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_DRB_SHIFT 26 /* 64MiB grain */ 77df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 78df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b) 79df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 80df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 63:48 Error Column Address (ERRCOL) 81df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 47:32 Error Row Address (ERRROW) 82df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 31:29 Error Bank Address (ERRBANK) 83df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 28:27 Error Rank Address (ERRRANK) 84df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 26:24 reserved 85df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 23:16 Error Syndrome (ERRSYND) 86df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 15: 2 reserved 87df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 1 Multiple Bit Error Status (MERRSTS) 88df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * 0 Correctable Error Status (CERRSTS) 89df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 90df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_C1ECCERRLOG 0x680 /* Channel 1 ECC Error Log (64b) */ 91df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ECCERRLOG_CE 0x1 92df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ECCERRLOG_UE 0x2 93df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ECCERRLOG_RANK_BITS 0x18000000 94df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_ECCERRLOG_SYNDROME_BITS 0xff0000 95df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 96df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake#define X38_CAPID0 0xe0 /* see P.94 of spec for details */ 97df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 98df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int x38_channel_num; 99df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 100df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int how_many_channel(struct pci_dev *pdev) 101df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 102df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake unsigned char capid0_8b; /* 8th byte of CAPID0 */ 103df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 104df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b); 105df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ 106df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("In single channel mode.\n"); 107df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_channel_num = 1; 108df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } else { 109df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("In dual channel mode.\n"); 110df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_channel_num = 2; 111df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 112df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 113df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return x38_channel_num; 114df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 115df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 116df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic unsigned long eccerrlog_syndrome(u64 log) 117df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 118df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16; 119df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 120df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 121df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int eccerrlog_row(int channel, u64 log) 122df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 123df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) | 124df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake (channel * X38_RANKS_PER_CHANNEL); 125df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 126df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 127df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakeenum x38_chips { 128df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake X38 = 0, 129df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 130df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 131df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestruct x38_dev_info { 132df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake const char *ctl_name; 133df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 134df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 135df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestruct x38_error_info { 136df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 errsts; 137df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 errsts2; 138df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u64 eccerrlog[X38_CHANNELS]; 139df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 140df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 141df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic const struct x38_dev_info x38_devs[] = { 142df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake [X38] = { 143df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake .ctl_name = "x38"}, 144df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 145df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 146df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic struct pci_dev *mci_pdev; 147df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int x38_registered = 1; 148df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 149df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 150df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void x38_clear_error_info(struct mem_ctl_info *mci) 151df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 152df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct pci_dev *pdev; 153df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 154df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pdev = to_pci_dev(mci->dev); 155df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 156df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* 157df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * Clear any error bits. 158df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * (Yes, we really clear bits by writing 1 to them.) 159df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 160df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS, 161df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake X38_ERRSTS_BITS); 162df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 163df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 164df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic u64 x38_readq(const void __iomem *addr) 165df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 166df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return readl(addr) | (((u64)readl(addr + 4)) << 32); 167df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 168df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 169df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void x38_get_and_clear_error_info(struct mem_ctl_info *mci, 170df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct x38_error_info *info) 171df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 172df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct pci_dev *pdev; 173df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake void __iomem *window = mci->pvt_info; 174df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 175df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pdev = to_pci_dev(mci->dev); 176df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 177df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* 178df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * This is a mess because there is no atomic way to read all the 179df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * registers at once and the registers can transition from CE being 180df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * overwritten by UE. 181df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 182df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_word(pdev, X38_ERRSTS, &info->errsts); 183df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!(info->errsts & X38_ERRSTS_BITS)) 184df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return; 185df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 186df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG); 187df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (x38_channel_num == 2) 188df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake info->eccerrlog[1] = x38_readq(window + X38_C1ECCERRLOG); 189df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 190df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2); 191df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 192df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* 193df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * If the error is the same for both reads then the first set 194df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * of reads is valid. If there is a change then there is a CE 195df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * with no info and the second set of reads is valid and 196df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * should be UE info. 197df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 198df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) { 199df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG); 200df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (x38_channel_num == 2) 201df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake info->eccerrlog[1] = 202df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_readq(window + X38_C1ECCERRLOG); 203df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 204df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 205df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_clear_error_info(mci); 206df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 207df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 208df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void x38_process_error_info(struct mem_ctl_info *mci, 209df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct x38_error_info *info) 210df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 211df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int channel; 212df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u64 log; 213df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 214df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!(info->errsts & X38_ERRSTS_BITS)) 215df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return; 216df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 217df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) { 218df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); 219df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake info->errsts = info->errsts2; 220df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 221df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 222df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake for (channel = 0; channel < x38_channel_num; channel++) { 223df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake log = info->eccerrlog[channel]; 224df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (log & X38_ECCERRLOG_UE) { 225df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake edac_mc_handle_ue(mci, 0, 0, 226df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake eccerrlog_row(channel, log), "x38 UE"); 227df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } else if (log & X38_ECCERRLOG_CE) { 228df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake edac_mc_handle_ce(mci, 0, 0, 229df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake eccerrlog_syndrome(log), 230df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake eccerrlog_row(channel, log), 0, "x38 CE"); 231df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 232df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 233df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 234df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 235df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void x38_check(struct mem_ctl_info *mci) 236df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 237df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct x38_error_info info; 238df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 239df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf1("MC%d: %s()\n", mci->mc_idx, __func__); 240df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_get_and_clear_error_info(mci, &info); 241df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_process_error_info(mci, &info); 242df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 243df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 244df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 245df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakevoid __iomem *x38_map_mchbar(struct pci_dev *pdev) 246df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 247df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake union { 248df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u64 mchbar; 249df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct { 250df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u32 mchbar_low; 251df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u32 mchbar_high; 252df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake }; 253df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } u; 254df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake void __iomem *window; 255df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 256df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low); 257df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1); 258df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high); 259df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u.mchbar &= X38_MCHBAR_MASK; 260df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 261df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (u.mchbar != (resource_size_t)u.mchbar) { 262df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake printk(KERN_ERR 263df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake "x38: mmio space beyond accessible range (0x%llx)\n", 264df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake (unsigned long long)u.mchbar); 265df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return NULL; 266df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 267df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 268df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE); 269df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!window) 270df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n", 271df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake (unsigned long long)u.mchbar); 272df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 273df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return window; 274df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 275df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 276df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 277df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void x38_get_drbs(void __iomem *window, 278df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]) 279df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 280df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int i; 281df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 282df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) { 283df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK; 284df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK; 285df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 286df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 287df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 288df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic bool x38_is_stacked(struct pci_dev *pdev, 289df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]) 290df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 291df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 tom; 292df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 293df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_read_config_word(pdev, X38_TOM, &tom); 294df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake tom &= X38_TOM_MASK; 295df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 296df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom; 297df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 298df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 299df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic unsigned long drb_to_nr_pages( 300df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL], 301df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake bool stacked, int channel, int rank) 302df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 303df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int n; 304df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 305df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake n = drbs[channel][rank]; 306df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (rank > 0) 307df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake n -= drbs[channel][rank - 1]; 308df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (stacked && (channel == 1) && drbs[channel][rank] == 309df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake drbs[channel][X38_RANKS_PER_CHANNEL - 1]) { 310df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake n -= drbs[0][X38_RANKS_PER_CHANNEL - 1]; 311df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 312df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 313df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake n <<= (X38_DRB_SHIFT - PAGE_SHIFT); 314df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return n; 315df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 316df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 317df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int x38_probe1(struct pci_dev *pdev, int dev_idx) 318df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 319df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int rc; 320df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int i; 321df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct mem_ctl_info *mci = NULL; 322df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake unsigned long last_page; 323df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL]; 324df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake bool stacked; 325df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake void __iomem *window; 326df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 327df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("MC: %s()\n", __func__); 328df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 329df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake window = x38_map_mchbar(pdev); 330df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!window) 331df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return -ENODEV; 332df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 333df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_get_drbs(window, drbs); 334df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 335df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake how_many_channel(pdev); 336df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 337df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* FIXME: unconventional pvt_info usage */ 338df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci = edac_mc_alloc(0, X38_RANKS, x38_channel_num, 0); 339df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!mci) 340df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return -ENOMEM; 341df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 342df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf3("MC: %s(): init mci\n", __func__); 343df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 344df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->dev = &pdev->dev; 345df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->mtype_cap = MEM_FLAG_DDR2; 346df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 347df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->edac_ctl_cap = EDAC_FLAG_SECDED; 348df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->edac_cap = EDAC_FLAG_SECDED; 349df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 350df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->mod_name = EDAC_MOD_STR; 351df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->mod_ver = X38_REVISION; 352df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->ctl_name = x38_devs[dev_idx].ctl_name; 353df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->dev_name = pci_name(pdev); 354df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->edac_check = x38_check; 355df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->ctl_page_to_phys = NULL; 356df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci->pvt_info = window; 357df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 358df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake stacked = x38_is_stacked(pdev, drbs); 359df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 360df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* 361df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * The dram rank boundary (DRB) reg values are boundary addresses 362df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * for each DRAM rank with a granularity of 64MB. DRB regs are 363df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * cumulative; the last one will contain the total memory 364df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake * contained in all ranks. 365df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake */ 366df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake last_page = -1UL; 367df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake for (i = 0; i < mci->nr_csrows; i++) { 368df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake unsigned long nr_pages; 369df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct csrow_info *csrow = &mci->csrows[i]; 370df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 371df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake nr_pages = drb_to_nr_pages(drbs, stacked, 372df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake i / X38_RANKS_PER_CHANNEL, 373df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake i % X38_RANKS_PER_CHANNEL); 374df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 375df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (nr_pages == 0) { 376df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->mtype = MEM_EMPTY; 377df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake continue; 378df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 379df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 380df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->first_page = last_page + 1; 381df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake last_page += nr_pages; 382df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->last_page = last_page; 383df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->nr_pages = nr_pages; 384df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 385df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->grain = nr_pages << PAGE_SHIFT; 386df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->mtype = MEM_DDR2; 387df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->dtype = DEV_UNKNOWN; 388df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake csrow->edac_mode = EDAC_UNKNOWN; 389df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 390df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 391df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_clear_error_info(mci); 392df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 393df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake rc = -ENODEV; 394df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (edac_mc_add_mc(mci)) { 395df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__); 396df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake goto fail; 397df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 398df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 399df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* get this far and it's successful */ 400df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf3("MC: %s(): success\n", __func__); 401df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return 0; 402df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 403df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakefail: 404df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake iounmap(window); 405df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (mci) 406df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake edac_mc_free(mci); 407df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 408df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return rc; 409df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 410df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 411df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int __devinit x38_init_one(struct pci_dev *pdev, 412df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake const struct pci_device_id *ent) 413df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 414df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int rc; 415df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 416df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("MC: %s()\n", __func__); 417df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 418df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (pci_enable_device(pdev) < 0) 419df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return -EIO; 420df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 421df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake rc = x38_probe1(pdev, ent->driver_data); 422df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!mci_pdev) 423df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci_pdev = pci_dev_get(pdev); 424df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 425df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return rc; 426df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 427df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 428df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void __devexit x38_remove_one(struct pci_dev *pdev) 429df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 430df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake struct mem_ctl_info *mci; 431df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 432df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("%s()\n", __func__); 433df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 434df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci = edac_mc_del_mc(&pdev->dev); 435df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!mci) 436df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return; 437df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 438df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake iounmap(mci->pvt_info); 439df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 440df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake edac_mc_free(mci); 441df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 442df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 44336c46f31df910b092aaaed27c7c616bb8e2302a1Lionel Debrouxstatic DEFINE_PCI_DEVICE_TABLE(x38_pci_tbl) = { 444df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake { 445df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 446df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake X38}, 447df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake { 448df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 0, 449df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } /* 0 terminated list. */ 450df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 451df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 452df8bc08c192f00f155185bfd6f052d46a728814aHitoshi MitakeMODULE_DEVICE_TABLE(pci, x38_pci_tbl); 453df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 454df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic struct pci_driver x38_driver = { 455df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake .name = EDAC_MOD_STR, 456df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake .probe = x38_init_one, 457df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake .remove = __devexit_p(x38_remove_one), 458df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake .id_table = x38_pci_tbl, 459df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake}; 460df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 461df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic int __init x38_init(void) 462df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 463df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake int pci_rc; 464df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 465df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf3("MC: %s()\n", __func__); 466df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 467df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 468df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake opstate_init(); 469df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 470df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_rc = pci_register_driver(&x38_driver); 471df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (pci_rc < 0) 472df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake goto fail0; 473df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 474df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!mci_pdev) { 475df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_registered = 0; 476df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 477df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake PCI_DEVICE_ID_INTEL_X38_HB, NULL); 478df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!mci_pdev) { 479df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("x38 pci_get_device fail\n"); 480df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_rc = -ENODEV; 481df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake goto fail1; 482df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 483df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 484df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_rc = x38_init_one(mci_pdev, x38_pci_tbl); 485df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (pci_rc < 0) { 486df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf0("x38 init fail\n"); 487df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_rc = -ENODEV; 488df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake goto fail1; 489df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 490df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 491df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 492df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return 0; 493df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 494df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakefail1: 495df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_unregister_driver(&x38_driver); 496df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 497df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakefail0: 498df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (mci_pdev) 499df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_dev_put(mci_pdev); 500df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 501df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake return pci_rc; 502df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 503df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 504df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakestatic void __exit x38_exit(void) 505df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake{ 506df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake debugf3("MC: %s()\n", __func__); 507df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 508df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_unregister_driver(&x38_driver); 509df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake if (!x38_registered) { 510df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake x38_remove_one(mci_pdev); 511df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake pci_dev_put(mci_pdev); 512df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake } 513df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake} 514df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 515df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakemodule_init(x38_init); 516df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakemodule_exit(x38_exit); 517df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 518df8bc08c192f00f155185bfd6f052d46a728814aHitoshi MitakeMODULE_LICENSE("GPL"); 519df8bc08c192f00f155185bfd6f052d46a728814aHitoshi MitakeMODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake"); 520df8bc08c192f00f155185bfd6f052d46a728814aHitoshi MitakeMODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers"); 521df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitake 522df8bc08c192f00f155185bfd6f052d46a728814aHitoshi Mitakemodule_param(edac_op_state, int, 0444); 523df8bc08c192f00f155185bfd6f052d46a728814aHitoshi MitakeMODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 524