i915_dma.c revision 1b2f1489633888d4a06028315dc19d65768a1c05
1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2 */ 3/* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "drm_crtc_helper.h" 32#include "drm_fb_helper.h" 33#include "intel_drv.h" 34#include "i915_drm.h" 35#include "i915_drv.h" 36#include "i915_trace.h" 37#include <linux/pci.h> 38#include <linux/vgaarb.h> 39#include <linux/acpi.h> 40#include <linux/pnp.h> 41#include <linux/vga_switcheroo.h> 42#include <linux/slab.h> 43 44extern int intel_max_stolen; /* from AGP driver */ 45 46/** 47 * Sets up the hardware status page for devices that need a physical address 48 * in the register. 49 */ 50static int i915_init_phys_hws(struct drm_device *dev) 51{ 52 drm_i915_private_t *dev_priv = dev->dev_private; 53 /* Program Hardware Status Page */ 54 dev_priv->status_page_dmah = 55 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); 56 57 if (!dev_priv->status_page_dmah) { 58 DRM_ERROR("Can not allocate hardware status page\n"); 59 return -ENOMEM; 60 } 61 dev_priv->render_ring.status_page.page_addr 62 = dev_priv->status_page_dmah->vaddr; 63 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 64 65 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE); 66 67 if (IS_I965G(dev)) 68 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & 69 0xf0; 70 71 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 72 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 73 return 0; 74} 75 76/** 77 * Frees the hardware status page, whether it's a physical address or a virtual 78 * address set up by the X Server. 79 */ 80static void i915_free_hws(struct drm_device *dev) 81{ 82 drm_i915_private_t *dev_priv = dev->dev_private; 83 if (dev_priv->status_page_dmah) { 84 drm_pci_free(dev, dev_priv->status_page_dmah); 85 dev_priv->status_page_dmah = NULL; 86 } 87 88 if (dev_priv->render_ring.status_page.gfx_addr) { 89 dev_priv->render_ring.status_page.gfx_addr = 0; 90 drm_core_ioremapfree(&dev_priv->hws_map, dev); 91 } 92 93 /* Need to rewrite hardware status page */ 94 I915_WRITE(HWS_PGA, 0x1ffff000); 95} 96 97void i915_kernel_lost_context(struct drm_device * dev) 98{ 99 drm_i915_private_t *dev_priv = dev->dev_private; 100 struct drm_i915_master_private *master_priv; 101 struct intel_ring_buffer *ring = &dev_priv->render_ring; 102 103 /* 104 * We should never lose context on the ring with modesetting 105 * as we don't expose it to userspace 106 */ 107 if (drm_core_check_feature(dev, DRIVER_MODESET)) 108 return; 109 110 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 111 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 112 ring->space = ring->head - (ring->tail + 8); 113 if (ring->space < 0) 114 ring->space += ring->size; 115 116 if (!dev->primary->master) 117 return; 118 119 master_priv = dev->primary->master->driver_priv; 120 if (ring->head == ring->tail && master_priv->sarea_priv) 121 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 122} 123 124static int i915_dma_cleanup(struct drm_device * dev) 125{ 126 drm_i915_private_t *dev_priv = dev->dev_private; 127 /* Make sure interrupts are disabled here because the uninstall ioctl 128 * may not have been called from userspace and after dev_private 129 * is freed, it's too late. 130 */ 131 if (dev->irq_enabled) 132 drm_irq_uninstall(dev); 133 134 mutex_lock(&dev->struct_mutex); 135 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); 136 if (HAS_BSD(dev)) 137 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); 138 mutex_unlock(&dev->struct_mutex); 139 140 /* Clear the HWS virtual address at teardown */ 141 if (I915_NEED_GFX_HWS(dev)) 142 i915_free_hws(dev); 143 144 return 0; 145} 146 147static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) 148{ 149 drm_i915_private_t *dev_priv = dev->dev_private; 150 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 151 152 master_priv->sarea = drm_getsarea(dev); 153 if (master_priv->sarea) { 154 master_priv->sarea_priv = (drm_i915_sarea_t *) 155 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); 156 } else { 157 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); 158 } 159 160 if (init->ring_size != 0) { 161 if (dev_priv->render_ring.gem_object != NULL) { 162 i915_dma_cleanup(dev); 163 DRM_ERROR("Client tried to initialize ringbuffer in " 164 "GEM mode\n"); 165 return -EINVAL; 166 } 167 168 dev_priv->render_ring.size = init->ring_size; 169 170 dev_priv->render_ring.map.offset = init->ring_start; 171 dev_priv->render_ring.map.size = init->ring_size; 172 dev_priv->render_ring.map.type = 0; 173 dev_priv->render_ring.map.flags = 0; 174 dev_priv->render_ring.map.mtrr = 0; 175 176 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev); 177 178 if (dev_priv->render_ring.map.handle == NULL) { 179 i915_dma_cleanup(dev); 180 DRM_ERROR("can not ioremap virtual address for" 181 " ring buffer\n"); 182 return -ENOMEM; 183 } 184 } 185 186 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle; 187 188 dev_priv->cpp = init->cpp; 189 dev_priv->back_offset = init->back_offset; 190 dev_priv->front_offset = init->front_offset; 191 dev_priv->current_page = 0; 192 if (master_priv->sarea_priv) 193 master_priv->sarea_priv->pf_current_page = 0; 194 195 /* Allow hardware batchbuffers unless told otherwise. 196 */ 197 dev_priv->allow_batchbuffer = 1; 198 199 return 0; 200} 201 202static int i915_dma_resume(struct drm_device * dev) 203{ 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 205 206 struct intel_ring_buffer *ring; 207 DRM_DEBUG_DRIVER("%s\n", __func__); 208 209 ring = &dev_priv->render_ring; 210 211 if (ring->map.handle == NULL) { 212 DRM_ERROR("can not ioremap virtual address for" 213 " ring buffer\n"); 214 return -ENOMEM; 215 } 216 217 /* Program Hardware Status Page */ 218 if (!ring->status_page.page_addr) { 219 DRM_ERROR("Can not find hardware status page\n"); 220 return -EINVAL; 221 } 222 DRM_DEBUG_DRIVER("hw status page @ %p\n", 223 ring->status_page.page_addr); 224 if (ring->status_page.gfx_addr != 0) 225 ring->setup_status_page(dev, ring); 226 else 227 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 228 229 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 230 231 return 0; 232} 233 234static int i915_dma_init(struct drm_device *dev, void *data, 235 struct drm_file *file_priv) 236{ 237 drm_i915_init_t *init = data; 238 int retcode = 0; 239 240 switch (init->func) { 241 case I915_INIT_DMA: 242 retcode = i915_initialize(dev, init); 243 break; 244 case I915_CLEANUP_DMA: 245 retcode = i915_dma_cleanup(dev); 246 break; 247 case I915_RESUME_DMA: 248 retcode = i915_dma_resume(dev); 249 break; 250 default: 251 retcode = -EINVAL; 252 break; 253 } 254 255 return retcode; 256} 257 258/* Implement basically the same security restrictions as hardware does 259 * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 260 * 261 * Most of the calculations below involve calculating the size of a 262 * particular instruction. It's important to get the size right as 263 * that tells us where the next instruction to check is. Any illegal 264 * instruction detected will be given a size of zero, which is a 265 * signal to abort the rest of the buffer. 266 */ 267static int do_validate_cmd(int cmd) 268{ 269 switch (((cmd >> 29) & 0x7)) { 270 case 0x0: 271 switch ((cmd >> 23) & 0x3f) { 272 case 0x0: 273 return 1; /* MI_NOOP */ 274 case 0x4: 275 return 1; /* MI_FLUSH */ 276 default: 277 return 0; /* disallow everything else */ 278 } 279 break; 280 case 0x1: 281 return 0; /* reserved */ 282 case 0x2: 283 return (cmd & 0xff) + 2; /* 2d commands */ 284 case 0x3: 285 if (((cmd >> 24) & 0x1f) <= 0x18) 286 return 1; 287 288 switch ((cmd >> 24) & 0x1f) { 289 case 0x1c: 290 return 1; 291 case 0x1d: 292 switch ((cmd >> 16) & 0xff) { 293 case 0x3: 294 return (cmd & 0x1f) + 2; 295 case 0x4: 296 return (cmd & 0xf) + 2; 297 default: 298 return (cmd & 0xffff) + 2; 299 } 300 case 0x1e: 301 if (cmd & (1 << 23)) 302 return (cmd & 0xffff) + 1; 303 else 304 return 1; 305 case 0x1f: 306 if ((cmd & (1 << 23)) == 0) /* inline vertices */ 307 return (cmd & 0x1ffff) + 2; 308 else if (cmd & (1 << 17)) /* indirect random */ 309 if ((cmd & 0xffff) == 0) 310 return 0; /* unknown length, too hard */ 311 else 312 return (((cmd & 0xffff) + 1) / 2) + 1; 313 else 314 return 2; /* indirect sequential */ 315 default: 316 return 0; 317 } 318 default: 319 return 0; 320 } 321 322 return 0; 323} 324 325static int validate_cmd(int cmd) 326{ 327 int ret = do_validate_cmd(cmd); 328 329/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 330 331 return ret; 332} 333 334static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) 335{ 336 drm_i915_private_t *dev_priv = dev->dev_private; 337 int i; 338 339 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8) 340 return -EINVAL; 341 342 BEGIN_LP_RING((dwords+1)&~1); 343 344 for (i = 0; i < dwords;) { 345 int cmd, sz; 346 347 cmd = buffer[i]; 348 349 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 350 return -EINVAL; 351 352 OUT_RING(cmd); 353 354 while (++i, --sz) { 355 OUT_RING(buffer[i]); 356 } 357 } 358 359 if (dwords & 1) 360 OUT_RING(0); 361 362 ADVANCE_LP_RING(); 363 364 return 0; 365} 366 367int 368i915_emit_box(struct drm_device *dev, 369 struct drm_clip_rect *boxes, 370 int i, int DR1, int DR4) 371{ 372 struct drm_clip_rect box = boxes[i]; 373 374 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { 375 DRM_ERROR("Bad box %d,%d..%d,%d\n", 376 box.x1, box.y1, box.x2, box.y2); 377 return -EINVAL; 378 } 379 380 if (IS_I965G(dev)) { 381 BEGIN_LP_RING(4); 382 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 383 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 384 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 385 OUT_RING(DR4); 386 ADVANCE_LP_RING(); 387 } else { 388 BEGIN_LP_RING(6); 389 OUT_RING(GFX_OP_DRAWRECT_INFO); 390 OUT_RING(DR1); 391 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 392 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 393 OUT_RING(DR4); 394 OUT_RING(0); 395 ADVANCE_LP_RING(); 396 } 397 398 return 0; 399} 400 401/* XXX: Emitting the counter should really be moved to part of the IRQ 402 * emit. For now, do it in both places: 403 */ 404 405static void i915_emit_breadcrumb(struct drm_device *dev) 406{ 407 drm_i915_private_t *dev_priv = dev->dev_private; 408 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 409 410 dev_priv->counter++; 411 if (dev_priv->counter > 0x7FFFFFFFUL) 412 dev_priv->counter = 0; 413 if (master_priv->sarea_priv) 414 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 415 416 BEGIN_LP_RING(4); 417 OUT_RING(MI_STORE_DWORD_INDEX); 418 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 419 OUT_RING(dev_priv->counter); 420 OUT_RING(0); 421 ADVANCE_LP_RING(); 422} 423 424static int i915_dispatch_cmdbuffer(struct drm_device * dev, 425 drm_i915_cmdbuffer_t *cmd, 426 struct drm_clip_rect *cliprects, 427 void *cmdbuf) 428{ 429 int nbox = cmd->num_cliprects; 430 int i = 0, count, ret; 431 432 if (cmd->sz & 0x3) { 433 DRM_ERROR("alignment"); 434 return -EINVAL; 435 } 436 437 i915_kernel_lost_context(dev); 438 439 count = nbox ? nbox : 1; 440 441 for (i = 0; i < count; i++) { 442 if (i < nbox) { 443 ret = i915_emit_box(dev, cliprects, i, 444 cmd->DR1, cmd->DR4); 445 if (ret) 446 return ret; 447 } 448 449 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); 450 if (ret) 451 return ret; 452 } 453 454 i915_emit_breadcrumb(dev); 455 return 0; 456} 457 458static int i915_dispatch_batchbuffer(struct drm_device * dev, 459 drm_i915_batchbuffer_t * batch, 460 struct drm_clip_rect *cliprects) 461{ 462 int nbox = batch->num_cliprects; 463 int i = 0, count; 464 465 if ((batch->start | batch->used) & 0x7) { 466 DRM_ERROR("alignment"); 467 return -EINVAL; 468 } 469 470 i915_kernel_lost_context(dev); 471 472 count = nbox ? nbox : 1; 473 474 for (i = 0; i < count; i++) { 475 if (i < nbox) { 476 int ret = i915_emit_box(dev, cliprects, i, 477 batch->DR1, batch->DR4); 478 if (ret) 479 return ret; 480 } 481 482 if (!IS_I830(dev) && !IS_845G(dev)) { 483 BEGIN_LP_RING(2); 484 if (IS_I965G(dev)) { 485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); 486 OUT_RING(batch->start); 487 } else { 488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 489 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 490 } 491 ADVANCE_LP_RING(); 492 } else { 493 BEGIN_LP_RING(4); 494 OUT_RING(MI_BATCH_BUFFER); 495 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 496 OUT_RING(batch->start + batch->used - 4); 497 OUT_RING(0); 498 ADVANCE_LP_RING(); 499 } 500 } 501 502 i915_emit_breadcrumb(dev); 503 504 return 0; 505} 506 507static int i915_dispatch_flip(struct drm_device * dev) 508{ 509 drm_i915_private_t *dev_priv = dev->dev_private; 510 struct drm_i915_master_private *master_priv = 511 dev->primary->master->driver_priv; 512 513 if (!master_priv->sarea_priv) 514 return -EINVAL; 515 516 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", 517 __func__, 518 dev_priv->current_page, 519 master_priv->sarea_priv->pf_current_page); 520 521 i915_kernel_lost_context(dev); 522 523 BEGIN_LP_RING(2); 524 OUT_RING(MI_FLUSH | MI_READ_FLUSH); 525 OUT_RING(0); 526 ADVANCE_LP_RING(); 527 528 BEGIN_LP_RING(6); 529 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); 530 OUT_RING(0); 531 if (dev_priv->current_page == 0) { 532 OUT_RING(dev_priv->back_offset); 533 dev_priv->current_page = 1; 534 } else { 535 OUT_RING(dev_priv->front_offset); 536 dev_priv->current_page = 0; 537 } 538 OUT_RING(0); 539 ADVANCE_LP_RING(); 540 541 BEGIN_LP_RING(2); 542 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); 543 OUT_RING(0); 544 ADVANCE_LP_RING(); 545 546 master_priv->sarea_priv->last_enqueue = dev_priv->counter++; 547 548 BEGIN_LP_RING(4); 549 OUT_RING(MI_STORE_DWORD_INDEX); 550 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 551 OUT_RING(dev_priv->counter); 552 OUT_RING(0); 553 ADVANCE_LP_RING(); 554 555 master_priv->sarea_priv->pf_current_page = dev_priv->current_page; 556 return 0; 557} 558 559static int i915_quiescent(struct drm_device * dev) 560{ 561 drm_i915_private_t *dev_priv = dev->dev_private; 562 563 i915_kernel_lost_context(dev); 564 return intel_wait_ring_buffer(dev, &dev_priv->render_ring, 565 dev_priv->render_ring.size - 8); 566} 567 568static int i915_flush_ioctl(struct drm_device *dev, void *data, 569 struct drm_file *file_priv) 570{ 571 int ret; 572 573 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 574 575 mutex_lock(&dev->struct_mutex); 576 ret = i915_quiescent(dev); 577 mutex_unlock(&dev->struct_mutex); 578 579 return ret; 580} 581 582static int i915_batchbuffer(struct drm_device *dev, void *data, 583 struct drm_file *file_priv) 584{ 585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 586 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 587 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 588 master_priv->sarea_priv; 589 drm_i915_batchbuffer_t *batch = data; 590 int ret; 591 struct drm_clip_rect *cliprects = NULL; 592 593 if (!dev_priv->allow_batchbuffer) { 594 DRM_ERROR("Batchbuffer ioctl disabled\n"); 595 return -EINVAL; 596 } 597 598 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", 599 batch->start, batch->used, batch->num_cliprects); 600 601 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 602 603 if (batch->num_cliprects < 0) 604 return -EINVAL; 605 606 if (batch->num_cliprects) { 607 cliprects = kcalloc(batch->num_cliprects, 608 sizeof(struct drm_clip_rect), 609 GFP_KERNEL); 610 if (cliprects == NULL) 611 return -ENOMEM; 612 613 ret = copy_from_user(cliprects, batch->cliprects, 614 batch->num_cliprects * 615 sizeof(struct drm_clip_rect)); 616 if (ret != 0) 617 goto fail_free; 618 } 619 620 mutex_lock(&dev->struct_mutex); 621 ret = i915_dispatch_batchbuffer(dev, batch, cliprects); 622 mutex_unlock(&dev->struct_mutex); 623 624 if (sarea_priv) 625 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 626 627fail_free: 628 kfree(cliprects); 629 630 return ret; 631} 632 633static int i915_cmdbuffer(struct drm_device *dev, void *data, 634 struct drm_file *file_priv) 635{ 636 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 637 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 638 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 639 master_priv->sarea_priv; 640 drm_i915_cmdbuffer_t *cmdbuf = data; 641 struct drm_clip_rect *cliprects = NULL; 642 void *batch_data; 643 int ret; 644 645 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 646 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 647 648 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 649 650 if (cmdbuf->num_cliprects < 0) 651 return -EINVAL; 652 653 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); 654 if (batch_data == NULL) 655 return -ENOMEM; 656 657 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); 658 if (ret != 0) 659 goto fail_batch_free; 660 661 if (cmdbuf->num_cliprects) { 662 cliprects = kcalloc(cmdbuf->num_cliprects, 663 sizeof(struct drm_clip_rect), GFP_KERNEL); 664 if (cliprects == NULL) { 665 ret = -ENOMEM; 666 goto fail_batch_free; 667 } 668 669 ret = copy_from_user(cliprects, cmdbuf->cliprects, 670 cmdbuf->num_cliprects * 671 sizeof(struct drm_clip_rect)); 672 if (ret != 0) 673 goto fail_clip_free; 674 } 675 676 mutex_lock(&dev->struct_mutex); 677 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); 678 mutex_unlock(&dev->struct_mutex); 679 if (ret) { 680 DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 681 goto fail_clip_free; 682 } 683 684 if (sarea_priv) 685 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 686 687fail_clip_free: 688 kfree(cliprects); 689fail_batch_free: 690 kfree(batch_data); 691 692 return ret; 693} 694 695static int i915_flip_bufs(struct drm_device *dev, void *data, 696 struct drm_file *file_priv) 697{ 698 int ret; 699 700 DRM_DEBUG_DRIVER("%s\n", __func__); 701 702 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 703 704 mutex_lock(&dev->struct_mutex); 705 ret = i915_dispatch_flip(dev); 706 mutex_unlock(&dev->struct_mutex); 707 708 return ret; 709} 710 711static int i915_getparam(struct drm_device *dev, void *data, 712 struct drm_file *file_priv) 713{ 714 drm_i915_private_t *dev_priv = dev->dev_private; 715 drm_i915_getparam_t *param = data; 716 int value; 717 718 if (!dev_priv) { 719 DRM_ERROR("called with no initialization\n"); 720 return -EINVAL; 721 } 722 723 switch (param->param) { 724 case I915_PARAM_IRQ_ACTIVE: 725 value = dev->pdev->irq ? 1 : 0; 726 break; 727 case I915_PARAM_ALLOW_BATCHBUFFER: 728 value = dev_priv->allow_batchbuffer ? 1 : 0; 729 break; 730 case I915_PARAM_LAST_DISPATCH: 731 value = READ_BREADCRUMB(dev_priv); 732 break; 733 case I915_PARAM_CHIPSET_ID: 734 value = dev->pci_device; 735 break; 736 case I915_PARAM_HAS_GEM: 737 value = dev_priv->has_gem; 738 break; 739 case I915_PARAM_NUM_FENCES_AVAIL: 740 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 741 break; 742 case I915_PARAM_HAS_OVERLAY: 743 value = dev_priv->overlay ? 1 : 0; 744 break; 745 case I915_PARAM_HAS_PAGEFLIPPING: 746 value = 1; 747 break; 748 case I915_PARAM_HAS_EXECBUF2: 749 /* depends on GEM */ 750 value = dev_priv->has_gem; 751 break; 752 case I915_PARAM_HAS_BSD: 753 value = HAS_BSD(dev); 754 break; 755 default: 756 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 757 param->param); 758 return -EINVAL; 759 } 760 761 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 762 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 763 return -EFAULT; 764 } 765 766 return 0; 767} 768 769static int i915_setparam(struct drm_device *dev, void *data, 770 struct drm_file *file_priv) 771{ 772 drm_i915_private_t *dev_priv = dev->dev_private; 773 drm_i915_setparam_t *param = data; 774 775 if (!dev_priv) { 776 DRM_ERROR("called with no initialization\n"); 777 return -EINVAL; 778 } 779 780 switch (param->param) { 781 case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 782 break; 783 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 784 dev_priv->tex_lru_log_granularity = param->value; 785 break; 786 case I915_SETPARAM_ALLOW_BATCHBUFFER: 787 dev_priv->allow_batchbuffer = param->value; 788 break; 789 case I915_SETPARAM_NUM_USED_FENCES: 790 if (param->value > dev_priv->num_fence_regs || 791 param->value < 0) 792 return -EINVAL; 793 /* Userspace can use first N regs */ 794 dev_priv->fence_reg_start = param->value; 795 break; 796 default: 797 DRM_DEBUG_DRIVER("unknown parameter %d\n", 798 param->param); 799 return -EINVAL; 800 } 801 802 return 0; 803} 804 805static int i915_set_status_page(struct drm_device *dev, void *data, 806 struct drm_file *file_priv) 807{ 808 drm_i915_private_t *dev_priv = dev->dev_private; 809 drm_i915_hws_addr_t *hws = data; 810 struct intel_ring_buffer *ring = &dev_priv->render_ring; 811 812 if (!I915_NEED_GFX_HWS(dev)) 813 return -EINVAL; 814 815 if (!dev_priv) { 816 DRM_ERROR("called with no initialization\n"); 817 return -EINVAL; 818 } 819 820 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 821 WARN(1, "tried to set status page when mode setting active\n"); 822 return 0; 823 } 824 825 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); 826 827 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); 828 829 dev_priv->hws_map.offset = dev->agp->base + hws->addr; 830 dev_priv->hws_map.size = 4*1024; 831 dev_priv->hws_map.type = 0; 832 dev_priv->hws_map.flags = 0; 833 dev_priv->hws_map.mtrr = 0; 834 835 drm_core_ioremap_wc(&dev_priv->hws_map, dev); 836 if (dev_priv->hws_map.handle == NULL) { 837 i915_dma_cleanup(dev); 838 ring->status_page.gfx_addr = 0; 839 DRM_ERROR("can not ioremap virtual address for" 840 " G33 hw status page\n"); 841 return -ENOMEM; 842 } 843 ring->status_page.page_addr = dev_priv->hws_map.handle; 844 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 845 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); 846 847 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", 848 ring->status_page.gfx_addr); 849 DRM_DEBUG_DRIVER("load hws at %p\n", 850 ring->status_page.page_addr); 851 return 0; 852} 853 854static int i915_get_bridge_dev(struct drm_device *dev) 855{ 856 struct drm_i915_private *dev_priv = dev->dev_private; 857 858 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); 859 if (!dev_priv->bridge_dev) { 860 DRM_ERROR("bridge device not found\n"); 861 return -1; 862 } 863 return 0; 864} 865 866#define MCHBAR_I915 0x44 867#define MCHBAR_I965 0x48 868#define MCHBAR_SIZE (4*4096) 869 870#define DEVEN_REG 0x54 871#define DEVEN_MCHBAR_EN (1 << 28) 872 873/* Allocate space for the MCH regs if needed, return nonzero on error */ 874static int 875intel_alloc_mchbar_resource(struct drm_device *dev) 876{ 877 drm_i915_private_t *dev_priv = dev->dev_private; 878 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 879 u32 temp_lo, temp_hi = 0; 880 u64 mchbar_addr; 881 int ret = 0; 882 883 if (IS_I965G(dev)) 884 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 885 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 886 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 887 888 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 889#ifdef CONFIG_PNP 890 if (mchbar_addr && 891 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 892 ret = 0; 893 goto out; 894 } 895#endif 896 897 /* Get some space for it */ 898 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, 899 MCHBAR_SIZE, MCHBAR_SIZE, 900 PCIBIOS_MIN_MEM, 901 0, pcibios_align_resource, 902 dev_priv->bridge_dev); 903 if (ret) { 904 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); 905 dev_priv->mch_res.start = 0; 906 goto out; 907 } 908 909 if (IS_I965G(dev)) 910 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 911 upper_32_bits(dev_priv->mch_res.start)); 912 913 pci_write_config_dword(dev_priv->bridge_dev, reg, 914 lower_32_bits(dev_priv->mch_res.start)); 915out: 916 return ret; 917} 918 919/* Setup MCHBAR if possible, return true if we should disable it again */ 920static void 921intel_setup_mchbar(struct drm_device *dev) 922{ 923 drm_i915_private_t *dev_priv = dev->dev_private; 924 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 925 u32 temp; 926 bool enabled; 927 928 dev_priv->mchbar_need_disable = false; 929 930 if (IS_I915G(dev) || IS_I915GM(dev)) { 931 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); 932 enabled = !!(temp & DEVEN_MCHBAR_EN); 933 } else { 934 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 935 enabled = temp & 1; 936 } 937 938 /* If it's already enabled, don't have to do anything */ 939 if (enabled) 940 return; 941 942 if (intel_alloc_mchbar_resource(dev)) 943 return; 944 945 dev_priv->mchbar_need_disable = true; 946 947 /* Space is allocated or reserved, so enable it. */ 948 if (IS_I915G(dev) || IS_I915GM(dev)) { 949 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, 950 temp | DEVEN_MCHBAR_EN); 951 } else { 952 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 953 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 954 } 955} 956 957static void 958intel_teardown_mchbar(struct drm_device *dev) 959{ 960 drm_i915_private_t *dev_priv = dev->dev_private; 961 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 962 u32 temp; 963 964 if (dev_priv->mchbar_need_disable) { 965 if (IS_I915G(dev) || IS_I915GM(dev)) { 966 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); 967 temp &= ~DEVEN_MCHBAR_EN; 968 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); 969 } else { 970 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 971 temp &= ~1; 972 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); 973 } 974 } 975 976 if (dev_priv->mch_res.start) 977 release_resource(&dev_priv->mch_res); 978} 979 980/** 981 * i915_probe_agp - get AGP bootup configuration 982 * @pdev: PCI device 983 * @aperture_size: returns AGP aperture configured size 984 * @preallocated_size: returns size of BIOS preallocated AGP space 985 * 986 * Since Intel integrated graphics are UMA, the BIOS has to set aside 987 * some RAM for the framebuffer at early boot. This code figures out 988 * how much was set aside so we can use it for our own purposes. 989 */ 990static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 991 uint32_t *preallocated_size, 992 uint32_t *start) 993{ 994 struct drm_i915_private *dev_priv = dev->dev_private; 995 u16 tmp = 0; 996 unsigned long overhead; 997 unsigned long stolen; 998 999 /* Get the fb aperture size and "stolen" memory amount. */ 1000 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); 1001 1002 *aperture_size = 1024 * 1024; 1003 *preallocated_size = 1024 * 1024; 1004 1005 switch (dev->pdev->device) { 1006 case PCI_DEVICE_ID_INTEL_82830_CGC: 1007 case PCI_DEVICE_ID_INTEL_82845G_IG: 1008 case PCI_DEVICE_ID_INTEL_82855GM_IG: 1009 case PCI_DEVICE_ID_INTEL_82865_IG: 1010 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) 1011 *aperture_size *= 64; 1012 else 1013 *aperture_size *= 128; 1014 break; 1015 default: 1016 /* 9xx supports large sizes, just look at the length */ 1017 *aperture_size = pci_resource_len(dev->pdev, 2); 1018 break; 1019 } 1020 1021 /* 1022 * Some of the preallocated space is taken by the GTT 1023 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 1024 */ 1025 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) 1026 overhead = 4096; 1027 else 1028 overhead = (*aperture_size / 1024) + 4096; 1029 1030 if (IS_GEN6(dev)) { 1031 /* SNB has memory control reg at 0x50.w */ 1032 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp); 1033 1034 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) { 1035 case INTEL_855_GMCH_GMS_DISABLED: 1036 DRM_ERROR("video memory is disabled\n"); 1037 return -1; 1038 case SNB_GMCH_GMS_STOLEN_32M: 1039 stolen = 32 * 1024 * 1024; 1040 break; 1041 case SNB_GMCH_GMS_STOLEN_64M: 1042 stolen = 64 * 1024 * 1024; 1043 break; 1044 case SNB_GMCH_GMS_STOLEN_96M: 1045 stolen = 96 * 1024 * 1024; 1046 break; 1047 case SNB_GMCH_GMS_STOLEN_128M: 1048 stolen = 128 * 1024 * 1024; 1049 break; 1050 case SNB_GMCH_GMS_STOLEN_160M: 1051 stolen = 160 * 1024 * 1024; 1052 break; 1053 case SNB_GMCH_GMS_STOLEN_192M: 1054 stolen = 192 * 1024 * 1024; 1055 break; 1056 case SNB_GMCH_GMS_STOLEN_224M: 1057 stolen = 224 * 1024 * 1024; 1058 break; 1059 case SNB_GMCH_GMS_STOLEN_256M: 1060 stolen = 256 * 1024 * 1024; 1061 break; 1062 case SNB_GMCH_GMS_STOLEN_288M: 1063 stolen = 288 * 1024 * 1024; 1064 break; 1065 case SNB_GMCH_GMS_STOLEN_320M: 1066 stolen = 320 * 1024 * 1024; 1067 break; 1068 case SNB_GMCH_GMS_STOLEN_352M: 1069 stolen = 352 * 1024 * 1024; 1070 break; 1071 case SNB_GMCH_GMS_STOLEN_384M: 1072 stolen = 384 * 1024 * 1024; 1073 break; 1074 case SNB_GMCH_GMS_STOLEN_416M: 1075 stolen = 416 * 1024 * 1024; 1076 break; 1077 case SNB_GMCH_GMS_STOLEN_448M: 1078 stolen = 448 * 1024 * 1024; 1079 break; 1080 case SNB_GMCH_GMS_STOLEN_480M: 1081 stolen = 480 * 1024 * 1024; 1082 break; 1083 case SNB_GMCH_GMS_STOLEN_512M: 1084 stolen = 512 * 1024 * 1024; 1085 break; 1086 default: 1087 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", 1088 tmp & SNB_GMCH_GMS_STOLEN_MASK); 1089 return -1; 1090 } 1091 } else { 1092 switch (tmp & INTEL_GMCH_GMS_MASK) { 1093 case INTEL_855_GMCH_GMS_DISABLED: 1094 DRM_ERROR("video memory is disabled\n"); 1095 return -1; 1096 case INTEL_855_GMCH_GMS_STOLEN_1M: 1097 stolen = 1 * 1024 * 1024; 1098 break; 1099 case INTEL_855_GMCH_GMS_STOLEN_4M: 1100 stolen = 4 * 1024 * 1024; 1101 break; 1102 case INTEL_855_GMCH_GMS_STOLEN_8M: 1103 stolen = 8 * 1024 * 1024; 1104 break; 1105 case INTEL_855_GMCH_GMS_STOLEN_16M: 1106 stolen = 16 * 1024 * 1024; 1107 break; 1108 case INTEL_855_GMCH_GMS_STOLEN_32M: 1109 stolen = 32 * 1024 * 1024; 1110 break; 1111 case INTEL_915G_GMCH_GMS_STOLEN_48M: 1112 stolen = 48 * 1024 * 1024; 1113 break; 1114 case INTEL_915G_GMCH_GMS_STOLEN_64M: 1115 stolen = 64 * 1024 * 1024; 1116 break; 1117 case INTEL_GMCH_GMS_STOLEN_128M: 1118 stolen = 128 * 1024 * 1024; 1119 break; 1120 case INTEL_GMCH_GMS_STOLEN_256M: 1121 stolen = 256 * 1024 * 1024; 1122 break; 1123 case INTEL_GMCH_GMS_STOLEN_96M: 1124 stolen = 96 * 1024 * 1024; 1125 break; 1126 case INTEL_GMCH_GMS_STOLEN_160M: 1127 stolen = 160 * 1024 * 1024; 1128 break; 1129 case INTEL_GMCH_GMS_STOLEN_224M: 1130 stolen = 224 * 1024 * 1024; 1131 break; 1132 case INTEL_GMCH_GMS_STOLEN_352M: 1133 stolen = 352 * 1024 * 1024; 1134 break; 1135 default: 1136 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", 1137 tmp & INTEL_GMCH_GMS_MASK); 1138 return -1; 1139 } 1140 } 1141 1142 *preallocated_size = stolen - overhead; 1143 *start = overhead; 1144 1145 return 0; 1146} 1147 1148#define PTE_ADDRESS_MASK 0xfffff000 1149#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ 1150#define PTE_MAPPING_TYPE_UNCACHED (0 << 1) 1151#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ 1152#define PTE_MAPPING_TYPE_CACHED (3 << 1) 1153#define PTE_MAPPING_TYPE_MASK (3 << 1) 1154#define PTE_VALID (1 << 0) 1155 1156/** 1157 * i915_gtt_to_phys - take a GTT address and turn it into a physical one 1158 * @dev: drm device 1159 * @gtt_addr: address to translate 1160 * 1161 * Some chip functions require allocations from stolen space but need the 1162 * physical address of the memory in question. We use this routine 1163 * to get a physical address suitable for register programming from a given 1164 * GTT address. 1165 */ 1166static unsigned long i915_gtt_to_phys(struct drm_device *dev, 1167 unsigned long gtt_addr) 1168{ 1169 unsigned long *gtt; 1170 unsigned long entry, phys; 1171 int gtt_bar = IS_I9XX(dev) ? 0 : 1; 1172 int gtt_offset, gtt_size; 1173 1174 if (IS_I965G(dev)) { 1175 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { 1176 gtt_offset = 2*1024*1024; 1177 gtt_size = 2*1024*1024; 1178 } else { 1179 gtt_offset = 512*1024; 1180 gtt_size = 512*1024; 1181 } 1182 } else { 1183 gtt_bar = 3; 1184 gtt_offset = 0; 1185 gtt_size = pci_resource_len(dev->pdev, gtt_bar); 1186 } 1187 1188 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, 1189 gtt_size); 1190 if (!gtt) { 1191 DRM_ERROR("ioremap of GTT failed\n"); 1192 return 0; 1193 } 1194 1195 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); 1196 1197 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); 1198 1199 /* Mask out these reserved bits on this hardware. */ 1200 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || 1201 IS_I945G(dev) || IS_I945GM(dev)) { 1202 entry &= ~PTE_ADDRESS_MASK_HIGH; 1203 } 1204 1205 /* If it's not a mapping type we know, then bail. */ 1206 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && 1207 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { 1208 iounmap(gtt); 1209 return 0; 1210 } 1211 1212 if (!(entry & PTE_VALID)) { 1213 DRM_ERROR("bad GTT entry in stolen space\n"); 1214 iounmap(gtt); 1215 return 0; 1216 } 1217 1218 iounmap(gtt); 1219 1220 phys =(entry & PTE_ADDRESS_MASK) | 1221 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); 1222 1223 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); 1224 1225 return phys; 1226} 1227 1228static void i915_warn_stolen(struct drm_device *dev) 1229{ 1230 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); 1231 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); 1232} 1233 1234static void i915_setup_compression(struct drm_device *dev, int size) 1235{ 1236 struct drm_i915_private *dev_priv = dev->dev_private; 1237 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); 1238 unsigned long cfb_base; 1239 unsigned long ll_base = 0; 1240 1241 /* Leave 1M for line length buffer & misc. */ 1242 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); 1243 if (!compressed_fb) { 1244 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 1245 i915_warn_stolen(dev); 1246 return; 1247 } 1248 1249 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); 1250 if (!compressed_fb) { 1251 i915_warn_stolen(dev); 1252 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 1253 return; 1254 } 1255 1256 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); 1257 if (!cfb_base) { 1258 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1259 drm_mm_put_block(compressed_fb); 1260 } 1261 1262 if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) { 1263 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 1264 4096, 0); 1265 if (!compressed_llb) { 1266 i915_warn_stolen(dev); 1267 return; 1268 } 1269 1270 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); 1271 if (!compressed_llb) { 1272 i915_warn_stolen(dev); 1273 return; 1274 } 1275 1276 ll_base = i915_gtt_to_phys(dev, compressed_llb->start); 1277 if (!ll_base) { 1278 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1279 drm_mm_put_block(compressed_fb); 1280 drm_mm_put_block(compressed_llb); 1281 } 1282 } 1283 1284 dev_priv->cfb_size = size; 1285 1286 intel_disable_fbc(dev); 1287 dev_priv->compressed_fb = compressed_fb; 1288 if (IS_IRONLAKE_M(dev)) 1289 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); 1290 else if (IS_GM45(dev)) { 1291 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); 1292 } else { 1293 I915_WRITE(FBC_CFB_BASE, cfb_base); 1294 I915_WRITE(FBC_LL_BASE, ll_base); 1295 dev_priv->compressed_llb = compressed_llb; 1296 } 1297 1298 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, 1299 ll_base, size >> 20); 1300} 1301 1302static void i915_cleanup_compression(struct drm_device *dev) 1303{ 1304 struct drm_i915_private *dev_priv = dev->dev_private; 1305 1306 drm_mm_put_block(dev_priv->compressed_fb); 1307 if (dev_priv->compressed_llb) 1308 drm_mm_put_block(dev_priv->compressed_llb); 1309} 1310 1311/* true = enable decode, false = disable decoder */ 1312static unsigned int i915_vga_set_decode(void *cookie, bool state) 1313{ 1314 struct drm_device *dev = cookie; 1315 1316 intel_modeset_vga_set_state(dev, state); 1317 if (state) 1318 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1319 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1320 else 1321 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1322} 1323 1324static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1325{ 1326 struct drm_device *dev = pci_get_drvdata(pdev); 1327 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 1328 if (state == VGA_SWITCHEROO_ON) { 1329 printk(KERN_INFO "i915: switched on\n"); 1330 /* i915 resume handler doesn't set to D0 */ 1331 pci_set_power_state(dev->pdev, PCI_D0); 1332 i915_resume(dev); 1333 drm_kms_helper_poll_enable(dev); 1334 } else { 1335 printk(KERN_ERR "i915: switched off\n"); 1336 drm_kms_helper_poll_disable(dev); 1337 i915_suspend(dev, pmm); 1338 } 1339} 1340 1341static bool i915_switcheroo_can_switch(struct pci_dev *pdev) 1342{ 1343 struct drm_device *dev = pci_get_drvdata(pdev); 1344 bool can_switch; 1345 1346 spin_lock(&dev->count_lock); 1347 can_switch = (dev->open_count == 0); 1348 spin_unlock(&dev->count_lock); 1349 return can_switch; 1350} 1351 1352static int i915_load_modeset_init(struct drm_device *dev, 1353 unsigned long prealloc_start, 1354 unsigned long prealloc_size, 1355 unsigned long agp_size) 1356{ 1357 struct drm_i915_private *dev_priv = dev->dev_private; 1358 int fb_bar = IS_I9XX(dev) ? 2 : 0; 1359 int ret = 0; 1360 1361 dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) & 1362 0xff000000; 1363 1364 /* Basic memrange allocator for stolen space (aka vram) */ 1365 drm_mm_init(&dev_priv->vram, 0, prealloc_size); 1366 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); 1367 1368 /* We're off and running w/KMS */ 1369 dev_priv->mm.suspended = 0; 1370 1371 /* Let GEM Manage from end of prealloc space to end of aperture. 1372 * 1373 * However, leave one page at the end still bound to the scratch page. 1374 * There are a number of places where the hardware apparently 1375 * prefetches past the end of the object, and we've seen multiple 1376 * hangs with the GPU head pointer stuck in a batchbuffer bound 1377 * at the last page of the aperture. One page should be enough to 1378 * keep any prefetching inside of the aperture. 1379 */ 1380 i915_gem_do_init(dev, prealloc_size, agp_size - 4096); 1381 1382 mutex_lock(&dev->struct_mutex); 1383 ret = i915_gem_init_ringbuffer(dev); 1384 mutex_unlock(&dev->struct_mutex); 1385 if (ret) 1386 goto out; 1387 1388 /* Try to set up FBC with a reasonable compressed buffer size */ 1389 if (I915_HAS_FBC(dev) && i915_powersave) { 1390 int cfb_size; 1391 1392 /* Try to get an 8M buffer... */ 1393 if (prealloc_size > (9*1024*1024)) 1394 cfb_size = 8*1024*1024; 1395 else /* fall back to 7/8 of the stolen space */ 1396 cfb_size = prealloc_size * 7 / 8; 1397 i915_setup_compression(dev, cfb_size); 1398 } 1399 1400 /* Allow hardware batchbuffers unless told otherwise. 1401 */ 1402 dev_priv->allow_batchbuffer = 1; 1403 1404 ret = intel_init_bios(dev); 1405 if (ret) 1406 DRM_INFO("failed to find VBIOS tables\n"); 1407 1408 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1409 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1410 if (ret) 1411 goto cleanup_ringbuffer; 1412 1413 ret = vga_switcheroo_register_client(dev->pdev, 1414 i915_switcheroo_set_state, 1415 i915_switcheroo_can_switch); 1416 if (ret) 1417 goto cleanup_vga_client; 1418 1419 /* IIR "flip pending" bit means done if this bit is set */ 1420 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) 1421 dev_priv->flip_pending_is_done = true; 1422 1423 intel_modeset_init(dev); 1424 1425 ret = drm_irq_install(dev); 1426 if (ret) 1427 goto cleanup_vga_switcheroo; 1428 1429 /* Always safe in the mode setting case. */ 1430 /* FIXME: do pre/post-mode set stuff in core KMS code */ 1431 dev->vblank_disable_allowed = 1; 1432 1433 /* 1434 * Initialize the hardware status page IRQ location. 1435 */ 1436 1437 I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); 1438 1439 ret = intel_fbdev_init(dev); 1440 if (ret) 1441 goto cleanup_irq; 1442 1443 drm_kms_helper_poll_init(dev); 1444 return 0; 1445 1446cleanup_irq: 1447 drm_irq_uninstall(dev); 1448cleanup_vga_switcheroo: 1449 vga_switcheroo_unregister_client(dev->pdev); 1450cleanup_vga_client: 1451 vga_client_register(dev->pdev, NULL, NULL, NULL); 1452cleanup_ringbuffer: 1453 mutex_lock(&dev->struct_mutex); 1454 i915_gem_cleanup_ringbuffer(dev); 1455 mutex_unlock(&dev->struct_mutex); 1456out: 1457 return ret; 1458} 1459 1460int i915_master_create(struct drm_device *dev, struct drm_master *master) 1461{ 1462 struct drm_i915_master_private *master_priv; 1463 1464 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); 1465 if (!master_priv) 1466 return -ENOMEM; 1467 1468 master->driver_priv = master_priv; 1469 return 0; 1470} 1471 1472void i915_master_destroy(struct drm_device *dev, struct drm_master *master) 1473{ 1474 struct drm_i915_master_private *master_priv = master->driver_priv; 1475 1476 if (!master_priv) 1477 return; 1478 1479 kfree(master_priv); 1480 1481 master->driver_priv = NULL; 1482} 1483 1484static void i915_pineview_get_mem_freq(struct drm_device *dev) 1485{ 1486 drm_i915_private_t *dev_priv = dev->dev_private; 1487 u32 tmp; 1488 1489 tmp = I915_READ(CLKCFG); 1490 1491 switch (tmp & CLKCFG_FSB_MASK) { 1492 case CLKCFG_FSB_533: 1493 dev_priv->fsb_freq = 533; /* 133*4 */ 1494 break; 1495 case CLKCFG_FSB_800: 1496 dev_priv->fsb_freq = 800; /* 200*4 */ 1497 break; 1498 case CLKCFG_FSB_667: 1499 dev_priv->fsb_freq = 667; /* 167*4 */ 1500 break; 1501 case CLKCFG_FSB_400: 1502 dev_priv->fsb_freq = 400; /* 100*4 */ 1503 break; 1504 } 1505 1506 switch (tmp & CLKCFG_MEM_MASK) { 1507 case CLKCFG_MEM_533: 1508 dev_priv->mem_freq = 533; 1509 break; 1510 case CLKCFG_MEM_667: 1511 dev_priv->mem_freq = 667; 1512 break; 1513 case CLKCFG_MEM_800: 1514 dev_priv->mem_freq = 800; 1515 break; 1516 } 1517 1518 /* detect pineview DDR3 setting */ 1519 tmp = I915_READ(CSHRDDR3CTL); 1520 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 1521} 1522 1523static void i915_ironlake_get_mem_freq(struct drm_device *dev) 1524{ 1525 drm_i915_private_t *dev_priv = dev->dev_private; 1526 u16 ddrpll, csipll; 1527 1528 ddrpll = I915_READ16(DDRMPLL1); 1529 csipll = I915_READ16(CSIPLL0); 1530 1531 switch (ddrpll & 0xff) { 1532 case 0xc: 1533 dev_priv->mem_freq = 800; 1534 break; 1535 case 0x10: 1536 dev_priv->mem_freq = 1066; 1537 break; 1538 case 0x14: 1539 dev_priv->mem_freq = 1333; 1540 break; 1541 case 0x18: 1542 dev_priv->mem_freq = 1600; 1543 break; 1544 default: 1545 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 1546 ddrpll & 0xff); 1547 dev_priv->mem_freq = 0; 1548 break; 1549 } 1550 1551 dev_priv->r_t = dev_priv->mem_freq; 1552 1553 switch (csipll & 0x3ff) { 1554 case 0x00c: 1555 dev_priv->fsb_freq = 3200; 1556 break; 1557 case 0x00e: 1558 dev_priv->fsb_freq = 3733; 1559 break; 1560 case 0x010: 1561 dev_priv->fsb_freq = 4266; 1562 break; 1563 case 0x012: 1564 dev_priv->fsb_freq = 4800; 1565 break; 1566 case 0x014: 1567 dev_priv->fsb_freq = 5333; 1568 break; 1569 case 0x016: 1570 dev_priv->fsb_freq = 5866; 1571 break; 1572 case 0x018: 1573 dev_priv->fsb_freq = 6400; 1574 break; 1575 default: 1576 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 1577 csipll & 0x3ff); 1578 dev_priv->fsb_freq = 0; 1579 break; 1580 } 1581 1582 if (dev_priv->fsb_freq == 3200) { 1583 dev_priv->c_m = 0; 1584 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 1585 dev_priv->c_m = 1; 1586 } else { 1587 dev_priv->c_m = 2; 1588 } 1589} 1590 1591struct v_table { 1592 u8 vid; 1593 unsigned long vd; /* in .1 mil */ 1594 unsigned long vm; /* in .1 mil */ 1595 u8 pvid; 1596}; 1597 1598static struct v_table v_table[] = { 1599 { 0, 16125, 15000, 0x7f, }, 1600 { 1, 16000, 14875, 0x7e, }, 1601 { 2, 15875, 14750, 0x7d, }, 1602 { 3, 15750, 14625, 0x7c, }, 1603 { 4, 15625, 14500, 0x7b, }, 1604 { 5, 15500, 14375, 0x7a, }, 1605 { 6, 15375, 14250, 0x79, }, 1606 { 7, 15250, 14125, 0x78, }, 1607 { 8, 15125, 14000, 0x77, }, 1608 { 9, 15000, 13875, 0x76, }, 1609 { 10, 14875, 13750, 0x75, }, 1610 { 11, 14750, 13625, 0x74, }, 1611 { 12, 14625, 13500, 0x73, }, 1612 { 13, 14500, 13375, 0x72, }, 1613 { 14, 14375, 13250, 0x71, }, 1614 { 15, 14250, 13125, 0x70, }, 1615 { 16, 14125, 13000, 0x6f, }, 1616 { 17, 14000, 12875, 0x6e, }, 1617 { 18, 13875, 12750, 0x6d, }, 1618 { 19, 13750, 12625, 0x6c, }, 1619 { 20, 13625, 12500, 0x6b, }, 1620 { 21, 13500, 12375, 0x6a, }, 1621 { 22, 13375, 12250, 0x69, }, 1622 { 23, 13250, 12125, 0x68, }, 1623 { 24, 13125, 12000, 0x67, }, 1624 { 25, 13000, 11875, 0x66, }, 1625 { 26, 12875, 11750, 0x65, }, 1626 { 27, 12750, 11625, 0x64, }, 1627 { 28, 12625, 11500, 0x63, }, 1628 { 29, 12500, 11375, 0x62, }, 1629 { 30, 12375, 11250, 0x61, }, 1630 { 31, 12250, 11125, 0x60, }, 1631 { 32, 12125, 11000, 0x5f, }, 1632 { 33, 12000, 10875, 0x5e, }, 1633 { 34, 11875, 10750, 0x5d, }, 1634 { 35, 11750, 10625, 0x5c, }, 1635 { 36, 11625, 10500, 0x5b, }, 1636 { 37, 11500, 10375, 0x5a, }, 1637 { 38, 11375, 10250, 0x59, }, 1638 { 39, 11250, 10125, 0x58, }, 1639 { 40, 11125, 10000, 0x57, }, 1640 { 41, 11000, 9875, 0x56, }, 1641 { 42, 10875, 9750, 0x55, }, 1642 { 43, 10750, 9625, 0x54, }, 1643 { 44, 10625, 9500, 0x53, }, 1644 { 45, 10500, 9375, 0x52, }, 1645 { 46, 10375, 9250, 0x51, }, 1646 { 47, 10250, 9125, 0x50, }, 1647 { 48, 10125, 9000, 0x4f, }, 1648 { 49, 10000, 8875, 0x4e, }, 1649 { 50, 9875, 8750, 0x4d, }, 1650 { 51, 9750, 8625, 0x4c, }, 1651 { 52, 9625, 8500, 0x4b, }, 1652 { 53, 9500, 8375, 0x4a, }, 1653 { 54, 9375, 8250, 0x49, }, 1654 { 55, 9250, 8125, 0x48, }, 1655 { 56, 9125, 8000, 0x47, }, 1656 { 57, 9000, 7875, 0x46, }, 1657 { 58, 8875, 7750, 0x45, }, 1658 { 59, 8750, 7625, 0x44, }, 1659 { 60, 8625, 7500, 0x43, }, 1660 { 61, 8500, 7375, 0x42, }, 1661 { 62, 8375, 7250, 0x41, }, 1662 { 63, 8250, 7125, 0x40, }, 1663 { 64, 8125, 7000, 0x3f, }, 1664 { 65, 8000, 6875, 0x3e, }, 1665 { 66, 7875, 6750, 0x3d, }, 1666 { 67, 7750, 6625, 0x3c, }, 1667 { 68, 7625, 6500, 0x3b, }, 1668 { 69, 7500, 6375, 0x3a, }, 1669 { 70, 7375, 6250, 0x39, }, 1670 { 71, 7250, 6125, 0x38, }, 1671 { 72, 7125, 6000, 0x37, }, 1672 { 73, 7000, 5875, 0x36, }, 1673 { 74, 6875, 5750, 0x35, }, 1674 { 75, 6750, 5625, 0x34, }, 1675 { 76, 6625, 5500, 0x33, }, 1676 { 77, 6500, 5375, 0x32, }, 1677 { 78, 6375, 5250, 0x31, }, 1678 { 79, 6250, 5125, 0x30, }, 1679 { 80, 6125, 5000, 0x2f, }, 1680 { 81, 6000, 4875, 0x2e, }, 1681 { 82, 5875, 4750, 0x2d, }, 1682 { 83, 5750, 4625, 0x2c, }, 1683 { 84, 5625, 4500, 0x2b, }, 1684 { 85, 5500, 4375, 0x2a, }, 1685 { 86, 5375, 4250, 0x29, }, 1686 { 87, 5250, 4125, 0x28, }, 1687 { 88, 5125, 4000, 0x27, }, 1688 { 89, 5000, 3875, 0x26, }, 1689 { 90, 4875, 3750, 0x25, }, 1690 { 91, 4750, 3625, 0x24, }, 1691 { 92, 4625, 3500, 0x23, }, 1692 { 93, 4500, 3375, 0x22, }, 1693 { 94, 4375, 3250, 0x21, }, 1694 { 95, 4250, 3125, 0x20, }, 1695 { 96, 4125, 3000, 0x1f, }, 1696 { 97, 4125, 3000, 0x1e, }, 1697 { 98, 4125, 3000, 0x1d, }, 1698 { 99, 4125, 3000, 0x1c, }, 1699 { 100, 4125, 3000, 0x1b, }, 1700 { 101, 4125, 3000, 0x1a, }, 1701 { 102, 4125, 3000, 0x19, }, 1702 { 103, 4125, 3000, 0x18, }, 1703 { 104, 4125, 3000, 0x17, }, 1704 { 105, 4125, 3000, 0x16, }, 1705 { 106, 4125, 3000, 0x15, }, 1706 { 107, 4125, 3000, 0x14, }, 1707 { 108, 4125, 3000, 0x13, }, 1708 { 109, 4125, 3000, 0x12, }, 1709 { 110, 4125, 3000, 0x11, }, 1710 { 111, 4125, 3000, 0x10, }, 1711 { 112, 4125, 3000, 0x0f, }, 1712 { 113, 4125, 3000, 0x0e, }, 1713 { 114, 4125, 3000, 0x0d, }, 1714 { 115, 4125, 3000, 0x0c, }, 1715 { 116, 4125, 3000, 0x0b, }, 1716 { 117, 4125, 3000, 0x0a, }, 1717 { 118, 4125, 3000, 0x09, }, 1718 { 119, 4125, 3000, 0x08, }, 1719 { 120, 1125, 0, 0x07, }, 1720 { 121, 1000, 0, 0x06, }, 1721 { 122, 875, 0, 0x05, }, 1722 { 123, 750, 0, 0x04, }, 1723 { 124, 625, 0, 0x03, }, 1724 { 125, 500, 0, 0x02, }, 1725 { 126, 375, 0, 0x01, }, 1726 { 127, 0, 0, 0x00, }, 1727}; 1728 1729struct cparams { 1730 int i; 1731 int t; 1732 int m; 1733 int c; 1734}; 1735 1736static struct cparams cparams[] = { 1737 { 1, 1333, 301, 28664 }, 1738 { 1, 1066, 294, 24460 }, 1739 { 1, 800, 294, 25192 }, 1740 { 0, 1333, 276, 27605 }, 1741 { 0, 1066, 276, 27605 }, 1742 { 0, 800, 231, 23784 }, 1743}; 1744 1745unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 1746{ 1747 u64 total_count, diff, ret; 1748 u32 count1, count2, count3, m = 0, c = 0; 1749 unsigned long now = jiffies_to_msecs(jiffies), diff1; 1750 int i; 1751 1752 diff1 = now - dev_priv->last_time1; 1753 1754 count1 = I915_READ(DMIEC); 1755 count2 = I915_READ(DDREC); 1756 count3 = I915_READ(CSIEC); 1757 1758 total_count = count1 + count2 + count3; 1759 1760 /* FIXME: handle per-counter overflow */ 1761 if (total_count < dev_priv->last_count1) { 1762 diff = ~0UL - dev_priv->last_count1; 1763 diff += total_count; 1764 } else { 1765 diff = total_count - dev_priv->last_count1; 1766 } 1767 1768 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 1769 if (cparams[i].i == dev_priv->c_m && 1770 cparams[i].t == dev_priv->r_t) { 1771 m = cparams[i].m; 1772 c = cparams[i].c; 1773 break; 1774 } 1775 } 1776 1777 div_u64(diff, diff1); 1778 ret = ((m * diff) + c); 1779 div_u64(ret, 10); 1780 1781 dev_priv->last_count1 = total_count; 1782 dev_priv->last_time1 = now; 1783 1784 return ret; 1785} 1786 1787unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 1788{ 1789 unsigned long m, x, b; 1790 u32 tsfs; 1791 1792 tsfs = I915_READ(TSFS); 1793 1794 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 1795 x = I915_READ8(TR1); 1796 1797 b = tsfs & TSFS_INTR_MASK; 1798 1799 return ((m * x) / 127) - b; 1800} 1801 1802static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 1803{ 1804 unsigned long val = 0; 1805 int i; 1806 1807 for (i = 0; i < ARRAY_SIZE(v_table); i++) { 1808 if (v_table[i].pvid == pxvid) { 1809 if (IS_MOBILE(dev_priv->dev)) 1810 val = v_table[i].vm; 1811 else 1812 val = v_table[i].vd; 1813 } 1814 } 1815 1816 return val; 1817} 1818 1819void i915_update_gfx_val(struct drm_i915_private *dev_priv) 1820{ 1821 struct timespec now, diff1; 1822 u64 diff; 1823 unsigned long diffms; 1824 u32 count; 1825 1826 getrawmonotonic(&now); 1827 diff1 = timespec_sub(now, dev_priv->last_time2); 1828 1829 /* Don't divide by 0 */ 1830 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 1831 if (!diffms) 1832 return; 1833 1834 count = I915_READ(GFXEC); 1835 1836 if (count < dev_priv->last_count2) { 1837 diff = ~0UL - dev_priv->last_count2; 1838 diff += count; 1839 } else { 1840 diff = count - dev_priv->last_count2; 1841 } 1842 1843 dev_priv->last_count2 = count; 1844 dev_priv->last_time2 = now; 1845 1846 /* More magic constants... */ 1847 diff = diff * 1181; 1848 div_u64(diff, diffms * 10); 1849 dev_priv->gfx_power = diff; 1850} 1851 1852unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 1853{ 1854 unsigned long t, corr, state1, corr2, state2; 1855 u32 pxvid, ext_v; 1856 1857 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); 1858 pxvid = (pxvid >> 24) & 0x7f; 1859 ext_v = pvid_to_extvid(dev_priv, pxvid); 1860 1861 state1 = ext_v; 1862 1863 t = i915_mch_val(dev_priv); 1864 1865 /* Revel in the empirically derived constants */ 1866 1867 /* Correction factor in 1/100000 units */ 1868 if (t > 80) 1869 corr = ((t * 2349) + 135940); 1870 else if (t >= 50) 1871 corr = ((t * 964) + 29317); 1872 else /* < 50 */ 1873 corr = ((t * 301) + 1004); 1874 1875 corr = corr * ((150142 * state1) / 10000 - 78642); 1876 corr /= 100000; 1877 corr2 = (corr * dev_priv->corr); 1878 1879 state2 = (corr2 * state1) / 10000; 1880 state2 /= 100; /* convert to mW */ 1881 1882 i915_update_gfx_val(dev_priv); 1883 1884 return dev_priv->gfx_power + state2; 1885} 1886 1887/* Global for IPS driver to get at the current i915 device */ 1888static struct drm_i915_private *i915_mch_dev; 1889/* 1890 * Lock protecting IPS related data structures 1891 * - i915_mch_dev 1892 * - dev_priv->max_delay 1893 * - dev_priv->min_delay 1894 * - dev_priv->fmax 1895 * - dev_priv->gpu_busy 1896 */ 1897DEFINE_SPINLOCK(mchdev_lock); 1898 1899/** 1900 * i915_read_mch_val - return value for IPS use 1901 * 1902 * Calculate and return a value for the IPS driver to use when deciding whether 1903 * we have thermal and power headroom to increase CPU or GPU power budget. 1904 */ 1905unsigned long i915_read_mch_val(void) 1906{ 1907 struct drm_i915_private *dev_priv; 1908 unsigned long chipset_val, graphics_val, ret = 0; 1909 1910 spin_lock(&mchdev_lock); 1911 if (!i915_mch_dev) 1912 goto out_unlock; 1913 dev_priv = i915_mch_dev; 1914 1915 chipset_val = i915_chipset_val(dev_priv); 1916 graphics_val = i915_gfx_val(dev_priv); 1917 1918 ret = chipset_val + graphics_val; 1919 1920out_unlock: 1921 spin_unlock(&mchdev_lock); 1922 1923 return ret; 1924} 1925EXPORT_SYMBOL_GPL(i915_read_mch_val); 1926 1927/** 1928 * i915_gpu_raise - raise GPU frequency limit 1929 * 1930 * Raise the limit; IPS indicates we have thermal headroom. 1931 */ 1932bool i915_gpu_raise(void) 1933{ 1934 struct drm_i915_private *dev_priv; 1935 bool ret = true; 1936 1937 spin_lock(&mchdev_lock); 1938 if (!i915_mch_dev) { 1939 ret = false; 1940 goto out_unlock; 1941 } 1942 dev_priv = i915_mch_dev; 1943 1944 if (dev_priv->max_delay > dev_priv->fmax) 1945 dev_priv->max_delay--; 1946 1947out_unlock: 1948 spin_unlock(&mchdev_lock); 1949 1950 return ret; 1951} 1952EXPORT_SYMBOL_GPL(i915_gpu_raise); 1953 1954/** 1955 * i915_gpu_lower - lower GPU frequency limit 1956 * 1957 * IPS indicates we're close to a thermal limit, so throttle back the GPU 1958 * frequency maximum. 1959 */ 1960bool i915_gpu_lower(void) 1961{ 1962 struct drm_i915_private *dev_priv; 1963 bool ret = true; 1964 1965 spin_lock(&mchdev_lock); 1966 if (!i915_mch_dev) { 1967 ret = false; 1968 goto out_unlock; 1969 } 1970 dev_priv = i915_mch_dev; 1971 1972 if (dev_priv->max_delay < dev_priv->min_delay) 1973 dev_priv->max_delay++; 1974 1975out_unlock: 1976 spin_unlock(&mchdev_lock); 1977 1978 return ret; 1979} 1980EXPORT_SYMBOL_GPL(i915_gpu_lower); 1981 1982/** 1983 * i915_gpu_busy - indicate GPU business to IPS 1984 * 1985 * Tell the IPS driver whether or not the GPU is busy. 1986 */ 1987bool i915_gpu_busy(void) 1988{ 1989 struct drm_i915_private *dev_priv; 1990 bool ret = false; 1991 1992 spin_lock(&mchdev_lock); 1993 if (!i915_mch_dev) 1994 goto out_unlock; 1995 dev_priv = i915_mch_dev; 1996 1997 ret = dev_priv->busy; 1998 1999out_unlock: 2000 spin_unlock(&mchdev_lock); 2001 2002 return ret; 2003} 2004EXPORT_SYMBOL_GPL(i915_gpu_busy); 2005 2006/** 2007 * i915_gpu_turbo_disable - disable graphics turbo 2008 * 2009 * Disable graphics turbo by resetting the max frequency and setting the 2010 * current frequency to the default. 2011 */ 2012bool i915_gpu_turbo_disable(void) 2013{ 2014 struct drm_i915_private *dev_priv; 2015 bool ret = true; 2016 2017 spin_lock(&mchdev_lock); 2018 if (!i915_mch_dev) { 2019 ret = false; 2020 goto out_unlock; 2021 } 2022 dev_priv = i915_mch_dev; 2023 2024 dev_priv->max_delay = dev_priv->fstart; 2025 2026 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) 2027 ret = false; 2028 2029out_unlock: 2030 spin_unlock(&mchdev_lock); 2031 2032 return ret; 2033} 2034EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 2035 2036/** 2037 * i915_driver_load - setup chip and create an initial config 2038 * @dev: DRM device 2039 * @flags: startup flags 2040 * 2041 * The driver load routine has to do several things: 2042 * - drive output discovery via intel_modeset_init() 2043 * - initialize the memory manager 2044 * - allocate initial config memory 2045 * - setup the DRM framebuffer with the allocated memory 2046 */ 2047int i915_driver_load(struct drm_device *dev, unsigned long flags) 2048{ 2049 struct drm_i915_private *dev_priv; 2050 resource_size_t base, size; 2051 int ret = 0, mmio_bar; 2052 uint32_t agp_size, prealloc_size, prealloc_start; 2053 /* i915 has 4 more counters */ 2054 dev->counters += 4; 2055 dev->types[6] = _DRM_STAT_IRQ; 2056 dev->types[7] = _DRM_STAT_PRIMARY; 2057 dev->types[8] = _DRM_STAT_SECONDARY; 2058 dev->types[9] = _DRM_STAT_DMA; 2059 2060 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); 2061 if (dev_priv == NULL) 2062 return -ENOMEM; 2063 2064 dev->dev_private = (void *)dev_priv; 2065 dev_priv->dev = dev; 2066 dev_priv->info = (struct intel_device_info *) flags; 2067 2068 /* Add register map (needed for suspend/resume) */ 2069 mmio_bar = IS_I9XX(dev) ? 0 : 1; 2070 base = pci_resource_start(dev->pdev, mmio_bar); 2071 size = pci_resource_len(dev->pdev, mmio_bar); 2072 2073 if (i915_get_bridge_dev(dev)) { 2074 ret = -EIO; 2075 goto free_priv; 2076 } 2077 2078 dev_priv->regs = ioremap(base, size); 2079 if (!dev_priv->regs) { 2080 DRM_ERROR("failed to map registers\n"); 2081 ret = -EIO; 2082 goto put_bridge; 2083 } 2084 2085 dev_priv->mm.gtt_mapping = 2086 io_mapping_create_wc(dev->agp->base, 2087 dev->agp->agp_info.aper_size * 1024*1024); 2088 if (dev_priv->mm.gtt_mapping == NULL) { 2089 ret = -EIO; 2090 goto out_rmmap; 2091 } 2092 2093 /* Set up a WC MTRR for non-PAT systems. This is more common than 2094 * one would think, because the kernel disables PAT on first 2095 * generation Core chips because WC PAT gets overridden by a UC 2096 * MTRR if present. Even if a UC MTRR isn't present. 2097 */ 2098 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, 2099 dev->agp->agp_info.aper_size * 2100 1024 * 1024, 2101 MTRR_TYPE_WRCOMB, 1); 2102 if (dev_priv->mm.gtt_mtrr < 0) { 2103 DRM_INFO("MTRR allocation failed. Graphics " 2104 "performance may suffer.\n"); 2105 } 2106 2107 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); 2108 if (ret) 2109 goto out_iomapfree; 2110 2111 if (prealloc_size > intel_max_stolen) { 2112 DRM_INFO("detected %dM stolen memory, trimming to %dM\n", 2113 prealloc_size >> 20, intel_max_stolen >> 20); 2114 prealloc_size = intel_max_stolen; 2115 } 2116 2117 dev_priv->wq = create_singlethread_workqueue("i915"); 2118 if (dev_priv->wq == NULL) { 2119 DRM_ERROR("Failed to create our workqueue.\n"); 2120 ret = -ENOMEM; 2121 goto out_iomapfree; 2122 } 2123 2124 /* enable GEM by default */ 2125 dev_priv->has_gem = 1; 2126 2127 if (prealloc_size > agp_size * 3 / 4) { 2128 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " 2129 "memory stolen.\n", 2130 prealloc_size / 1024, agp_size / 1024); 2131 DRM_ERROR("Disabling GEM. (try reducing stolen memory or " 2132 "updating the BIOS to fix).\n"); 2133 dev_priv->has_gem = 0; 2134 } 2135 2136 if (dev_priv->has_gem == 0 && 2137 drm_core_check_feature(dev, DRIVER_MODESET)) { 2138 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n"); 2139 ret = -ENODEV; 2140 goto out_iomapfree; 2141 } 2142 2143 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2144 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2145 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { 2146 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2147 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2148 } 2149 2150 /* Try to make sure MCHBAR is enabled before poking at it */ 2151 intel_setup_mchbar(dev); 2152 2153 i915_gem_load(dev); 2154 2155 /* Init HWS */ 2156 if (!I915_NEED_GFX_HWS(dev)) { 2157 ret = i915_init_phys_hws(dev); 2158 if (ret != 0) 2159 goto out_workqueue_free; 2160 } 2161 2162 if (IS_PINEVIEW(dev)) 2163 i915_pineview_get_mem_freq(dev); 2164 else if (IS_IRONLAKE(dev)) 2165 i915_ironlake_get_mem_freq(dev); 2166 2167 /* On the 945G/GM, the chipset reports the MSI capability on the 2168 * integrated graphics even though the support isn't actually there 2169 * according to the published specs. It doesn't appear to function 2170 * correctly in testing on 945G. 2171 * This may be a side effect of MSI having been made available for PEG 2172 * and the registers being closely associated. 2173 * 2174 * According to chipset errata, on the 965GM, MSI interrupts may 2175 * be lost or delayed, but we use them anyways to avoid 2176 * stuck interrupts on some machines. 2177 */ 2178 if (!IS_I945G(dev) && !IS_I945GM(dev)) 2179 pci_enable_msi(dev->pdev); 2180 2181 spin_lock_init(&dev_priv->user_irq_lock); 2182 spin_lock_init(&dev_priv->error_lock); 2183 dev_priv->trace_irq_seqno = 0; 2184 2185 ret = drm_vblank_init(dev, I915_NUM_PIPE); 2186 2187 if (ret) { 2188 (void) i915_driver_unload(dev); 2189 return ret; 2190 } 2191 2192 /* Start out suspended */ 2193 dev_priv->mm.suspended = 1; 2194 2195 intel_detect_pch(dev); 2196 2197 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 2198 ret = i915_load_modeset_init(dev, prealloc_start, 2199 prealloc_size, agp_size); 2200 if (ret < 0) { 2201 DRM_ERROR("failed to init modeset\n"); 2202 goto out_workqueue_free; 2203 } 2204 } 2205 2206 /* Must be done after probing outputs */ 2207 intel_opregion_init(dev, 0); 2208 2209 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 2210 (unsigned long) dev); 2211 2212 spin_lock(&mchdev_lock); 2213 i915_mch_dev = dev_priv; 2214 dev_priv->mchdev_lock = &mchdev_lock; 2215 spin_unlock(&mchdev_lock); 2216 2217 return 0; 2218 2219out_workqueue_free: 2220 destroy_workqueue(dev_priv->wq); 2221out_iomapfree: 2222 io_mapping_free(dev_priv->mm.gtt_mapping); 2223out_rmmap: 2224 iounmap(dev_priv->regs); 2225put_bridge: 2226 pci_dev_put(dev_priv->bridge_dev); 2227free_priv: 2228 kfree(dev_priv); 2229 return ret; 2230} 2231 2232int i915_driver_unload(struct drm_device *dev) 2233{ 2234 struct drm_i915_private *dev_priv = dev->dev_private; 2235 2236 i915_destroy_error_state(dev); 2237 2238 spin_lock(&mchdev_lock); 2239 i915_mch_dev = NULL; 2240 spin_unlock(&mchdev_lock); 2241 2242 destroy_workqueue(dev_priv->wq); 2243 del_timer_sync(&dev_priv->hangcheck_timer); 2244 2245 io_mapping_free(dev_priv->mm.gtt_mapping); 2246 if (dev_priv->mm.gtt_mtrr >= 0) { 2247 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, 2248 dev->agp->agp_info.aper_size * 1024 * 1024); 2249 dev_priv->mm.gtt_mtrr = -1; 2250 } 2251 2252 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 2253 intel_modeset_cleanup(dev); 2254 2255 /* 2256 * free the memory space allocated for the child device 2257 * config parsed from VBT 2258 */ 2259 if (dev_priv->child_dev && dev_priv->child_dev_num) { 2260 kfree(dev_priv->child_dev); 2261 dev_priv->child_dev = NULL; 2262 dev_priv->child_dev_num = 0; 2263 } 2264 drm_irq_uninstall(dev); 2265 vga_switcheroo_unregister_client(dev->pdev); 2266 vga_client_register(dev->pdev, NULL, NULL, NULL); 2267 } 2268 2269 if (dev->pdev->msi_enabled) 2270 pci_disable_msi(dev->pdev); 2271 2272 if (dev_priv->regs != NULL) 2273 iounmap(dev_priv->regs); 2274 2275 intel_opregion_free(dev, 0); 2276 2277 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 2278 i915_gem_free_all_phys_object(dev); 2279 2280 mutex_lock(&dev->struct_mutex); 2281 i915_gem_cleanup_ringbuffer(dev); 2282 mutex_unlock(&dev->struct_mutex); 2283 if (I915_HAS_FBC(dev) && i915_powersave) 2284 i915_cleanup_compression(dev); 2285 drm_mm_takedown(&dev_priv->vram); 2286 i915_gem_lastclose(dev); 2287 2288 intel_cleanup_overlay(dev); 2289 } 2290 2291 intel_teardown_mchbar(dev); 2292 2293 pci_dev_put(dev_priv->bridge_dev); 2294 kfree(dev->dev_private); 2295 2296 return 0; 2297} 2298 2299int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 2300{ 2301 struct drm_i915_file_private *i915_file_priv; 2302 2303 DRM_DEBUG_DRIVER("\n"); 2304 i915_file_priv = (struct drm_i915_file_private *) 2305 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); 2306 2307 if (!i915_file_priv) 2308 return -ENOMEM; 2309 2310 file_priv->driver_priv = i915_file_priv; 2311 2312 INIT_LIST_HEAD(&i915_file_priv->mm.request_list); 2313 2314 return 0; 2315} 2316 2317/** 2318 * i915_driver_lastclose - clean up after all DRM clients have exited 2319 * @dev: DRM device 2320 * 2321 * Take care of cleaning up after all DRM clients have exited. In the 2322 * mode setting case, we want to restore the kernel's initial mode (just 2323 * in case the last client left us in a bad state). 2324 * 2325 * Additionally, in the non-mode setting case, we'll tear down the AGP 2326 * and DMA structures, since the kernel won't be using them, and clea 2327 * up any GEM state. 2328 */ 2329void i915_driver_lastclose(struct drm_device * dev) 2330{ 2331 drm_i915_private_t *dev_priv = dev->dev_private; 2332 2333 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { 2334 drm_fb_helper_restore(); 2335 vga_switcheroo_process_delayed_switch(); 2336 return; 2337 } 2338 2339 i915_gem_lastclose(dev); 2340 2341 if (dev_priv->agp_heap) 2342 i915_mem_takedown(&(dev_priv->agp_heap)); 2343 2344 i915_dma_cleanup(dev); 2345} 2346 2347void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 2348{ 2349 drm_i915_private_t *dev_priv = dev->dev_private; 2350 i915_gem_release(dev, file_priv); 2351 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 2352 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 2353} 2354 2355void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 2356{ 2357 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 2358 2359 kfree(i915_file_priv); 2360} 2361 2362struct drm_ioctl_desc i915_ioctls[] = { 2363 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2364 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 2365 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), 2366 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 2367 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 2368 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 2369 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), 2370 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2371 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH), 2372 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH), 2373 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2374 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 2375 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2376 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2377 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), 2378 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 2379 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2380 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2381 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), 2382 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), 2383 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2384 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2385 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 2386 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), 2387 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2388 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2389 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), 2390 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), 2391 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), 2392 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), 2393 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), 2394 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), 2395 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), 2396 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), 2397 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), 2398 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), 2399 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), 2400 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), 2401 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2402 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2403}; 2404 2405int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 2406 2407/** 2408 * Determine if the device really is AGP or not. 2409 * 2410 * All Intel graphics chipsets are treated as AGP, even if they are really 2411 * PCI-e. 2412 * 2413 * \param dev The device to be tested. 2414 * 2415 * \returns 2416 * A value of 1 is always retured to indictate every i9x5 is AGP. 2417 */ 2418int i915_driver_device_is_agp(struct drm_device * dev) 2419{ 2420 return 1; 2421} 2422