i915_dma.c revision 8187a2b70e34c727a06617441f74f202b6fefaf9
1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2 */ 3/* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "drm_crtc_helper.h" 32#include "drm_fb_helper.h" 33#include "intel_drv.h" 34#include "i915_drm.h" 35#include "i915_drv.h" 36#include "i915_trace.h" 37#include <linux/vgaarb.h> 38#include <linux/acpi.h> 39#include <linux/pnp.h> 40#include <linux/vga_switcheroo.h> 41#include <linux/slab.h> 42 43/** 44 * Sets up the hardware status page for devices that need a physical address 45 * in the register. 46 */ 47static int i915_init_phys_hws(struct drm_device *dev) 48{ 49 drm_i915_private_t *dev_priv = dev->dev_private; 50 /* Program Hardware Status Page */ 51 dev_priv->status_page_dmah = 52 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); 53 54 if (!dev_priv->status_page_dmah) { 55 DRM_ERROR("Can not allocate hardware status page\n"); 56 return -ENOMEM; 57 } 58 dev_priv->render_ring.status_page.page_addr 59 = dev_priv->status_page_dmah->vaddr; 60 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 61 62 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE); 63 64 if (IS_I965G(dev)) 65 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & 66 0xf0; 67 68 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 69 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 70 return 0; 71} 72 73/** 74 * Frees the hardware status page, whether it's a physical address or a virtual 75 * address set up by the X Server. 76 */ 77static void i915_free_hws(struct drm_device *dev) 78{ 79 drm_i915_private_t *dev_priv = dev->dev_private; 80 if (dev_priv->status_page_dmah) { 81 drm_pci_free(dev, dev_priv->status_page_dmah); 82 dev_priv->status_page_dmah = NULL; 83 } 84 85 if (dev_priv->status_gfx_addr) { 86 dev_priv->status_gfx_addr = 0; 87 drm_core_ioremapfree(&dev_priv->hws_map, dev); 88 } 89 90 /* Need to rewrite hardware status page */ 91 I915_WRITE(HWS_PGA, 0x1ffff000); 92} 93 94void i915_kernel_lost_context(struct drm_device * dev) 95{ 96 drm_i915_private_t *dev_priv = dev->dev_private; 97 struct drm_i915_master_private *master_priv; 98 struct intel_ring_buffer *ring = &dev_priv->render_ring; 99 100 /* 101 * We should never lose context on the ring with modesetting 102 * as we don't expose it to userspace 103 */ 104 if (drm_core_check_feature(dev, DRIVER_MODESET)) 105 return; 106 107 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 108 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 109 ring->space = ring->head - (ring->tail + 8); 110 if (ring->space < 0) 111 ring->space += ring->size; 112 113 if (!dev->primary->master) 114 return; 115 116 master_priv = dev->primary->master->driver_priv; 117 if (ring->head == ring->tail && master_priv->sarea_priv) 118 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 119} 120 121static int i915_dma_cleanup(struct drm_device * dev) 122{ 123 drm_i915_private_t *dev_priv = dev->dev_private; 124 /* Make sure interrupts are disabled here because the uninstall ioctl 125 * may not have been called from userspace and after dev_private 126 * is freed, it's too late. 127 */ 128 if (dev->irq_enabled) 129 drm_irq_uninstall(dev); 130 131 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); 132 133 /* Clear the HWS virtual address at teardown */ 134 if (I915_NEED_GFX_HWS(dev)) 135 i915_free_hws(dev); 136 137 return 0; 138} 139 140static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) 141{ 142 drm_i915_private_t *dev_priv = dev->dev_private; 143 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 144 145 master_priv->sarea = drm_getsarea(dev); 146 if (master_priv->sarea) { 147 master_priv->sarea_priv = (drm_i915_sarea_t *) 148 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); 149 } else { 150 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); 151 } 152 153 if (init->ring_size != 0) { 154 if (dev_priv->render_ring.gem_object != NULL) { 155 i915_dma_cleanup(dev); 156 DRM_ERROR("Client tried to initialize ringbuffer in " 157 "GEM mode\n"); 158 return -EINVAL; 159 } 160 161 dev_priv->render_ring.size = init->ring_size; 162 163 dev_priv->render_ring.map.offset = init->ring_start; 164 dev_priv->render_ring.map.size = init->ring_size; 165 dev_priv->render_ring.map.type = 0; 166 dev_priv->render_ring.map.flags = 0; 167 dev_priv->render_ring.map.mtrr = 0; 168 169 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev); 170 171 if (dev_priv->render_ring.map.handle == NULL) { 172 i915_dma_cleanup(dev); 173 DRM_ERROR("can not ioremap virtual address for" 174 " ring buffer\n"); 175 return -ENOMEM; 176 } 177 } 178 179 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle; 180 181 dev_priv->cpp = init->cpp; 182 dev_priv->back_offset = init->back_offset; 183 dev_priv->front_offset = init->front_offset; 184 dev_priv->current_page = 0; 185 if (master_priv->sarea_priv) 186 master_priv->sarea_priv->pf_current_page = 0; 187 188 /* Allow hardware batchbuffers unless told otherwise. 189 */ 190 dev_priv->allow_batchbuffer = 1; 191 192 return 0; 193} 194 195static int i915_dma_resume(struct drm_device * dev) 196{ 197 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 198 199 struct intel_ring_buffer *ring; 200 DRM_DEBUG_DRIVER("%s\n", __func__); 201 202 ring = &dev_priv->render_ring; 203 204 if (ring->map.handle == NULL) { 205 DRM_ERROR("can not ioremap virtual address for" 206 " ring buffer\n"); 207 return -ENOMEM; 208 } 209 210 /* Program Hardware Status Page */ 211 if (!ring->status_page.page_addr) { 212 DRM_ERROR("Can not find hardware status page\n"); 213 return -EINVAL; 214 } 215 DRM_DEBUG_DRIVER("hw status page @ %p\n", 216 ring->status_page.page_addr); 217 if (ring->status_page.gfx_addr != 0) 218 ring->setup_status_page(dev, ring); 219 else 220 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 221 222 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 223 224 return 0; 225} 226 227static int i915_dma_init(struct drm_device *dev, void *data, 228 struct drm_file *file_priv) 229{ 230 drm_i915_init_t *init = data; 231 int retcode = 0; 232 233 switch (init->func) { 234 case I915_INIT_DMA: 235 retcode = i915_initialize(dev, init); 236 break; 237 case I915_CLEANUP_DMA: 238 retcode = i915_dma_cleanup(dev); 239 break; 240 case I915_RESUME_DMA: 241 retcode = i915_dma_resume(dev); 242 break; 243 default: 244 retcode = -EINVAL; 245 break; 246 } 247 248 return retcode; 249} 250 251/* Implement basically the same security restrictions as hardware does 252 * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 253 * 254 * Most of the calculations below involve calculating the size of a 255 * particular instruction. It's important to get the size right as 256 * that tells us where the next instruction to check is. Any illegal 257 * instruction detected will be given a size of zero, which is a 258 * signal to abort the rest of the buffer. 259 */ 260static int do_validate_cmd(int cmd) 261{ 262 switch (((cmd >> 29) & 0x7)) { 263 case 0x0: 264 switch ((cmd >> 23) & 0x3f) { 265 case 0x0: 266 return 1; /* MI_NOOP */ 267 case 0x4: 268 return 1; /* MI_FLUSH */ 269 default: 270 return 0; /* disallow everything else */ 271 } 272 break; 273 case 0x1: 274 return 0; /* reserved */ 275 case 0x2: 276 return (cmd & 0xff) + 2; /* 2d commands */ 277 case 0x3: 278 if (((cmd >> 24) & 0x1f) <= 0x18) 279 return 1; 280 281 switch ((cmd >> 24) & 0x1f) { 282 case 0x1c: 283 return 1; 284 case 0x1d: 285 switch ((cmd >> 16) & 0xff) { 286 case 0x3: 287 return (cmd & 0x1f) + 2; 288 case 0x4: 289 return (cmd & 0xf) + 2; 290 default: 291 return (cmd & 0xffff) + 2; 292 } 293 case 0x1e: 294 if (cmd & (1 << 23)) 295 return (cmd & 0xffff) + 1; 296 else 297 return 1; 298 case 0x1f: 299 if ((cmd & (1 << 23)) == 0) /* inline vertices */ 300 return (cmd & 0x1ffff) + 2; 301 else if (cmd & (1 << 17)) /* indirect random */ 302 if ((cmd & 0xffff) == 0) 303 return 0; /* unknown length, too hard */ 304 else 305 return (((cmd & 0xffff) + 1) / 2) + 1; 306 else 307 return 2; /* indirect sequential */ 308 default: 309 return 0; 310 } 311 default: 312 return 0; 313 } 314 315 return 0; 316} 317 318static int validate_cmd(int cmd) 319{ 320 int ret = do_validate_cmd(cmd); 321 322/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 323 324 return ret; 325} 326 327static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) 328{ 329 drm_i915_private_t *dev_priv = dev->dev_private; 330 int i; 331 332 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8) 333 return -EINVAL; 334 335 BEGIN_LP_RING((dwords+1)&~1); 336 337 for (i = 0; i < dwords;) { 338 int cmd, sz; 339 340 cmd = buffer[i]; 341 342 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 343 return -EINVAL; 344 345 OUT_RING(cmd); 346 347 while (++i, --sz) { 348 OUT_RING(buffer[i]); 349 } 350 } 351 352 if (dwords & 1) 353 OUT_RING(0); 354 355 ADVANCE_LP_RING(); 356 357 return 0; 358} 359 360int 361i915_emit_box(struct drm_device *dev, 362 struct drm_clip_rect *boxes, 363 int i, int DR1, int DR4) 364{ 365 struct drm_clip_rect box = boxes[i]; 366 367 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { 368 DRM_ERROR("Bad box %d,%d..%d,%d\n", 369 box.x1, box.y1, box.x2, box.y2); 370 return -EINVAL; 371 } 372 373 if (IS_I965G(dev)) { 374 BEGIN_LP_RING(4); 375 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 376 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 377 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 378 OUT_RING(DR4); 379 ADVANCE_LP_RING(); 380 } else { 381 BEGIN_LP_RING(6); 382 OUT_RING(GFX_OP_DRAWRECT_INFO); 383 OUT_RING(DR1); 384 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 385 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 386 OUT_RING(DR4); 387 OUT_RING(0); 388 ADVANCE_LP_RING(); 389 } 390 391 return 0; 392} 393 394/* XXX: Emitting the counter should really be moved to part of the IRQ 395 * emit. For now, do it in both places: 396 */ 397 398static void i915_emit_breadcrumb(struct drm_device *dev) 399{ 400 drm_i915_private_t *dev_priv = dev->dev_private; 401 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 402 403 dev_priv->counter++; 404 if (dev_priv->counter > 0x7FFFFFFFUL) 405 dev_priv->counter = 0; 406 if (master_priv->sarea_priv) 407 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 408 409 BEGIN_LP_RING(4); 410 OUT_RING(MI_STORE_DWORD_INDEX); 411 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 412 OUT_RING(dev_priv->counter); 413 OUT_RING(0); 414 ADVANCE_LP_RING(); 415} 416 417static int i915_dispatch_cmdbuffer(struct drm_device * dev, 418 drm_i915_cmdbuffer_t *cmd, 419 struct drm_clip_rect *cliprects, 420 void *cmdbuf) 421{ 422 int nbox = cmd->num_cliprects; 423 int i = 0, count, ret; 424 425 if (cmd->sz & 0x3) { 426 DRM_ERROR("alignment"); 427 return -EINVAL; 428 } 429 430 i915_kernel_lost_context(dev); 431 432 count = nbox ? nbox : 1; 433 434 for (i = 0; i < count; i++) { 435 if (i < nbox) { 436 ret = i915_emit_box(dev, cliprects, i, 437 cmd->DR1, cmd->DR4); 438 if (ret) 439 return ret; 440 } 441 442 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); 443 if (ret) 444 return ret; 445 } 446 447 i915_emit_breadcrumb(dev); 448 return 0; 449} 450 451static int i915_dispatch_batchbuffer(struct drm_device * dev, 452 drm_i915_batchbuffer_t * batch, 453 struct drm_clip_rect *cliprects) 454{ 455 int nbox = batch->num_cliprects; 456 int i = 0, count; 457 458 if ((batch->start | batch->used) & 0x7) { 459 DRM_ERROR("alignment"); 460 return -EINVAL; 461 } 462 463 i915_kernel_lost_context(dev); 464 465 count = nbox ? nbox : 1; 466 467 for (i = 0; i < count; i++) { 468 if (i < nbox) { 469 int ret = i915_emit_box(dev, cliprects, i, 470 batch->DR1, batch->DR4); 471 if (ret) 472 return ret; 473 } 474 475 if (!IS_I830(dev) && !IS_845G(dev)) { 476 BEGIN_LP_RING(2); 477 if (IS_I965G(dev)) { 478 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); 479 OUT_RING(batch->start); 480 } else { 481 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 482 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 483 } 484 ADVANCE_LP_RING(); 485 } else { 486 BEGIN_LP_RING(4); 487 OUT_RING(MI_BATCH_BUFFER); 488 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 489 OUT_RING(batch->start + batch->used - 4); 490 OUT_RING(0); 491 ADVANCE_LP_RING(); 492 } 493 } 494 495 i915_emit_breadcrumb(dev); 496 497 return 0; 498} 499 500static int i915_dispatch_flip(struct drm_device * dev) 501{ 502 drm_i915_private_t *dev_priv = dev->dev_private; 503 struct drm_i915_master_private *master_priv = 504 dev->primary->master->driver_priv; 505 506 if (!master_priv->sarea_priv) 507 return -EINVAL; 508 509 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", 510 __func__, 511 dev_priv->current_page, 512 master_priv->sarea_priv->pf_current_page); 513 514 i915_kernel_lost_context(dev); 515 516 BEGIN_LP_RING(2); 517 OUT_RING(MI_FLUSH | MI_READ_FLUSH); 518 OUT_RING(0); 519 ADVANCE_LP_RING(); 520 521 BEGIN_LP_RING(6); 522 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); 523 OUT_RING(0); 524 if (dev_priv->current_page == 0) { 525 OUT_RING(dev_priv->back_offset); 526 dev_priv->current_page = 1; 527 } else { 528 OUT_RING(dev_priv->front_offset); 529 dev_priv->current_page = 0; 530 } 531 OUT_RING(0); 532 ADVANCE_LP_RING(); 533 534 BEGIN_LP_RING(2); 535 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); 536 OUT_RING(0); 537 ADVANCE_LP_RING(); 538 539 master_priv->sarea_priv->last_enqueue = dev_priv->counter++; 540 541 BEGIN_LP_RING(4); 542 OUT_RING(MI_STORE_DWORD_INDEX); 543 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 544 OUT_RING(dev_priv->counter); 545 OUT_RING(0); 546 ADVANCE_LP_RING(); 547 548 master_priv->sarea_priv->pf_current_page = dev_priv->current_page; 549 return 0; 550} 551 552static int i915_quiescent(struct drm_device * dev) 553{ 554 drm_i915_private_t *dev_priv = dev->dev_private; 555 556 i915_kernel_lost_context(dev); 557 return intel_wait_ring_buffer(dev, &dev_priv->render_ring, 558 dev_priv->render_ring.size - 8); 559} 560 561static int i915_flush_ioctl(struct drm_device *dev, void *data, 562 struct drm_file *file_priv) 563{ 564 int ret; 565 566 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 567 568 mutex_lock(&dev->struct_mutex); 569 ret = i915_quiescent(dev); 570 mutex_unlock(&dev->struct_mutex); 571 572 return ret; 573} 574 575static int i915_batchbuffer(struct drm_device *dev, void *data, 576 struct drm_file *file_priv) 577{ 578 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 579 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 580 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 581 master_priv->sarea_priv; 582 drm_i915_batchbuffer_t *batch = data; 583 int ret; 584 struct drm_clip_rect *cliprects = NULL; 585 586 if (!dev_priv->allow_batchbuffer) { 587 DRM_ERROR("Batchbuffer ioctl disabled\n"); 588 return -EINVAL; 589 } 590 591 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", 592 batch->start, batch->used, batch->num_cliprects); 593 594 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 595 596 if (batch->num_cliprects < 0) 597 return -EINVAL; 598 599 if (batch->num_cliprects) { 600 cliprects = kcalloc(batch->num_cliprects, 601 sizeof(struct drm_clip_rect), 602 GFP_KERNEL); 603 if (cliprects == NULL) 604 return -ENOMEM; 605 606 ret = copy_from_user(cliprects, batch->cliprects, 607 batch->num_cliprects * 608 sizeof(struct drm_clip_rect)); 609 if (ret != 0) 610 goto fail_free; 611 } 612 613 mutex_lock(&dev->struct_mutex); 614 ret = i915_dispatch_batchbuffer(dev, batch, cliprects); 615 mutex_unlock(&dev->struct_mutex); 616 617 if (sarea_priv) 618 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 619 620fail_free: 621 kfree(cliprects); 622 623 return ret; 624} 625 626static int i915_cmdbuffer(struct drm_device *dev, void *data, 627 struct drm_file *file_priv) 628{ 629 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 630 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 631 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 632 master_priv->sarea_priv; 633 drm_i915_cmdbuffer_t *cmdbuf = data; 634 struct drm_clip_rect *cliprects = NULL; 635 void *batch_data; 636 int ret; 637 638 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 639 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 640 641 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 642 643 if (cmdbuf->num_cliprects < 0) 644 return -EINVAL; 645 646 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); 647 if (batch_data == NULL) 648 return -ENOMEM; 649 650 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); 651 if (ret != 0) 652 goto fail_batch_free; 653 654 if (cmdbuf->num_cliprects) { 655 cliprects = kcalloc(cmdbuf->num_cliprects, 656 sizeof(struct drm_clip_rect), GFP_KERNEL); 657 if (cliprects == NULL) { 658 ret = -ENOMEM; 659 goto fail_batch_free; 660 } 661 662 ret = copy_from_user(cliprects, cmdbuf->cliprects, 663 cmdbuf->num_cliprects * 664 sizeof(struct drm_clip_rect)); 665 if (ret != 0) 666 goto fail_clip_free; 667 } 668 669 mutex_lock(&dev->struct_mutex); 670 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); 671 mutex_unlock(&dev->struct_mutex); 672 if (ret) { 673 DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 674 goto fail_clip_free; 675 } 676 677 if (sarea_priv) 678 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 679 680fail_clip_free: 681 kfree(cliprects); 682fail_batch_free: 683 kfree(batch_data); 684 685 return ret; 686} 687 688static int i915_flip_bufs(struct drm_device *dev, void *data, 689 struct drm_file *file_priv) 690{ 691 int ret; 692 693 DRM_DEBUG_DRIVER("%s\n", __func__); 694 695 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 696 697 mutex_lock(&dev->struct_mutex); 698 ret = i915_dispatch_flip(dev); 699 mutex_unlock(&dev->struct_mutex); 700 701 return ret; 702} 703 704static int i915_getparam(struct drm_device *dev, void *data, 705 struct drm_file *file_priv) 706{ 707 drm_i915_private_t *dev_priv = dev->dev_private; 708 drm_i915_getparam_t *param = data; 709 int value; 710 711 if (!dev_priv) { 712 DRM_ERROR("called with no initialization\n"); 713 return -EINVAL; 714 } 715 716 switch (param->param) { 717 case I915_PARAM_IRQ_ACTIVE: 718 value = dev->pdev->irq ? 1 : 0; 719 break; 720 case I915_PARAM_ALLOW_BATCHBUFFER: 721 value = dev_priv->allow_batchbuffer ? 1 : 0; 722 break; 723 case I915_PARAM_LAST_DISPATCH: 724 value = READ_BREADCRUMB(dev_priv); 725 break; 726 case I915_PARAM_CHIPSET_ID: 727 value = dev->pci_device; 728 break; 729 case I915_PARAM_HAS_GEM: 730 value = dev_priv->has_gem; 731 break; 732 case I915_PARAM_NUM_FENCES_AVAIL: 733 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 734 break; 735 case I915_PARAM_HAS_OVERLAY: 736 value = dev_priv->overlay ? 1 : 0; 737 break; 738 case I915_PARAM_HAS_PAGEFLIPPING: 739 value = 1; 740 break; 741 case I915_PARAM_HAS_EXECBUF2: 742 /* depends on GEM */ 743 value = dev_priv->has_gem; 744 break; 745 default: 746 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 747 param->param); 748 return -EINVAL; 749 } 750 751 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 752 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 753 return -EFAULT; 754 } 755 756 return 0; 757} 758 759static int i915_setparam(struct drm_device *dev, void *data, 760 struct drm_file *file_priv) 761{ 762 drm_i915_private_t *dev_priv = dev->dev_private; 763 drm_i915_setparam_t *param = data; 764 765 if (!dev_priv) { 766 DRM_ERROR("called with no initialization\n"); 767 return -EINVAL; 768 } 769 770 switch (param->param) { 771 case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 772 break; 773 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 774 dev_priv->tex_lru_log_granularity = param->value; 775 break; 776 case I915_SETPARAM_ALLOW_BATCHBUFFER: 777 dev_priv->allow_batchbuffer = param->value; 778 break; 779 case I915_SETPARAM_NUM_USED_FENCES: 780 if (param->value > dev_priv->num_fence_regs || 781 param->value < 0) 782 return -EINVAL; 783 /* Userspace can use first N regs */ 784 dev_priv->fence_reg_start = param->value; 785 break; 786 default: 787 DRM_DEBUG_DRIVER("unknown parameter %d\n", 788 param->param); 789 return -EINVAL; 790 } 791 792 return 0; 793} 794 795static int i915_set_status_page(struct drm_device *dev, void *data, 796 struct drm_file *file_priv) 797{ 798 drm_i915_private_t *dev_priv = dev->dev_private; 799 drm_i915_hws_addr_t *hws = data; 800 struct intel_ring_buffer *ring = &dev_priv->render_ring; 801 802 if (!I915_NEED_GFX_HWS(dev)) 803 return -EINVAL; 804 805 if (!dev_priv) { 806 DRM_ERROR("called with no initialization\n"); 807 return -EINVAL; 808 } 809 810 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 811 WARN(1, "tried to set status page when mode setting active\n"); 812 return 0; 813 } 814 815 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); 816 817 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); 818 819 dev_priv->hws_map.offset = dev->agp->base + hws->addr; 820 dev_priv->hws_map.size = 4*1024; 821 dev_priv->hws_map.type = 0; 822 dev_priv->hws_map.flags = 0; 823 dev_priv->hws_map.mtrr = 0; 824 825 drm_core_ioremap_wc(&dev_priv->hws_map, dev); 826 if (dev_priv->hws_map.handle == NULL) { 827 i915_dma_cleanup(dev); 828 dev_priv->status_gfx_addr = 0; 829 DRM_ERROR("can not ioremap virtual address for" 830 " G33 hw status page\n"); 831 return -ENOMEM; 832 } 833 ring->status_page.page_addr = dev_priv->hws_map.handle; 834 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 835 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); 836 837 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", 838 dev_priv->status_gfx_addr); 839 DRM_DEBUG_DRIVER("load hws at %p\n", 840 dev_priv->hw_status_page); 841 return 0; 842} 843 844static int i915_get_bridge_dev(struct drm_device *dev) 845{ 846 struct drm_i915_private *dev_priv = dev->dev_private; 847 848 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); 849 if (!dev_priv->bridge_dev) { 850 DRM_ERROR("bridge device not found\n"); 851 return -1; 852 } 853 return 0; 854} 855 856#define MCHBAR_I915 0x44 857#define MCHBAR_I965 0x48 858#define MCHBAR_SIZE (4*4096) 859 860#define DEVEN_REG 0x54 861#define DEVEN_MCHBAR_EN (1 << 28) 862 863/* Allocate space for the MCH regs if needed, return nonzero on error */ 864static int 865intel_alloc_mchbar_resource(struct drm_device *dev) 866{ 867 drm_i915_private_t *dev_priv = dev->dev_private; 868 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 869 u32 temp_lo, temp_hi = 0; 870 u64 mchbar_addr; 871 int ret = 0; 872 873 if (IS_I965G(dev)) 874 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 875 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 876 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 877 878 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 879#ifdef CONFIG_PNP 880 if (mchbar_addr && 881 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 882 ret = 0; 883 goto out; 884 } 885#endif 886 887 /* Get some space for it */ 888 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, 889 MCHBAR_SIZE, MCHBAR_SIZE, 890 PCIBIOS_MIN_MEM, 891 0, pcibios_align_resource, 892 dev_priv->bridge_dev); 893 if (ret) { 894 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); 895 dev_priv->mch_res.start = 0; 896 goto out; 897 } 898 899 if (IS_I965G(dev)) 900 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 901 upper_32_bits(dev_priv->mch_res.start)); 902 903 pci_write_config_dword(dev_priv->bridge_dev, reg, 904 lower_32_bits(dev_priv->mch_res.start)); 905out: 906 return ret; 907} 908 909/* Setup MCHBAR if possible, return true if we should disable it again */ 910static void 911intel_setup_mchbar(struct drm_device *dev) 912{ 913 drm_i915_private_t *dev_priv = dev->dev_private; 914 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 915 u32 temp; 916 bool enabled; 917 918 dev_priv->mchbar_need_disable = false; 919 920 if (IS_I915G(dev) || IS_I915GM(dev)) { 921 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); 922 enabled = !!(temp & DEVEN_MCHBAR_EN); 923 } else { 924 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 925 enabled = temp & 1; 926 } 927 928 /* If it's already enabled, don't have to do anything */ 929 if (enabled) 930 return; 931 932 if (intel_alloc_mchbar_resource(dev)) 933 return; 934 935 dev_priv->mchbar_need_disable = true; 936 937 /* Space is allocated or reserved, so enable it. */ 938 if (IS_I915G(dev) || IS_I915GM(dev)) { 939 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, 940 temp | DEVEN_MCHBAR_EN); 941 } else { 942 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 943 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 944 } 945} 946 947static void 948intel_teardown_mchbar(struct drm_device *dev) 949{ 950 drm_i915_private_t *dev_priv = dev->dev_private; 951 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 952 u32 temp; 953 954 if (dev_priv->mchbar_need_disable) { 955 if (IS_I915G(dev) || IS_I915GM(dev)) { 956 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); 957 temp &= ~DEVEN_MCHBAR_EN; 958 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); 959 } else { 960 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 961 temp &= ~1; 962 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); 963 } 964 } 965 966 if (dev_priv->mch_res.start) 967 release_resource(&dev_priv->mch_res); 968} 969 970/** 971 * i915_probe_agp - get AGP bootup configuration 972 * @pdev: PCI device 973 * @aperture_size: returns AGP aperture configured size 974 * @preallocated_size: returns size of BIOS preallocated AGP space 975 * 976 * Since Intel integrated graphics are UMA, the BIOS has to set aside 977 * some RAM for the framebuffer at early boot. This code figures out 978 * how much was set aside so we can use it for our own purposes. 979 */ 980static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 981 uint32_t *preallocated_size, 982 uint32_t *start) 983{ 984 struct drm_i915_private *dev_priv = dev->dev_private; 985 u16 tmp = 0; 986 unsigned long overhead; 987 unsigned long stolen; 988 989 /* Get the fb aperture size and "stolen" memory amount. */ 990 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); 991 992 *aperture_size = 1024 * 1024; 993 *preallocated_size = 1024 * 1024; 994 995 switch (dev->pdev->device) { 996 case PCI_DEVICE_ID_INTEL_82830_CGC: 997 case PCI_DEVICE_ID_INTEL_82845G_IG: 998 case PCI_DEVICE_ID_INTEL_82855GM_IG: 999 case PCI_DEVICE_ID_INTEL_82865_IG: 1000 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) 1001 *aperture_size *= 64; 1002 else 1003 *aperture_size *= 128; 1004 break; 1005 default: 1006 /* 9xx supports large sizes, just look at the length */ 1007 *aperture_size = pci_resource_len(dev->pdev, 2); 1008 break; 1009 } 1010 1011 /* 1012 * Some of the preallocated space is taken by the GTT 1013 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 1014 */ 1015 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) 1016 overhead = 4096; 1017 else 1018 overhead = (*aperture_size / 1024) + 4096; 1019 1020 if (IS_GEN6(dev)) { 1021 /* SNB has memory control reg at 0x50.w */ 1022 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp); 1023 1024 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) { 1025 case INTEL_855_GMCH_GMS_DISABLED: 1026 DRM_ERROR("video memory is disabled\n"); 1027 return -1; 1028 case SNB_GMCH_GMS_STOLEN_32M: 1029 stolen = 32 * 1024 * 1024; 1030 break; 1031 case SNB_GMCH_GMS_STOLEN_64M: 1032 stolen = 64 * 1024 * 1024; 1033 break; 1034 case SNB_GMCH_GMS_STOLEN_96M: 1035 stolen = 96 * 1024 * 1024; 1036 break; 1037 case SNB_GMCH_GMS_STOLEN_128M: 1038 stolen = 128 * 1024 * 1024; 1039 break; 1040 case SNB_GMCH_GMS_STOLEN_160M: 1041 stolen = 160 * 1024 * 1024; 1042 break; 1043 case SNB_GMCH_GMS_STOLEN_192M: 1044 stolen = 192 * 1024 * 1024; 1045 break; 1046 case SNB_GMCH_GMS_STOLEN_224M: 1047 stolen = 224 * 1024 * 1024; 1048 break; 1049 case SNB_GMCH_GMS_STOLEN_256M: 1050 stolen = 256 * 1024 * 1024; 1051 break; 1052 case SNB_GMCH_GMS_STOLEN_288M: 1053 stolen = 288 * 1024 * 1024; 1054 break; 1055 case SNB_GMCH_GMS_STOLEN_320M: 1056 stolen = 320 * 1024 * 1024; 1057 break; 1058 case SNB_GMCH_GMS_STOLEN_352M: 1059 stolen = 352 * 1024 * 1024; 1060 break; 1061 case SNB_GMCH_GMS_STOLEN_384M: 1062 stolen = 384 * 1024 * 1024; 1063 break; 1064 case SNB_GMCH_GMS_STOLEN_416M: 1065 stolen = 416 * 1024 * 1024; 1066 break; 1067 case SNB_GMCH_GMS_STOLEN_448M: 1068 stolen = 448 * 1024 * 1024; 1069 break; 1070 case SNB_GMCH_GMS_STOLEN_480M: 1071 stolen = 480 * 1024 * 1024; 1072 break; 1073 case SNB_GMCH_GMS_STOLEN_512M: 1074 stolen = 512 * 1024 * 1024; 1075 break; 1076 default: 1077 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", 1078 tmp & SNB_GMCH_GMS_STOLEN_MASK); 1079 return -1; 1080 } 1081 } else { 1082 switch (tmp & INTEL_GMCH_GMS_MASK) { 1083 case INTEL_855_GMCH_GMS_DISABLED: 1084 DRM_ERROR("video memory is disabled\n"); 1085 return -1; 1086 case INTEL_855_GMCH_GMS_STOLEN_1M: 1087 stolen = 1 * 1024 * 1024; 1088 break; 1089 case INTEL_855_GMCH_GMS_STOLEN_4M: 1090 stolen = 4 * 1024 * 1024; 1091 break; 1092 case INTEL_855_GMCH_GMS_STOLEN_8M: 1093 stolen = 8 * 1024 * 1024; 1094 break; 1095 case INTEL_855_GMCH_GMS_STOLEN_16M: 1096 stolen = 16 * 1024 * 1024; 1097 break; 1098 case INTEL_855_GMCH_GMS_STOLEN_32M: 1099 stolen = 32 * 1024 * 1024; 1100 break; 1101 case INTEL_915G_GMCH_GMS_STOLEN_48M: 1102 stolen = 48 * 1024 * 1024; 1103 break; 1104 case INTEL_915G_GMCH_GMS_STOLEN_64M: 1105 stolen = 64 * 1024 * 1024; 1106 break; 1107 case INTEL_GMCH_GMS_STOLEN_128M: 1108 stolen = 128 * 1024 * 1024; 1109 break; 1110 case INTEL_GMCH_GMS_STOLEN_256M: 1111 stolen = 256 * 1024 * 1024; 1112 break; 1113 case INTEL_GMCH_GMS_STOLEN_96M: 1114 stolen = 96 * 1024 * 1024; 1115 break; 1116 case INTEL_GMCH_GMS_STOLEN_160M: 1117 stolen = 160 * 1024 * 1024; 1118 break; 1119 case INTEL_GMCH_GMS_STOLEN_224M: 1120 stolen = 224 * 1024 * 1024; 1121 break; 1122 case INTEL_GMCH_GMS_STOLEN_352M: 1123 stolen = 352 * 1024 * 1024; 1124 break; 1125 default: 1126 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", 1127 tmp & INTEL_GMCH_GMS_MASK); 1128 return -1; 1129 } 1130 } 1131 1132 *preallocated_size = stolen - overhead; 1133 *start = overhead; 1134 1135 return 0; 1136} 1137 1138#define PTE_ADDRESS_MASK 0xfffff000 1139#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ 1140#define PTE_MAPPING_TYPE_UNCACHED (0 << 1) 1141#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ 1142#define PTE_MAPPING_TYPE_CACHED (3 << 1) 1143#define PTE_MAPPING_TYPE_MASK (3 << 1) 1144#define PTE_VALID (1 << 0) 1145 1146/** 1147 * i915_gtt_to_phys - take a GTT address and turn it into a physical one 1148 * @dev: drm device 1149 * @gtt_addr: address to translate 1150 * 1151 * Some chip functions require allocations from stolen space but need the 1152 * physical address of the memory in question. We use this routine 1153 * to get a physical address suitable for register programming from a given 1154 * GTT address. 1155 */ 1156static unsigned long i915_gtt_to_phys(struct drm_device *dev, 1157 unsigned long gtt_addr) 1158{ 1159 unsigned long *gtt; 1160 unsigned long entry, phys; 1161 int gtt_bar = IS_I9XX(dev) ? 0 : 1; 1162 int gtt_offset, gtt_size; 1163 1164 if (IS_I965G(dev)) { 1165 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { 1166 gtt_offset = 2*1024*1024; 1167 gtt_size = 2*1024*1024; 1168 } else { 1169 gtt_offset = 512*1024; 1170 gtt_size = 512*1024; 1171 } 1172 } else { 1173 gtt_bar = 3; 1174 gtt_offset = 0; 1175 gtt_size = pci_resource_len(dev->pdev, gtt_bar); 1176 } 1177 1178 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, 1179 gtt_size); 1180 if (!gtt) { 1181 DRM_ERROR("ioremap of GTT failed\n"); 1182 return 0; 1183 } 1184 1185 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); 1186 1187 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); 1188 1189 /* Mask out these reserved bits on this hardware. */ 1190 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || 1191 IS_I945G(dev) || IS_I945GM(dev)) { 1192 entry &= ~PTE_ADDRESS_MASK_HIGH; 1193 } 1194 1195 /* If it's not a mapping type we know, then bail. */ 1196 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && 1197 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { 1198 iounmap(gtt); 1199 return 0; 1200 } 1201 1202 if (!(entry & PTE_VALID)) { 1203 DRM_ERROR("bad GTT entry in stolen space\n"); 1204 iounmap(gtt); 1205 return 0; 1206 } 1207 1208 iounmap(gtt); 1209 1210 phys =(entry & PTE_ADDRESS_MASK) | 1211 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); 1212 1213 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); 1214 1215 return phys; 1216} 1217 1218static void i915_warn_stolen(struct drm_device *dev) 1219{ 1220 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); 1221 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); 1222} 1223 1224static void i915_setup_compression(struct drm_device *dev, int size) 1225{ 1226 struct drm_i915_private *dev_priv = dev->dev_private; 1227 struct drm_mm_node *compressed_fb, *compressed_llb; 1228 unsigned long cfb_base; 1229 unsigned long ll_base = 0; 1230 1231 /* Leave 1M for line length buffer & misc. */ 1232 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); 1233 if (!compressed_fb) { 1234 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 1235 i915_warn_stolen(dev); 1236 return; 1237 } 1238 1239 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); 1240 if (!compressed_fb) { 1241 i915_warn_stolen(dev); 1242 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 1243 return; 1244 } 1245 1246 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); 1247 if (!cfb_base) { 1248 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1249 drm_mm_put_block(compressed_fb); 1250 } 1251 1252 if (!IS_GM45(dev)) { 1253 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 1254 4096, 0); 1255 if (!compressed_llb) { 1256 i915_warn_stolen(dev); 1257 return; 1258 } 1259 1260 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); 1261 if (!compressed_llb) { 1262 i915_warn_stolen(dev); 1263 return; 1264 } 1265 1266 ll_base = i915_gtt_to_phys(dev, compressed_llb->start); 1267 if (!ll_base) { 1268 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1269 drm_mm_put_block(compressed_fb); 1270 drm_mm_put_block(compressed_llb); 1271 } 1272 } 1273 1274 dev_priv->cfb_size = size; 1275 1276 intel_disable_fbc(dev); 1277 dev_priv->compressed_fb = compressed_fb; 1278 1279 if (IS_GM45(dev)) { 1280 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); 1281 } else { 1282 I915_WRITE(FBC_CFB_BASE, cfb_base); 1283 I915_WRITE(FBC_LL_BASE, ll_base); 1284 dev_priv->compressed_llb = compressed_llb; 1285 } 1286 1287 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, 1288 ll_base, size >> 20); 1289} 1290 1291static void i915_cleanup_compression(struct drm_device *dev) 1292{ 1293 struct drm_i915_private *dev_priv = dev->dev_private; 1294 1295 drm_mm_put_block(dev_priv->compressed_fb); 1296 if (!IS_GM45(dev)) 1297 drm_mm_put_block(dev_priv->compressed_llb); 1298} 1299 1300/* true = enable decode, false = disable decoder */ 1301static unsigned int i915_vga_set_decode(void *cookie, bool state) 1302{ 1303 struct drm_device *dev = cookie; 1304 1305 intel_modeset_vga_set_state(dev, state); 1306 if (state) 1307 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1308 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1309 else 1310 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1311} 1312 1313static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1314{ 1315 struct drm_device *dev = pci_get_drvdata(pdev); 1316 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 1317 if (state == VGA_SWITCHEROO_ON) { 1318 printk(KERN_INFO "i915: switched off\n"); 1319 /* i915 resume handler doesn't set to D0 */ 1320 pci_set_power_state(dev->pdev, PCI_D0); 1321 i915_resume(dev); 1322 } else { 1323 printk(KERN_ERR "i915: switched off\n"); 1324 i915_suspend(dev, pmm); 1325 } 1326} 1327 1328static bool i915_switcheroo_can_switch(struct pci_dev *pdev) 1329{ 1330 struct drm_device *dev = pci_get_drvdata(pdev); 1331 bool can_switch; 1332 1333 spin_lock(&dev->count_lock); 1334 can_switch = (dev->open_count == 0); 1335 spin_unlock(&dev->count_lock); 1336 return can_switch; 1337} 1338 1339static int i915_load_modeset_init(struct drm_device *dev, 1340 unsigned long prealloc_start, 1341 unsigned long prealloc_size, 1342 unsigned long agp_size) 1343{ 1344 struct drm_i915_private *dev_priv = dev->dev_private; 1345 int fb_bar = IS_I9XX(dev) ? 2 : 0; 1346 int ret = 0; 1347 1348 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & 1349 0xff000000; 1350 1351 /* Basic memrange allocator for stolen space (aka vram) */ 1352 drm_mm_init(&dev_priv->vram, 0, prealloc_size); 1353 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); 1354 1355 /* We're off and running w/KMS */ 1356 dev_priv->mm.suspended = 0; 1357 1358 /* Let GEM Manage from end of prealloc space to end of aperture. 1359 * 1360 * However, leave one page at the end still bound to the scratch page. 1361 * There are a number of places where the hardware apparently 1362 * prefetches past the end of the object, and we've seen multiple 1363 * hangs with the GPU head pointer stuck in a batchbuffer bound 1364 * at the last page of the aperture. One page should be enough to 1365 * keep any prefetching inside of the aperture. 1366 */ 1367 i915_gem_do_init(dev, prealloc_size, agp_size - 4096); 1368 1369 mutex_lock(&dev->struct_mutex); 1370 ret = i915_gem_init_ringbuffer(dev); 1371 mutex_unlock(&dev->struct_mutex); 1372 if (ret) 1373 goto out; 1374 1375 /* Try to set up FBC with a reasonable compressed buffer size */ 1376 if (I915_HAS_FBC(dev) && i915_powersave) { 1377 int cfb_size; 1378 1379 /* Try to get an 8M buffer... */ 1380 if (prealloc_size > (9*1024*1024)) 1381 cfb_size = 8*1024*1024; 1382 else /* fall back to 7/8 of the stolen space */ 1383 cfb_size = prealloc_size * 7 / 8; 1384 i915_setup_compression(dev, cfb_size); 1385 } 1386 1387 /* Allow hardware batchbuffers unless told otherwise. 1388 */ 1389 dev_priv->allow_batchbuffer = 1; 1390 1391 ret = intel_init_bios(dev); 1392 if (ret) 1393 DRM_INFO("failed to find VBIOS tables\n"); 1394 1395 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1396 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1397 if (ret) 1398 goto destroy_ringbuffer; 1399 1400 ret = vga_switcheroo_register_client(dev->pdev, 1401 i915_switcheroo_set_state, 1402 i915_switcheroo_can_switch); 1403 if (ret) 1404 goto destroy_ringbuffer; 1405 1406 intel_modeset_init(dev); 1407 1408 ret = drm_irq_install(dev); 1409 if (ret) 1410 goto destroy_ringbuffer; 1411 1412 /* Always safe in the mode setting case. */ 1413 /* FIXME: do pre/post-mode set stuff in core KMS code */ 1414 dev->vblank_disable_allowed = 1; 1415 1416 /* 1417 * Initialize the hardware status page IRQ location. 1418 */ 1419 1420 I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); 1421 1422 intel_fbdev_init(dev); 1423 drm_kms_helper_poll_init(dev); 1424 return 0; 1425 1426destroy_ringbuffer: 1427 mutex_lock(&dev->struct_mutex); 1428 i915_gem_cleanup_ringbuffer(dev); 1429 mutex_unlock(&dev->struct_mutex); 1430out: 1431 return ret; 1432} 1433 1434int i915_master_create(struct drm_device *dev, struct drm_master *master) 1435{ 1436 struct drm_i915_master_private *master_priv; 1437 1438 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); 1439 if (!master_priv) 1440 return -ENOMEM; 1441 1442 master->driver_priv = master_priv; 1443 return 0; 1444} 1445 1446void i915_master_destroy(struct drm_device *dev, struct drm_master *master) 1447{ 1448 struct drm_i915_master_private *master_priv = master->driver_priv; 1449 1450 if (!master_priv) 1451 return; 1452 1453 kfree(master_priv); 1454 1455 master->driver_priv = NULL; 1456} 1457 1458static void i915_get_mem_freq(struct drm_device *dev) 1459{ 1460 drm_i915_private_t *dev_priv = dev->dev_private; 1461 u32 tmp; 1462 1463 if (!IS_PINEVIEW(dev)) 1464 return; 1465 1466 tmp = I915_READ(CLKCFG); 1467 1468 switch (tmp & CLKCFG_FSB_MASK) { 1469 case CLKCFG_FSB_533: 1470 dev_priv->fsb_freq = 533; /* 133*4 */ 1471 break; 1472 case CLKCFG_FSB_800: 1473 dev_priv->fsb_freq = 800; /* 200*4 */ 1474 break; 1475 case CLKCFG_FSB_667: 1476 dev_priv->fsb_freq = 667; /* 167*4 */ 1477 break; 1478 case CLKCFG_FSB_400: 1479 dev_priv->fsb_freq = 400; /* 100*4 */ 1480 break; 1481 } 1482 1483 switch (tmp & CLKCFG_MEM_MASK) { 1484 case CLKCFG_MEM_533: 1485 dev_priv->mem_freq = 533; 1486 break; 1487 case CLKCFG_MEM_667: 1488 dev_priv->mem_freq = 667; 1489 break; 1490 case CLKCFG_MEM_800: 1491 dev_priv->mem_freq = 800; 1492 break; 1493 } 1494} 1495 1496/** 1497 * i915_driver_load - setup chip and create an initial config 1498 * @dev: DRM device 1499 * @flags: startup flags 1500 * 1501 * The driver load routine has to do several things: 1502 * - drive output discovery via intel_modeset_init() 1503 * - initialize the memory manager 1504 * - allocate initial config memory 1505 * - setup the DRM framebuffer with the allocated memory 1506 */ 1507int i915_driver_load(struct drm_device *dev, unsigned long flags) 1508{ 1509 struct drm_i915_private *dev_priv; 1510 resource_size_t base, size; 1511 int ret = 0, mmio_bar; 1512 uint32_t agp_size, prealloc_size, prealloc_start; 1513 1514 /* i915 has 4 more counters */ 1515 dev->counters += 4; 1516 dev->types[6] = _DRM_STAT_IRQ; 1517 dev->types[7] = _DRM_STAT_PRIMARY; 1518 dev->types[8] = _DRM_STAT_SECONDARY; 1519 dev->types[9] = _DRM_STAT_DMA; 1520 1521 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); 1522 if (dev_priv == NULL) 1523 return -ENOMEM; 1524 1525 dev->dev_private = (void *)dev_priv; 1526 dev_priv->dev = dev; 1527 dev_priv->info = (struct intel_device_info *) flags; 1528 1529 /* Add register map (needed for suspend/resume) */ 1530 mmio_bar = IS_I9XX(dev) ? 0 : 1; 1531 base = drm_get_resource_start(dev, mmio_bar); 1532 size = drm_get_resource_len(dev, mmio_bar); 1533 1534 if (i915_get_bridge_dev(dev)) { 1535 ret = -EIO; 1536 goto free_priv; 1537 } 1538 1539 dev_priv->regs = ioremap(base, size); 1540 if (!dev_priv->regs) { 1541 DRM_ERROR("failed to map registers\n"); 1542 ret = -EIO; 1543 goto put_bridge; 1544 } 1545 1546 dev_priv->mm.gtt_mapping = 1547 io_mapping_create_wc(dev->agp->base, 1548 dev->agp->agp_info.aper_size * 1024*1024); 1549 if (dev_priv->mm.gtt_mapping == NULL) { 1550 ret = -EIO; 1551 goto out_rmmap; 1552 } 1553 1554 /* Set up a WC MTRR for non-PAT systems. This is more common than 1555 * one would think, because the kernel disables PAT on first 1556 * generation Core chips because WC PAT gets overridden by a UC 1557 * MTRR if present. Even if a UC MTRR isn't present. 1558 */ 1559 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, 1560 dev->agp->agp_info.aper_size * 1561 1024 * 1024, 1562 MTRR_TYPE_WRCOMB, 1); 1563 if (dev_priv->mm.gtt_mtrr < 0) { 1564 DRM_INFO("MTRR allocation failed. Graphics " 1565 "performance may suffer.\n"); 1566 } 1567 1568 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); 1569 if (ret) 1570 goto out_iomapfree; 1571 1572 dev_priv->wq = create_singlethread_workqueue("i915"); 1573 if (dev_priv->wq == NULL) { 1574 DRM_ERROR("Failed to create our workqueue.\n"); 1575 ret = -ENOMEM; 1576 goto out_iomapfree; 1577 } 1578 1579 /* enable GEM by default */ 1580 dev_priv->has_gem = 1; 1581 1582 if (prealloc_size > agp_size * 3 / 4) { 1583 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " 1584 "memory stolen.\n", 1585 prealloc_size / 1024, agp_size / 1024); 1586 DRM_ERROR("Disabling GEM. (try reducing stolen memory or " 1587 "updating the BIOS to fix).\n"); 1588 dev_priv->has_gem = 0; 1589 } 1590 1591 if (dev_priv->has_gem == 0 && 1592 drm_core_check_feature(dev, DRIVER_MODESET)) { 1593 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n"); 1594 ret = -ENODEV; 1595 goto out_iomapfree; 1596 } 1597 1598 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1599 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1600 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { 1601 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1602 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1603 } 1604 1605 /* Try to make sure MCHBAR is enabled before poking at it */ 1606 intel_setup_mchbar(dev); 1607 1608 i915_gem_load(dev); 1609 1610 /* Init HWS */ 1611 if (!I915_NEED_GFX_HWS(dev)) { 1612 ret = i915_init_phys_hws(dev); 1613 if (ret != 0) 1614 goto out_workqueue_free; 1615 } 1616 1617 i915_get_mem_freq(dev); 1618 1619 /* On the 945G/GM, the chipset reports the MSI capability on the 1620 * integrated graphics even though the support isn't actually there 1621 * according to the published specs. It doesn't appear to function 1622 * correctly in testing on 945G. 1623 * This may be a side effect of MSI having been made available for PEG 1624 * and the registers being closely associated. 1625 * 1626 * According to chipset errata, on the 965GM, MSI interrupts may 1627 * be lost or delayed, but we use them anyways to avoid 1628 * stuck interrupts on some machines. 1629 */ 1630 if (!IS_I945G(dev) && !IS_I945GM(dev)) 1631 pci_enable_msi(dev->pdev); 1632 1633 spin_lock_init(&dev_priv->user_irq_lock); 1634 spin_lock_init(&dev_priv->error_lock); 1635 dev_priv->trace_irq_seqno = 0; 1636 1637 ret = drm_vblank_init(dev, I915_NUM_PIPE); 1638 1639 if (ret) { 1640 (void) i915_driver_unload(dev); 1641 return ret; 1642 } 1643 1644 /* Start out suspended */ 1645 dev_priv->mm.suspended = 1; 1646 1647 intel_detect_pch(dev); 1648 1649 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1650 ret = i915_load_modeset_init(dev, prealloc_start, 1651 prealloc_size, agp_size); 1652 if (ret < 0) { 1653 DRM_ERROR("failed to init modeset\n"); 1654 goto out_workqueue_free; 1655 } 1656 } 1657 1658 /* Must be done after probing outputs */ 1659 intel_opregion_init(dev, 0); 1660 1661 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 1662 (unsigned long) dev); 1663 return 0; 1664 1665out_workqueue_free: 1666 destroy_workqueue(dev_priv->wq); 1667out_iomapfree: 1668 io_mapping_free(dev_priv->mm.gtt_mapping); 1669out_rmmap: 1670 iounmap(dev_priv->regs); 1671put_bridge: 1672 pci_dev_put(dev_priv->bridge_dev); 1673free_priv: 1674 kfree(dev_priv); 1675 return ret; 1676} 1677 1678int i915_driver_unload(struct drm_device *dev) 1679{ 1680 struct drm_i915_private *dev_priv = dev->dev_private; 1681 1682 i915_destroy_error_state(dev); 1683 1684 destroy_workqueue(dev_priv->wq); 1685 del_timer_sync(&dev_priv->hangcheck_timer); 1686 1687 io_mapping_free(dev_priv->mm.gtt_mapping); 1688 if (dev_priv->mm.gtt_mtrr >= 0) { 1689 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, 1690 dev->agp->agp_info.aper_size * 1024 * 1024); 1691 dev_priv->mm.gtt_mtrr = -1; 1692 } 1693 1694 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1695 intel_modeset_cleanup(dev); 1696 1697 /* 1698 * free the memory space allocated for the child device 1699 * config parsed from VBT 1700 */ 1701 if (dev_priv->child_dev && dev_priv->child_dev_num) { 1702 kfree(dev_priv->child_dev); 1703 dev_priv->child_dev = NULL; 1704 dev_priv->child_dev_num = 0; 1705 } 1706 drm_irq_uninstall(dev); 1707 vga_switcheroo_unregister_client(dev->pdev); 1708 vga_client_register(dev->pdev, NULL, NULL, NULL); 1709 } 1710 1711 if (dev->pdev->msi_enabled) 1712 pci_disable_msi(dev->pdev); 1713 1714 if (dev_priv->regs != NULL) 1715 iounmap(dev_priv->regs); 1716 1717 intel_opregion_free(dev, 0); 1718 1719 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1720 i915_gem_free_all_phys_object(dev); 1721 1722 mutex_lock(&dev->struct_mutex); 1723 i915_gem_cleanup_ringbuffer(dev); 1724 mutex_unlock(&dev->struct_mutex); 1725 if (I915_HAS_FBC(dev) && i915_powersave) 1726 i915_cleanup_compression(dev); 1727 drm_mm_takedown(&dev_priv->vram); 1728 i915_gem_lastclose(dev); 1729 1730 intel_cleanup_overlay(dev); 1731 } 1732 1733 intel_teardown_mchbar(dev); 1734 1735 pci_dev_put(dev_priv->bridge_dev); 1736 kfree(dev->dev_private); 1737 1738 return 0; 1739} 1740 1741int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1742{ 1743 struct drm_i915_file_private *i915_file_priv; 1744 1745 DRM_DEBUG_DRIVER("\n"); 1746 i915_file_priv = (struct drm_i915_file_private *) 1747 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); 1748 1749 if (!i915_file_priv) 1750 return -ENOMEM; 1751 1752 file_priv->driver_priv = i915_file_priv; 1753 1754 INIT_LIST_HEAD(&i915_file_priv->mm.request_list); 1755 1756 return 0; 1757} 1758 1759/** 1760 * i915_driver_lastclose - clean up after all DRM clients have exited 1761 * @dev: DRM device 1762 * 1763 * Take care of cleaning up after all DRM clients have exited. In the 1764 * mode setting case, we want to restore the kernel's initial mode (just 1765 * in case the last client left us in a bad state). 1766 * 1767 * Additionally, in the non-mode setting case, we'll tear down the AGP 1768 * and DMA structures, since the kernel won't be using them, and clea 1769 * up any GEM state. 1770 */ 1771void i915_driver_lastclose(struct drm_device * dev) 1772{ 1773 drm_i915_private_t *dev_priv = dev->dev_private; 1774 1775 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { 1776 drm_fb_helper_restore(); 1777 vga_switcheroo_process_delayed_switch(); 1778 return; 1779 } 1780 1781 i915_gem_lastclose(dev); 1782 1783 if (dev_priv->agp_heap) 1784 i915_mem_takedown(&(dev_priv->agp_heap)); 1785 1786 i915_dma_cleanup(dev); 1787} 1788 1789void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1790{ 1791 drm_i915_private_t *dev_priv = dev->dev_private; 1792 i915_gem_release(dev, file_priv); 1793 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 1794 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 1795} 1796 1797void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 1798{ 1799 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 1800 1801 kfree(i915_file_priv); 1802} 1803 1804struct drm_ioctl_desc i915_ioctls[] = { 1805 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1806 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 1807 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 1808 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 1809 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 1810 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 1811 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 1812 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1813 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 1814 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 1815 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1816 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 1817 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1818 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1819 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 1820 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 1821 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1822 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1823 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), 1824 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), 1825 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1826 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1827 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 1828 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), 1829 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1830 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1831 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), 1832 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), 1833 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), 1834 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), 1835 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), 1836 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), 1837 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), 1838 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), 1839 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), 1840 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), 1841 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), 1842 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), 1843 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1844 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1845}; 1846 1847int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1848 1849/** 1850 * Determine if the device really is AGP or not. 1851 * 1852 * All Intel graphics chipsets are treated as AGP, even if they are really 1853 * PCI-e. 1854 * 1855 * \param dev The device to be tested. 1856 * 1857 * \returns 1858 * A value of 1 is always retured to indictate every i9x5 is AGP. 1859 */ 1860int i915_driver_device_is_agp(struct drm_device * dev) 1861{ 1862 return 1; 1863} 1864