i915_dma.c revision a40e8d3139e9eb54bf1d29f91639a6c5e05f652e
1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2 */ 3/* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "drm_crtc_helper.h" 32#include "drm_fb_helper.h" 33#include "intel_drv.h" 34#include "i915_drm.h" 35#include "i915_drv.h" 36#include "i915_trace.h" 37#include <linux/vgaarb.h> 38 39/* Really want an OS-independent resettable timer. Would like to have 40 * this loop run for (eg) 3 sec, but have the timer reset every time 41 * the head pointer changes, so that EBUSY only happens if the ring 42 * actually stalls for (eg) 3 seconds. 43 */ 44int i915_wait_ring(struct drm_device * dev, int n, const char *caller) 45{ 46 drm_i915_private_t *dev_priv = dev->dev_private; 47 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 48 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; 49 u32 last_acthd = I915_READ(acthd_reg); 50 u32 acthd; 51 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 52 int i; 53 54 trace_i915_ring_wait_begin (dev); 55 56 for (i = 0; i < 100000; i++) { 57 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 58 acthd = I915_READ(acthd_reg); 59 ring->space = ring->head - (ring->tail + 8); 60 if (ring->space < 0) 61 ring->space += ring->Size; 62 if (ring->space >= n) { 63 trace_i915_ring_wait_end (dev); 64 return 0; 65 } 66 67 if (dev->primary->master) { 68 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 69 if (master_priv->sarea_priv) 70 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 71 } 72 73 74 if (ring->head != last_head) 75 i = 0; 76 if (acthd != last_acthd) 77 i = 0; 78 79 last_head = ring->head; 80 last_acthd = acthd; 81 msleep_interruptible(10); 82 83 } 84 85 trace_i915_ring_wait_end (dev); 86 return -EBUSY; 87} 88 89/* As a ringbuffer is only allowed to wrap between instructions, fill 90 * the tail with NOOPs. 91 */ 92int i915_wrap_ring(struct drm_device *dev) 93{ 94 drm_i915_private_t *dev_priv = dev->dev_private; 95 volatile unsigned int *virt; 96 int rem; 97 98 rem = dev_priv->ring.Size - dev_priv->ring.tail; 99 if (dev_priv->ring.space < rem) { 100 int ret = i915_wait_ring(dev, rem, __func__); 101 if (ret) 102 return ret; 103 } 104 dev_priv->ring.space -= rem; 105 106 virt = (unsigned int *) 107 (dev_priv->ring.virtual_start + dev_priv->ring.tail); 108 rem /= 4; 109 while (rem--) 110 *virt++ = MI_NOOP; 111 112 dev_priv->ring.tail = 0; 113 114 return 0; 115} 116 117/** 118 * Sets up the hardware status page for devices that need a physical address 119 * in the register. 120 */ 121static int i915_init_phys_hws(struct drm_device *dev) 122{ 123 drm_i915_private_t *dev_priv = dev->dev_private; 124 /* Program Hardware Status Page */ 125 dev_priv->status_page_dmah = 126 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); 127 128 if (!dev_priv->status_page_dmah) { 129 DRM_ERROR("Can not allocate hardware status page\n"); 130 return -ENOMEM; 131 } 132 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; 133 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 134 135 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 136 137 if (IS_I965G(dev)) 138 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & 139 0xf0; 140 141 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 142 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 143 return 0; 144} 145 146/** 147 * Frees the hardware status page, whether it's a physical address or a virtual 148 * address set up by the X Server. 149 */ 150static void i915_free_hws(struct drm_device *dev) 151{ 152 drm_i915_private_t *dev_priv = dev->dev_private; 153 if (dev_priv->status_page_dmah) { 154 drm_pci_free(dev, dev_priv->status_page_dmah); 155 dev_priv->status_page_dmah = NULL; 156 } 157 158 if (dev_priv->status_gfx_addr) { 159 dev_priv->status_gfx_addr = 0; 160 drm_core_ioremapfree(&dev_priv->hws_map, dev); 161 } 162 163 /* Need to rewrite hardware status page */ 164 I915_WRITE(HWS_PGA, 0x1ffff000); 165} 166 167void i915_kernel_lost_context(struct drm_device * dev) 168{ 169 drm_i915_private_t *dev_priv = dev->dev_private; 170 struct drm_i915_master_private *master_priv; 171 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 172 173 /* 174 * We should never lose context on the ring with modesetting 175 * as we don't expose it to userspace 176 */ 177 if (drm_core_check_feature(dev, DRIVER_MODESET)) 178 return; 179 180 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 181 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 182 ring->space = ring->head - (ring->tail + 8); 183 if (ring->space < 0) 184 ring->space += ring->Size; 185 186 if (!dev->primary->master) 187 return; 188 189 master_priv = dev->primary->master->driver_priv; 190 if (ring->head == ring->tail && master_priv->sarea_priv) 191 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 192} 193 194static int i915_dma_cleanup(struct drm_device * dev) 195{ 196 drm_i915_private_t *dev_priv = dev->dev_private; 197 /* Make sure interrupts are disabled here because the uninstall ioctl 198 * may not have been called from userspace and after dev_private 199 * is freed, it's too late. 200 */ 201 if (dev->irq_enabled) 202 drm_irq_uninstall(dev); 203 204 if (dev_priv->ring.virtual_start) { 205 drm_core_ioremapfree(&dev_priv->ring.map, dev); 206 dev_priv->ring.virtual_start = NULL; 207 dev_priv->ring.map.handle = NULL; 208 dev_priv->ring.map.size = 0; 209 } 210 211 /* Clear the HWS virtual address at teardown */ 212 if (I915_NEED_GFX_HWS(dev)) 213 i915_free_hws(dev); 214 215 return 0; 216} 217 218static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) 219{ 220 drm_i915_private_t *dev_priv = dev->dev_private; 221 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 222 223 master_priv->sarea = drm_getsarea(dev); 224 if (master_priv->sarea) { 225 master_priv->sarea_priv = (drm_i915_sarea_t *) 226 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); 227 } else { 228 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); 229 } 230 231 if (init->ring_size != 0) { 232 if (dev_priv->ring.ring_obj != NULL) { 233 i915_dma_cleanup(dev); 234 DRM_ERROR("Client tried to initialize ringbuffer in " 235 "GEM mode\n"); 236 return -EINVAL; 237 } 238 239 dev_priv->ring.Size = init->ring_size; 240 241 dev_priv->ring.map.offset = init->ring_start; 242 dev_priv->ring.map.size = init->ring_size; 243 dev_priv->ring.map.type = 0; 244 dev_priv->ring.map.flags = 0; 245 dev_priv->ring.map.mtrr = 0; 246 247 drm_core_ioremap_wc(&dev_priv->ring.map, dev); 248 249 if (dev_priv->ring.map.handle == NULL) { 250 i915_dma_cleanup(dev); 251 DRM_ERROR("can not ioremap virtual address for" 252 " ring buffer\n"); 253 return -ENOMEM; 254 } 255 } 256 257 dev_priv->ring.virtual_start = dev_priv->ring.map.handle; 258 259 dev_priv->cpp = init->cpp; 260 dev_priv->back_offset = init->back_offset; 261 dev_priv->front_offset = init->front_offset; 262 dev_priv->current_page = 0; 263 if (master_priv->sarea_priv) 264 master_priv->sarea_priv->pf_current_page = 0; 265 266 /* Allow hardware batchbuffers unless told otherwise. 267 */ 268 dev_priv->allow_batchbuffer = 1; 269 270 return 0; 271} 272 273static int i915_dma_resume(struct drm_device * dev) 274{ 275 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 276 277 DRM_DEBUG_DRIVER("%s\n", __func__); 278 279 if (dev_priv->ring.map.handle == NULL) { 280 DRM_ERROR("can not ioremap virtual address for" 281 " ring buffer\n"); 282 return -ENOMEM; 283 } 284 285 /* Program Hardware Status Page */ 286 if (!dev_priv->hw_status_page) { 287 DRM_ERROR("Can not find hardware status page\n"); 288 return -EINVAL; 289 } 290 DRM_DEBUG_DRIVER("hw status page @ %p\n", 291 dev_priv->hw_status_page); 292 293 if (dev_priv->status_gfx_addr != 0) 294 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 295 else 296 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 297 DRM_DEBUG_DRIVER("Enabled hardware status page\n"); 298 299 return 0; 300} 301 302static int i915_dma_init(struct drm_device *dev, void *data, 303 struct drm_file *file_priv) 304{ 305 drm_i915_init_t *init = data; 306 int retcode = 0; 307 308 switch (init->func) { 309 case I915_INIT_DMA: 310 retcode = i915_initialize(dev, init); 311 break; 312 case I915_CLEANUP_DMA: 313 retcode = i915_dma_cleanup(dev); 314 break; 315 case I915_RESUME_DMA: 316 retcode = i915_dma_resume(dev); 317 break; 318 default: 319 retcode = -EINVAL; 320 break; 321 } 322 323 return retcode; 324} 325 326/* Implement basically the same security restrictions as hardware does 327 * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 328 * 329 * Most of the calculations below involve calculating the size of a 330 * particular instruction. It's important to get the size right as 331 * that tells us where the next instruction to check is. Any illegal 332 * instruction detected will be given a size of zero, which is a 333 * signal to abort the rest of the buffer. 334 */ 335static int do_validate_cmd(int cmd) 336{ 337 switch (((cmd >> 29) & 0x7)) { 338 case 0x0: 339 switch ((cmd >> 23) & 0x3f) { 340 case 0x0: 341 return 1; /* MI_NOOP */ 342 case 0x4: 343 return 1; /* MI_FLUSH */ 344 default: 345 return 0; /* disallow everything else */ 346 } 347 break; 348 case 0x1: 349 return 0; /* reserved */ 350 case 0x2: 351 return (cmd & 0xff) + 2; /* 2d commands */ 352 case 0x3: 353 if (((cmd >> 24) & 0x1f) <= 0x18) 354 return 1; 355 356 switch ((cmd >> 24) & 0x1f) { 357 case 0x1c: 358 return 1; 359 case 0x1d: 360 switch ((cmd >> 16) & 0xff) { 361 case 0x3: 362 return (cmd & 0x1f) + 2; 363 case 0x4: 364 return (cmd & 0xf) + 2; 365 default: 366 return (cmd & 0xffff) + 2; 367 } 368 case 0x1e: 369 if (cmd & (1 << 23)) 370 return (cmd & 0xffff) + 1; 371 else 372 return 1; 373 case 0x1f: 374 if ((cmd & (1 << 23)) == 0) /* inline vertices */ 375 return (cmd & 0x1ffff) + 2; 376 else if (cmd & (1 << 17)) /* indirect random */ 377 if ((cmd & 0xffff) == 0) 378 return 0; /* unknown length, too hard */ 379 else 380 return (((cmd & 0xffff) + 1) / 2) + 1; 381 else 382 return 2; /* indirect sequential */ 383 default: 384 return 0; 385 } 386 default: 387 return 0; 388 } 389 390 return 0; 391} 392 393static int validate_cmd(int cmd) 394{ 395 int ret = do_validate_cmd(cmd); 396 397/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 398 399 return ret; 400} 401 402static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) 403{ 404 drm_i915_private_t *dev_priv = dev->dev_private; 405 int i; 406 RING_LOCALS; 407 408 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) 409 return -EINVAL; 410 411 BEGIN_LP_RING((dwords+1)&~1); 412 413 for (i = 0; i < dwords;) { 414 int cmd, sz; 415 416 cmd = buffer[i]; 417 418 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 419 return -EINVAL; 420 421 OUT_RING(cmd); 422 423 while (++i, --sz) { 424 OUT_RING(buffer[i]); 425 } 426 } 427 428 if (dwords & 1) 429 OUT_RING(0); 430 431 ADVANCE_LP_RING(); 432 433 return 0; 434} 435 436int 437i915_emit_box(struct drm_device *dev, 438 struct drm_clip_rect *boxes, 439 int i, int DR1, int DR4) 440{ 441 drm_i915_private_t *dev_priv = dev->dev_private; 442 struct drm_clip_rect box = boxes[i]; 443 RING_LOCALS; 444 445 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { 446 DRM_ERROR("Bad box %d,%d..%d,%d\n", 447 box.x1, box.y1, box.x2, box.y2); 448 return -EINVAL; 449 } 450 451 if (IS_I965G(dev)) { 452 BEGIN_LP_RING(4); 453 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 454 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 455 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 456 OUT_RING(DR4); 457 ADVANCE_LP_RING(); 458 } else { 459 BEGIN_LP_RING(6); 460 OUT_RING(GFX_OP_DRAWRECT_INFO); 461 OUT_RING(DR1); 462 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 463 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 464 OUT_RING(DR4); 465 OUT_RING(0); 466 ADVANCE_LP_RING(); 467 } 468 469 return 0; 470} 471 472/* XXX: Emitting the counter should really be moved to part of the IRQ 473 * emit. For now, do it in both places: 474 */ 475 476static void i915_emit_breadcrumb(struct drm_device *dev) 477{ 478 drm_i915_private_t *dev_priv = dev->dev_private; 479 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 480 RING_LOCALS; 481 482 dev_priv->counter++; 483 if (dev_priv->counter > 0x7FFFFFFFUL) 484 dev_priv->counter = 0; 485 if (master_priv->sarea_priv) 486 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 487 488 BEGIN_LP_RING(4); 489 OUT_RING(MI_STORE_DWORD_INDEX); 490 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 491 OUT_RING(dev_priv->counter); 492 OUT_RING(0); 493 ADVANCE_LP_RING(); 494} 495 496static int i915_dispatch_cmdbuffer(struct drm_device * dev, 497 drm_i915_cmdbuffer_t *cmd, 498 struct drm_clip_rect *cliprects, 499 void *cmdbuf) 500{ 501 int nbox = cmd->num_cliprects; 502 int i = 0, count, ret; 503 504 if (cmd->sz & 0x3) { 505 DRM_ERROR("alignment"); 506 return -EINVAL; 507 } 508 509 i915_kernel_lost_context(dev); 510 511 count = nbox ? nbox : 1; 512 513 for (i = 0; i < count; i++) { 514 if (i < nbox) { 515 ret = i915_emit_box(dev, cliprects, i, 516 cmd->DR1, cmd->DR4); 517 if (ret) 518 return ret; 519 } 520 521 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); 522 if (ret) 523 return ret; 524 } 525 526 i915_emit_breadcrumb(dev); 527 return 0; 528} 529 530static int i915_dispatch_batchbuffer(struct drm_device * dev, 531 drm_i915_batchbuffer_t * batch, 532 struct drm_clip_rect *cliprects) 533{ 534 drm_i915_private_t *dev_priv = dev->dev_private; 535 int nbox = batch->num_cliprects; 536 int i = 0, count; 537 RING_LOCALS; 538 539 if ((batch->start | batch->used) & 0x7) { 540 DRM_ERROR("alignment"); 541 return -EINVAL; 542 } 543 544 i915_kernel_lost_context(dev); 545 546 count = nbox ? nbox : 1; 547 548 for (i = 0; i < count; i++) { 549 if (i < nbox) { 550 int ret = i915_emit_box(dev, cliprects, i, 551 batch->DR1, batch->DR4); 552 if (ret) 553 return ret; 554 } 555 556 if (!IS_I830(dev) && !IS_845G(dev)) { 557 BEGIN_LP_RING(2); 558 if (IS_I965G(dev)) { 559 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); 560 OUT_RING(batch->start); 561 } else { 562 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 563 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 564 } 565 ADVANCE_LP_RING(); 566 } else { 567 BEGIN_LP_RING(4); 568 OUT_RING(MI_BATCH_BUFFER); 569 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 570 OUT_RING(batch->start + batch->used - 4); 571 OUT_RING(0); 572 ADVANCE_LP_RING(); 573 } 574 } 575 576 i915_emit_breadcrumb(dev); 577 578 return 0; 579} 580 581static int i915_dispatch_flip(struct drm_device * dev) 582{ 583 drm_i915_private_t *dev_priv = dev->dev_private; 584 struct drm_i915_master_private *master_priv = 585 dev->primary->master->driver_priv; 586 RING_LOCALS; 587 588 if (!master_priv->sarea_priv) 589 return -EINVAL; 590 591 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", 592 __func__, 593 dev_priv->current_page, 594 master_priv->sarea_priv->pf_current_page); 595 596 i915_kernel_lost_context(dev); 597 598 BEGIN_LP_RING(2); 599 OUT_RING(MI_FLUSH | MI_READ_FLUSH); 600 OUT_RING(0); 601 ADVANCE_LP_RING(); 602 603 BEGIN_LP_RING(6); 604 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); 605 OUT_RING(0); 606 if (dev_priv->current_page == 0) { 607 OUT_RING(dev_priv->back_offset); 608 dev_priv->current_page = 1; 609 } else { 610 OUT_RING(dev_priv->front_offset); 611 dev_priv->current_page = 0; 612 } 613 OUT_RING(0); 614 ADVANCE_LP_RING(); 615 616 BEGIN_LP_RING(2); 617 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); 618 OUT_RING(0); 619 ADVANCE_LP_RING(); 620 621 master_priv->sarea_priv->last_enqueue = dev_priv->counter++; 622 623 BEGIN_LP_RING(4); 624 OUT_RING(MI_STORE_DWORD_INDEX); 625 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 626 OUT_RING(dev_priv->counter); 627 OUT_RING(0); 628 ADVANCE_LP_RING(); 629 630 master_priv->sarea_priv->pf_current_page = dev_priv->current_page; 631 return 0; 632} 633 634static int i915_quiescent(struct drm_device * dev) 635{ 636 drm_i915_private_t *dev_priv = dev->dev_private; 637 638 i915_kernel_lost_context(dev); 639 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); 640} 641 642static int i915_flush_ioctl(struct drm_device *dev, void *data, 643 struct drm_file *file_priv) 644{ 645 int ret; 646 647 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 648 649 mutex_lock(&dev->struct_mutex); 650 ret = i915_quiescent(dev); 651 mutex_unlock(&dev->struct_mutex); 652 653 return ret; 654} 655 656static int i915_batchbuffer(struct drm_device *dev, void *data, 657 struct drm_file *file_priv) 658{ 659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 660 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 661 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 662 master_priv->sarea_priv; 663 drm_i915_batchbuffer_t *batch = data; 664 int ret; 665 struct drm_clip_rect *cliprects = NULL; 666 667 if (!dev_priv->allow_batchbuffer) { 668 DRM_ERROR("Batchbuffer ioctl disabled\n"); 669 return -EINVAL; 670 } 671 672 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", 673 batch->start, batch->used, batch->num_cliprects); 674 675 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 676 677 if (batch->num_cliprects < 0) 678 return -EINVAL; 679 680 if (batch->num_cliprects) { 681 cliprects = kcalloc(batch->num_cliprects, 682 sizeof(struct drm_clip_rect), 683 GFP_KERNEL); 684 if (cliprects == NULL) 685 return -ENOMEM; 686 687 ret = copy_from_user(cliprects, batch->cliprects, 688 batch->num_cliprects * 689 sizeof(struct drm_clip_rect)); 690 if (ret != 0) 691 goto fail_free; 692 } 693 694 mutex_lock(&dev->struct_mutex); 695 ret = i915_dispatch_batchbuffer(dev, batch, cliprects); 696 mutex_unlock(&dev->struct_mutex); 697 698 if (sarea_priv) 699 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 700 701fail_free: 702 kfree(cliprects); 703 704 return ret; 705} 706 707static int i915_cmdbuffer(struct drm_device *dev, void *data, 708 struct drm_file *file_priv) 709{ 710 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 711 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 712 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 713 master_priv->sarea_priv; 714 drm_i915_cmdbuffer_t *cmdbuf = data; 715 struct drm_clip_rect *cliprects = NULL; 716 void *batch_data; 717 int ret; 718 719 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 720 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 721 722 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 723 724 if (cmdbuf->num_cliprects < 0) 725 return -EINVAL; 726 727 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); 728 if (batch_data == NULL) 729 return -ENOMEM; 730 731 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); 732 if (ret != 0) 733 goto fail_batch_free; 734 735 if (cmdbuf->num_cliprects) { 736 cliprects = kcalloc(cmdbuf->num_cliprects, 737 sizeof(struct drm_clip_rect), GFP_KERNEL); 738 if (cliprects == NULL) { 739 ret = -ENOMEM; 740 goto fail_batch_free; 741 } 742 743 ret = copy_from_user(cliprects, cmdbuf->cliprects, 744 cmdbuf->num_cliprects * 745 sizeof(struct drm_clip_rect)); 746 if (ret != 0) 747 goto fail_clip_free; 748 } 749 750 mutex_lock(&dev->struct_mutex); 751 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); 752 mutex_unlock(&dev->struct_mutex); 753 if (ret) { 754 DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 755 goto fail_clip_free; 756 } 757 758 if (sarea_priv) 759 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 760 761fail_clip_free: 762 kfree(cliprects); 763fail_batch_free: 764 kfree(batch_data); 765 766 return ret; 767} 768 769static int i915_flip_bufs(struct drm_device *dev, void *data, 770 struct drm_file *file_priv) 771{ 772 int ret; 773 774 DRM_DEBUG_DRIVER("%s\n", __func__); 775 776 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 777 778 mutex_lock(&dev->struct_mutex); 779 ret = i915_dispatch_flip(dev); 780 mutex_unlock(&dev->struct_mutex); 781 782 return ret; 783} 784 785static int i915_getparam(struct drm_device *dev, void *data, 786 struct drm_file *file_priv) 787{ 788 drm_i915_private_t *dev_priv = dev->dev_private; 789 drm_i915_getparam_t *param = data; 790 int value; 791 792 if (!dev_priv) { 793 DRM_ERROR("called with no initialization\n"); 794 return -EINVAL; 795 } 796 797 switch (param->param) { 798 case I915_PARAM_IRQ_ACTIVE: 799 value = dev->pdev->irq ? 1 : 0; 800 break; 801 case I915_PARAM_ALLOW_BATCHBUFFER: 802 value = dev_priv->allow_batchbuffer ? 1 : 0; 803 break; 804 case I915_PARAM_LAST_DISPATCH: 805 value = READ_BREADCRUMB(dev_priv); 806 break; 807 case I915_PARAM_CHIPSET_ID: 808 value = dev->pci_device; 809 break; 810 case I915_PARAM_HAS_GEM: 811 value = dev_priv->has_gem; 812 break; 813 case I915_PARAM_NUM_FENCES_AVAIL: 814 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 815 break; 816 case I915_PARAM_HAS_OVERLAY: 817 value = dev_priv->overlay ? 1 : 0; 818 break; 819 case I915_PARAM_HAS_PAGEFLIPPING: 820 value = 1; 821 break; 822 case I915_PARAM_HAS_EXECBUF2: 823 /* depends on GEM */ 824 value = dev_priv->has_gem; 825 break; 826 default: 827 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 828 param->param); 829 return -EINVAL; 830 } 831 832 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 833 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 834 return -EFAULT; 835 } 836 837 return 0; 838} 839 840static int i915_setparam(struct drm_device *dev, void *data, 841 struct drm_file *file_priv) 842{ 843 drm_i915_private_t *dev_priv = dev->dev_private; 844 drm_i915_setparam_t *param = data; 845 846 if (!dev_priv) { 847 DRM_ERROR("called with no initialization\n"); 848 return -EINVAL; 849 } 850 851 switch (param->param) { 852 case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 853 break; 854 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 855 dev_priv->tex_lru_log_granularity = param->value; 856 break; 857 case I915_SETPARAM_ALLOW_BATCHBUFFER: 858 dev_priv->allow_batchbuffer = param->value; 859 break; 860 case I915_SETPARAM_NUM_USED_FENCES: 861 if (param->value > dev_priv->num_fence_regs || 862 param->value < 0) 863 return -EINVAL; 864 /* Userspace can use first N regs */ 865 dev_priv->fence_reg_start = param->value; 866 break; 867 default: 868 DRM_DEBUG_DRIVER("unknown parameter %d\n", 869 param->param); 870 return -EINVAL; 871 } 872 873 return 0; 874} 875 876static int i915_set_status_page(struct drm_device *dev, void *data, 877 struct drm_file *file_priv) 878{ 879 drm_i915_private_t *dev_priv = dev->dev_private; 880 drm_i915_hws_addr_t *hws = data; 881 882 if (!I915_NEED_GFX_HWS(dev)) 883 return -EINVAL; 884 885 if (!dev_priv) { 886 DRM_ERROR("called with no initialization\n"); 887 return -EINVAL; 888 } 889 890 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 891 WARN(1, "tried to set status page when mode setting active\n"); 892 return 0; 893 } 894 895 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); 896 897 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); 898 899 dev_priv->hws_map.offset = dev->agp->base + hws->addr; 900 dev_priv->hws_map.size = 4*1024; 901 dev_priv->hws_map.type = 0; 902 dev_priv->hws_map.flags = 0; 903 dev_priv->hws_map.mtrr = 0; 904 905 drm_core_ioremap_wc(&dev_priv->hws_map, dev); 906 if (dev_priv->hws_map.handle == NULL) { 907 i915_dma_cleanup(dev); 908 dev_priv->status_gfx_addr = 0; 909 DRM_ERROR("can not ioremap virtual address for" 910 " G33 hw status page\n"); 911 return -ENOMEM; 912 } 913 dev_priv->hw_status_page = dev_priv->hws_map.handle; 914 915 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 916 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 917 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", 918 dev_priv->status_gfx_addr); 919 DRM_DEBUG_DRIVER("load hws at %p\n", 920 dev_priv->hw_status_page); 921 return 0; 922} 923 924static int i915_get_bridge_dev(struct drm_device *dev) 925{ 926 struct drm_i915_private *dev_priv = dev->dev_private; 927 928 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); 929 if (!dev_priv->bridge_dev) { 930 DRM_ERROR("bridge device not found\n"); 931 return -1; 932 } 933 return 0; 934} 935 936/** 937 * i915_probe_agp - get AGP bootup configuration 938 * @pdev: PCI device 939 * @aperture_size: returns AGP aperture configured size 940 * @preallocated_size: returns size of BIOS preallocated AGP space 941 * 942 * Since Intel integrated graphics are UMA, the BIOS has to set aside 943 * some RAM for the framebuffer at early boot. This code figures out 944 * how much was set aside so we can use it for our own purposes. 945 */ 946static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 947 uint32_t *preallocated_size, 948 uint32_t *start) 949{ 950 struct drm_i915_private *dev_priv = dev->dev_private; 951 u16 tmp = 0; 952 unsigned long overhead; 953 unsigned long stolen; 954 955 /* Get the fb aperture size and "stolen" memory amount. */ 956 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); 957 958 *aperture_size = 1024 * 1024; 959 *preallocated_size = 1024 * 1024; 960 961 switch (dev->pdev->device) { 962 case PCI_DEVICE_ID_INTEL_82830_CGC: 963 case PCI_DEVICE_ID_INTEL_82845G_IG: 964 case PCI_DEVICE_ID_INTEL_82855GM_IG: 965 case PCI_DEVICE_ID_INTEL_82865_IG: 966 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) 967 *aperture_size *= 64; 968 else 969 *aperture_size *= 128; 970 break; 971 default: 972 /* 9xx supports large sizes, just look at the length */ 973 *aperture_size = pci_resource_len(dev->pdev, 2); 974 break; 975 } 976 977 /* 978 * Some of the preallocated space is taken by the GTT 979 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 980 */ 981 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev)) 982 overhead = 4096; 983 else 984 overhead = (*aperture_size / 1024) + 4096; 985 986 switch (tmp & INTEL_GMCH_GMS_MASK) { 987 case INTEL_855_GMCH_GMS_DISABLED: 988 DRM_ERROR("video memory is disabled\n"); 989 return -1; 990 case INTEL_855_GMCH_GMS_STOLEN_1M: 991 stolen = 1 * 1024 * 1024; 992 break; 993 case INTEL_855_GMCH_GMS_STOLEN_4M: 994 stolen = 4 * 1024 * 1024; 995 break; 996 case INTEL_855_GMCH_GMS_STOLEN_8M: 997 stolen = 8 * 1024 * 1024; 998 break; 999 case INTEL_855_GMCH_GMS_STOLEN_16M: 1000 stolen = 16 * 1024 * 1024; 1001 break; 1002 case INTEL_855_GMCH_GMS_STOLEN_32M: 1003 stolen = 32 * 1024 * 1024; 1004 break; 1005 case INTEL_915G_GMCH_GMS_STOLEN_48M: 1006 stolen = 48 * 1024 * 1024; 1007 break; 1008 case INTEL_915G_GMCH_GMS_STOLEN_64M: 1009 stolen = 64 * 1024 * 1024; 1010 break; 1011 case INTEL_GMCH_GMS_STOLEN_128M: 1012 stolen = 128 * 1024 * 1024; 1013 break; 1014 case INTEL_GMCH_GMS_STOLEN_256M: 1015 stolen = 256 * 1024 * 1024; 1016 break; 1017 case INTEL_GMCH_GMS_STOLEN_96M: 1018 stolen = 96 * 1024 * 1024; 1019 break; 1020 case INTEL_GMCH_GMS_STOLEN_160M: 1021 stolen = 160 * 1024 * 1024; 1022 break; 1023 case INTEL_GMCH_GMS_STOLEN_224M: 1024 stolen = 224 * 1024 * 1024; 1025 break; 1026 case INTEL_GMCH_GMS_STOLEN_352M: 1027 stolen = 352 * 1024 * 1024; 1028 break; 1029 default: 1030 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", 1031 tmp & INTEL_GMCH_GMS_MASK); 1032 return -1; 1033 } 1034 *preallocated_size = stolen - overhead; 1035 *start = overhead; 1036 1037 return 0; 1038} 1039 1040#define PTE_ADDRESS_MASK 0xfffff000 1041#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ 1042#define PTE_MAPPING_TYPE_UNCACHED (0 << 1) 1043#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ 1044#define PTE_MAPPING_TYPE_CACHED (3 << 1) 1045#define PTE_MAPPING_TYPE_MASK (3 << 1) 1046#define PTE_VALID (1 << 0) 1047 1048/** 1049 * i915_gtt_to_phys - take a GTT address and turn it into a physical one 1050 * @dev: drm device 1051 * @gtt_addr: address to translate 1052 * 1053 * Some chip functions require allocations from stolen space but need the 1054 * physical address of the memory in question. We use this routine 1055 * to get a physical address suitable for register programming from a given 1056 * GTT address. 1057 */ 1058static unsigned long i915_gtt_to_phys(struct drm_device *dev, 1059 unsigned long gtt_addr) 1060{ 1061 unsigned long *gtt; 1062 unsigned long entry, phys; 1063 int gtt_bar = IS_I9XX(dev) ? 0 : 1; 1064 int gtt_offset, gtt_size; 1065 1066 if (IS_I965G(dev)) { 1067 if (IS_G4X(dev) || IS_IRONLAKE(dev)) { 1068 gtt_offset = 2*1024*1024; 1069 gtt_size = 2*1024*1024; 1070 } else { 1071 gtt_offset = 512*1024; 1072 gtt_size = 512*1024; 1073 } 1074 } else { 1075 gtt_bar = 3; 1076 gtt_offset = 0; 1077 gtt_size = pci_resource_len(dev->pdev, gtt_bar); 1078 } 1079 1080 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset, 1081 gtt_size); 1082 if (!gtt) { 1083 DRM_ERROR("ioremap of GTT failed\n"); 1084 return 0; 1085 } 1086 1087 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); 1088 1089 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); 1090 1091 /* Mask out these reserved bits on this hardware. */ 1092 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || 1093 IS_I945G(dev) || IS_I945GM(dev)) { 1094 entry &= ~PTE_ADDRESS_MASK_HIGH; 1095 } 1096 1097 /* If it's not a mapping type we know, then bail. */ 1098 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && 1099 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) { 1100 iounmap(gtt); 1101 return 0; 1102 } 1103 1104 if (!(entry & PTE_VALID)) { 1105 DRM_ERROR("bad GTT entry in stolen space\n"); 1106 iounmap(gtt); 1107 return 0; 1108 } 1109 1110 iounmap(gtt); 1111 1112 phys =(entry & PTE_ADDRESS_MASK) | 1113 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); 1114 1115 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); 1116 1117 return phys; 1118} 1119 1120static void i915_warn_stolen(struct drm_device *dev) 1121{ 1122 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); 1123 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); 1124} 1125 1126static void i915_setup_compression(struct drm_device *dev, int size) 1127{ 1128 struct drm_i915_private *dev_priv = dev->dev_private; 1129 struct drm_mm_node *compressed_fb, *compressed_llb; 1130 unsigned long cfb_base; 1131 unsigned long ll_base = 0; 1132 1133 /* Leave 1M for line length buffer & misc. */ 1134 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); 1135 if (!compressed_fb) { 1136 i915_warn_stolen(dev); 1137 return; 1138 } 1139 1140 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); 1141 if (!compressed_fb) { 1142 i915_warn_stolen(dev); 1143 return; 1144 } 1145 1146 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start); 1147 if (!cfb_base) { 1148 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1149 drm_mm_put_block(compressed_fb); 1150 } 1151 1152 if (!IS_GM45(dev)) { 1153 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 1154 4096, 0); 1155 if (!compressed_llb) { 1156 i915_warn_stolen(dev); 1157 return; 1158 } 1159 1160 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096); 1161 if (!compressed_llb) { 1162 i915_warn_stolen(dev); 1163 return; 1164 } 1165 1166 ll_base = i915_gtt_to_phys(dev, compressed_llb->start); 1167 if (!ll_base) { 1168 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n"); 1169 drm_mm_put_block(compressed_fb); 1170 drm_mm_put_block(compressed_llb); 1171 } 1172 } 1173 1174 dev_priv->cfb_size = size; 1175 1176 if (IS_GM45(dev)) { 1177 g4x_disable_fbc(dev); 1178 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); 1179 } else { 1180 i8xx_disable_fbc(dev); 1181 I915_WRITE(FBC_CFB_BASE, cfb_base); 1182 I915_WRITE(FBC_LL_BASE, ll_base); 1183 } 1184 1185 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, 1186 ll_base, size >> 20); 1187} 1188 1189/* true = enable decode, false = disable decoder */ 1190static unsigned int i915_vga_set_decode(void *cookie, bool state) 1191{ 1192 struct drm_device *dev = cookie; 1193 1194 intel_modeset_vga_set_state(dev, state); 1195 if (state) 1196 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1197 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1198 else 1199 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1200} 1201 1202static int i915_load_modeset_init(struct drm_device *dev, 1203 unsigned long prealloc_start, 1204 unsigned long prealloc_size, 1205 unsigned long agp_size) 1206{ 1207 struct drm_i915_private *dev_priv = dev->dev_private; 1208 int fb_bar = IS_I9XX(dev) ? 2 : 0; 1209 int ret = 0; 1210 1211 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) & 1212 0xff000000; 1213 1214 /* Basic memrange allocator for stolen space (aka vram) */ 1215 drm_mm_init(&dev_priv->vram, 0, prealloc_size); 1216 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024)); 1217 1218 /* We're off and running w/KMS */ 1219 dev_priv->mm.suspended = 0; 1220 1221 /* Let GEM Manage from end of prealloc space to end of aperture. 1222 * 1223 * However, leave one page at the end still bound to the scratch page. 1224 * There are a number of places where the hardware apparently 1225 * prefetches past the end of the object, and we've seen multiple 1226 * hangs with the GPU head pointer stuck in a batchbuffer bound 1227 * at the last page of the aperture. One page should be enough to 1228 * keep any prefetching inside of the aperture. 1229 */ 1230 i915_gem_do_init(dev, prealloc_size, agp_size - 4096); 1231 1232 mutex_lock(&dev->struct_mutex); 1233 ret = i915_gem_init_ringbuffer(dev); 1234 mutex_unlock(&dev->struct_mutex); 1235 if (ret) 1236 goto out; 1237 1238 /* Try to set up FBC with a reasonable compressed buffer size */ 1239 if (I915_HAS_FBC(dev) && i915_powersave) { 1240 int cfb_size; 1241 1242 /* Try to get an 8M buffer... */ 1243 if (prealloc_size > (9*1024*1024)) 1244 cfb_size = 8*1024*1024; 1245 else /* fall back to 7/8 of the stolen space */ 1246 cfb_size = prealloc_size * 7 / 8; 1247 i915_setup_compression(dev, cfb_size); 1248 } 1249 1250 /* Allow hardware batchbuffers unless told otherwise. 1251 */ 1252 dev_priv->allow_batchbuffer = 1; 1253 1254 ret = intel_init_bios(dev); 1255 if (ret) 1256 DRM_INFO("failed to find VBIOS tables\n"); 1257 1258 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1259 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1260 if (ret) 1261 goto destroy_ringbuffer; 1262 1263 intel_modeset_init(dev); 1264 1265 ret = drm_irq_install(dev); 1266 if (ret) 1267 goto destroy_ringbuffer; 1268 1269 /* Always safe in the mode setting case. */ 1270 /* FIXME: do pre/post-mode set stuff in core KMS code */ 1271 dev->vblank_disable_allowed = 1; 1272 1273 /* 1274 * Initialize the hardware status page IRQ location. 1275 */ 1276 1277 I915_WRITE(INSTPM, (1 << 5) | (1 << 21)); 1278 1279 drm_helper_initial_config(dev); 1280 1281 return 0; 1282 1283destroy_ringbuffer: 1284 i915_gem_cleanup_ringbuffer(dev); 1285out: 1286 return ret; 1287} 1288 1289int i915_master_create(struct drm_device *dev, struct drm_master *master) 1290{ 1291 struct drm_i915_master_private *master_priv; 1292 1293 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); 1294 if (!master_priv) 1295 return -ENOMEM; 1296 1297 master->driver_priv = master_priv; 1298 return 0; 1299} 1300 1301void i915_master_destroy(struct drm_device *dev, struct drm_master *master) 1302{ 1303 struct drm_i915_master_private *master_priv = master->driver_priv; 1304 1305 if (!master_priv) 1306 return; 1307 1308 kfree(master_priv); 1309 1310 master->driver_priv = NULL; 1311} 1312 1313static void i915_get_mem_freq(struct drm_device *dev) 1314{ 1315 drm_i915_private_t *dev_priv = dev->dev_private; 1316 u32 tmp; 1317 1318 if (!IS_PINEVIEW(dev)) 1319 return; 1320 1321 tmp = I915_READ(CLKCFG); 1322 1323 switch (tmp & CLKCFG_FSB_MASK) { 1324 case CLKCFG_FSB_533: 1325 dev_priv->fsb_freq = 533; /* 133*4 */ 1326 break; 1327 case CLKCFG_FSB_800: 1328 dev_priv->fsb_freq = 800; /* 200*4 */ 1329 break; 1330 case CLKCFG_FSB_667: 1331 dev_priv->fsb_freq = 667; /* 167*4 */ 1332 break; 1333 case CLKCFG_FSB_400: 1334 dev_priv->fsb_freq = 400; /* 100*4 */ 1335 break; 1336 } 1337 1338 switch (tmp & CLKCFG_MEM_MASK) { 1339 case CLKCFG_MEM_533: 1340 dev_priv->mem_freq = 533; 1341 break; 1342 case CLKCFG_MEM_667: 1343 dev_priv->mem_freq = 667; 1344 break; 1345 case CLKCFG_MEM_800: 1346 dev_priv->mem_freq = 800; 1347 break; 1348 } 1349} 1350 1351/** 1352 * i915_driver_load - setup chip and create an initial config 1353 * @dev: DRM device 1354 * @flags: startup flags 1355 * 1356 * The driver load routine has to do several things: 1357 * - drive output discovery via intel_modeset_init() 1358 * - initialize the memory manager 1359 * - allocate initial config memory 1360 * - setup the DRM framebuffer with the allocated memory 1361 */ 1362int i915_driver_load(struct drm_device *dev, unsigned long flags) 1363{ 1364 struct drm_i915_private *dev_priv = dev->dev_private; 1365 resource_size_t base, size; 1366 int ret = 0, mmio_bar; 1367 uint32_t agp_size, prealloc_size, prealloc_start; 1368 1369 /* i915 has 4 more counters */ 1370 dev->counters += 4; 1371 dev->types[6] = _DRM_STAT_IRQ; 1372 dev->types[7] = _DRM_STAT_PRIMARY; 1373 dev->types[8] = _DRM_STAT_SECONDARY; 1374 dev->types[9] = _DRM_STAT_DMA; 1375 1376 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); 1377 if (dev_priv == NULL) 1378 return -ENOMEM; 1379 1380 dev->dev_private = (void *)dev_priv; 1381 dev_priv->dev = dev; 1382 dev_priv->info = (struct intel_device_info *) flags; 1383 1384 /* Add register map (needed for suspend/resume) */ 1385 mmio_bar = IS_I9XX(dev) ? 0 : 1; 1386 base = drm_get_resource_start(dev, mmio_bar); 1387 size = drm_get_resource_len(dev, mmio_bar); 1388 1389 if (i915_get_bridge_dev(dev)) { 1390 ret = -EIO; 1391 goto free_priv; 1392 } 1393 1394 dev_priv->regs = ioremap(base, size); 1395 if (!dev_priv->regs) { 1396 DRM_ERROR("failed to map registers\n"); 1397 ret = -EIO; 1398 goto put_bridge; 1399 } 1400 1401 dev_priv->mm.gtt_mapping = 1402 io_mapping_create_wc(dev->agp->base, 1403 dev->agp->agp_info.aper_size * 1024*1024); 1404 if (dev_priv->mm.gtt_mapping == NULL) { 1405 ret = -EIO; 1406 goto out_rmmap; 1407 } 1408 1409 /* Set up a WC MTRR for non-PAT systems. This is more common than 1410 * one would think, because the kernel disables PAT on first 1411 * generation Core chips because WC PAT gets overridden by a UC 1412 * MTRR if present. Even if a UC MTRR isn't present. 1413 */ 1414 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, 1415 dev->agp->agp_info.aper_size * 1416 1024 * 1024, 1417 MTRR_TYPE_WRCOMB, 1); 1418 if (dev_priv->mm.gtt_mtrr < 0) { 1419 DRM_INFO("MTRR allocation failed. Graphics " 1420 "performance may suffer.\n"); 1421 } 1422 1423 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); 1424 if (ret) 1425 goto out_iomapfree; 1426 1427 dev_priv->wq = create_singlethread_workqueue("i915"); 1428 if (dev_priv->wq == NULL) { 1429 DRM_ERROR("Failed to create our workqueue.\n"); 1430 ret = -ENOMEM; 1431 goto out_iomapfree; 1432 } 1433 1434 /* enable GEM by default */ 1435 dev_priv->has_gem = 1; 1436 1437 if (prealloc_size > agp_size * 3 / 4) { 1438 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video " 1439 "memory stolen.\n", 1440 prealloc_size / 1024, agp_size / 1024); 1441 DRM_ERROR("Disabling GEM. (try reducing stolen memory or " 1442 "updating the BIOS to fix).\n"); 1443 dev_priv->has_gem = 0; 1444 } 1445 1446 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1447 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1448 if (IS_G4X(dev) || IS_IRONLAKE(dev)) { 1449 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1450 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1451 } 1452 1453 i915_gem_load(dev); 1454 1455 /* Init HWS */ 1456 if (!I915_NEED_GFX_HWS(dev)) { 1457 ret = i915_init_phys_hws(dev); 1458 if (ret != 0) 1459 goto out_workqueue_free; 1460 } 1461 1462 i915_get_mem_freq(dev); 1463 1464 /* On the 945G/GM, the chipset reports the MSI capability on the 1465 * integrated graphics even though the support isn't actually there 1466 * according to the published specs. It doesn't appear to function 1467 * correctly in testing on 945G. 1468 * This may be a side effect of MSI having been made available for PEG 1469 * and the registers being closely associated. 1470 * 1471 * According to chipset errata, on the 965GM, MSI interrupts may 1472 * be lost or delayed, but we use them anyways to avoid 1473 * stuck interrupts on some machines. 1474 */ 1475 if (!IS_I945G(dev) && !IS_I945GM(dev)) 1476 pci_enable_msi(dev->pdev); 1477 1478 spin_lock_init(&dev_priv->user_irq_lock); 1479 spin_lock_init(&dev_priv->error_lock); 1480 dev_priv->user_irq_refcount = 0; 1481 dev_priv->trace_irq_seqno = 0; 1482 1483 ret = drm_vblank_init(dev, I915_NUM_PIPE); 1484 1485 if (ret) { 1486 (void) i915_driver_unload(dev); 1487 return ret; 1488 } 1489 1490 /* Start out suspended */ 1491 dev_priv->mm.suspended = 1; 1492 1493 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1494 ret = i915_load_modeset_init(dev, prealloc_start, 1495 prealloc_size, agp_size); 1496 if (ret < 0) { 1497 DRM_ERROR("failed to init modeset\n"); 1498 goto out_workqueue_free; 1499 } 1500 } 1501 1502 /* Must be done after probing outputs */ 1503 intel_opregion_init(dev, 0); 1504 1505 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 1506 (unsigned long) dev); 1507 return 0; 1508 1509out_workqueue_free: 1510 destroy_workqueue(dev_priv->wq); 1511out_iomapfree: 1512 io_mapping_free(dev_priv->mm.gtt_mapping); 1513out_rmmap: 1514 iounmap(dev_priv->regs); 1515put_bridge: 1516 pci_dev_put(dev_priv->bridge_dev); 1517free_priv: 1518 kfree(dev_priv); 1519 return ret; 1520} 1521 1522int i915_driver_unload(struct drm_device *dev) 1523{ 1524 struct drm_i915_private *dev_priv = dev->dev_private; 1525 1526 destroy_workqueue(dev_priv->wq); 1527 del_timer_sync(&dev_priv->hangcheck_timer); 1528 1529 io_mapping_free(dev_priv->mm.gtt_mapping); 1530 if (dev_priv->mm.gtt_mtrr >= 0) { 1531 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, 1532 dev->agp->agp_info.aper_size * 1024 * 1024); 1533 dev_priv->mm.gtt_mtrr = -1; 1534 } 1535 1536 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1537 /* 1538 * free the memory space allocated for the child device 1539 * config parsed from VBT 1540 */ 1541 if (dev_priv->child_dev && dev_priv->child_dev_num) { 1542 kfree(dev_priv->child_dev); 1543 dev_priv->child_dev = NULL; 1544 dev_priv->child_dev_num = 0; 1545 } 1546 drm_irq_uninstall(dev); 1547 vga_client_register(dev->pdev, NULL, NULL, NULL); 1548 } 1549 1550 if (dev->pdev->msi_enabled) 1551 pci_disable_msi(dev->pdev); 1552 1553 if (dev_priv->regs != NULL) 1554 iounmap(dev_priv->regs); 1555 1556 intel_opregion_free(dev, 0); 1557 1558 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1559 intel_modeset_cleanup(dev); 1560 1561 i915_gem_free_all_phys_object(dev); 1562 1563 mutex_lock(&dev->struct_mutex); 1564 i915_gem_cleanup_ringbuffer(dev); 1565 mutex_unlock(&dev->struct_mutex); 1566 drm_mm_takedown(&dev_priv->vram); 1567 i915_gem_lastclose(dev); 1568 1569 intel_cleanup_overlay(dev); 1570 } 1571 1572 pci_dev_put(dev_priv->bridge_dev); 1573 kfree(dev->dev_private); 1574 1575 return 0; 1576} 1577 1578int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1579{ 1580 struct drm_i915_file_private *i915_file_priv; 1581 1582 DRM_DEBUG_DRIVER("\n"); 1583 i915_file_priv = (struct drm_i915_file_private *) 1584 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); 1585 1586 if (!i915_file_priv) 1587 return -ENOMEM; 1588 1589 file_priv->driver_priv = i915_file_priv; 1590 1591 INIT_LIST_HEAD(&i915_file_priv->mm.request_list); 1592 1593 return 0; 1594} 1595 1596/** 1597 * i915_driver_lastclose - clean up after all DRM clients have exited 1598 * @dev: DRM device 1599 * 1600 * Take care of cleaning up after all DRM clients have exited. In the 1601 * mode setting case, we want to restore the kernel's initial mode (just 1602 * in case the last client left us in a bad state). 1603 * 1604 * Additionally, in the non-mode setting case, we'll tear down the AGP 1605 * and DMA structures, since the kernel won't be using them, and clea 1606 * up any GEM state. 1607 */ 1608void i915_driver_lastclose(struct drm_device * dev) 1609{ 1610 drm_i915_private_t *dev_priv = dev->dev_private; 1611 1612 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { 1613 drm_fb_helper_restore(); 1614 return; 1615 } 1616 1617 i915_gem_lastclose(dev); 1618 1619 if (dev_priv->agp_heap) 1620 i915_mem_takedown(&(dev_priv->agp_heap)); 1621 1622 i915_dma_cleanup(dev); 1623} 1624 1625void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1626{ 1627 drm_i915_private_t *dev_priv = dev->dev_private; 1628 i915_gem_release(dev, file_priv); 1629 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 1630 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 1631} 1632 1633void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 1634{ 1635 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 1636 1637 kfree(i915_file_priv); 1638} 1639 1640struct drm_ioctl_desc i915_ioctls[] = { 1641 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1642 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 1643 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 1644 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 1645 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 1646 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 1647 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 1648 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1649 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 1650 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 1651 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1652 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 1653 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1654 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1655 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 1656 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 1657 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1658 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1659 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), 1660 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH), 1661 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1662 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1663 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), 1664 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), 1665 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1666 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1667 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), 1668 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), 1669 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), 1670 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), 1671 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0), 1672 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), 1673 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), 1674 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 1675 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 1676 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), 1677 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), 1678 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0), 1679 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), 1680 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), 1681}; 1682 1683int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1684 1685/** 1686 * Determine if the device really is AGP or not. 1687 * 1688 * All Intel graphics chipsets are treated as AGP, even if they are really 1689 * PCI-e. 1690 * 1691 * \param dev The device to be tested. 1692 * 1693 * \returns 1694 * A value of 1 is always retured to indictate every i9x5 is AGP. 1695 */ 1696int i915_driver_device_is_agp(struct drm_device * dev) 1697{ 1698 return 1; 1699} 1700