intel_lvds.c revision fe16d949b45036d9f80e20e07bde1ddacc930b10
1/* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30#include <acpi/button.h> 31#include <linux/dmi.h> 32#include <linux/i2c.h> 33#include <linux/slab.h> 34#include "drmP.h" 35#include "drm.h" 36#include "drm_crtc.h" 37#include "drm_edid.h" 38#include "intel_drv.h" 39#include "i915_drm.h" 40#include "i915_drv.h" 41#include <linux/acpi.h> 42 43/* Private structure for the integrated LVDS support */ 44struct intel_lvds { 45 struct intel_encoder base; 46 47 struct edid *edid; 48 49 int fitting_mode; 50 u32 pfit_control; 51 u32 pfit_pgm_ratios; 52 bool pfit_dirty; 53 54 struct drm_display_mode *fixed_mode; 55}; 56 57static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) 58{ 59 return container_of(encoder, struct intel_lvds, base.base); 60} 61 62static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) 63{ 64 return container_of(intel_attached_encoder(connector), 65 struct intel_lvds, base); 66} 67 68/** 69 * Sets the power state for the panel. 70 */ 71static void intel_lvds_enable(struct intel_lvds *intel_lvds) 72{ 73 struct drm_device *dev = intel_lvds->base.base.dev; 74 struct drm_i915_private *dev_priv = dev->dev_private; 75 u32 ctl_reg, lvds_reg; 76 77 if (HAS_PCH_SPLIT(dev)) { 78 ctl_reg = PCH_PP_CONTROL; 79 lvds_reg = PCH_LVDS; 80 } else { 81 ctl_reg = PP_CONTROL; 82 lvds_reg = LVDS; 83 } 84 85 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); 86 87 if (intel_lvds->pfit_dirty) { 88 /* 89 * Enable automatic panel scaling so that non-native modes 90 * fill the screen. The panel fitter should only be 91 * adjusted whilst the pipe is disabled, according to 92 * register description and PRM. 93 */ 94 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", 95 intel_lvds->pfit_control, 96 intel_lvds->pfit_pgm_ratios); 97 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) { 98 DRM_ERROR("timed out waiting for panel to power off\n"); 99 } else { 100 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); 101 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); 102 intel_lvds->pfit_dirty = false; 103 } 104 } 105 106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 107 POSTING_READ(lvds_reg); 108 109 intel_panel_enable_backlight(dev); 110} 111 112static void intel_lvds_disable(struct intel_lvds *intel_lvds) 113{ 114 struct drm_device *dev = intel_lvds->base.base.dev; 115 struct drm_i915_private *dev_priv = dev->dev_private; 116 u32 ctl_reg, lvds_reg; 117 118 if (HAS_PCH_SPLIT(dev)) { 119 ctl_reg = PCH_PP_CONTROL; 120 lvds_reg = PCH_LVDS; 121 } else { 122 ctl_reg = PP_CONTROL; 123 lvds_reg = LVDS; 124 } 125 126 intel_panel_disable_backlight(dev); 127 128 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); 129 130 if (intel_lvds->pfit_control) { 131 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) 132 DRM_ERROR("timed out waiting for panel to power off\n"); 133 134 I915_WRITE(PFIT_CONTROL, 0); 135 intel_lvds->pfit_dirty = true; 136 } 137 138 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); 139 POSTING_READ(lvds_reg); 140} 141 142static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) 143{ 144 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 145 146 if (mode == DRM_MODE_DPMS_ON) 147 intel_lvds_enable(intel_lvds); 148 else 149 intel_lvds_disable(intel_lvds); 150 151 /* XXX: We never power down the LVDS pairs. */ 152} 153 154static int intel_lvds_mode_valid(struct drm_connector *connector, 155 struct drm_display_mode *mode) 156{ 157 struct intel_lvds *intel_lvds = intel_attached_lvds(connector); 158 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; 159 160 if (mode->hdisplay > fixed_mode->hdisplay) 161 return MODE_PANEL; 162 if (mode->vdisplay > fixed_mode->vdisplay) 163 return MODE_PANEL; 164 165 return MODE_OK; 166} 167 168static void 169centre_horizontally(struct drm_display_mode *mode, 170 int width) 171{ 172 u32 border, sync_pos, blank_width, sync_width; 173 174 /* keep the hsync and hblank widths constant */ 175 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; 176 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; 177 sync_pos = (blank_width - sync_width + 1) / 2; 178 179 border = (mode->hdisplay - width + 1) / 2; 180 border += border & 1; /* make the border even */ 181 182 mode->crtc_hdisplay = width; 183 mode->crtc_hblank_start = width + border; 184 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; 185 186 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; 187 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; 188} 189 190static void 191centre_vertically(struct drm_display_mode *mode, 192 int height) 193{ 194 u32 border, sync_pos, blank_width, sync_width; 195 196 /* keep the vsync and vblank widths constant */ 197 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; 198 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; 199 sync_pos = (blank_width - sync_width + 1) / 2; 200 201 border = (mode->vdisplay - height + 1) / 2; 202 203 mode->crtc_vdisplay = height; 204 mode->crtc_vblank_start = height + border; 205 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; 206 207 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; 208 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; 209} 210 211static inline u32 panel_fitter_scaling(u32 source, u32 target) 212{ 213 /* 214 * Floating point operation is not supported. So the FACTOR 215 * is defined, which can avoid the floating point computation 216 * when calculating the panel ratio. 217 */ 218#define ACCURACY 12 219#define FACTOR (1 << ACCURACY) 220 u32 ratio = source * FACTOR / target; 221 return (FACTOR * ratio + FACTOR/2) / FACTOR; 222} 223 224static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, 225 struct drm_display_mode *mode, 226 struct drm_display_mode *adjusted_mode) 227{ 228 struct drm_device *dev = encoder->dev; 229 struct drm_i915_private *dev_priv = dev->dev_private; 230 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 232 struct drm_encoder *tmp_encoder; 233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 234 int pipe; 235 236 /* Should never happen!! */ 237 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 238 DRM_ERROR("Can't support LVDS on pipe A\n"); 239 return false; 240 } 241 242 /* Should never happen!! */ 243 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { 244 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { 245 DRM_ERROR("Can't enable LVDS and another " 246 "encoder on the same pipe\n"); 247 return false; 248 } 249 } 250 251 /* 252 * We have timings from the BIOS for the panel, put them in 253 * to the adjusted mode. The CRTC will be set up for this mode, 254 * with the panel scaling set up to source from the H/VDisplay 255 * of the original mode. 256 */ 257 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); 258 259 if (HAS_PCH_SPLIT(dev)) { 260 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, 261 mode, adjusted_mode); 262 return true; 263 } 264 265 /* Make sure pre-965s set dither correctly */ 266 if (INTEL_INFO(dev)->gen < 4) { 267 if (dev_priv->lvds_dither) 268 pfit_control |= PANEL_8TO6_DITHER_ENABLE; 269 } 270 271 /* Native modes don't need fitting */ 272 if (adjusted_mode->hdisplay == mode->hdisplay && 273 adjusted_mode->vdisplay == mode->vdisplay) 274 goto out; 275 276 /* 965+ wants fuzzy fitting */ 277 if (INTEL_INFO(dev)->gen >= 4) 278 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | 279 PFIT_FILTER_FUZZY); 280 281 /* 282 * Enable automatic panel scaling for non-native modes so that they fill 283 * the screen. Should be enabled before the pipe is enabled, according 284 * to register description and PRM. 285 * Change the value here to see the borders for debugging 286 */ 287 for_each_pipe(pipe) 288 I915_WRITE(BCLRPAT(pipe), 0); 289 290 switch (intel_lvds->fitting_mode) { 291 case DRM_MODE_SCALE_CENTER: 292 /* 293 * For centered modes, we have to calculate border widths & 294 * heights and modify the values programmed into the CRTC. 295 */ 296 centre_horizontally(adjusted_mode, mode->hdisplay); 297 centre_vertically(adjusted_mode, mode->vdisplay); 298 border = LVDS_BORDER_ENABLE; 299 break; 300 301 case DRM_MODE_SCALE_ASPECT: 302 /* Scale but preserve the aspect ratio */ 303 if (INTEL_INFO(dev)->gen >= 4) { 304 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; 305 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; 306 307 /* 965+ is easy, it does everything in hw */ 308 if (scaled_width > scaled_height) 309 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; 310 else if (scaled_width < scaled_height) 311 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; 312 else if (adjusted_mode->hdisplay != mode->hdisplay) 313 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; 314 } else { 315 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; 316 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; 317 /* 318 * For earlier chips we have to calculate the scaling 319 * ratio by hand and program it into the 320 * PFIT_PGM_RATIO register 321 */ 322 if (scaled_width > scaled_height) { /* pillar */ 323 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); 324 325 border = LVDS_BORDER_ENABLE; 326 if (mode->vdisplay != adjusted_mode->vdisplay) { 327 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); 328 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | 329 bits << PFIT_VERT_SCALE_SHIFT); 330 pfit_control |= (PFIT_ENABLE | 331 VERT_INTERP_BILINEAR | 332 HORIZ_INTERP_BILINEAR); 333 } 334 } else if (scaled_width < scaled_height) { /* letter */ 335 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); 336 337 border = LVDS_BORDER_ENABLE; 338 if (mode->hdisplay != adjusted_mode->hdisplay) { 339 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); 340 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | 341 bits << PFIT_VERT_SCALE_SHIFT); 342 pfit_control |= (PFIT_ENABLE | 343 VERT_INTERP_BILINEAR | 344 HORIZ_INTERP_BILINEAR); 345 } 346 } else 347 /* Aspects match, Let hw scale both directions */ 348 pfit_control |= (PFIT_ENABLE | 349 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | 350 VERT_INTERP_BILINEAR | 351 HORIZ_INTERP_BILINEAR); 352 } 353 break; 354 355 case DRM_MODE_SCALE_FULLSCREEN: 356 /* 357 * Full scaling, even if it changes the aspect ratio. 358 * Fortunately this is all done for us in hw. 359 */ 360 if (mode->vdisplay != adjusted_mode->vdisplay || 361 mode->hdisplay != adjusted_mode->hdisplay) { 362 pfit_control |= PFIT_ENABLE; 363 if (INTEL_INFO(dev)->gen >= 4) 364 pfit_control |= PFIT_SCALING_AUTO; 365 else 366 pfit_control |= (VERT_AUTO_SCALE | 367 VERT_INTERP_BILINEAR | 368 HORIZ_AUTO_SCALE | 369 HORIZ_INTERP_BILINEAR); 370 } 371 break; 372 373 default: 374 break; 375 } 376 377out: 378 if ((pfit_control & PFIT_ENABLE) == 0) { 379 pfit_control = 0; 380 pfit_pgm_ratios = 0; 381 } 382 if (pfit_control != intel_lvds->pfit_control || 383 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { 384 intel_lvds->pfit_control = pfit_control; 385 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; 386 intel_lvds->pfit_dirty = true; 387 } 388 dev_priv->lvds_border_bits = border; 389 390 /* 391 * XXX: It would be nice to support lower refresh rates on the 392 * panels to reduce power consumption, and perhaps match the 393 * user's requested refresh rate. 394 */ 395 396 return true; 397} 398 399static void intel_lvds_prepare(struct drm_encoder *encoder) 400{ 401 struct drm_device *dev = encoder->dev; 402 struct drm_i915_private *dev_priv = dev->dev_private; 403 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 404 405 /* We try to do the minimum that is necessary in order to unlock 406 * the registers for mode setting. 407 * 408 * On Ironlake, this is quite simple as we just set the unlock key 409 * and ignore all subtleties. (This may cause some issues...) 410 * 411 * Prior to Ironlake, we must disable the pipe if we want to adjust 412 * the panel fitter. However at all other times we can just reset 413 * the registers regardless. 414 */ 415 416 if (HAS_PCH_SPLIT(dev)) { 417 I915_WRITE(PCH_PP_CONTROL, 418 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); 419 } else if (intel_lvds->pfit_dirty) { 420 I915_WRITE(PP_CONTROL, 421 (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS) 422 & ~POWER_TARGET_ON); 423 } else { 424 I915_WRITE(PP_CONTROL, 425 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); 426 } 427} 428 429static void intel_lvds_commit(struct drm_encoder *encoder) 430{ 431 struct drm_device *dev = encoder->dev; 432 struct drm_i915_private *dev_priv = dev->dev_private; 433 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 434 435 /* Undo any unlocking done in prepare to prevent accidental 436 * adjustment of the registers. 437 */ 438 if (HAS_PCH_SPLIT(dev)) { 439 u32 val = I915_READ(PCH_PP_CONTROL); 440 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) 441 I915_WRITE(PCH_PP_CONTROL, val & 0x3); 442 } else { 443 u32 val = I915_READ(PP_CONTROL); 444 if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) 445 I915_WRITE(PP_CONTROL, val & 0x3); 446 } 447 448 /* Always do a full power on as we do not know what state 449 * we were left in. 450 */ 451 intel_lvds_enable(intel_lvds); 452} 453 454static void intel_lvds_mode_set(struct drm_encoder *encoder, 455 struct drm_display_mode *mode, 456 struct drm_display_mode *adjusted_mode) 457{ 458 /* 459 * The LVDS pin pair will already have been turned on in the 460 * intel_crtc_mode_set since it has a large impact on the DPLL 461 * settings. 462 */ 463} 464 465/** 466 * Detect the LVDS connection. 467 * 468 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 469 * connected and closed means disconnected. We also send hotplug events as 470 * needed, using lid status notification from the input layer. 471 */ 472static enum drm_connector_status 473intel_lvds_detect(struct drm_connector *connector, bool force) 474{ 475 struct drm_device *dev = connector->dev; 476 enum drm_connector_status status = connector_status_connected; 477 478 status = intel_panel_detect(dev); 479 if (status != connector_status_unknown) 480 return status; 481 482 /* ACPI lid methods were generally unreliable in this generation, so 483 * don't even bother. 484 */ 485 if (IS_GEN2(dev) || IS_GEN3(dev)) 486 return connector_status_connected; 487 488 return status; 489} 490 491/** 492 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 493 */ 494static int intel_lvds_get_modes(struct drm_connector *connector) 495{ 496 struct intel_lvds *intel_lvds = intel_attached_lvds(connector); 497 struct drm_device *dev = connector->dev; 498 struct drm_display_mode *mode; 499 500 if (intel_lvds->edid) 501 return drm_add_edid_modes(connector, intel_lvds->edid); 502 503 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); 504 if (mode == NULL) 505 return 0; 506 507 drm_mode_probed_add(connector, mode); 508 return 1; 509} 510 511static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 512{ 513 DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); 514 return 1; 515} 516 517/* The GPU hangs up on these systems if modeset is performed on LID open */ 518static const struct dmi_system_id intel_no_modeset_on_lid[] = { 519 { 520 .callback = intel_no_modeset_on_lid_dmi_callback, 521 .ident = "Toshiba Tecra A11", 522 .matches = { 523 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 524 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 525 }, 526 }, 527 528 { } /* terminating entry */ 529}; 530 531/* 532 * Lid events. Note the use of 'modeset_on_lid': 533 * - we set it on lid close, and reset it on open 534 * - we use it as a "only once" bit (ie we ignore 535 * duplicate events where it was already properly 536 * set/reset) 537 * - the suspend/resume paths will also set it to 538 * zero, since they restore the mode ("lid open"). 539 */ 540static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 541 void *unused) 542{ 543 struct drm_i915_private *dev_priv = 544 container_of(nb, struct drm_i915_private, lid_notifier); 545 struct drm_device *dev = dev_priv->dev; 546 struct drm_connector *connector = dev_priv->int_lvds_connector; 547 548 /* 549 * check and update the status of LVDS connector after receiving 550 * the LID nofication event. 551 */ 552 if (connector) 553 connector->status = connector->funcs->detect(connector, 554 false); 555 556 /* Don't force modeset on machines where it causes a GPU lockup */ 557 if (dmi_check_system(intel_no_modeset_on_lid)) 558 return NOTIFY_OK; 559 if (!acpi_lid_open()) { 560 dev_priv->modeset_on_lid = 1; 561 return NOTIFY_OK; 562 } 563 564 if (!dev_priv->modeset_on_lid) 565 return NOTIFY_OK; 566 567 dev_priv->modeset_on_lid = 0; 568 569 mutex_lock(&dev->mode_config.mutex); 570 drm_helper_resume_force_mode(dev); 571 mutex_unlock(&dev->mode_config.mutex); 572 573 return NOTIFY_OK; 574} 575 576/** 577 * intel_lvds_destroy - unregister and free LVDS structures 578 * @connector: connector to free 579 * 580 * Unregister the DDC bus for this connector then free the driver private 581 * structure. 582 */ 583static void intel_lvds_destroy(struct drm_connector *connector) 584{ 585 struct drm_device *dev = connector->dev; 586 struct drm_i915_private *dev_priv = dev->dev_private; 587 588 if (dev_priv->lid_notifier.notifier_call) 589 acpi_lid_notifier_unregister(&dev_priv->lid_notifier); 590 drm_sysfs_connector_remove(connector); 591 drm_connector_cleanup(connector); 592 kfree(connector); 593} 594 595static int intel_lvds_set_property(struct drm_connector *connector, 596 struct drm_property *property, 597 uint64_t value) 598{ 599 struct intel_lvds *intel_lvds = intel_attached_lvds(connector); 600 struct drm_device *dev = connector->dev; 601 602 if (property == dev->mode_config.scaling_mode_property) { 603 struct drm_crtc *crtc = intel_lvds->base.base.crtc; 604 605 if (value == DRM_MODE_SCALE_NONE) { 606 DRM_DEBUG_KMS("no scaling not supported\n"); 607 return -EINVAL; 608 } 609 610 if (intel_lvds->fitting_mode == value) { 611 /* the LVDS scaling property is not changed */ 612 return 0; 613 } 614 intel_lvds->fitting_mode = value; 615 if (crtc && crtc->enabled) { 616 /* 617 * If the CRTC is enabled, the display will be changed 618 * according to the new panel fitting mode. 619 */ 620 drm_crtc_helper_set_mode(crtc, &crtc->mode, 621 crtc->x, crtc->y, crtc->fb); 622 } 623 } 624 625 return 0; 626} 627 628static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { 629 .dpms = intel_lvds_dpms, 630 .mode_fixup = intel_lvds_mode_fixup, 631 .prepare = intel_lvds_prepare, 632 .mode_set = intel_lvds_mode_set, 633 .commit = intel_lvds_commit, 634}; 635 636static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 637 .get_modes = intel_lvds_get_modes, 638 .mode_valid = intel_lvds_mode_valid, 639 .best_encoder = intel_best_encoder, 640}; 641 642static const struct drm_connector_funcs intel_lvds_connector_funcs = { 643 .dpms = drm_helper_connector_dpms, 644 .detect = intel_lvds_detect, 645 .fill_modes = drm_helper_probe_single_connector_modes, 646 .set_property = intel_lvds_set_property, 647 .destroy = intel_lvds_destroy, 648}; 649 650static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 651 .destroy = intel_encoder_destroy, 652}; 653 654static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 655{ 656 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); 657 return 1; 658} 659 660/* These systems claim to have LVDS, but really don't */ 661static const struct dmi_system_id intel_no_lvds[] = { 662 { 663 .callback = intel_no_lvds_dmi_callback, 664 .ident = "Apple Mac Mini (Core series)", 665 .matches = { 666 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 667 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 668 }, 669 }, 670 { 671 .callback = intel_no_lvds_dmi_callback, 672 .ident = "Apple Mac Mini (Core 2 series)", 673 .matches = { 674 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 675 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 676 }, 677 }, 678 { 679 .callback = intel_no_lvds_dmi_callback, 680 .ident = "MSI IM-945GSE-A", 681 .matches = { 682 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 683 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 684 }, 685 }, 686 { 687 .callback = intel_no_lvds_dmi_callback, 688 .ident = "Dell Studio Hybrid", 689 .matches = { 690 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 691 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 692 }, 693 }, 694 { 695 .callback = intel_no_lvds_dmi_callback, 696 .ident = "AOpen Mini PC", 697 .matches = { 698 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 699 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 700 }, 701 }, 702 { 703 .callback = intel_no_lvds_dmi_callback, 704 .ident = "AOpen Mini PC MP915", 705 .matches = { 706 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 707 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 708 }, 709 }, 710 { 711 .callback = intel_no_lvds_dmi_callback, 712 .ident = "AOpen i915GMm-HFS", 713 .matches = { 714 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 715 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 716 }, 717 }, 718 { 719 .callback = intel_no_lvds_dmi_callback, 720 .ident = "Aopen i945GTt-VFA", 721 .matches = { 722 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 723 }, 724 }, 725 { 726 .callback = intel_no_lvds_dmi_callback, 727 .ident = "Clientron U800", 728 .matches = { 729 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 730 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 731 }, 732 }, 733 734 { } /* terminating entry */ 735}; 736 737/** 738 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID 739 * @dev: drm device 740 * @connector: LVDS connector 741 * 742 * Find the reduced downclock for LVDS in EDID. 743 */ 744static void intel_find_lvds_downclock(struct drm_device *dev, 745 struct drm_display_mode *fixed_mode, 746 struct drm_connector *connector) 747{ 748 struct drm_i915_private *dev_priv = dev->dev_private; 749 struct drm_display_mode *scan; 750 int temp_downclock; 751 752 temp_downclock = fixed_mode->clock; 753 list_for_each_entry(scan, &connector->probed_modes, head) { 754 /* 755 * If one mode has the same resolution with the fixed_panel 756 * mode while they have the different refresh rate, it means 757 * that the reduced downclock is found for the LVDS. In such 758 * case we can set the different FPx0/1 to dynamically select 759 * between low and high frequency. 760 */ 761 if (scan->hdisplay == fixed_mode->hdisplay && 762 scan->hsync_start == fixed_mode->hsync_start && 763 scan->hsync_end == fixed_mode->hsync_end && 764 scan->htotal == fixed_mode->htotal && 765 scan->vdisplay == fixed_mode->vdisplay && 766 scan->vsync_start == fixed_mode->vsync_start && 767 scan->vsync_end == fixed_mode->vsync_end && 768 scan->vtotal == fixed_mode->vtotal) { 769 if (scan->clock < temp_downclock) { 770 /* 771 * The downclock is already found. But we 772 * expect to find the lower downclock. 773 */ 774 temp_downclock = scan->clock; 775 } 776 } 777 } 778 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { 779 /* We found the downclock for LVDS. */ 780 dev_priv->lvds_downclock_avail = 1; 781 dev_priv->lvds_downclock = temp_downclock; 782 DRM_DEBUG_KMS("LVDS downclock is found in EDID. " 783 "Normal clock %dKhz, downclock %dKhz\n", 784 fixed_mode->clock, temp_downclock); 785 } 786} 787 788/* 789 * Enumerate the child dev array parsed from VBT to check whether 790 * the LVDS is present. 791 * If it is present, return 1. 792 * If it is not present, return false. 793 * If no child dev is parsed from VBT, it assumes that the LVDS is present. 794 */ 795static bool lvds_is_present_in_vbt(struct drm_device *dev, 796 u8 *i2c_pin) 797{ 798 struct drm_i915_private *dev_priv = dev->dev_private; 799 int i; 800 801 if (!dev_priv->child_dev_num) 802 return true; 803 804 for (i = 0; i < dev_priv->child_dev_num; i++) { 805 struct child_device_config *child = dev_priv->child_dev + i; 806 807 /* If the device type is not LFP, continue. 808 * We have to check both the new identifiers as well as the 809 * old for compatibility with some BIOSes. 810 */ 811 if (child->device_type != DEVICE_TYPE_INT_LFP && 812 child->device_type != DEVICE_TYPE_LFP) 813 continue; 814 815 if (child->i2c_pin) 816 *i2c_pin = child->i2c_pin; 817 818 /* However, we cannot trust the BIOS writers to populate 819 * the VBT correctly. Since LVDS requires additional 820 * information from AIM blocks, a non-zero addin offset is 821 * a good indicator that the LVDS is actually present. 822 */ 823 if (child->addin_offset) 824 return true; 825 826 /* But even then some BIOS writers perform some black magic 827 * and instantiate the device without reference to any 828 * additional data. Trust that if the VBT was written into 829 * the OpRegion then they have validated the LVDS's existence. 830 */ 831 if (dev_priv->opregion.vbt) 832 return true; 833 } 834 835 return false; 836} 837 838static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin) 839{ 840 struct drm_i915_private *dev_priv = dev->dev_private; 841 u8 buf = 0; 842 struct i2c_msg msgs[] = { 843 { 844 .addr = 0xA0, 845 .flags = 0, 846 .len = 1, 847 .buf = &buf, 848 }, 849 }; 850 struct i2c_adapter *i2c = &dev_priv->gmbus[pin].adapter; 851 /* XXX this only appears to work when using GMBUS */ 852 if (intel_gmbus_is_forced_bit(i2c)) 853 return true; 854 return i2c_transfer(i2c, msgs, 1) == 1; 855} 856 857/** 858 * intel_lvds_init - setup LVDS connectors on this device 859 * @dev: drm device 860 * 861 * Create the connector, register the LVDS DDC bus, and try to figure out what 862 * modes we can display on the LVDS panel (if present). 863 */ 864bool intel_lvds_init(struct drm_device *dev) 865{ 866 struct drm_i915_private *dev_priv = dev->dev_private; 867 struct intel_lvds *intel_lvds; 868 struct intel_encoder *intel_encoder; 869 struct intel_connector *intel_connector; 870 struct drm_connector *connector; 871 struct drm_encoder *encoder; 872 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 873 struct drm_crtc *crtc; 874 u32 lvds; 875 int pipe; 876 u8 pin; 877 878 /* Skip init on machines we know falsely report LVDS */ 879 if (dmi_check_system(intel_no_lvds)) 880 return false; 881 882 pin = GMBUS_PORT_PANEL; 883 if (!lvds_is_present_in_vbt(dev, &pin)) { 884 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 885 return false; 886 } 887 888 if (HAS_PCH_SPLIT(dev)) { 889 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 890 return false; 891 if (dev_priv->edp.support) { 892 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 893 return false; 894 } 895 } 896 897 if (!intel_lvds_ddc_probe(dev, pin)) { 898 DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n"); 899 return false; 900 } 901 902 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); 903 if (!intel_lvds) { 904 return false; 905 } 906 907 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 908 if (!intel_connector) { 909 kfree(intel_lvds); 910 return false; 911 } 912 913 if (!HAS_PCH_SPLIT(dev)) { 914 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); 915 } 916 917 intel_encoder = &intel_lvds->base; 918 encoder = &intel_encoder->base; 919 connector = &intel_connector->base; 920 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 921 DRM_MODE_CONNECTOR_LVDS); 922 923 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 924 DRM_MODE_ENCODER_LVDS); 925 926 intel_connector_attach_encoder(intel_connector, intel_encoder); 927 intel_encoder->type = INTEL_OUTPUT_LVDS; 928 929 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); 930 intel_encoder->crtc_mask = (1 << 1); 931 if (INTEL_INFO(dev)->gen >= 5) 932 intel_encoder->crtc_mask |= (1 << 0); 933 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 934 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 935 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 936 connector->interlace_allowed = false; 937 connector->doublescan_allowed = false; 938 939 /* create the scaling mode property */ 940 drm_mode_create_scaling_mode_property(dev); 941 /* 942 * the initial panel fitting mode will be FULL_SCREEN. 943 */ 944 945 drm_connector_attach_property(&intel_connector->base, 946 dev->mode_config.scaling_mode_property, 947 DRM_MODE_SCALE_ASPECT); 948 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; 949 /* 950 * LVDS discovery: 951 * 1) check for EDID on DDC 952 * 2) check for VBT data 953 * 3) check to see if LVDS is already on 954 * if none of the above, no panel 955 * 4) make sure lid is open 956 * if closed, act like it's not there for now 957 */ 958 959 /* 960 * Attempt to get the fixed panel mode from DDC. Assume that the 961 * preferred mode is the right one. 962 */ 963 intel_lvds->edid = drm_get_edid(connector, 964 &dev_priv->gmbus[pin].adapter); 965 if (intel_lvds->edid) { 966 if (drm_add_edid_modes(connector, 967 intel_lvds->edid)) { 968 drm_mode_connector_update_edid_property(connector, 969 intel_lvds->edid); 970 } else { 971 kfree(intel_lvds->edid); 972 intel_lvds->edid = NULL; 973 } 974 } 975 if (!intel_lvds->edid) { 976 /* Didn't get an EDID, so 977 * Set wide sync ranges so we get all modes 978 * handed to valid_mode for checking 979 */ 980 connector->display_info.min_vfreq = 0; 981 connector->display_info.max_vfreq = 200; 982 connector->display_info.min_hfreq = 0; 983 connector->display_info.max_hfreq = 200; 984 } 985 986 list_for_each_entry(scan, &connector->probed_modes, head) { 987 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 988 intel_lvds->fixed_mode = 989 drm_mode_duplicate(dev, scan); 990 intel_find_lvds_downclock(dev, 991 intel_lvds->fixed_mode, 992 connector); 993 goto out; 994 } 995 } 996 997 /* Failed to get EDID, what about VBT? */ 998 if (dev_priv->lfp_lvds_vbt_mode) { 999 intel_lvds->fixed_mode = 1000 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1001 if (intel_lvds->fixed_mode) { 1002 intel_lvds->fixed_mode->type |= 1003 DRM_MODE_TYPE_PREFERRED; 1004 goto out; 1005 } 1006 } 1007 1008 /* 1009 * If we didn't get EDID, try checking if the panel is already turned 1010 * on. If so, assume that whatever is currently programmed is the 1011 * correct mode. 1012 */ 1013 1014 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1015 if (HAS_PCH_SPLIT(dev)) 1016 goto failed; 1017 1018 lvds = I915_READ(LVDS); 1019 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1020 crtc = intel_get_crtc_for_pipe(dev, pipe); 1021 1022 if (crtc && (lvds & LVDS_PORT_EN)) { 1023 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); 1024 if (intel_lvds->fixed_mode) { 1025 intel_lvds->fixed_mode->type |= 1026 DRM_MODE_TYPE_PREFERRED; 1027 goto out; 1028 } 1029 } 1030 1031 /* If we still don't have a mode after all that, give up. */ 1032 if (!intel_lvds->fixed_mode) 1033 goto failed; 1034 1035out: 1036 if (HAS_PCH_SPLIT(dev)) { 1037 u32 pwm; 1038 1039 pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0; 1040 1041 /* make sure PWM is enabled and locked to the LVDS pipe */ 1042 pwm = I915_READ(BLC_PWM_CPU_CTL2); 1043 if (pipe == 0 && (pwm & PWM_PIPE_B)) 1044 I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); 1045 if (pipe) 1046 pwm |= PWM_PIPE_B; 1047 else 1048 pwm &= ~PWM_PIPE_B; 1049 I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); 1050 1051 pwm = I915_READ(BLC_PWM_PCH_CTL1); 1052 pwm |= PWM_PCH_ENABLE; 1053 I915_WRITE(BLC_PWM_PCH_CTL1, pwm); 1054 } 1055 dev_priv->lid_notifier.notifier_call = intel_lid_notify; 1056 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { 1057 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1058 dev_priv->lid_notifier.notifier_call = NULL; 1059 } 1060 /* keep the LVDS connector */ 1061 dev_priv->int_lvds_connector = connector; 1062 drm_sysfs_connector_add(connector); 1063 return true; 1064 1065failed: 1066 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1067 drm_connector_cleanup(connector); 1068 drm_encoder_cleanup(encoder); 1069 kfree(intel_lvds); 1070 kfree(intel_connector); 1071 return false; 1072} 1073