nouveau_drv.h revision 02076da97a15bbf7477bffed71d02f726de2afc2
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 15 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 struct ttm_bo_kmap_obj kmap; 80 struct list_head head; 81 82 /* protected by ttm_bo_reserve() */ 83 struct drm_file *reserved_by; 84 struct list_head entry; 85 int pbbo_index; 86 87 struct nouveau_channel *channel; 88 89 bool mappable; 90 bool no_vm; 91 92 uint32_t tile_mode; 93 uint32_t tile_flags; 94 struct nouveau_tile_reg *tile; 95 96 struct drm_gem_object *gem; 97 struct drm_file *cpu_filp; 98 int pin_refcnt; 99}; 100 101static inline struct nouveau_bo * 102nouveau_bo(struct ttm_buffer_object *bo) 103{ 104 return container_of(bo, struct nouveau_bo, bo); 105} 106 107static inline struct nouveau_bo * 108nouveau_gem_object(struct drm_gem_object *gem) 109{ 110 return gem ? gem->driver_private : NULL; 111} 112 113/* TODO: submit equivalent to TTM generic API upstream? */ 114static inline void __iomem * 115nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 116{ 117 bool is_iomem; 118 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 119 &nvbo->kmap, &is_iomem); 120 WARN_ON_ONCE(ioptr && !is_iomem); 121 return ioptr; 122} 123 124struct mem_block { 125 struct mem_block *next; 126 struct mem_block *prev; 127 uint64_t start; 128 uint64_t size; 129 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 130}; 131 132enum nouveau_flags { 133 NV_NFORCE = 0x10000000, 134 NV_NFORCE2 = 0x20000000 135}; 136 137#define NVOBJ_ENGINE_SW 0 138#define NVOBJ_ENGINE_GR 1 139#define NVOBJ_ENGINE_DISPLAY 2 140#define NVOBJ_ENGINE_INT 0xdeadbeef 141 142#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 144#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 145#define NVOBJ_FLAG_FAKE (1 << 3) 146struct nouveau_gpuobj { 147 struct list_head list; 148 149 struct nouveau_channel *im_channel; 150 struct mem_block *im_pramin; 151 struct nouveau_bo *im_backing; 152 uint32_t im_backing_start; 153 uint32_t *im_backing_suspend; 154 int im_bound; 155 156 uint32_t flags; 157 int refcount; 158 159 uint32_t engine; 160 uint32_t class; 161 162 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 163 void *priv; 164}; 165 166struct nouveau_gpuobj_ref { 167 struct list_head list; 168 169 struct nouveau_gpuobj *gpuobj; 170 uint32_t instance; 171 172 struct nouveau_channel *channel; 173 int handle; 174}; 175 176struct nouveau_channel { 177 struct drm_device *dev; 178 int id; 179 180 /* owner of this fifo */ 181 struct drm_file *file_priv; 182 /* mapping of the fifo itself */ 183 struct drm_local_map *map; 184 185 /* mapping of the regs controling the fifo */ 186 void __iomem *user; 187 uint32_t user_get; 188 uint32_t user_put; 189 190 /* Fencing */ 191 struct { 192 /* lock protects the pending list only */ 193 spinlock_t lock; 194 struct list_head pending; 195 uint32_t sequence; 196 uint32_t sequence_ack; 197 uint32_t last_sequence_irq; 198 } fence; 199 200 /* DMA push buffer */ 201 struct nouveau_gpuobj_ref *pushbuf; 202 struct nouveau_bo *pushbuf_bo; 203 uint32_t pushbuf_base; 204 205 /* Notifier memory */ 206 struct nouveau_bo *notifier_bo; 207 struct mem_block *notifier_heap; 208 209 /* PFIFO context */ 210 struct nouveau_gpuobj_ref *ramfc; 211 struct nouveau_gpuobj_ref *cache; 212 213 /* PGRAPH context */ 214 /* XXX may be merge 2 pointers as private data ??? */ 215 struct nouveau_gpuobj_ref *ramin_grctx; 216 void *pgraph_ctx; 217 218 /* NV50 VM */ 219 struct nouveau_gpuobj *vm_pd; 220 struct nouveau_gpuobj_ref *vm_gart_pt; 221 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 222 223 /* Objects */ 224 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 225 struct mem_block *ramin_heap; /* Private PRAMIN heap */ 226 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 227 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 228 229 /* GPU object info for stuff used in-kernel (mm_enabled) */ 230 uint32_t m2mf_ntfy; 231 uint32_t vram_handle; 232 uint32_t gart_handle; 233 bool accel_done; 234 235 /* Push buffer state (only for drm's channel on !mm_enabled) */ 236 struct { 237 int max; 238 int free; 239 int cur; 240 int put; 241 /* access via pushbuf_bo */ 242 } dma; 243 244 uint32_t sw_subchannel[8]; 245 246 struct { 247 struct nouveau_gpuobj *vblsem; 248 uint32_t vblsem_offset; 249 uint32_t vblsem_rval; 250 struct list_head vbl_wait; 251 } nvsw; 252 253 struct { 254 bool active; 255 char name[32]; 256 struct drm_info_list info; 257 } debugfs; 258}; 259 260struct nouveau_instmem_engine { 261 void *priv; 262 263 int (*init)(struct drm_device *dev); 264 void (*takedown)(struct drm_device *dev); 265 int (*suspend)(struct drm_device *dev); 266 void (*resume)(struct drm_device *dev); 267 268 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 269 uint32_t *size); 270 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 272 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 273 void (*prepare_access)(struct drm_device *, bool write); 274 void (*finish_access)(struct drm_device *); 275}; 276 277struct nouveau_mc_engine { 278 int (*init)(struct drm_device *dev); 279 void (*takedown)(struct drm_device *dev); 280}; 281 282struct nouveau_timer_engine { 283 int (*init)(struct drm_device *dev); 284 void (*takedown)(struct drm_device *dev); 285 uint64_t (*read)(struct drm_device *dev); 286}; 287 288struct nouveau_fb_engine { 289 int num_tiles; 290 291 int (*init)(struct drm_device *dev); 292 void (*takedown)(struct drm_device *dev); 293 294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 295 uint32_t size, uint32_t pitch); 296}; 297 298struct nouveau_fifo_engine { 299 void *priv; 300 301 int channels; 302 303 int (*init)(struct drm_device *); 304 void (*takedown)(struct drm_device *); 305 306 void (*disable)(struct drm_device *); 307 void (*enable)(struct drm_device *); 308 bool (*reassign)(struct drm_device *, bool enable); 309 bool (*cache_flush)(struct drm_device *dev); 310 bool (*cache_pull)(struct drm_device *dev, bool enable); 311 312 int (*channel_id)(struct drm_device *); 313 314 int (*create_context)(struct nouveau_channel *); 315 void (*destroy_context)(struct nouveau_channel *); 316 int (*load_context)(struct nouveau_channel *); 317 int (*unload_context)(struct drm_device *); 318}; 319 320struct nouveau_pgraph_object_method { 321 int id; 322 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 323 uint32_t data); 324}; 325 326struct nouveau_pgraph_object_class { 327 int id; 328 bool software; 329 struct nouveau_pgraph_object_method *methods; 330}; 331 332struct nouveau_pgraph_engine { 333 struct nouveau_pgraph_object_class *grclass; 334 bool accel_blocked; 335 void *ctxprog; 336 void *ctxvals; 337 int grctx_size; 338 339 int (*init)(struct drm_device *); 340 void (*takedown)(struct drm_device *); 341 342 void (*fifo_access)(struct drm_device *, bool); 343 344 struct nouveau_channel *(*channel)(struct drm_device *); 345 int (*create_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *); 348 int (*unload_context)(struct drm_device *); 349 350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 351 uint32_t size, uint32_t pitch); 352}; 353 354struct nouveau_engine { 355 struct nouveau_instmem_engine instmem; 356 struct nouveau_mc_engine mc; 357 struct nouveau_timer_engine timer; 358 struct nouveau_fb_engine fb; 359 struct nouveau_pgraph_engine graph; 360 struct nouveau_fifo_engine fifo; 361}; 362 363struct nouveau_pll_vals { 364 union { 365 struct { 366#ifdef __BIG_ENDIAN 367 uint8_t N1, M1, N2, M2; 368#else 369 uint8_t M1, N1, M2, N2; 370#endif 371 }; 372 struct { 373 uint16_t NM1, NM2; 374 } __attribute__((packed)); 375 }; 376 int log2P; 377 378 int refclk; 379}; 380 381enum nv04_fp_display_regs { 382 FP_DISPLAY_END, 383 FP_TOTAL, 384 FP_CRTC, 385 FP_SYNC_START, 386 FP_SYNC_END, 387 FP_VALID_START, 388 FP_VALID_END 389}; 390 391struct nv04_crtc_reg { 392 unsigned char MiscOutReg; /* */ 393 uint8_t CRTC[0x9f]; 394 uint8_t CR58[0x10]; 395 uint8_t Sequencer[5]; 396 uint8_t Graphics[9]; 397 uint8_t Attribute[21]; 398 unsigned char DAC[768]; /* Internal Colorlookuptable */ 399 400 /* PCRTC regs */ 401 uint32_t fb_start; 402 uint32_t crtc_cfg; 403 uint32_t cursor_cfg; 404 uint32_t gpio_ext; 405 uint32_t crtc_830; 406 uint32_t crtc_834; 407 uint32_t crtc_850; 408 uint32_t crtc_eng_ctrl; 409 410 /* PRAMDAC regs */ 411 uint32_t nv10_cursync; 412 struct nouveau_pll_vals pllvals; 413 uint32_t ramdac_gen_ctrl; 414 uint32_t ramdac_630; 415 uint32_t ramdac_634; 416 uint32_t tv_setup; 417 uint32_t tv_vtotal; 418 uint32_t tv_vskew; 419 uint32_t tv_vsync_delay; 420 uint32_t tv_htotal; 421 uint32_t tv_hskew; 422 uint32_t tv_hsync_delay; 423 uint32_t tv_hsync_delay2; 424 uint32_t fp_horiz_regs[7]; 425 uint32_t fp_vert_regs[7]; 426 uint32_t dither; 427 uint32_t fp_control; 428 uint32_t dither_regs[6]; 429 uint32_t fp_debug_0; 430 uint32_t fp_debug_1; 431 uint32_t fp_debug_2; 432 uint32_t fp_margin_color; 433 uint32_t ramdac_8c0; 434 uint32_t ramdac_a20; 435 uint32_t ramdac_a24; 436 uint32_t ramdac_a34; 437 uint32_t ctv_regs[38]; 438}; 439 440struct nv04_output_reg { 441 uint32_t output; 442 int head; 443}; 444 445struct nv04_mode_state { 446 uint32_t bpp; 447 uint32_t width; 448 uint32_t height; 449 uint32_t interlace; 450 uint32_t repaint0; 451 uint32_t repaint1; 452 uint32_t screen; 453 uint32_t scale; 454 uint32_t dither; 455 uint32_t extra; 456 uint32_t fifo; 457 uint32_t pixel; 458 uint32_t horiz; 459 int arbitration0; 460 int arbitration1; 461 uint32_t pll; 462 uint32_t pllB; 463 uint32_t vpll; 464 uint32_t vpll2; 465 uint32_t vpllB; 466 uint32_t vpll2B; 467 uint32_t pllsel; 468 uint32_t sel_clk; 469 uint32_t general; 470 uint32_t crtcOwner; 471 uint32_t head; 472 uint32_t head2; 473 uint32_t cursorConfig; 474 uint32_t cursor0; 475 uint32_t cursor1; 476 uint32_t cursor2; 477 uint32_t timingH; 478 uint32_t timingV; 479 uint32_t displayV; 480 uint32_t crtcSync; 481 482 struct nv04_crtc_reg crtc_reg[2]; 483}; 484 485enum nouveau_card_type { 486 NV_04 = 0x00, 487 NV_10 = 0x10, 488 NV_20 = 0x20, 489 NV_30 = 0x30, 490 NV_40 = 0x40, 491 NV_50 = 0x50, 492}; 493 494struct drm_nouveau_private { 495 struct drm_device *dev; 496 enum { 497 NOUVEAU_CARD_INIT_DOWN, 498 NOUVEAU_CARD_INIT_DONE, 499 NOUVEAU_CARD_INIT_FAILED 500 } init_state; 501 502 /* the card type, takes NV_* as values */ 503 enum nouveau_card_type card_type; 504 /* exact chipset, derived from NV_PMC_BOOT_0 */ 505 int chipset; 506 int flags; 507 508 void __iomem *mmio; 509 void __iomem *ramin; 510 uint32_t ramin_size; 511 512 struct workqueue_struct *wq; 513 struct work_struct irq_work; 514 515 struct list_head vbl_waiting; 516 517 struct { 518 struct ttm_global_reference mem_global_ref; 519 struct ttm_bo_global_ref bo_global_ref; 520 struct ttm_bo_device bdev; 521 spinlock_t bo_list_lock; 522 struct list_head bo_list; 523 atomic_t validate_sequence; 524 } ttm; 525 526 struct fb_info *fbdev_info; 527 528 int fifo_alloc_count; 529 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 530 531 struct nouveau_engine engine; 532 struct nouveau_channel *channel; 533 534 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 535 struct nouveau_gpuobj *ramht; 536 uint32_t ramin_rsvd_vram; 537 uint32_t ramht_offset; 538 uint32_t ramht_size; 539 uint32_t ramht_bits; 540 uint32_t ramfc_offset; 541 uint32_t ramfc_size; 542 uint32_t ramro_offset; 543 uint32_t ramro_size; 544 545 /* base physical adresses */ 546 uint64_t fb_phys; 547 uint64_t fb_available_size; 548 uint64_t fb_mappable_pages; 549 uint64_t fb_aper_free; 550 551 struct { 552 enum { 553 NOUVEAU_GART_NONE = 0, 554 NOUVEAU_GART_AGP, 555 NOUVEAU_GART_SGDMA 556 } type; 557 uint64_t aper_base; 558 uint64_t aper_size; 559 uint64_t aper_free; 560 561 struct nouveau_gpuobj *sg_ctxdma; 562 struct page *sg_dummy_page; 563 dma_addr_t sg_dummy_bus; 564 565 /* nottm hack */ 566 struct drm_ttm_backend *sg_be; 567 unsigned long sg_handle; 568 } gart_info; 569 570 /* nv10-nv40 tiling regions */ 571 struct { 572 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 573 spinlock_t lock; 574 } tile; 575 576 /* G8x/G9x virtual address space */ 577 uint64_t vm_gart_base; 578 uint64_t vm_gart_size; 579 uint64_t vm_vram_base; 580 uint64_t vm_vram_size; 581 uint64_t vm_end; 582 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 583 int vm_vram_pt_nr; 584 585 /* the mtrr covering the FB */ 586 int fb_mtrr; 587 588 struct mem_block *ramin_heap; 589 590 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ 591 uint32_t ctx_table_size; 592 struct nouveau_gpuobj_ref *ctx_table; 593 594 struct list_head gpuobj_list; 595 596 struct nvbios VBIOS; 597 struct nouveau_bios_info *vbios; 598 599 struct nv04_mode_state mode_reg; 600 struct nv04_mode_state saved_reg; 601 uint32_t saved_vga_font[4][16384]; 602 uint32_t crtc_owner; 603 uint32_t dac_users[4]; 604 605 struct nouveau_suspend_resume { 606 uint32_t fifo_mode; 607 uint32_t graph_ctx_control; 608 uint32_t graph_state; 609 uint32_t *ramin_copy; 610 uint64_t ramin_size; 611 } susres; 612 613 struct backlight_device *backlight; 614 bool acpi_dsm; 615 616 struct nouveau_channel *evo; 617 618 struct { 619 struct dentry *channel_root; 620 } debugfs; 621}; 622 623static inline struct drm_nouveau_private * 624nouveau_bdev(struct ttm_bo_device *bd) 625{ 626 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 627} 628 629static inline int 630nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 631{ 632 struct nouveau_bo *prev; 633 634 if (!pnvbo) 635 return -EINVAL; 636 prev = *pnvbo; 637 638 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 639 if (prev) { 640 struct ttm_buffer_object *bo = &prev->bo; 641 642 ttm_bo_unref(&bo); 643 } 644 645 return 0; 646} 647 648#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ 649 struct drm_nouveau_private *nv = dev->dev_private; \ 650 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ 651 NV_ERROR(dev, "called without init\n"); \ 652 return -EINVAL; \ 653 } \ 654} while (0) 655 656#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 657 struct drm_nouveau_private *nv = dev->dev_private; \ 658 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 659 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 660 DRM_CURRENTPID, (id)); \ 661 return -EPERM; \ 662 } \ 663 (ch) = nv->fifos[(id)]; \ 664} while (0) 665 666/* nouveau_drv.c */ 667extern int nouveau_noagp; 668extern int nouveau_duallink; 669extern int nouveau_uscript_lvds; 670extern int nouveau_uscript_tmds; 671extern int nouveau_vram_pushbuf; 672extern int nouveau_vram_notify; 673extern int nouveau_fbpercrtc; 674extern char *nouveau_tv_norm; 675extern int nouveau_reg_debug; 676extern char *nouveau_vbios; 677extern int nouveau_ctxfw; 678 679/* nouveau_state.c */ 680extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 681extern int nouveau_load(struct drm_device *, unsigned long flags); 682extern int nouveau_firstopen(struct drm_device *); 683extern void nouveau_lastclose(struct drm_device *); 684extern int nouveau_unload(struct drm_device *); 685extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 686 struct drm_file *); 687extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 688 struct drm_file *); 689extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 690 uint32_t reg, uint32_t mask, uint32_t val); 691extern bool nouveau_wait_for_idle(struct drm_device *); 692extern int nouveau_card_init(struct drm_device *); 693extern int nouveau_ioctl_card_init(struct drm_device *, void *data, 694 struct drm_file *); 695extern int nouveau_ioctl_suspend(struct drm_device *, void *data, 696 struct drm_file *); 697extern int nouveau_ioctl_resume(struct drm_device *, void *data, 698 struct drm_file *); 699 700/* nouveau_mem.c */ 701extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, 702 uint64_t size); 703extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, 704 uint64_t size, int align2, 705 struct drm_file *, int tail); 706extern void nouveau_mem_takedown(struct mem_block **heap); 707extern void nouveau_mem_free_block(struct mem_block *); 708extern uint64_t nouveau_mem_fb_amount(struct drm_device *); 709extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 710extern int nouveau_mem_init(struct drm_device *); 711extern int nouveau_mem_init_agp(struct drm_device *); 712extern void nouveau_mem_close(struct drm_device *); 713extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 714 uint32_t addr, 715 uint32_t size, 716 uint32_t pitch); 717extern void nv10_mem_expire_tiling(struct drm_device *dev, 718 struct nouveau_tile_reg *tile, 719 struct nouveau_fence *fence); 720extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 721 uint32_t size, uint32_t flags, 722 uint64_t phys); 723extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 724 uint32_t size); 725 726/* nouveau_notifier.c */ 727extern int nouveau_notifier_init_channel(struct nouveau_channel *); 728extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 729extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 730 int cout, uint32_t *offset); 731extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 732extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 733 struct drm_file *); 734extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 735 struct drm_file *); 736 737/* nouveau_channel.c */ 738extern struct drm_ioctl_desc nouveau_ioctls[]; 739extern int nouveau_max_ioctl; 740extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 741extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 742 int channel); 743extern int nouveau_channel_alloc(struct drm_device *dev, 744 struct nouveau_channel **chan, 745 struct drm_file *file_priv, 746 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 747extern void nouveau_channel_free(struct nouveau_channel *); 748extern int nouveau_channel_idle(struct nouveau_channel *chan); 749 750/* nouveau_object.c */ 751extern int nouveau_gpuobj_early_init(struct drm_device *); 752extern int nouveau_gpuobj_init(struct drm_device *); 753extern void nouveau_gpuobj_takedown(struct drm_device *); 754extern void nouveau_gpuobj_late_takedown(struct drm_device *); 755extern int nouveau_gpuobj_suspend(struct drm_device *dev); 756extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 757extern void nouveau_gpuobj_resume(struct drm_device *dev); 758extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 759 uint32_t vram_h, uint32_t tt_h); 760extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 761extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 762 uint32_t size, int align, uint32_t flags, 763 struct nouveau_gpuobj **); 764extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 765extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 766 uint32_t handle, struct nouveau_gpuobj *, 767 struct nouveau_gpuobj_ref **); 768extern int nouveau_gpuobj_ref_del(struct drm_device *, 769 struct nouveau_gpuobj_ref **); 770extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 771 struct nouveau_gpuobj_ref **ref_ret); 772extern int nouveau_gpuobj_new_ref(struct drm_device *, 773 struct nouveau_channel *alloc_chan, 774 struct nouveau_channel *ref_chan, 775 uint32_t handle, uint32_t size, int align, 776 uint32_t flags, struct nouveau_gpuobj_ref **); 777extern int nouveau_gpuobj_new_fake(struct drm_device *, 778 uint32_t p_offset, uint32_t b_offset, 779 uint32_t size, uint32_t flags, 780 struct nouveau_gpuobj **, 781 struct nouveau_gpuobj_ref**); 782extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 783 uint64_t offset, uint64_t size, int access, 784 int target, struct nouveau_gpuobj **); 785extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 786 uint64_t offset, uint64_t size, 787 int access, struct nouveau_gpuobj **, 788 uint32_t *o_ret); 789extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 790 struct nouveau_gpuobj **); 791extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 792 struct drm_file *); 793extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 794 struct drm_file *); 795 796/* nouveau_irq.c */ 797extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 798extern void nouveau_irq_preinstall(struct drm_device *); 799extern int nouveau_irq_postinstall(struct drm_device *); 800extern void nouveau_irq_uninstall(struct drm_device *); 801 802/* nouveau_sgdma.c */ 803extern int nouveau_sgdma_init(struct drm_device *); 804extern void nouveau_sgdma_takedown(struct drm_device *); 805extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 806 uint32_t *page); 807extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 808 809/* nouveau_debugfs.c */ 810#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 811extern int nouveau_debugfs_init(struct drm_minor *); 812extern void nouveau_debugfs_takedown(struct drm_minor *); 813extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 814extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 815#else 816static inline int 817nouveau_debugfs_init(struct drm_minor *minor) 818{ 819 return 0; 820} 821 822static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 823{ 824} 825 826static inline int 827nouveau_debugfs_channel_init(struct nouveau_channel *chan) 828{ 829 return 0; 830} 831 832static inline void 833nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 834{ 835} 836#endif 837 838/* nouveau_dma.c */ 839extern int nouveau_dma_init(struct nouveau_channel *); 840extern int nouveau_dma_wait(struct nouveau_channel *, int size); 841 842/* nouveau_acpi.c */ 843#ifdef CONFIG_ACPI 844extern int nouveau_hybrid_setup(struct drm_device *dev); 845extern bool nouveau_dsm_probe(struct drm_device *dev); 846#else 847static inline int nouveau_hybrid_setup(struct drm_device *dev) 848{ 849 return 0; 850} 851static inline bool nouveau_dsm_probe(struct drm_device *dev) 852{ 853 return false; 854} 855#endif 856 857/* nouveau_backlight.c */ 858#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 859extern int nouveau_backlight_init(struct drm_device *); 860extern void nouveau_backlight_exit(struct drm_device *); 861#else 862static inline int nouveau_backlight_init(struct drm_device *dev) 863{ 864 return 0; 865} 866 867static inline void nouveau_backlight_exit(struct drm_device *dev) { } 868#endif 869 870/* nouveau_bios.c */ 871extern int nouveau_bios_init(struct drm_device *); 872extern void nouveau_bios_takedown(struct drm_device *dev); 873extern int nouveau_run_vbios_init(struct drm_device *); 874extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 875 struct dcb_entry *); 876extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 877 enum dcb_gpio_tag); 878extern struct dcb_connector_table_entry * 879nouveau_bios_connector_entry(struct drm_device *, int index); 880extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 881 struct pll_lims *); 882extern int nouveau_bios_run_display_table(struct drm_device *, 883 struct dcb_entry *, 884 uint32_t script, int pxclk); 885extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 886 int *length); 887extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 888extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 889extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 890 bool *dl, bool *if_is_24bit); 891extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 892 int head, int pxclk); 893extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 894 enum LVDS_script, int pxclk); 895 896/* nouveau_ttm.c */ 897int nouveau_ttm_global_init(struct drm_nouveau_private *); 898void nouveau_ttm_global_release(struct drm_nouveau_private *); 899int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 900 901/* nouveau_dp.c */ 902int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 903 uint8_t *data, int data_nr); 904bool nouveau_dp_detect(struct drm_encoder *); 905bool nouveau_dp_link_train(struct drm_encoder *); 906 907/* nv04_fb.c */ 908extern int nv04_fb_init(struct drm_device *); 909extern void nv04_fb_takedown(struct drm_device *); 910 911/* nv10_fb.c */ 912extern int nv10_fb_init(struct drm_device *); 913extern void nv10_fb_takedown(struct drm_device *); 914extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 915 uint32_t, uint32_t); 916 917/* nv40_fb.c */ 918extern int nv40_fb_init(struct drm_device *); 919extern void nv40_fb_takedown(struct drm_device *); 920extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 921 uint32_t, uint32_t); 922 923/* nv04_fifo.c */ 924extern int nv04_fifo_init(struct drm_device *); 925extern void nv04_fifo_disable(struct drm_device *); 926extern void nv04_fifo_enable(struct drm_device *); 927extern bool nv04_fifo_reassign(struct drm_device *, bool); 928extern bool nv04_fifo_cache_flush(struct drm_device *); 929extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 930extern int nv04_fifo_channel_id(struct drm_device *); 931extern int nv04_fifo_create_context(struct nouveau_channel *); 932extern void nv04_fifo_destroy_context(struct nouveau_channel *); 933extern int nv04_fifo_load_context(struct nouveau_channel *); 934extern int nv04_fifo_unload_context(struct drm_device *); 935 936/* nv10_fifo.c */ 937extern int nv10_fifo_init(struct drm_device *); 938extern int nv10_fifo_channel_id(struct drm_device *); 939extern int nv10_fifo_create_context(struct nouveau_channel *); 940extern void nv10_fifo_destroy_context(struct nouveau_channel *); 941extern int nv10_fifo_load_context(struct nouveau_channel *); 942extern int nv10_fifo_unload_context(struct drm_device *); 943 944/* nv40_fifo.c */ 945extern int nv40_fifo_init(struct drm_device *); 946extern int nv40_fifo_create_context(struct nouveau_channel *); 947extern void nv40_fifo_destroy_context(struct nouveau_channel *); 948extern int nv40_fifo_load_context(struct nouveau_channel *); 949extern int nv40_fifo_unload_context(struct drm_device *); 950 951/* nv50_fifo.c */ 952extern int nv50_fifo_init(struct drm_device *); 953extern void nv50_fifo_takedown(struct drm_device *); 954extern int nv50_fifo_channel_id(struct drm_device *); 955extern int nv50_fifo_create_context(struct nouveau_channel *); 956extern void nv50_fifo_destroy_context(struct nouveau_channel *); 957extern int nv50_fifo_load_context(struct nouveau_channel *); 958extern int nv50_fifo_unload_context(struct drm_device *); 959 960/* nv04_graph.c */ 961extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 962extern int nv04_graph_init(struct drm_device *); 963extern void nv04_graph_takedown(struct drm_device *); 964extern void nv04_graph_fifo_access(struct drm_device *, bool); 965extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 966extern int nv04_graph_create_context(struct nouveau_channel *); 967extern void nv04_graph_destroy_context(struct nouveau_channel *); 968extern int nv04_graph_load_context(struct nouveau_channel *); 969extern int nv04_graph_unload_context(struct drm_device *); 970extern void nv04_graph_context_switch(struct drm_device *); 971 972/* nv10_graph.c */ 973extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 974extern int nv10_graph_init(struct drm_device *); 975extern void nv10_graph_takedown(struct drm_device *); 976extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 977extern int nv10_graph_create_context(struct nouveau_channel *); 978extern void nv10_graph_destroy_context(struct nouveau_channel *); 979extern int nv10_graph_load_context(struct nouveau_channel *); 980extern int nv10_graph_unload_context(struct drm_device *); 981extern void nv10_graph_context_switch(struct drm_device *); 982extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 983 uint32_t, uint32_t); 984 985/* nv20_graph.c */ 986extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 987extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 988extern int nv20_graph_create_context(struct nouveau_channel *); 989extern void nv20_graph_destroy_context(struct nouveau_channel *); 990extern int nv20_graph_load_context(struct nouveau_channel *); 991extern int nv20_graph_unload_context(struct drm_device *); 992extern int nv20_graph_init(struct drm_device *); 993extern void nv20_graph_takedown(struct drm_device *); 994extern int nv30_graph_init(struct drm_device *); 995extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 996 uint32_t, uint32_t); 997 998/* nv40_graph.c */ 999extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1000extern int nv40_graph_init(struct drm_device *); 1001extern void nv40_graph_takedown(struct drm_device *); 1002extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1003extern int nv40_graph_create_context(struct nouveau_channel *); 1004extern void nv40_graph_destroy_context(struct nouveau_channel *); 1005extern int nv40_graph_load_context(struct nouveau_channel *); 1006extern int nv40_graph_unload_context(struct drm_device *); 1007extern void nv40_grctx_init(struct nouveau_grctx *); 1008extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1009 uint32_t, uint32_t); 1010 1011/* nv50_graph.c */ 1012extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1013extern int nv50_graph_init(struct drm_device *); 1014extern void nv50_graph_takedown(struct drm_device *); 1015extern void nv50_graph_fifo_access(struct drm_device *, bool); 1016extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1017extern int nv50_graph_create_context(struct nouveau_channel *); 1018extern void nv50_graph_destroy_context(struct nouveau_channel *); 1019extern int nv50_graph_load_context(struct nouveau_channel *); 1020extern int nv50_graph_unload_context(struct drm_device *); 1021extern void nv50_graph_context_switch(struct drm_device *); 1022 1023/* nouveau_grctx.c */ 1024extern int nouveau_grctx_prog_load(struct drm_device *); 1025extern void nouveau_grctx_vals_load(struct drm_device *, 1026 struct nouveau_gpuobj *); 1027extern void nouveau_grctx_fini(struct drm_device *); 1028 1029/* nv04_instmem.c */ 1030extern int nv04_instmem_init(struct drm_device *); 1031extern void nv04_instmem_takedown(struct drm_device *); 1032extern int nv04_instmem_suspend(struct drm_device *); 1033extern void nv04_instmem_resume(struct drm_device *); 1034extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1035 uint32_t *size); 1036extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1037extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1038extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1039extern void nv04_instmem_prepare_access(struct drm_device *, bool write); 1040extern void nv04_instmem_finish_access(struct drm_device *); 1041 1042/* nv50_instmem.c */ 1043extern int nv50_instmem_init(struct drm_device *); 1044extern void nv50_instmem_takedown(struct drm_device *); 1045extern int nv50_instmem_suspend(struct drm_device *); 1046extern void nv50_instmem_resume(struct drm_device *); 1047extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1048 uint32_t *size); 1049extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1050extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1051extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1052extern void nv50_instmem_prepare_access(struct drm_device *, bool write); 1053extern void nv50_instmem_finish_access(struct drm_device *); 1054 1055/* nv04_mc.c */ 1056extern int nv04_mc_init(struct drm_device *); 1057extern void nv04_mc_takedown(struct drm_device *); 1058 1059/* nv40_mc.c */ 1060extern int nv40_mc_init(struct drm_device *); 1061extern void nv40_mc_takedown(struct drm_device *); 1062 1063/* nv50_mc.c */ 1064extern int nv50_mc_init(struct drm_device *); 1065extern void nv50_mc_takedown(struct drm_device *); 1066 1067/* nv04_timer.c */ 1068extern int nv04_timer_init(struct drm_device *); 1069extern uint64_t nv04_timer_read(struct drm_device *); 1070extern void nv04_timer_takedown(struct drm_device *); 1071 1072extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1073 unsigned long arg); 1074 1075/* nv04_dac.c */ 1076extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1077extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1078extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1079extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1080 1081/* nv04_dfp.c */ 1082extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry); 1083extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1084extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1085 int head, bool dl); 1086extern void nv04_dfp_disable(struct drm_device *dev, int head); 1087extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1088 1089/* nv04_tv.c */ 1090extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1091extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1092 1093/* nv17_tv.c */ 1094extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1095 1096/* nv04_display.c */ 1097extern int nv04_display_create(struct drm_device *); 1098extern void nv04_display_destroy(struct drm_device *); 1099extern void nv04_display_restore(struct drm_device *); 1100 1101/* nv04_crtc.c */ 1102extern int nv04_crtc_create(struct drm_device *, int index); 1103 1104/* nouveau_bo.c */ 1105extern struct ttm_bo_driver nouveau_bo_driver; 1106extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1107 int size, int align, uint32_t flags, 1108 uint32_t tile_mode, uint32_t tile_flags, 1109 bool no_vm, bool mappable, struct nouveau_bo **); 1110extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1111extern int nouveau_bo_unpin(struct nouveau_bo *); 1112extern int nouveau_bo_map(struct nouveau_bo *); 1113extern void nouveau_bo_unmap(struct nouveau_bo *); 1114extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); 1115extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1116extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1117extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1118extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1119 1120/* nouveau_fence.c */ 1121struct nouveau_fence; 1122extern int nouveau_fence_init(struct nouveau_channel *); 1123extern void nouveau_fence_fini(struct nouveau_channel *); 1124extern void nouveau_fence_update(struct nouveau_channel *); 1125extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1126 bool emit); 1127extern int nouveau_fence_emit(struct nouveau_fence *); 1128struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1129extern bool nouveau_fence_signalled(void *obj, void *arg); 1130extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1131extern int nouveau_fence_flush(void *obj, void *arg); 1132extern void nouveau_fence_unref(void **obj); 1133extern void *nouveau_fence_ref(void *obj); 1134extern void nouveau_fence_handler(struct drm_device *dev, int channel); 1135 1136/* nouveau_gem.c */ 1137extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1138 int size, int align, uint32_t flags, 1139 uint32_t tile_mode, uint32_t tile_flags, 1140 bool no_vm, bool mappable, struct nouveau_bo **); 1141extern int nouveau_gem_object_new(struct drm_gem_object *); 1142extern void nouveau_gem_object_del(struct drm_gem_object *); 1143extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1144 struct drm_file *); 1145extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1146 struct drm_file *); 1147extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *, 1148 struct drm_file *); 1149extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *, 1150 struct drm_file *); 1151extern int nouveau_gem_ioctl_pin(struct drm_device *, void *, 1152 struct drm_file *); 1153extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *, 1154 struct drm_file *); 1155extern int nouveau_gem_ioctl_tile(struct drm_device *, void *, 1156 struct drm_file *); 1157extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1158 struct drm_file *); 1159extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1160 struct drm_file *); 1161extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1162 struct drm_file *); 1163 1164/* nv17_gpio.c */ 1165int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1166int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1167 1168#ifndef ioread32_native 1169#ifdef __BIG_ENDIAN 1170#define ioread16_native ioread16be 1171#define iowrite16_native iowrite16be 1172#define ioread32_native ioread32be 1173#define iowrite32_native iowrite32be 1174#else /* def __BIG_ENDIAN */ 1175#define ioread16_native ioread16 1176#define iowrite16_native iowrite16 1177#define ioread32_native ioread32 1178#define iowrite32_native iowrite32 1179#endif /* def __BIG_ENDIAN else */ 1180#endif /* !ioread32_native */ 1181 1182/* channel control reg access */ 1183static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1184{ 1185 return ioread32_native(chan->user + reg); 1186} 1187 1188static inline void nvchan_wr32(struct nouveau_channel *chan, 1189 unsigned reg, u32 val) 1190{ 1191 iowrite32_native(val, chan->user + reg); 1192} 1193 1194/* register access */ 1195static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1196{ 1197 struct drm_nouveau_private *dev_priv = dev->dev_private; 1198 return ioread32_native(dev_priv->mmio + reg); 1199} 1200 1201static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1202{ 1203 struct drm_nouveau_private *dev_priv = dev->dev_private; 1204 iowrite32_native(val, dev_priv->mmio + reg); 1205} 1206 1207static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1208{ 1209 struct drm_nouveau_private *dev_priv = dev->dev_private; 1210 return ioread8(dev_priv->mmio + reg); 1211} 1212 1213static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1214{ 1215 struct drm_nouveau_private *dev_priv = dev->dev_private; 1216 iowrite8(val, dev_priv->mmio + reg); 1217} 1218 1219#define nv_wait(reg, mask, val) \ 1220 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1221 1222/* PRAMIN access */ 1223static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1224{ 1225 struct drm_nouveau_private *dev_priv = dev->dev_private; 1226 return ioread32_native(dev_priv->ramin + offset); 1227} 1228 1229static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1230{ 1231 struct drm_nouveau_private *dev_priv = dev->dev_private; 1232 iowrite32_native(val, dev_priv->ramin + offset); 1233} 1234 1235/* object access */ 1236static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1237 unsigned index) 1238{ 1239 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1240} 1241 1242static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1243 unsigned index, u32 val) 1244{ 1245 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1246} 1247 1248/* 1249 * Logging 1250 * Argument d is (struct drm_device *). 1251 */ 1252#define NV_PRINTK(level, d, fmt, arg...) \ 1253 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1254 pci_name(d->pdev), ##arg) 1255#ifndef NV_DEBUG_NOTRACE 1256#define NV_DEBUG(d, fmt, arg...) do { \ 1257 if (drm_debug & DRM_UT_DRIVER) { \ 1258 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1259 __LINE__, ##arg); \ 1260 } \ 1261} while (0) 1262#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1263 if (drm_debug & DRM_UT_KMS) { \ 1264 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1265 __LINE__, ##arg); \ 1266 } \ 1267} while (0) 1268#else 1269#define NV_DEBUG(d, fmt, arg...) do { \ 1270 if (drm_debug & DRM_UT_DRIVER) \ 1271 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1272} while (0) 1273#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1274 if (drm_debug & DRM_UT_KMS) \ 1275 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1276} while (0) 1277#endif 1278#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1279#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1280#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1281#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1282#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1283 1284/* nouveau_reg_debug bitmask */ 1285enum { 1286 NOUVEAU_REG_DEBUG_MC = 0x1, 1287 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1288 NOUVEAU_REG_DEBUG_FB = 0x4, 1289 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1290 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1291 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1292 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1293 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1294 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1295 NOUVEAU_REG_DEBUG_EVO = 0x200, 1296}; 1297 1298#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1299 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1300 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1301} while (0) 1302 1303static inline bool 1304nv_two_heads(struct drm_device *dev) 1305{ 1306 struct drm_nouveau_private *dev_priv = dev->dev_private; 1307 const int impl = dev->pci_device & 0x0ff0; 1308 1309 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1310 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1311 return true; 1312 1313 return false; 1314} 1315 1316static inline bool 1317nv_gf4_disp_arch(struct drm_device *dev) 1318{ 1319 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1320} 1321 1322static inline bool 1323nv_two_reg_pll(struct drm_device *dev) 1324{ 1325 struct drm_nouveau_private *dev_priv = dev->dev_private; 1326 const int impl = dev->pci_device & 0x0ff0; 1327 1328 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1329 return true; 1330 return false; 1331} 1332 1333#define NV50_NVSW 0x0000506e 1334#define NV50_NVSW_DMA_SEMAPHORE 0x00000060 1335#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 1336#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 1337#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c 1338#define NV50_NVSW_DMA_VBLSEM 0x0000018c 1339#define NV50_NVSW_VBLSEM_OFFSET 0x00000400 1340#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 1341#define NV50_NVSW_VBLSEM_RELEASE 0x00000408 1342 1343#endif /* __NOUVEAU_DRV_H__ */ 1344