nouveau_drv.h revision 047d1d3cae2c4fc5be4fa20a97c8f5ba4fea1c56
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 138#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 139#define NVOBJ_FLAG_FAKE (1 << 3) 140struct nouveau_gpuobj { 141 struct list_head list; 142 143 struct nouveau_channel *im_channel; 144 struct drm_mm_node *im_pramin; 145 struct nouveau_bo *im_backing; 146 uint32_t im_backing_start; 147 uint32_t *im_backing_suspend; 148 int im_bound; 149 150 uint32_t flags; 151 int refcount; 152 153 uint32_t engine; 154 uint32_t class; 155 156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 157 void *priv; 158}; 159 160struct nouveau_gpuobj_ref { 161 struct list_head list; 162 163 struct nouveau_gpuobj *gpuobj; 164 uint32_t instance; 165 166 struct nouveau_channel *channel; 167 int handle; 168}; 169 170struct nouveau_channel { 171 struct drm_device *dev; 172 int id; 173 174 /* owner of this fifo */ 175 struct drm_file *file_priv; 176 /* mapping of the fifo itself */ 177 struct drm_local_map *map; 178 179 /* mapping of the regs controling the fifo */ 180 void __iomem *user; 181 uint32_t user_get; 182 uint32_t user_put; 183 184 /* Fencing */ 185 struct { 186 /* lock protects the pending list only */ 187 spinlock_t lock; 188 struct list_head pending; 189 uint32_t sequence; 190 uint32_t sequence_ack; 191 atomic_t last_sequence_irq; 192 } fence; 193 194 /* DMA push buffer */ 195 struct nouveau_gpuobj_ref *pushbuf; 196 struct nouveau_bo *pushbuf_bo; 197 uint32_t pushbuf_base; 198 199 /* Notifier memory */ 200 struct nouveau_bo *notifier_bo; 201 struct drm_mm notifier_heap; 202 203 /* PFIFO context */ 204 struct nouveau_gpuobj_ref *ramfc; 205 struct nouveau_gpuobj_ref *cache; 206 207 /* PGRAPH context */ 208 /* XXX may be merge 2 pointers as private data ??? */ 209 struct nouveau_gpuobj_ref *ramin_grctx; 210 void *pgraph_ctx; 211 212 /* NV50 VM */ 213 struct nouveau_gpuobj *vm_pd; 214 struct nouveau_gpuobj_ref *vm_gart_pt; 215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 216 217 /* Objects */ 218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 221 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 222 223 /* GPU object info for stuff used in-kernel (mm_enabled) */ 224 uint32_t m2mf_ntfy; 225 uint32_t vram_handle; 226 uint32_t gart_handle; 227 bool accel_done; 228 229 /* Push buffer state (only for drm's channel on !mm_enabled) */ 230 struct { 231 int max; 232 int free; 233 int cur; 234 int put; 235 /* access via pushbuf_bo */ 236 237 int ib_base; 238 int ib_max; 239 int ib_free; 240 int ib_put; 241 } dma; 242 243 uint32_t sw_subchannel[8]; 244 245 struct { 246 struct nouveau_gpuobj *vblsem; 247 uint32_t vblsem_offset; 248 uint32_t vblsem_rval; 249 struct list_head vbl_wait; 250 } nvsw; 251 252 struct { 253 bool active; 254 char name[32]; 255 struct drm_info_list info; 256 } debugfs; 257}; 258 259struct nouveau_instmem_engine { 260 void *priv; 261 262 int (*init)(struct drm_device *dev); 263 void (*takedown)(struct drm_device *dev); 264 int (*suspend)(struct drm_device *dev); 265 void (*resume)(struct drm_device *dev); 266 267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 268 uint32_t *size); 269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 272 void (*flush)(struct drm_device *); 273}; 274 275struct nouveau_mc_engine { 276 int (*init)(struct drm_device *dev); 277 void (*takedown)(struct drm_device *dev); 278}; 279 280struct nouveau_timer_engine { 281 int (*init)(struct drm_device *dev); 282 void (*takedown)(struct drm_device *dev); 283 uint64_t (*read)(struct drm_device *dev); 284}; 285 286struct nouveau_fb_engine { 287 int num_tiles; 288 289 int (*init)(struct drm_device *dev); 290 void (*takedown)(struct drm_device *dev); 291 292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 293 uint32_t size, uint32_t pitch); 294}; 295 296struct nouveau_fifo_engine { 297 int channels; 298 299 struct nouveau_gpuobj_ref *playlist[2]; 300 int cur_playlist; 301 302 int (*init)(struct drm_device *); 303 void (*takedown)(struct drm_device *); 304 305 void (*disable)(struct drm_device *); 306 void (*enable)(struct drm_device *); 307 bool (*reassign)(struct drm_device *, bool enable); 308 bool (*cache_flush)(struct drm_device *dev); 309 bool (*cache_pull)(struct drm_device *dev, bool enable); 310 311 int (*channel_id)(struct drm_device *); 312 313 int (*create_context)(struct nouveau_channel *); 314 void (*destroy_context)(struct nouveau_channel *); 315 int (*load_context)(struct nouveau_channel *); 316 int (*unload_context)(struct drm_device *); 317}; 318 319struct nouveau_pgraph_object_method { 320 int id; 321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 322 uint32_t data); 323}; 324 325struct nouveau_pgraph_object_class { 326 int id; 327 bool software; 328 struct nouveau_pgraph_object_method *methods; 329}; 330 331struct nouveau_pgraph_engine { 332 struct nouveau_pgraph_object_class *grclass; 333 bool accel_blocked; 334 int grctx_size; 335 336 /* NV2x/NV3x context table (0x400780) */ 337 struct nouveau_gpuobj_ref *ctx_table; 338 339 int (*init)(struct drm_device *); 340 void (*takedown)(struct drm_device *); 341 342 void (*fifo_access)(struct drm_device *, bool); 343 344 struct nouveau_channel *(*channel)(struct drm_device *); 345 int (*create_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *); 348 int (*unload_context)(struct drm_device *); 349 350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 351 uint32_t size, uint32_t pitch); 352}; 353 354struct nouveau_engine { 355 struct nouveau_instmem_engine instmem; 356 struct nouveau_mc_engine mc; 357 struct nouveau_timer_engine timer; 358 struct nouveau_fb_engine fb; 359 struct nouveau_pgraph_engine graph; 360 struct nouveau_fifo_engine fifo; 361}; 362 363struct nouveau_pll_vals { 364 union { 365 struct { 366#ifdef __BIG_ENDIAN 367 uint8_t N1, M1, N2, M2; 368#else 369 uint8_t M1, N1, M2, N2; 370#endif 371 }; 372 struct { 373 uint16_t NM1, NM2; 374 } __attribute__((packed)); 375 }; 376 int log2P; 377 378 int refclk; 379}; 380 381enum nv04_fp_display_regs { 382 FP_DISPLAY_END, 383 FP_TOTAL, 384 FP_CRTC, 385 FP_SYNC_START, 386 FP_SYNC_END, 387 FP_VALID_START, 388 FP_VALID_END 389}; 390 391struct nv04_crtc_reg { 392 unsigned char MiscOutReg; /* */ 393 uint8_t CRTC[0x9f]; 394 uint8_t CR58[0x10]; 395 uint8_t Sequencer[5]; 396 uint8_t Graphics[9]; 397 uint8_t Attribute[21]; 398 unsigned char DAC[768]; /* Internal Colorlookuptable */ 399 400 /* PCRTC regs */ 401 uint32_t fb_start; 402 uint32_t crtc_cfg; 403 uint32_t cursor_cfg; 404 uint32_t gpio_ext; 405 uint32_t crtc_830; 406 uint32_t crtc_834; 407 uint32_t crtc_850; 408 uint32_t crtc_eng_ctrl; 409 410 /* PRAMDAC regs */ 411 uint32_t nv10_cursync; 412 struct nouveau_pll_vals pllvals; 413 uint32_t ramdac_gen_ctrl; 414 uint32_t ramdac_630; 415 uint32_t ramdac_634; 416 uint32_t tv_setup; 417 uint32_t tv_vtotal; 418 uint32_t tv_vskew; 419 uint32_t tv_vsync_delay; 420 uint32_t tv_htotal; 421 uint32_t tv_hskew; 422 uint32_t tv_hsync_delay; 423 uint32_t tv_hsync_delay2; 424 uint32_t fp_horiz_regs[7]; 425 uint32_t fp_vert_regs[7]; 426 uint32_t dither; 427 uint32_t fp_control; 428 uint32_t dither_regs[6]; 429 uint32_t fp_debug_0; 430 uint32_t fp_debug_1; 431 uint32_t fp_debug_2; 432 uint32_t fp_margin_color; 433 uint32_t ramdac_8c0; 434 uint32_t ramdac_a20; 435 uint32_t ramdac_a24; 436 uint32_t ramdac_a34; 437 uint32_t ctv_regs[38]; 438}; 439 440struct nv04_output_reg { 441 uint32_t output; 442 int head; 443}; 444 445struct nv04_mode_state { 446 uint32_t bpp; 447 uint32_t width; 448 uint32_t height; 449 uint32_t interlace; 450 uint32_t repaint0; 451 uint32_t repaint1; 452 uint32_t screen; 453 uint32_t scale; 454 uint32_t dither; 455 uint32_t extra; 456 uint32_t fifo; 457 uint32_t pixel; 458 uint32_t horiz; 459 int arbitration0; 460 int arbitration1; 461 uint32_t pll; 462 uint32_t pllB; 463 uint32_t vpll; 464 uint32_t vpll2; 465 uint32_t vpllB; 466 uint32_t vpll2B; 467 uint32_t pllsel; 468 uint32_t sel_clk; 469 uint32_t general; 470 uint32_t crtcOwner; 471 uint32_t head; 472 uint32_t head2; 473 uint32_t cursorConfig; 474 uint32_t cursor0; 475 uint32_t cursor1; 476 uint32_t cursor2; 477 uint32_t timingH; 478 uint32_t timingV; 479 uint32_t displayV; 480 uint32_t crtcSync; 481 482 struct nv04_crtc_reg crtc_reg[2]; 483}; 484 485enum nouveau_card_type { 486 NV_04 = 0x00, 487 NV_10 = 0x10, 488 NV_20 = 0x20, 489 NV_30 = 0x30, 490 NV_40 = 0x40, 491 NV_50 = 0x50, 492}; 493 494struct drm_nouveau_private { 495 struct drm_device *dev; 496 497 /* the card type, takes NV_* as values */ 498 enum nouveau_card_type card_type; 499 /* exact chipset, derived from NV_PMC_BOOT_0 */ 500 int chipset; 501 int flags; 502 503 void __iomem *mmio; 504 void __iomem *ramin; 505 uint32_t ramin_size; 506 507 struct nouveau_bo *vga_ram; 508 509 struct workqueue_struct *wq; 510 struct work_struct irq_work; 511 struct work_struct hpd_work; 512 513 struct list_head vbl_waiting; 514 515 struct { 516 struct ttm_global_reference mem_global_ref; 517 struct ttm_bo_global_ref bo_global_ref; 518 struct ttm_bo_device bdev; 519 spinlock_t bo_list_lock; 520 struct list_head bo_list; 521 atomic_t validate_sequence; 522 } ttm; 523 524 int fifo_alloc_count; 525 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 526 527 struct nouveau_engine engine; 528 struct nouveau_channel *channel; 529 530 /* For PFIFO and PGRAPH. */ 531 spinlock_t context_switch_lock; 532 533 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 534 struct nouveau_gpuobj *ramht; 535 uint32_t ramin_rsvd_vram; 536 uint32_t ramht_offset; 537 uint32_t ramht_size; 538 uint32_t ramht_bits; 539 uint32_t ramfc_offset; 540 uint32_t ramfc_size; 541 uint32_t ramro_offset; 542 uint32_t ramro_size; 543 544 struct { 545 enum { 546 NOUVEAU_GART_NONE = 0, 547 NOUVEAU_GART_AGP, 548 NOUVEAU_GART_SGDMA 549 } type; 550 uint64_t aper_base; 551 uint64_t aper_size; 552 uint64_t aper_free; 553 554 struct nouveau_gpuobj *sg_ctxdma; 555 struct page *sg_dummy_page; 556 dma_addr_t sg_dummy_bus; 557 } gart_info; 558 559 /* nv10-nv40 tiling regions */ 560 struct { 561 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 562 spinlock_t lock; 563 } tile; 564 565 /* VRAM/fb configuration */ 566 uint64_t vram_size; 567 uint64_t vram_sys_base; 568 569 uint64_t fb_phys; 570 uint64_t fb_available_size; 571 uint64_t fb_mappable_pages; 572 uint64_t fb_aper_free; 573 int fb_mtrr; 574 575 /* G8x/G9x virtual address space */ 576 uint64_t vm_gart_base; 577 uint64_t vm_gart_size; 578 uint64_t vm_vram_base; 579 uint64_t vm_vram_size; 580 uint64_t vm_end; 581 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 582 int vm_vram_pt_nr; 583 584 struct drm_mm ramin_heap; 585 586 struct list_head gpuobj_list; 587 588 struct nvbios vbios; 589 590 struct nv04_mode_state mode_reg; 591 struct nv04_mode_state saved_reg; 592 uint32_t saved_vga_font[4][16384]; 593 uint32_t crtc_owner; 594 uint32_t dac_users[4]; 595 596 struct nouveau_suspend_resume { 597 uint32_t *ramin_copy; 598 } susres; 599 600 struct backlight_device *backlight; 601 602 struct nouveau_channel *evo; 603 struct { 604 struct dcb_entry *dcb; 605 u16 script; 606 u32 pclk; 607 } evo_irq; 608 609 struct { 610 struct dentry *channel_root; 611 } debugfs; 612 613 struct nouveau_fbdev *nfbdev; 614 struct apertures_struct *apertures; 615}; 616 617static inline struct drm_nouveau_private * 618nouveau_bdev(struct ttm_bo_device *bd) 619{ 620 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 621} 622 623static inline int 624nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 625{ 626 struct nouveau_bo *prev; 627 628 if (!pnvbo) 629 return -EINVAL; 630 prev = *pnvbo; 631 632 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 633 if (prev) { 634 struct ttm_buffer_object *bo = &prev->bo; 635 636 ttm_bo_unref(&bo); 637 } 638 639 return 0; 640} 641 642#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 643 struct drm_nouveau_private *nv = dev->dev_private; \ 644 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 645 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 646 DRM_CURRENTPID, (id)); \ 647 return -EPERM; \ 648 } \ 649 (ch) = nv->fifos[(id)]; \ 650} while (0) 651 652/* nouveau_drv.c */ 653extern int nouveau_noagp; 654extern int nouveau_duallink; 655extern int nouveau_uscript_lvds; 656extern int nouveau_uscript_tmds; 657extern int nouveau_vram_pushbuf; 658extern int nouveau_vram_notify; 659extern int nouveau_fbpercrtc; 660extern int nouveau_tv_disable; 661extern char *nouveau_tv_norm; 662extern int nouveau_reg_debug; 663extern char *nouveau_vbios; 664extern int nouveau_ignorelid; 665extern int nouveau_nofbaccel; 666extern int nouveau_noaccel; 667extern int nouveau_override_conntype; 668 669extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 670extern int nouveau_pci_resume(struct pci_dev *pdev); 671 672/* nouveau_state.c */ 673extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 674extern int nouveau_load(struct drm_device *, unsigned long flags); 675extern int nouveau_firstopen(struct drm_device *); 676extern void nouveau_lastclose(struct drm_device *); 677extern int nouveau_unload(struct drm_device *); 678extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 679 struct drm_file *); 680extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 681 struct drm_file *); 682extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 683 uint32_t reg, uint32_t mask, uint32_t val); 684extern bool nouveau_wait_for_idle(struct drm_device *); 685extern int nouveau_card_init(struct drm_device *); 686 687/* nouveau_mem.c */ 688extern int nouveau_mem_detect(struct drm_device *dev); 689extern int nouveau_mem_init(struct drm_device *); 690extern int nouveau_mem_init_agp(struct drm_device *); 691extern void nouveau_mem_close(struct drm_device *); 692extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 693 uint32_t addr, 694 uint32_t size, 695 uint32_t pitch); 696extern void nv10_mem_expire_tiling(struct drm_device *dev, 697 struct nouveau_tile_reg *tile, 698 struct nouveau_fence *fence); 699extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 700 uint32_t size, uint32_t flags, 701 uint64_t phys); 702extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 703 uint32_t size); 704 705/* nouveau_notifier.c */ 706extern int nouveau_notifier_init_channel(struct nouveau_channel *); 707extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 708extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 709 int cout, uint32_t *offset); 710extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 711extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 712 struct drm_file *); 713extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 714 struct drm_file *); 715 716/* nouveau_channel.c */ 717extern struct drm_ioctl_desc nouveau_ioctls[]; 718extern int nouveau_max_ioctl; 719extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 720extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 721 int channel); 722extern int nouveau_channel_alloc(struct drm_device *dev, 723 struct nouveau_channel **chan, 724 struct drm_file *file_priv, 725 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 726extern void nouveau_channel_free(struct nouveau_channel *); 727 728/* nouveau_object.c */ 729extern int nouveau_gpuobj_early_init(struct drm_device *); 730extern int nouveau_gpuobj_init(struct drm_device *); 731extern void nouveau_gpuobj_takedown(struct drm_device *); 732extern void nouveau_gpuobj_late_takedown(struct drm_device *); 733extern int nouveau_gpuobj_suspend(struct drm_device *dev); 734extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 735extern void nouveau_gpuobj_resume(struct drm_device *dev); 736extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 737 uint32_t vram_h, uint32_t tt_h); 738extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 739extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 740 uint32_t size, int align, uint32_t flags, 741 struct nouveau_gpuobj **); 742extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 743extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 744 uint32_t handle, struct nouveau_gpuobj *, 745 struct nouveau_gpuobj_ref **); 746extern int nouveau_gpuobj_ref_del(struct drm_device *, 747 struct nouveau_gpuobj_ref **); 748extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 749 struct nouveau_gpuobj_ref **ref_ret); 750extern int nouveau_gpuobj_new_ref(struct drm_device *, 751 struct nouveau_channel *alloc_chan, 752 struct nouveau_channel *ref_chan, 753 uint32_t handle, uint32_t size, int align, 754 uint32_t flags, struct nouveau_gpuobj_ref **); 755extern int nouveau_gpuobj_new_fake(struct drm_device *, 756 uint32_t p_offset, uint32_t b_offset, 757 uint32_t size, uint32_t flags, 758 struct nouveau_gpuobj **, 759 struct nouveau_gpuobj_ref**); 760extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 761 uint64_t offset, uint64_t size, int access, 762 int target, struct nouveau_gpuobj **); 763extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 764 uint64_t offset, uint64_t size, 765 int access, struct nouveau_gpuobj **, 766 uint32_t *o_ret); 767extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 768 struct nouveau_gpuobj **); 769extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 770 struct nouveau_gpuobj **); 771extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 772 struct drm_file *); 773extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 774 struct drm_file *); 775 776/* nouveau_irq.c */ 777extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 778extern void nouveau_irq_preinstall(struct drm_device *); 779extern int nouveau_irq_postinstall(struct drm_device *); 780extern void nouveau_irq_uninstall(struct drm_device *); 781 782/* nouveau_sgdma.c */ 783extern int nouveau_sgdma_init(struct drm_device *); 784extern void nouveau_sgdma_takedown(struct drm_device *); 785extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 786 uint32_t *page); 787extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 788 789/* nouveau_debugfs.c */ 790#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 791extern int nouveau_debugfs_init(struct drm_minor *); 792extern void nouveau_debugfs_takedown(struct drm_minor *); 793extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 794extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 795#else 796static inline int 797nouveau_debugfs_init(struct drm_minor *minor) 798{ 799 return 0; 800} 801 802static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 803{ 804} 805 806static inline int 807nouveau_debugfs_channel_init(struct nouveau_channel *chan) 808{ 809 return 0; 810} 811 812static inline void 813nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 814{ 815} 816#endif 817 818/* nouveau_dma.c */ 819extern void nouveau_dma_pre_init(struct nouveau_channel *); 820extern int nouveau_dma_init(struct nouveau_channel *); 821extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 822 823/* nouveau_acpi.c */ 824#define ROM_BIOS_PAGE 4096 825#if defined(CONFIG_ACPI) 826void nouveau_register_dsm_handler(void); 827void nouveau_unregister_dsm_handler(void); 828int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 829bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 830#else 831static inline void nouveau_register_dsm_handler(void) {} 832static inline void nouveau_unregister_dsm_handler(void) {} 833static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 834static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 835#endif 836 837/* nouveau_backlight.c */ 838#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 839extern int nouveau_backlight_init(struct drm_device *); 840extern void nouveau_backlight_exit(struct drm_device *); 841#else 842static inline int nouveau_backlight_init(struct drm_device *dev) 843{ 844 return 0; 845} 846 847static inline void nouveau_backlight_exit(struct drm_device *dev) { } 848#endif 849 850/* nouveau_bios.c */ 851extern int nouveau_bios_init(struct drm_device *); 852extern void nouveau_bios_takedown(struct drm_device *dev); 853extern int nouveau_run_vbios_init(struct drm_device *); 854extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 855 struct dcb_entry *); 856extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 857 enum dcb_gpio_tag); 858extern struct dcb_connector_table_entry * 859nouveau_bios_connector_entry(struct drm_device *, int index); 860extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 861 struct pll_lims *); 862extern int nouveau_bios_run_display_table(struct drm_device *, 863 struct dcb_entry *, 864 uint32_t script, int pxclk); 865extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 866 int *length); 867extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 868extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 869extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 870 bool *dl, bool *if_is_24bit); 871extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 872 int head, int pxclk); 873extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 874 enum LVDS_script, int pxclk); 875 876/* nouveau_ttm.c */ 877int nouveau_ttm_global_init(struct drm_nouveau_private *); 878void nouveau_ttm_global_release(struct drm_nouveau_private *); 879int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 880 881/* nouveau_dp.c */ 882int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 883 uint8_t *data, int data_nr); 884bool nouveau_dp_detect(struct drm_encoder *); 885bool nouveau_dp_link_train(struct drm_encoder *); 886 887/* nv04_fb.c */ 888extern int nv04_fb_init(struct drm_device *); 889extern void nv04_fb_takedown(struct drm_device *); 890 891/* nv10_fb.c */ 892extern int nv10_fb_init(struct drm_device *); 893extern void nv10_fb_takedown(struct drm_device *); 894extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 895 uint32_t, uint32_t); 896 897/* nv40_fb.c */ 898extern int nv40_fb_init(struct drm_device *); 899extern void nv40_fb_takedown(struct drm_device *); 900extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 901 uint32_t, uint32_t); 902 903/* nv50_fb.c */ 904extern int nv50_fb_init(struct drm_device *); 905extern void nv50_fb_takedown(struct drm_device *); 906 907/* nv04_fifo.c */ 908extern int nv04_fifo_init(struct drm_device *); 909extern void nv04_fifo_disable(struct drm_device *); 910extern void nv04_fifo_enable(struct drm_device *); 911extern bool nv04_fifo_reassign(struct drm_device *, bool); 912extern bool nv04_fifo_cache_flush(struct drm_device *); 913extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 914extern int nv04_fifo_channel_id(struct drm_device *); 915extern int nv04_fifo_create_context(struct nouveau_channel *); 916extern void nv04_fifo_destroy_context(struct nouveau_channel *); 917extern int nv04_fifo_load_context(struct nouveau_channel *); 918extern int nv04_fifo_unload_context(struct drm_device *); 919 920/* nv10_fifo.c */ 921extern int nv10_fifo_init(struct drm_device *); 922extern int nv10_fifo_channel_id(struct drm_device *); 923extern int nv10_fifo_create_context(struct nouveau_channel *); 924extern void nv10_fifo_destroy_context(struct nouveau_channel *); 925extern int nv10_fifo_load_context(struct nouveau_channel *); 926extern int nv10_fifo_unload_context(struct drm_device *); 927 928/* nv40_fifo.c */ 929extern int nv40_fifo_init(struct drm_device *); 930extern int nv40_fifo_create_context(struct nouveau_channel *); 931extern void nv40_fifo_destroy_context(struct nouveau_channel *); 932extern int nv40_fifo_load_context(struct nouveau_channel *); 933extern int nv40_fifo_unload_context(struct drm_device *); 934 935/* nv50_fifo.c */ 936extern int nv50_fifo_init(struct drm_device *); 937extern void nv50_fifo_takedown(struct drm_device *); 938extern int nv50_fifo_channel_id(struct drm_device *); 939extern int nv50_fifo_create_context(struct nouveau_channel *); 940extern void nv50_fifo_destroy_context(struct nouveau_channel *); 941extern int nv50_fifo_load_context(struct nouveau_channel *); 942extern int nv50_fifo_unload_context(struct drm_device *); 943 944/* nv04_graph.c */ 945extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 946extern int nv04_graph_init(struct drm_device *); 947extern void nv04_graph_takedown(struct drm_device *); 948extern void nv04_graph_fifo_access(struct drm_device *, bool); 949extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 950extern int nv04_graph_create_context(struct nouveau_channel *); 951extern void nv04_graph_destroy_context(struct nouveau_channel *); 952extern int nv04_graph_load_context(struct nouveau_channel *); 953extern int nv04_graph_unload_context(struct drm_device *); 954extern void nv04_graph_context_switch(struct drm_device *); 955 956/* nv10_graph.c */ 957extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 958extern int nv10_graph_init(struct drm_device *); 959extern void nv10_graph_takedown(struct drm_device *); 960extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 961extern int nv10_graph_create_context(struct nouveau_channel *); 962extern void nv10_graph_destroy_context(struct nouveau_channel *); 963extern int nv10_graph_load_context(struct nouveau_channel *); 964extern int nv10_graph_unload_context(struct drm_device *); 965extern void nv10_graph_context_switch(struct drm_device *); 966extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 967 uint32_t, uint32_t); 968 969/* nv20_graph.c */ 970extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 971extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 972extern int nv20_graph_create_context(struct nouveau_channel *); 973extern void nv20_graph_destroy_context(struct nouveau_channel *); 974extern int nv20_graph_load_context(struct nouveau_channel *); 975extern int nv20_graph_unload_context(struct drm_device *); 976extern int nv20_graph_init(struct drm_device *); 977extern void nv20_graph_takedown(struct drm_device *); 978extern int nv30_graph_init(struct drm_device *); 979extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 980 uint32_t, uint32_t); 981 982/* nv40_graph.c */ 983extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 984extern int nv40_graph_init(struct drm_device *); 985extern void nv40_graph_takedown(struct drm_device *); 986extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 987extern int nv40_graph_create_context(struct nouveau_channel *); 988extern void nv40_graph_destroy_context(struct nouveau_channel *); 989extern int nv40_graph_load_context(struct nouveau_channel *); 990extern int nv40_graph_unload_context(struct drm_device *); 991extern void nv40_grctx_init(struct nouveau_grctx *); 992extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 993 uint32_t, uint32_t); 994 995/* nv50_graph.c */ 996extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 997extern int nv50_graph_init(struct drm_device *); 998extern void nv50_graph_takedown(struct drm_device *); 999extern void nv50_graph_fifo_access(struct drm_device *, bool); 1000extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1001extern int nv50_graph_create_context(struct nouveau_channel *); 1002extern void nv50_graph_destroy_context(struct nouveau_channel *); 1003extern int nv50_graph_load_context(struct nouveau_channel *); 1004extern int nv50_graph_unload_context(struct drm_device *); 1005extern void nv50_graph_context_switch(struct drm_device *); 1006extern int nv50_grctx_init(struct nouveau_grctx *); 1007 1008/* nv04_instmem.c */ 1009extern int nv04_instmem_init(struct drm_device *); 1010extern void nv04_instmem_takedown(struct drm_device *); 1011extern int nv04_instmem_suspend(struct drm_device *); 1012extern void nv04_instmem_resume(struct drm_device *); 1013extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1014 uint32_t *size); 1015extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1016extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1017extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1018extern void nv04_instmem_flush(struct drm_device *); 1019 1020/* nv50_instmem.c */ 1021extern int nv50_instmem_init(struct drm_device *); 1022extern void nv50_instmem_takedown(struct drm_device *); 1023extern int nv50_instmem_suspend(struct drm_device *); 1024extern void nv50_instmem_resume(struct drm_device *); 1025extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1026 uint32_t *size); 1027extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1028extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1029extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1030extern void nv50_instmem_flush(struct drm_device *); 1031extern void nv50_vm_flush(struct drm_device *, int engine); 1032 1033/* nv04_mc.c */ 1034extern int nv04_mc_init(struct drm_device *); 1035extern void nv04_mc_takedown(struct drm_device *); 1036 1037/* nv40_mc.c */ 1038extern int nv40_mc_init(struct drm_device *); 1039extern void nv40_mc_takedown(struct drm_device *); 1040 1041/* nv50_mc.c */ 1042extern int nv50_mc_init(struct drm_device *); 1043extern void nv50_mc_takedown(struct drm_device *); 1044 1045/* nv04_timer.c */ 1046extern int nv04_timer_init(struct drm_device *); 1047extern uint64_t nv04_timer_read(struct drm_device *); 1048extern void nv04_timer_takedown(struct drm_device *); 1049 1050extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1051 unsigned long arg); 1052 1053/* nv04_dac.c */ 1054extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1055extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1056extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1057extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1058extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1059 1060/* nv04_dfp.c */ 1061extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1062extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1063extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1064 int head, bool dl); 1065extern void nv04_dfp_disable(struct drm_device *dev, int head); 1066extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1067 1068/* nv04_tv.c */ 1069extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1070extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1071 1072/* nv17_tv.c */ 1073extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1074 1075/* nv04_display.c */ 1076extern int nv04_display_create(struct drm_device *); 1077extern void nv04_display_destroy(struct drm_device *); 1078extern void nv04_display_restore(struct drm_device *); 1079 1080/* nv04_crtc.c */ 1081extern int nv04_crtc_create(struct drm_device *, int index); 1082 1083/* nouveau_bo.c */ 1084extern struct ttm_bo_driver nouveau_bo_driver; 1085extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1086 int size, int align, uint32_t flags, 1087 uint32_t tile_mode, uint32_t tile_flags, 1088 bool no_vm, bool mappable, struct nouveau_bo **); 1089extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1090extern int nouveau_bo_unpin(struct nouveau_bo *); 1091extern int nouveau_bo_map(struct nouveau_bo *); 1092extern void nouveau_bo_unmap(struct nouveau_bo *); 1093extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1094 uint32_t busy); 1095extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1096extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1097extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1098extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1099 1100/* nouveau_fence.c */ 1101struct nouveau_fence; 1102extern int nouveau_fence_init(struct nouveau_channel *); 1103extern void nouveau_fence_fini(struct nouveau_channel *); 1104extern void nouveau_fence_update(struct nouveau_channel *); 1105extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1106 bool emit); 1107extern int nouveau_fence_emit(struct nouveau_fence *); 1108struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1109extern bool nouveau_fence_signalled(void *obj, void *arg); 1110extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1111extern int nouveau_fence_flush(void *obj, void *arg); 1112extern void nouveau_fence_unref(void **obj); 1113extern void *nouveau_fence_ref(void *obj); 1114 1115/* nouveau_gem.c */ 1116extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1117 int size, int align, uint32_t flags, 1118 uint32_t tile_mode, uint32_t tile_flags, 1119 bool no_vm, bool mappable, struct nouveau_bo **); 1120extern int nouveau_gem_object_new(struct drm_gem_object *); 1121extern void nouveau_gem_object_del(struct drm_gem_object *); 1122extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1123 struct drm_file *); 1124extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1125 struct drm_file *); 1126extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1127 struct drm_file *); 1128extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1129 struct drm_file *); 1130extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1131 struct drm_file *); 1132 1133/* nv17_gpio.c */ 1134int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1135int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1136 1137/* nv50_gpio.c */ 1138int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1139int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1140 1141/* nv50_calc. */ 1142int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1143 int *N1, int *M1, int *N2, int *M2, int *P); 1144int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1145 int clk, int *N, int *fN, int *M, int *P); 1146 1147#ifndef ioread32_native 1148#ifdef __BIG_ENDIAN 1149#define ioread16_native ioread16be 1150#define iowrite16_native iowrite16be 1151#define ioread32_native ioread32be 1152#define iowrite32_native iowrite32be 1153#else /* def __BIG_ENDIAN */ 1154#define ioread16_native ioread16 1155#define iowrite16_native iowrite16 1156#define ioread32_native ioread32 1157#define iowrite32_native iowrite32 1158#endif /* def __BIG_ENDIAN else */ 1159#endif /* !ioread32_native */ 1160 1161/* channel control reg access */ 1162static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1163{ 1164 return ioread32_native(chan->user + reg); 1165} 1166 1167static inline void nvchan_wr32(struct nouveau_channel *chan, 1168 unsigned reg, u32 val) 1169{ 1170 iowrite32_native(val, chan->user + reg); 1171} 1172 1173/* register access */ 1174static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1175{ 1176 struct drm_nouveau_private *dev_priv = dev->dev_private; 1177 return ioread32_native(dev_priv->mmio + reg); 1178} 1179 1180static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1181{ 1182 struct drm_nouveau_private *dev_priv = dev->dev_private; 1183 iowrite32_native(val, dev_priv->mmio + reg); 1184} 1185 1186static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1187{ 1188 struct drm_nouveau_private *dev_priv = dev->dev_private; 1189 return ioread8(dev_priv->mmio + reg); 1190} 1191 1192static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1193{ 1194 struct drm_nouveau_private *dev_priv = dev->dev_private; 1195 iowrite8(val, dev_priv->mmio + reg); 1196} 1197 1198#define nv_wait(reg, mask, val) \ 1199 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1200 1201/* PRAMIN access */ 1202static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1203{ 1204 struct drm_nouveau_private *dev_priv = dev->dev_private; 1205 return ioread32_native(dev_priv->ramin + offset); 1206} 1207 1208static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1209{ 1210 struct drm_nouveau_private *dev_priv = dev->dev_private; 1211 iowrite32_native(val, dev_priv->ramin + offset); 1212} 1213 1214/* object access */ 1215static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1216 unsigned index) 1217{ 1218 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1219} 1220 1221static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1222 unsigned index, u32 val) 1223{ 1224 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1225} 1226 1227/* 1228 * Logging 1229 * Argument d is (struct drm_device *). 1230 */ 1231#define NV_PRINTK(level, d, fmt, arg...) \ 1232 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1233 pci_name(d->pdev), ##arg) 1234#ifndef NV_DEBUG_NOTRACE 1235#define NV_DEBUG(d, fmt, arg...) do { \ 1236 if (drm_debug & DRM_UT_DRIVER) { \ 1237 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1238 __LINE__, ##arg); \ 1239 } \ 1240} while (0) 1241#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1242 if (drm_debug & DRM_UT_KMS) { \ 1243 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1244 __LINE__, ##arg); \ 1245 } \ 1246} while (0) 1247#else 1248#define NV_DEBUG(d, fmt, arg...) do { \ 1249 if (drm_debug & DRM_UT_DRIVER) \ 1250 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1251} while (0) 1252#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1253 if (drm_debug & DRM_UT_KMS) \ 1254 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1255} while (0) 1256#endif 1257#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1258#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1259#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1260#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1261#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1262 1263/* nouveau_reg_debug bitmask */ 1264enum { 1265 NOUVEAU_REG_DEBUG_MC = 0x1, 1266 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1267 NOUVEAU_REG_DEBUG_FB = 0x4, 1268 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1269 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1270 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1271 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1272 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1273 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1274 NOUVEAU_REG_DEBUG_EVO = 0x200, 1275}; 1276 1277#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1278 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1279 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1280} while (0) 1281 1282static inline bool 1283nv_two_heads(struct drm_device *dev) 1284{ 1285 struct drm_nouveau_private *dev_priv = dev->dev_private; 1286 const int impl = dev->pci_device & 0x0ff0; 1287 1288 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1289 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1290 return true; 1291 1292 return false; 1293} 1294 1295static inline bool 1296nv_gf4_disp_arch(struct drm_device *dev) 1297{ 1298 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1299} 1300 1301static inline bool 1302nv_two_reg_pll(struct drm_device *dev) 1303{ 1304 struct drm_nouveau_private *dev_priv = dev->dev_private; 1305 const int impl = dev->pci_device & 0x0ff0; 1306 1307 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1308 return true; 1309 return false; 1310} 1311 1312#define NV_SW 0x0000506e 1313#define NV_SW_DMA_SEMAPHORE 0x00000060 1314#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1315#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1316#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1317#define NV_SW_DMA_VBLSEM 0x0000018c 1318#define NV_SW_VBLSEM_OFFSET 0x00000400 1319#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1320#define NV_SW_VBLSEM_RELEASE 0x00000408 1321 1322#endif /* __NOUVEAU_DRV_H__ */ 1323