nouveau_drv.h revision 04a39c577f4114a3f098ee8ef0e20f7778b5ddad
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 struct ttm_bo_kmap_obj kmap; 80 struct list_head head; 81 82 /* protected by ttm_bo_reserve() */ 83 struct drm_file *reserved_by; 84 struct list_head entry; 85 int pbbo_index; 86 bool validate_mapped; 87 88 struct nouveau_channel *channel; 89 90 bool mappable; 91 bool no_vm; 92 93 uint32_t tile_mode; 94 uint32_t tile_flags; 95 struct nouveau_tile_reg *tile; 96 97 struct drm_gem_object *gem; 98 struct drm_file *cpu_filp; 99 int pin_refcnt; 100}; 101 102static inline struct nouveau_bo * 103nouveau_bo(struct ttm_buffer_object *bo) 104{ 105 return container_of(bo, struct nouveau_bo, bo); 106} 107 108static inline struct nouveau_bo * 109nouveau_gem_object(struct drm_gem_object *gem) 110{ 111 return gem ? gem->driver_private : NULL; 112} 113 114/* TODO: submit equivalent to TTM generic API upstream? */ 115static inline void __iomem * 116nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 117{ 118 bool is_iomem; 119 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 120 &nvbo->kmap, &is_iomem); 121 WARN_ON_ONCE(ioptr && !is_iomem); 122 return ioptr; 123} 124 125struct mem_block { 126 struct mem_block *next; 127 struct mem_block *prev; 128 uint64_t start; 129 uint64_t size; 130 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 131}; 132 133enum nouveau_flags { 134 NV_NFORCE = 0x10000000, 135 NV_NFORCE2 = 0x20000000 136}; 137 138#define NVOBJ_ENGINE_SW 0 139#define NVOBJ_ENGINE_GR 1 140#define NVOBJ_ENGINE_DISPLAY 2 141#define NVOBJ_ENGINE_INT 0xdeadbeef 142 143#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 144#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 145#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 146#define NVOBJ_FLAG_FAKE (1 << 3) 147struct nouveau_gpuobj { 148 struct list_head list; 149 150 struct nouveau_channel *im_channel; 151 struct mem_block *im_pramin; 152 struct nouveau_bo *im_backing; 153 uint32_t im_backing_start; 154 uint32_t *im_backing_suspend; 155 int im_bound; 156 157 uint32_t flags; 158 int refcount; 159 160 uint32_t engine; 161 uint32_t class; 162 163 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 164 void *priv; 165}; 166 167struct nouveau_gpuobj_ref { 168 struct list_head list; 169 170 struct nouveau_gpuobj *gpuobj; 171 uint32_t instance; 172 173 struct nouveau_channel *channel; 174 int handle; 175}; 176 177struct nouveau_channel { 178 struct drm_device *dev; 179 int id; 180 181 /* owner of this fifo */ 182 struct drm_file *file_priv; 183 /* mapping of the fifo itself */ 184 struct drm_local_map *map; 185 186 /* mapping of the regs controling the fifo */ 187 void __iomem *user; 188 uint32_t user_get; 189 uint32_t user_put; 190 191 /* Fencing */ 192 struct { 193 /* lock protects the pending list only */ 194 spinlock_t lock; 195 struct list_head pending; 196 uint32_t sequence; 197 uint32_t sequence_ack; 198 uint32_t last_sequence_irq; 199 } fence; 200 201 /* DMA push buffer */ 202 struct nouveau_gpuobj_ref *pushbuf; 203 struct nouveau_bo *pushbuf_bo; 204 uint32_t pushbuf_base; 205 206 /* Notifier memory */ 207 struct nouveau_bo *notifier_bo; 208 struct mem_block *notifier_heap; 209 210 /* PFIFO context */ 211 struct nouveau_gpuobj_ref *ramfc; 212 struct nouveau_gpuobj_ref *cache; 213 214 /* PGRAPH context */ 215 /* XXX may be merge 2 pointers as private data ??? */ 216 struct nouveau_gpuobj_ref *ramin_grctx; 217 void *pgraph_ctx; 218 219 /* NV50 VM */ 220 struct nouveau_gpuobj *vm_pd; 221 struct nouveau_gpuobj_ref *vm_gart_pt; 222 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 223 224 /* Objects */ 225 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 226 struct mem_block *ramin_heap; /* Private PRAMIN heap */ 227 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 228 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 229 230 /* GPU object info for stuff used in-kernel (mm_enabled) */ 231 uint32_t m2mf_ntfy; 232 uint32_t vram_handle; 233 uint32_t gart_handle; 234 bool accel_done; 235 236 /* Push buffer state (only for drm's channel on !mm_enabled) */ 237 struct { 238 int max; 239 int free; 240 int cur; 241 int put; 242 /* access via pushbuf_bo */ 243 244 int ib_base; 245 int ib_max; 246 int ib_free; 247 int ib_put; 248 } dma; 249 250 uint32_t sw_subchannel[8]; 251 252 struct { 253 struct nouveau_gpuobj *vblsem; 254 uint32_t vblsem_offset; 255 uint32_t vblsem_rval; 256 struct list_head vbl_wait; 257 } nvsw; 258 259 struct { 260 bool active; 261 char name[32]; 262 struct drm_info_list info; 263 } debugfs; 264}; 265 266struct nouveau_instmem_engine { 267 void *priv; 268 269 int (*init)(struct drm_device *dev); 270 void (*takedown)(struct drm_device *dev); 271 int (*suspend)(struct drm_device *dev); 272 void (*resume)(struct drm_device *dev); 273 274 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 275 uint32_t *size); 276 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 277 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 278 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 279 void (*prepare_access)(struct drm_device *, bool write); 280 void (*finish_access)(struct drm_device *); 281}; 282 283struct nouveau_mc_engine { 284 int (*init)(struct drm_device *dev); 285 void (*takedown)(struct drm_device *dev); 286}; 287 288struct nouveau_timer_engine { 289 int (*init)(struct drm_device *dev); 290 void (*takedown)(struct drm_device *dev); 291 uint64_t (*read)(struct drm_device *dev); 292}; 293 294struct nouveau_fb_engine { 295 int num_tiles; 296 297 int (*init)(struct drm_device *dev); 298 void (*takedown)(struct drm_device *dev); 299 300 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 301 uint32_t size, uint32_t pitch); 302}; 303 304struct nouveau_fifo_engine { 305 void *priv; 306 307 int channels; 308 309 int (*init)(struct drm_device *); 310 void (*takedown)(struct drm_device *); 311 312 void (*disable)(struct drm_device *); 313 void (*enable)(struct drm_device *); 314 bool (*reassign)(struct drm_device *, bool enable); 315 bool (*cache_flush)(struct drm_device *dev); 316 bool (*cache_pull)(struct drm_device *dev, bool enable); 317 318 int (*channel_id)(struct drm_device *); 319 320 int (*create_context)(struct nouveau_channel *); 321 void (*destroy_context)(struct nouveau_channel *); 322 int (*load_context)(struct nouveau_channel *); 323 int (*unload_context)(struct drm_device *); 324}; 325 326struct nouveau_pgraph_object_method { 327 int id; 328 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 329 uint32_t data); 330}; 331 332struct nouveau_pgraph_object_class { 333 int id; 334 bool software; 335 struct nouveau_pgraph_object_method *methods; 336}; 337 338struct nouveau_pgraph_engine { 339 struct nouveau_pgraph_object_class *grclass; 340 bool accel_blocked; 341 void *ctxprog; 342 void *ctxvals; 343 int grctx_size; 344 345 int (*init)(struct drm_device *); 346 void (*takedown)(struct drm_device *); 347 348 void (*fifo_access)(struct drm_device *, bool); 349 350 struct nouveau_channel *(*channel)(struct drm_device *); 351 int (*create_context)(struct nouveau_channel *); 352 void (*destroy_context)(struct nouveau_channel *); 353 int (*load_context)(struct nouveau_channel *); 354 int (*unload_context)(struct drm_device *); 355 356 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 357 uint32_t size, uint32_t pitch); 358}; 359 360struct nouveau_engine { 361 struct nouveau_instmem_engine instmem; 362 struct nouveau_mc_engine mc; 363 struct nouveau_timer_engine timer; 364 struct nouveau_fb_engine fb; 365 struct nouveau_pgraph_engine graph; 366 struct nouveau_fifo_engine fifo; 367}; 368 369struct nouveau_pll_vals { 370 union { 371 struct { 372#ifdef __BIG_ENDIAN 373 uint8_t N1, M1, N2, M2; 374#else 375 uint8_t M1, N1, M2, N2; 376#endif 377 }; 378 struct { 379 uint16_t NM1, NM2; 380 } __attribute__((packed)); 381 }; 382 int log2P; 383 384 int refclk; 385}; 386 387enum nv04_fp_display_regs { 388 FP_DISPLAY_END, 389 FP_TOTAL, 390 FP_CRTC, 391 FP_SYNC_START, 392 FP_SYNC_END, 393 FP_VALID_START, 394 FP_VALID_END 395}; 396 397struct nv04_crtc_reg { 398 unsigned char MiscOutReg; /* */ 399 uint8_t CRTC[0x9f]; 400 uint8_t CR58[0x10]; 401 uint8_t Sequencer[5]; 402 uint8_t Graphics[9]; 403 uint8_t Attribute[21]; 404 unsigned char DAC[768]; /* Internal Colorlookuptable */ 405 406 /* PCRTC regs */ 407 uint32_t fb_start; 408 uint32_t crtc_cfg; 409 uint32_t cursor_cfg; 410 uint32_t gpio_ext; 411 uint32_t crtc_830; 412 uint32_t crtc_834; 413 uint32_t crtc_850; 414 uint32_t crtc_eng_ctrl; 415 416 /* PRAMDAC regs */ 417 uint32_t nv10_cursync; 418 struct nouveau_pll_vals pllvals; 419 uint32_t ramdac_gen_ctrl; 420 uint32_t ramdac_630; 421 uint32_t ramdac_634; 422 uint32_t tv_setup; 423 uint32_t tv_vtotal; 424 uint32_t tv_vskew; 425 uint32_t tv_vsync_delay; 426 uint32_t tv_htotal; 427 uint32_t tv_hskew; 428 uint32_t tv_hsync_delay; 429 uint32_t tv_hsync_delay2; 430 uint32_t fp_horiz_regs[7]; 431 uint32_t fp_vert_regs[7]; 432 uint32_t dither; 433 uint32_t fp_control; 434 uint32_t dither_regs[6]; 435 uint32_t fp_debug_0; 436 uint32_t fp_debug_1; 437 uint32_t fp_debug_2; 438 uint32_t fp_margin_color; 439 uint32_t ramdac_8c0; 440 uint32_t ramdac_a20; 441 uint32_t ramdac_a24; 442 uint32_t ramdac_a34; 443 uint32_t ctv_regs[38]; 444}; 445 446struct nv04_output_reg { 447 uint32_t output; 448 int head; 449}; 450 451struct nv04_mode_state { 452 uint32_t bpp; 453 uint32_t width; 454 uint32_t height; 455 uint32_t interlace; 456 uint32_t repaint0; 457 uint32_t repaint1; 458 uint32_t screen; 459 uint32_t scale; 460 uint32_t dither; 461 uint32_t extra; 462 uint32_t fifo; 463 uint32_t pixel; 464 uint32_t horiz; 465 int arbitration0; 466 int arbitration1; 467 uint32_t pll; 468 uint32_t pllB; 469 uint32_t vpll; 470 uint32_t vpll2; 471 uint32_t vpllB; 472 uint32_t vpll2B; 473 uint32_t pllsel; 474 uint32_t sel_clk; 475 uint32_t general; 476 uint32_t crtcOwner; 477 uint32_t head; 478 uint32_t head2; 479 uint32_t cursorConfig; 480 uint32_t cursor0; 481 uint32_t cursor1; 482 uint32_t cursor2; 483 uint32_t timingH; 484 uint32_t timingV; 485 uint32_t displayV; 486 uint32_t crtcSync; 487 488 struct nv04_crtc_reg crtc_reg[2]; 489}; 490 491enum nouveau_card_type { 492 NV_04 = 0x00, 493 NV_10 = 0x10, 494 NV_20 = 0x20, 495 NV_30 = 0x30, 496 NV_40 = 0x40, 497 NV_50 = 0x50, 498}; 499 500struct drm_nouveau_private { 501 struct drm_device *dev; 502 enum { 503 NOUVEAU_CARD_INIT_DOWN, 504 NOUVEAU_CARD_INIT_DONE, 505 NOUVEAU_CARD_INIT_FAILED 506 } init_state; 507 508 /* the card type, takes NV_* as values */ 509 enum nouveau_card_type card_type; 510 /* exact chipset, derived from NV_PMC_BOOT_0 */ 511 int chipset; 512 int flags; 513 514 void __iomem *mmio; 515 void __iomem *ramin; 516 uint32_t ramin_size; 517 518 struct nouveau_bo *vga_ram; 519 520 struct workqueue_struct *wq; 521 struct work_struct irq_work; 522 523 struct list_head vbl_waiting; 524 525 struct { 526 struct ttm_global_reference mem_global_ref; 527 struct ttm_bo_global_ref bo_global_ref; 528 struct ttm_bo_device bdev; 529 spinlock_t bo_list_lock; 530 struct list_head bo_list; 531 atomic_t validate_sequence; 532 } ttm; 533 534 struct fb_info *fbdev_info; 535 536 int fifo_alloc_count; 537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 538 539 struct nouveau_engine engine; 540 struct nouveau_channel *channel; 541 542 /* For PFIFO and PGRAPH. */ 543 spinlock_t context_switch_lock; 544 545 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 546 struct nouveau_gpuobj *ramht; 547 uint32_t ramin_rsvd_vram; 548 uint32_t ramht_offset; 549 uint32_t ramht_size; 550 uint32_t ramht_bits; 551 uint32_t ramfc_offset; 552 uint32_t ramfc_size; 553 uint32_t ramro_offset; 554 uint32_t ramro_size; 555 556 /* base physical adresses */ 557 uint64_t fb_phys; 558 uint64_t fb_available_size; 559 uint64_t fb_mappable_pages; 560 uint64_t fb_aper_free; 561 562 struct { 563 enum { 564 NOUVEAU_GART_NONE = 0, 565 NOUVEAU_GART_AGP, 566 NOUVEAU_GART_SGDMA 567 } type; 568 uint64_t aper_base; 569 uint64_t aper_size; 570 uint64_t aper_free; 571 572 struct nouveau_gpuobj *sg_ctxdma; 573 struct page *sg_dummy_page; 574 dma_addr_t sg_dummy_bus; 575 576 /* nottm hack */ 577 struct drm_ttm_backend *sg_be; 578 unsigned long sg_handle; 579 } gart_info; 580 581 /* nv10-nv40 tiling regions */ 582 struct { 583 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 584 spinlock_t lock; 585 } tile; 586 587 /* G8x/G9x virtual address space */ 588 uint64_t vm_gart_base; 589 uint64_t vm_gart_size; 590 uint64_t vm_vram_base; 591 uint64_t vm_vram_size; 592 uint64_t vm_end; 593 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 594 int vm_vram_pt_nr; 595 uint64_t vram_sys_base; 596 597 /* the mtrr covering the FB */ 598 int fb_mtrr; 599 600 struct mem_block *ramin_heap; 601 602 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ 603 uint32_t ctx_table_size; 604 struct nouveau_gpuobj_ref *ctx_table; 605 606 struct list_head gpuobj_list; 607 608 struct nvbios vbios; 609 610 struct nv04_mode_state mode_reg; 611 struct nv04_mode_state saved_reg; 612 uint32_t saved_vga_font[4][16384]; 613 uint32_t crtc_owner; 614 uint32_t dac_users[4]; 615 616 struct nouveau_suspend_resume { 617 uint32_t fifo_mode; 618 uint32_t graph_ctx_control; 619 uint32_t graph_state; 620 uint32_t *ramin_copy; 621 uint64_t ramin_size; 622 } susres; 623 624 struct backlight_device *backlight; 625 bool acpi_dsm; 626 627 struct nouveau_channel *evo; 628 629 struct { 630 struct dentry *channel_root; 631 } debugfs; 632}; 633 634static inline struct drm_nouveau_private * 635nouveau_bdev(struct ttm_bo_device *bd) 636{ 637 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 638} 639 640static inline int 641nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 642{ 643 struct nouveau_bo *prev; 644 645 if (!pnvbo) 646 return -EINVAL; 647 prev = *pnvbo; 648 649 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 650 if (prev) { 651 struct ttm_buffer_object *bo = &prev->bo; 652 653 ttm_bo_unref(&bo); 654 } 655 656 return 0; 657} 658 659#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ 660 struct drm_nouveau_private *nv = dev->dev_private; \ 661 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ 662 NV_ERROR(dev, "called without init\n"); \ 663 return -EINVAL; \ 664 } \ 665} while (0) 666 667#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 668 struct drm_nouveau_private *nv = dev->dev_private; \ 669 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 670 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 671 DRM_CURRENTPID, (id)); \ 672 return -EPERM; \ 673 } \ 674 (ch) = nv->fifos[(id)]; \ 675} while (0) 676 677/* nouveau_drv.c */ 678extern int nouveau_noagp; 679extern int nouveau_duallink; 680extern int nouveau_uscript_lvds; 681extern int nouveau_uscript_tmds; 682extern int nouveau_vram_pushbuf; 683extern int nouveau_vram_notify; 684extern int nouveau_fbpercrtc; 685extern char *nouveau_tv_norm; 686extern int nouveau_reg_debug; 687extern char *nouveau_vbios; 688extern int nouveau_ctxfw; 689extern int nouveau_ignorelid; 690extern int nouveau_nofbaccel; 691extern int nouveau_noaccel; 692 693/* nouveau_state.c */ 694extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 695extern int nouveau_load(struct drm_device *, unsigned long flags); 696extern int nouveau_firstopen(struct drm_device *); 697extern void nouveau_lastclose(struct drm_device *); 698extern int nouveau_unload(struct drm_device *); 699extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 700 struct drm_file *); 701extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 702 struct drm_file *); 703extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 704 uint32_t reg, uint32_t mask, uint32_t val); 705extern bool nouveau_wait_for_idle(struct drm_device *); 706extern int nouveau_card_init(struct drm_device *); 707 708/* nouveau_mem.c */ 709extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, 710 uint64_t size); 711extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, 712 uint64_t size, int align2, 713 struct drm_file *, int tail); 714extern void nouveau_mem_takedown(struct mem_block **heap); 715extern void nouveau_mem_free_block(struct mem_block *); 716extern uint64_t nouveau_mem_fb_amount(struct drm_device *); 717extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 718extern int nouveau_mem_init(struct drm_device *); 719extern int nouveau_mem_init_agp(struct drm_device *); 720extern void nouveau_mem_close(struct drm_device *); 721extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 722 uint32_t addr, 723 uint32_t size, 724 uint32_t pitch); 725extern void nv10_mem_expire_tiling(struct drm_device *dev, 726 struct nouveau_tile_reg *tile, 727 struct nouveau_fence *fence); 728extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 729 uint32_t size, uint32_t flags, 730 uint64_t phys); 731extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 732 uint32_t size); 733 734/* nouveau_notifier.c */ 735extern int nouveau_notifier_init_channel(struct nouveau_channel *); 736extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 737extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 738 int cout, uint32_t *offset); 739extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 740extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 741 struct drm_file *); 742extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 743 struct drm_file *); 744 745/* nouveau_channel.c */ 746extern struct drm_ioctl_desc nouveau_ioctls[]; 747extern int nouveau_max_ioctl; 748extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 749extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 750 int channel); 751extern int nouveau_channel_alloc(struct drm_device *dev, 752 struct nouveau_channel **chan, 753 struct drm_file *file_priv, 754 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 755extern void nouveau_channel_free(struct nouveau_channel *); 756 757/* nouveau_object.c */ 758extern int nouveau_gpuobj_early_init(struct drm_device *); 759extern int nouveau_gpuobj_init(struct drm_device *); 760extern void nouveau_gpuobj_takedown(struct drm_device *); 761extern void nouveau_gpuobj_late_takedown(struct drm_device *); 762extern int nouveau_gpuobj_suspend(struct drm_device *dev); 763extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 764extern void nouveau_gpuobj_resume(struct drm_device *dev); 765extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 766 uint32_t vram_h, uint32_t tt_h); 767extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 768extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 769 uint32_t size, int align, uint32_t flags, 770 struct nouveau_gpuobj **); 771extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 772extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 773 uint32_t handle, struct nouveau_gpuobj *, 774 struct nouveau_gpuobj_ref **); 775extern int nouveau_gpuobj_ref_del(struct drm_device *, 776 struct nouveau_gpuobj_ref **); 777extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 778 struct nouveau_gpuobj_ref **ref_ret); 779extern int nouveau_gpuobj_new_ref(struct drm_device *, 780 struct nouveau_channel *alloc_chan, 781 struct nouveau_channel *ref_chan, 782 uint32_t handle, uint32_t size, int align, 783 uint32_t flags, struct nouveau_gpuobj_ref **); 784extern int nouveau_gpuobj_new_fake(struct drm_device *, 785 uint32_t p_offset, uint32_t b_offset, 786 uint32_t size, uint32_t flags, 787 struct nouveau_gpuobj **, 788 struct nouveau_gpuobj_ref**); 789extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 790 uint64_t offset, uint64_t size, int access, 791 int target, struct nouveau_gpuobj **); 792extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 793 uint64_t offset, uint64_t size, 794 int access, struct nouveau_gpuobj **, 795 uint32_t *o_ret); 796extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 797 struct nouveau_gpuobj **); 798extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 799 struct nouveau_gpuobj **); 800extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 801 struct drm_file *); 802extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 803 struct drm_file *); 804 805/* nouveau_irq.c */ 806extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 807extern void nouveau_irq_preinstall(struct drm_device *); 808extern int nouveau_irq_postinstall(struct drm_device *); 809extern void nouveau_irq_uninstall(struct drm_device *); 810 811/* nouveau_sgdma.c */ 812extern int nouveau_sgdma_init(struct drm_device *); 813extern void nouveau_sgdma_takedown(struct drm_device *); 814extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 815 uint32_t *page); 816extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 817 818/* nouveau_debugfs.c */ 819#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 820extern int nouveau_debugfs_init(struct drm_minor *); 821extern void nouveau_debugfs_takedown(struct drm_minor *); 822extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 823extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 824#else 825static inline int 826nouveau_debugfs_init(struct drm_minor *minor) 827{ 828 return 0; 829} 830 831static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 832{ 833} 834 835static inline int 836nouveau_debugfs_channel_init(struct nouveau_channel *chan) 837{ 838 return 0; 839} 840 841static inline void 842nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 843{ 844} 845#endif 846 847/* nouveau_dma.c */ 848extern void nouveau_dma_pre_init(struct nouveau_channel *); 849extern int nouveau_dma_init(struct nouveau_channel *); 850extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 851 852/* nouveau_acpi.c */ 853#ifdef CONFIG_ACPI 854extern int nouveau_hybrid_setup(struct drm_device *dev); 855extern bool nouveau_dsm_probe(struct drm_device *dev); 856#else 857static inline int nouveau_hybrid_setup(struct drm_device *dev) 858{ 859 return 0; 860} 861static inline bool nouveau_dsm_probe(struct drm_device *dev) 862{ 863 return false; 864} 865#endif 866 867/* nouveau_backlight.c */ 868#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 869extern int nouveau_backlight_init(struct drm_device *); 870extern void nouveau_backlight_exit(struct drm_device *); 871#else 872static inline int nouveau_backlight_init(struct drm_device *dev) 873{ 874 return 0; 875} 876 877static inline void nouveau_backlight_exit(struct drm_device *dev) { } 878#endif 879 880/* nouveau_bios.c */ 881extern int nouveau_bios_init(struct drm_device *); 882extern void nouveau_bios_takedown(struct drm_device *dev); 883extern int nouveau_run_vbios_init(struct drm_device *); 884extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 885 struct dcb_entry *); 886extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 887 enum dcb_gpio_tag); 888extern struct dcb_connector_table_entry * 889nouveau_bios_connector_entry(struct drm_device *, int index); 890extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 891 struct pll_lims *); 892extern int nouveau_bios_run_display_table(struct drm_device *, 893 struct dcb_entry *, 894 uint32_t script, int pxclk); 895extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 896 int *length); 897extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 898extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 899extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 900 bool *dl, bool *if_is_24bit); 901extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 902 int head, int pxclk); 903extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 904 enum LVDS_script, int pxclk); 905 906/* nouveau_ttm.c */ 907int nouveau_ttm_global_init(struct drm_nouveau_private *); 908void nouveau_ttm_global_release(struct drm_nouveau_private *); 909int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 910 911/* nouveau_dp.c */ 912int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 913 uint8_t *data, int data_nr); 914bool nouveau_dp_detect(struct drm_encoder *); 915bool nouveau_dp_link_train(struct drm_encoder *); 916 917/* nv04_fb.c */ 918extern int nv04_fb_init(struct drm_device *); 919extern void nv04_fb_takedown(struct drm_device *); 920 921/* nv10_fb.c */ 922extern int nv10_fb_init(struct drm_device *); 923extern void nv10_fb_takedown(struct drm_device *); 924extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 925 uint32_t, uint32_t); 926 927/* nv40_fb.c */ 928extern int nv40_fb_init(struct drm_device *); 929extern void nv40_fb_takedown(struct drm_device *); 930extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 931 uint32_t, uint32_t); 932 933/* nv04_fifo.c */ 934extern int nv04_fifo_init(struct drm_device *); 935extern void nv04_fifo_disable(struct drm_device *); 936extern void nv04_fifo_enable(struct drm_device *); 937extern bool nv04_fifo_reassign(struct drm_device *, bool); 938extern bool nv04_fifo_cache_flush(struct drm_device *); 939extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 940extern int nv04_fifo_channel_id(struct drm_device *); 941extern int nv04_fifo_create_context(struct nouveau_channel *); 942extern void nv04_fifo_destroy_context(struct nouveau_channel *); 943extern int nv04_fifo_load_context(struct nouveau_channel *); 944extern int nv04_fifo_unload_context(struct drm_device *); 945 946/* nv10_fifo.c */ 947extern int nv10_fifo_init(struct drm_device *); 948extern int nv10_fifo_channel_id(struct drm_device *); 949extern int nv10_fifo_create_context(struct nouveau_channel *); 950extern void nv10_fifo_destroy_context(struct nouveau_channel *); 951extern int nv10_fifo_load_context(struct nouveau_channel *); 952extern int nv10_fifo_unload_context(struct drm_device *); 953 954/* nv40_fifo.c */ 955extern int nv40_fifo_init(struct drm_device *); 956extern int nv40_fifo_create_context(struct nouveau_channel *); 957extern void nv40_fifo_destroy_context(struct nouveau_channel *); 958extern int nv40_fifo_load_context(struct nouveau_channel *); 959extern int nv40_fifo_unload_context(struct drm_device *); 960 961/* nv50_fifo.c */ 962extern int nv50_fifo_init(struct drm_device *); 963extern void nv50_fifo_takedown(struct drm_device *); 964extern int nv50_fifo_channel_id(struct drm_device *); 965extern int nv50_fifo_create_context(struct nouveau_channel *); 966extern void nv50_fifo_destroy_context(struct nouveau_channel *); 967extern int nv50_fifo_load_context(struct nouveau_channel *); 968extern int nv50_fifo_unload_context(struct drm_device *); 969 970/* nv04_graph.c */ 971extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 972extern int nv04_graph_init(struct drm_device *); 973extern void nv04_graph_takedown(struct drm_device *); 974extern void nv04_graph_fifo_access(struct drm_device *, bool); 975extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 976extern int nv04_graph_create_context(struct nouveau_channel *); 977extern void nv04_graph_destroy_context(struct nouveau_channel *); 978extern int nv04_graph_load_context(struct nouveau_channel *); 979extern int nv04_graph_unload_context(struct drm_device *); 980extern void nv04_graph_context_switch(struct drm_device *); 981 982/* nv10_graph.c */ 983extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 984extern int nv10_graph_init(struct drm_device *); 985extern void nv10_graph_takedown(struct drm_device *); 986extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 987extern int nv10_graph_create_context(struct nouveau_channel *); 988extern void nv10_graph_destroy_context(struct nouveau_channel *); 989extern int nv10_graph_load_context(struct nouveau_channel *); 990extern int nv10_graph_unload_context(struct drm_device *); 991extern void nv10_graph_context_switch(struct drm_device *); 992extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 993 uint32_t, uint32_t); 994 995/* nv20_graph.c */ 996extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 997extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 998extern int nv20_graph_create_context(struct nouveau_channel *); 999extern void nv20_graph_destroy_context(struct nouveau_channel *); 1000extern int nv20_graph_load_context(struct nouveau_channel *); 1001extern int nv20_graph_unload_context(struct drm_device *); 1002extern int nv20_graph_init(struct drm_device *); 1003extern void nv20_graph_takedown(struct drm_device *); 1004extern int nv30_graph_init(struct drm_device *); 1005extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1006 uint32_t, uint32_t); 1007 1008/* nv40_graph.c */ 1009extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1010extern int nv40_graph_init(struct drm_device *); 1011extern void nv40_graph_takedown(struct drm_device *); 1012extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1013extern int nv40_graph_create_context(struct nouveau_channel *); 1014extern void nv40_graph_destroy_context(struct nouveau_channel *); 1015extern int nv40_graph_load_context(struct nouveau_channel *); 1016extern int nv40_graph_unload_context(struct drm_device *); 1017extern void nv40_grctx_init(struct nouveau_grctx *); 1018extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1019 uint32_t, uint32_t); 1020 1021/* nv50_graph.c */ 1022extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1023extern int nv50_graph_init(struct drm_device *); 1024extern void nv50_graph_takedown(struct drm_device *); 1025extern void nv50_graph_fifo_access(struct drm_device *, bool); 1026extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1027extern int nv50_graph_create_context(struct nouveau_channel *); 1028extern void nv50_graph_destroy_context(struct nouveau_channel *); 1029extern int nv50_graph_load_context(struct nouveau_channel *); 1030extern int nv50_graph_unload_context(struct drm_device *); 1031extern void nv50_graph_context_switch(struct drm_device *); 1032 1033/* nouveau_grctx.c */ 1034extern int nouveau_grctx_prog_load(struct drm_device *); 1035extern void nouveau_grctx_vals_load(struct drm_device *, 1036 struct nouveau_gpuobj *); 1037extern void nouveau_grctx_fini(struct drm_device *); 1038 1039/* nv04_instmem.c */ 1040extern int nv04_instmem_init(struct drm_device *); 1041extern void nv04_instmem_takedown(struct drm_device *); 1042extern int nv04_instmem_suspend(struct drm_device *); 1043extern void nv04_instmem_resume(struct drm_device *); 1044extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1045 uint32_t *size); 1046extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1047extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1048extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1049extern void nv04_instmem_prepare_access(struct drm_device *, bool write); 1050extern void nv04_instmem_finish_access(struct drm_device *); 1051 1052/* nv50_instmem.c */ 1053extern int nv50_instmem_init(struct drm_device *); 1054extern void nv50_instmem_takedown(struct drm_device *); 1055extern int nv50_instmem_suspend(struct drm_device *); 1056extern void nv50_instmem_resume(struct drm_device *); 1057extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1058 uint32_t *size); 1059extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1060extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1061extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1062extern void nv50_instmem_prepare_access(struct drm_device *, bool write); 1063extern void nv50_instmem_finish_access(struct drm_device *); 1064 1065/* nv04_mc.c */ 1066extern int nv04_mc_init(struct drm_device *); 1067extern void nv04_mc_takedown(struct drm_device *); 1068 1069/* nv40_mc.c */ 1070extern int nv40_mc_init(struct drm_device *); 1071extern void nv40_mc_takedown(struct drm_device *); 1072 1073/* nv50_mc.c */ 1074extern int nv50_mc_init(struct drm_device *); 1075extern void nv50_mc_takedown(struct drm_device *); 1076 1077/* nv04_timer.c */ 1078extern int nv04_timer_init(struct drm_device *); 1079extern uint64_t nv04_timer_read(struct drm_device *); 1080extern void nv04_timer_takedown(struct drm_device *); 1081 1082extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1083 unsigned long arg); 1084 1085/* nv04_dac.c */ 1086extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1087extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1088extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1089extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1090 1091/* nv04_dfp.c */ 1092extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry); 1093extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1094extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1095 int head, bool dl); 1096extern void nv04_dfp_disable(struct drm_device *dev, int head); 1097extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1098 1099/* nv04_tv.c */ 1100extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1101extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1102 1103/* nv17_tv.c */ 1104extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1105 1106/* nv04_display.c */ 1107extern int nv04_display_create(struct drm_device *); 1108extern void nv04_display_destroy(struct drm_device *); 1109extern void nv04_display_restore(struct drm_device *); 1110 1111/* nv04_crtc.c */ 1112extern int nv04_crtc_create(struct drm_device *, int index); 1113 1114/* nouveau_bo.c */ 1115extern struct ttm_bo_driver nouveau_bo_driver; 1116extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1117 int size, int align, uint32_t flags, 1118 uint32_t tile_mode, uint32_t tile_flags, 1119 bool no_vm, bool mappable, struct nouveau_bo **); 1120extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1121extern int nouveau_bo_unpin(struct nouveau_bo *); 1122extern int nouveau_bo_map(struct nouveau_bo *); 1123extern void nouveau_bo_unmap(struct nouveau_bo *); 1124extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); 1125extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1126extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1127extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1128extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1129 1130/* nouveau_fence.c */ 1131struct nouveau_fence; 1132extern int nouveau_fence_init(struct nouveau_channel *); 1133extern void nouveau_fence_fini(struct nouveau_channel *); 1134extern void nouveau_fence_update(struct nouveau_channel *); 1135extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1136 bool emit); 1137extern int nouveau_fence_emit(struct nouveau_fence *); 1138struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1139extern bool nouveau_fence_signalled(void *obj, void *arg); 1140extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1141extern int nouveau_fence_flush(void *obj, void *arg); 1142extern void nouveau_fence_unref(void **obj); 1143extern void *nouveau_fence_ref(void *obj); 1144extern void nouveau_fence_handler(struct drm_device *dev, int channel); 1145 1146/* nouveau_gem.c */ 1147extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1148 int size, int align, uint32_t flags, 1149 uint32_t tile_mode, uint32_t tile_flags, 1150 bool no_vm, bool mappable, struct nouveau_bo **); 1151extern int nouveau_gem_object_new(struct drm_gem_object *); 1152extern void nouveau_gem_object_del(struct drm_gem_object *); 1153extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1154 struct drm_file *); 1155extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1156 struct drm_file *); 1157extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1158 struct drm_file *); 1159extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1160 struct drm_file *); 1161extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1162 struct drm_file *); 1163 1164/* nv17_gpio.c */ 1165int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1166int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1167 1168#ifndef ioread32_native 1169#ifdef __BIG_ENDIAN 1170#define ioread16_native ioread16be 1171#define iowrite16_native iowrite16be 1172#define ioread32_native ioread32be 1173#define iowrite32_native iowrite32be 1174#else /* def __BIG_ENDIAN */ 1175#define ioread16_native ioread16 1176#define iowrite16_native iowrite16 1177#define ioread32_native ioread32 1178#define iowrite32_native iowrite32 1179#endif /* def __BIG_ENDIAN else */ 1180#endif /* !ioread32_native */ 1181 1182/* channel control reg access */ 1183static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1184{ 1185 return ioread32_native(chan->user + reg); 1186} 1187 1188static inline void nvchan_wr32(struct nouveau_channel *chan, 1189 unsigned reg, u32 val) 1190{ 1191 iowrite32_native(val, chan->user + reg); 1192} 1193 1194/* register access */ 1195static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1196{ 1197 struct drm_nouveau_private *dev_priv = dev->dev_private; 1198 return ioread32_native(dev_priv->mmio + reg); 1199} 1200 1201static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1202{ 1203 struct drm_nouveau_private *dev_priv = dev->dev_private; 1204 iowrite32_native(val, dev_priv->mmio + reg); 1205} 1206 1207static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1208{ 1209 struct drm_nouveau_private *dev_priv = dev->dev_private; 1210 return ioread8(dev_priv->mmio + reg); 1211} 1212 1213static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1214{ 1215 struct drm_nouveau_private *dev_priv = dev->dev_private; 1216 iowrite8(val, dev_priv->mmio + reg); 1217} 1218 1219#define nv_wait(reg, mask, val) \ 1220 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1221 1222/* PRAMIN access */ 1223static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1224{ 1225 struct drm_nouveau_private *dev_priv = dev->dev_private; 1226 return ioread32_native(dev_priv->ramin + offset); 1227} 1228 1229static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1230{ 1231 struct drm_nouveau_private *dev_priv = dev->dev_private; 1232 iowrite32_native(val, dev_priv->ramin + offset); 1233} 1234 1235/* object access */ 1236static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1237 unsigned index) 1238{ 1239 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1240} 1241 1242static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1243 unsigned index, u32 val) 1244{ 1245 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1246} 1247 1248/* 1249 * Logging 1250 * Argument d is (struct drm_device *). 1251 */ 1252#define NV_PRINTK(level, d, fmt, arg...) \ 1253 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1254 pci_name(d->pdev), ##arg) 1255#ifndef NV_DEBUG_NOTRACE 1256#define NV_DEBUG(d, fmt, arg...) do { \ 1257 if (drm_debug & DRM_UT_DRIVER) { \ 1258 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1259 __LINE__, ##arg); \ 1260 } \ 1261} while (0) 1262#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1263 if (drm_debug & DRM_UT_KMS) { \ 1264 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1265 __LINE__, ##arg); \ 1266 } \ 1267} while (0) 1268#else 1269#define NV_DEBUG(d, fmt, arg...) do { \ 1270 if (drm_debug & DRM_UT_DRIVER) \ 1271 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1272} while (0) 1273#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1274 if (drm_debug & DRM_UT_KMS) \ 1275 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1276} while (0) 1277#endif 1278#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1279#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1280#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1281#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1282#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1283 1284/* nouveau_reg_debug bitmask */ 1285enum { 1286 NOUVEAU_REG_DEBUG_MC = 0x1, 1287 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1288 NOUVEAU_REG_DEBUG_FB = 0x4, 1289 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1290 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1291 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1292 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1293 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1294 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1295 NOUVEAU_REG_DEBUG_EVO = 0x200, 1296}; 1297 1298#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1299 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1300 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1301} while (0) 1302 1303static inline bool 1304nv_two_heads(struct drm_device *dev) 1305{ 1306 struct drm_nouveau_private *dev_priv = dev->dev_private; 1307 const int impl = dev->pci_device & 0x0ff0; 1308 1309 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1310 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1311 return true; 1312 1313 return false; 1314} 1315 1316static inline bool 1317nv_gf4_disp_arch(struct drm_device *dev) 1318{ 1319 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1320} 1321 1322static inline bool 1323nv_two_reg_pll(struct drm_device *dev) 1324{ 1325 struct drm_nouveau_private *dev_priv = dev->dev_private; 1326 const int impl = dev->pci_device & 0x0ff0; 1327 1328 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1329 return true; 1330 return false; 1331} 1332 1333#define NV_SW 0x0000506e 1334#define NV_SW_DMA_SEMAPHORE 0x00000060 1335#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1336#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1337#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1338#define NV_SW_DMA_VBLSEM 0x0000018c 1339#define NV_SW_VBLSEM_OFFSET 0x00000400 1340#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1341#define NV_SW_VBLSEM_RELEASE 0x00000408 1342 1343#endif /* __NOUVEAU_DRV_H__ */ 1344