nouveau_drv.h revision 085028ce3bf7136c5ab2eeb8bf012024d88905c8
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435/* Exclusive upper limits */ 436#define NV_MEM_CL_DDR2_MAX 8 437#define NV_MEM_WR_DDR2_MAX 9 438#define NV_MEM_CL_DDR3_MAX 17 439#define NV_MEM_WR_DDR3_MAX 17 440#define NV_MEM_CL_GDDR3_MAX 16 441#define NV_MEM_WR_GDDR3_MAX 18 442#define NV_MEM_CL_GDDR5_MAX 21 443#define NV_MEM_WR_GDDR5_MAX 20 444 445struct nouveau_pm_memtiming { 446 int id; 447 448 u32 reg[9]; 449 u32 mr[4]; 450 451 u8 tCWL; 452 453 u8 odt; 454 u8 drive_strength; 455}; 456 457struct nouveau_pm_tbl_header { 458 u8 version; 459 u8 header_len; 460 u8 entry_cnt; 461 u8 entry_len; 462}; 463 464struct nouveau_pm_tbl_entry { 465 u8 tWR; 466 u8 tWTR; 467 u8 tCL; 468 u8 tRC; 469 u8 empty_4; 470 u8 tRFC; /* Byte 5 */ 471 u8 empty_6; 472 u8 tRAS; /* Byte 7 */ 473 u8 empty_8; 474 u8 tRP; /* Byte 9 */ 475 u8 tRCDRD; 476 u8 tRCDWR; 477 u8 tRRD; 478 u8 tUNK_13; 479 u8 RAM_FT1; /* 14, a bitmask of random RAM features */ 480 u8 empty_15; 481 u8 tUNK_16; 482 u8 empty_17; 483 u8 tUNK_18; 484 u8 tCWL; 485 u8 tUNK_20, tUNK_21; 486}; 487 488#define NOUVEAU_PM_MAX_LEVEL 8 489struct nouveau_pm_level { 490 struct device_attribute dev_attr; 491 char name[32]; 492 int id; 493 494 u32 memory; 495 u16 memscript; 496 struct nouveau_pm_memtiming timing; 497 498 u32 core; 499 u32 shader; 500 u32 rop; 501 u32 copy; 502 u32 daemon; 503 u32 vdec; 504 u32 dom6; 505 u32 unka0; /* nva3:nvc0 */ 506 u32 hub01; /* nvc0- */ 507 u32 hub06; /* nvc0- */ 508 u32 hub07; /* nvc0- */ 509 510 u32 volt_min; /* microvolts */ 511 u32 volt_max; 512 u8 fanspeed; 513}; 514 515struct nouveau_pm_temp_sensor_constants { 516 u16 offset_constant; 517 s16 offset_mult; 518 s16 offset_div; 519 s16 slope_mult; 520 s16 slope_div; 521}; 522 523struct nouveau_pm_threshold_temp { 524 s16 critical; 525 s16 down_clock; 526 s16 fan_boost; 527}; 528 529struct nouveau_pm_fan { 530 u32 percent; 531 u32 min_duty; 532 u32 max_duty; 533 u32 pwm_freq; 534 u32 pwm_divisor; 535}; 536 537struct nouveau_pm_engine { 538 struct nouveau_pm_voltage voltage; 539 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 540 int nr_perflvl; 541 struct nouveau_pm_temp_sensor_constants sensor_constants; 542 struct nouveau_pm_threshold_temp threshold_temp; 543 struct nouveau_pm_fan fan; 544 545 struct nouveau_pm_level boot; 546 struct nouveau_pm_level *cur; 547 548 struct device *hwmon; 549 struct notifier_block acpi_nb; 550 551 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 552 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 553 int (*clocks_set)(struct drm_device *, void *); 554 555 int (*voltage_get)(struct drm_device *); 556 int (*voltage_set)(struct drm_device *, int voltage); 557 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 558 int (*pwm_set)(struct drm_device *, int line, u32, u32); 559 int (*temp_get)(struct drm_device *); 560}; 561 562struct nouveau_vram_engine { 563 struct nouveau_mm mm; 564 565 int (*init)(struct drm_device *); 566 void (*takedown)(struct drm_device *dev); 567 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 568 u32 type, struct nouveau_mem **); 569 void (*put)(struct drm_device *, struct nouveau_mem **); 570 571 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 572}; 573 574struct nouveau_engine { 575 struct nouveau_instmem_engine instmem; 576 struct nouveau_mc_engine mc; 577 struct nouveau_timer_engine timer; 578 struct nouveau_fb_engine fb; 579 struct nouveau_fifo_engine fifo; 580 struct nouveau_display_engine display; 581 struct nouveau_gpio_engine gpio; 582 struct nouveau_pm_engine pm; 583 struct nouveau_vram_engine vram; 584}; 585 586struct nouveau_pll_vals { 587 union { 588 struct { 589#ifdef __BIG_ENDIAN 590 uint8_t N1, M1, N2, M2; 591#else 592 uint8_t M1, N1, M2, N2; 593#endif 594 }; 595 struct { 596 uint16_t NM1, NM2; 597 } __attribute__((packed)); 598 }; 599 int log2P; 600 601 int refclk; 602}; 603 604enum nv04_fp_display_regs { 605 FP_DISPLAY_END, 606 FP_TOTAL, 607 FP_CRTC, 608 FP_SYNC_START, 609 FP_SYNC_END, 610 FP_VALID_START, 611 FP_VALID_END 612}; 613 614struct nv04_crtc_reg { 615 unsigned char MiscOutReg; 616 uint8_t CRTC[0xa0]; 617 uint8_t CR58[0x10]; 618 uint8_t Sequencer[5]; 619 uint8_t Graphics[9]; 620 uint8_t Attribute[21]; 621 unsigned char DAC[768]; 622 623 /* PCRTC regs */ 624 uint32_t fb_start; 625 uint32_t crtc_cfg; 626 uint32_t cursor_cfg; 627 uint32_t gpio_ext; 628 uint32_t crtc_830; 629 uint32_t crtc_834; 630 uint32_t crtc_850; 631 uint32_t crtc_eng_ctrl; 632 633 /* PRAMDAC regs */ 634 uint32_t nv10_cursync; 635 struct nouveau_pll_vals pllvals; 636 uint32_t ramdac_gen_ctrl; 637 uint32_t ramdac_630; 638 uint32_t ramdac_634; 639 uint32_t tv_setup; 640 uint32_t tv_vtotal; 641 uint32_t tv_vskew; 642 uint32_t tv_vsync_delay; 643 uint32_t tv_htotal; 644 uint32_t tv_hskew; 645 uint32_t tv_hsync_delay; 646 uint32_t tv_hsync_delay2; 647 uint32_t fp_horiz_regs[7]; 648 uint32_t fp_vert_regs[7]; 649 uint32_t dither; 650 uint32_t fp_control; 651 uint32_t dither_regs[6]; 652 uint32_t fp_debug_0; 653 uint32_t fp_debug_1; 654 uint32_t fp_debug_2; 655 uint32_t fp_margin_color; 656 uint32_t ramdac_8c0; 657 uint32_t ramdac_a20; 658 uint32_t ramdac_a24; 659 uint32_t ramdac_a34; 660 uint32_t ctv_regs[38]; 661}; 662 663struct nv04_output_reg { 664 uint32_t output; 665 int head; 666}; 667 668struct nv04_mode_state { 669 struct nv04_crtc_reg crtc_reg[2]; 670 uint32_t pllsel; 671 uint32_t sel_clk; 672}; 673 674enum nouveau_card_type { 675 NV_04 = 0x00, 676 NV_10 = 0x10, 677 NV_20 = 0x20, 678 NV_30 = 0x30, 679 NV_40 = 0x40, 680 NV_50 = 0x50, 681 NV_C0 = 0xc0, 682 NV_D0 = 0xd0 683}; 684 685struct drm_nouveau_private { 686 struct drm_device *dev; 687 bool noaccel; 688 689 /* the card type, takes NV_* as values */ 690 enum nouveau_card_type card_type; 691 /* exact chipset, derived from NV_PMC_BOOT_0 */ 692 int chipset; 693 int flags; 694 u32 crystal; 695 696 void __iomem *mmio; 697 698 spinlock_t ramin_lock; 699 void __iomem *ramin; 700 u32 ramin_size; 701 u32 ramin_base; 702 bool ramin_available; 703 struct drm_mm ramin_heap; 704 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 705 struct list_head gpuobj_list; 706 struct list_head classes; 707 708 struct nouveau_bo *vga_ram; 709 710 /* interrupt handling */ 711 void (*irq_handler[32])(struct drm_device *); 712 bool msi_enabled; 713 714 struct list_head vbl_waiting; 715 716 struct { 717 struct drm_global_reference mem_global_ref; 718 struct ttm_bo_global_ref bo_global_ref; 719 struct ttm_bo_device bdev; 720 atomic_t validate_sequence; 721 } ttm; 722 723 struct { 724 spinlock_t lock; 725 struct drm_mm heap; 726 struct nouveau_bo *bo; 727 } fence; 728 729 struct { 730 spinlock_t lock; 731 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 732 } channels; 733 734 struct nouveau_engine engine; 735 struct nouveau_channel *channel; 736 737 /* For PFIFO and PGRAPH. */ 738 spinlock_t context_switch_lock; 739 740 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 741 spinlock_t vm_lock; 742 743 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 744 struct nouveau_ramht *ramht; 745 struct nouveau_gpuobj *ramfc; 746 struct nouveau_gpuobj *ramro; 747 748 uint32_t ramin_rsvd_vram; 749 750 struct { 751 enum { 752 NOUVEAU_GART_NONE = 0, 753 NOUVEAU_GART_AGP, /* AGP */ 754 NOUVEAU_GART_PDMA, /* paged dma object */ 755 NOUVEAU_GART_HW /* on-chip gart/vm */ 756 } type; 757 uint64_t aper_base; 758 uint64_t aper_size; 759 uint64_t aper_free; 760 761 struct ttm_backend_func *func; 762 763 struct { 764 struct page *page; 765 dma_addr_t addr; 766 } dummy; 767 768 struct nouveau_gpuobj *sg_ctxdma; 769 } gart_info; 770 771 /* nv10-nv40 tiling regions */ 772 struct { 773 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 774 spinlock_t lock; 775 } tile; 776 777 /* VRAM/fb configuration */ 778 enum { 779 NV_MEM_TYPE_UNKNOWN = 0, 780 NV_MEM_TYPE_STOLEN, 781 NV_MEM_TYPE_SGRAM, 782 NV_MEM_TYPE_SDRAM, 783 NV_MEM_TYPE_DDR1, 784 NV_MEM_TYPE_DDR2, 785 NV_MEM_TYPE_DDR3, 786 NV_MEM_TYPE_GDDR2, 787 NV_MEM_TYPE_GDDR3, 788 NV_MEM_TYPE_GDDR4, 789 NV_MEM_TYPE_GDDR5 790 } vram_type; 791 uint64_t vram_size; 792 uint64_t vram_sys_base; 793 bool vram_rank_B; 794 795 uint64_t fb_available_size; 796 uint64_t fb_mappable_pages; 797 uint64_t fb_aper_free; 798 int fb_mtrr; 799 800 /* BAR control (NV50-) */ 801 struct nouveau_vm *bar1_vm; 802 struct nouveau_vm *bar3_vm; 803 804 /* G8x/G9x virtual address space */ 805 struct nouveau_vm *chan_vm; 806 807 struct nvbios vbios; 808 u8 *mxms; 809 struct list_head i2c_ports; 810 811 struct nv04_mode_state mode_reg; 812 struct nv04_mode_state saved_reg; 813 uint32_t saved_vga_font[4][16384]; 814 uint32_t crtc_owner; 815 uint32_t dac_users[4]; 816 817 struct backlight_device *backlight; 818 819 struct { 820 struct dentry *channel_root; 821 } debugfs; 822 823 struct nouveau_fbdev *nfbdev; 824 struct apertures_struct *apertures; 825}; 826 827static inline struct drm_nouveau_private * 828nouveau_private(struct drm_device *dev) 829{ 830 return dev->dev_private; 831} 832 833static inline struct drm_nouveau_private * 834nouveau_bdev(struct ttm_bo_device *bd) 835{ 836 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 837} 838 839static inline int 840nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 841{ 842 struct nouveau_bo *prev; 843 844 if (!pnvbo) 845 return -EINVAL; 846 prev = *pnvbo; 847 848 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 849 if (prev) { 850 struct ttm_buffer_object *bo = &prev->bo; 851 852 ttm_bo_unref(&bo); 853 } 854 855 return 0; 856} 857 858/* nouveau_drv.c */ 859extern int nouveau_modeset; 860extern int nouveau_agpmode; 861extern int nouveau_duallink; 862extern int nouveau_uscript_lvds; 863extern int nouveau_uscript_tmds; 864extern int nouveau_vram_pushbuf; 865extern int nouveau_vram_notify; 866extern char *nouveau_vram_type; 867extern int nouveau_fbpercrtc; 868extern int nouveau_tv_disable; 869extern char *nouveau_tv_norm; 870extern int nouveau_reg_debug; 871extern char *nouveau_vbios; 872extern int nouveau_ignorelid; 873extern int nouveau_nofbaccel; 874extern int nouveau_noaccel; 875extern int nouveau_force_post; 876extern int nouveau_override_conntype; 877extern char *nouveau_perflvl; 878extern int nouveau_perflvl_wr; 879extern int nouveau_msi; 880extern int nouveau_ctxfw; 881extern int nouveau_mxmdcb; 882 883extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 884extern int nouveau_pci_resume(struct pci_dev *pdev); 885 886/* nouveau_state.c */ 887extern int nouveau_open(struct drm_device *, struct drm_file *); 888extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 889extern void nouveau_postclose(struct drm_device *, struct drm_file *); 890extern int nouveau_load(struct drm_device *, unsigned long flags); 891extern int nouveau_firstopen(struct drm_device *); 892extern void nouveau_lastclose(struct drm_device *); 893extern int nouveau_unload(struct drm_device *); 894extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 895 struct drm_file *); 896extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 897 struct drm_file *); 898extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 899 uint32_t reg, uint32_t mask, uint32_t val); 900extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 901 uint32_t reg, uint32_t mask, uint32_t val); 902extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 903 bool (*cond)(void *), void *); 904extern bool nouveau_wait_for_idle(struct drm_device *); 905extern int nouveau_card_init(struct drm_device *); 906 907/* nouveau_mem.c */ 908extern int nouveau_mem_vram_init(struct drm_device *); 909extern void nouveau_mem_vram_fini(struct drm_device *); 910extern int nouveau_mem_gart_init(struct drm_device *); 911extern void nouveau_mem_gart_fini(struct drm_device *); 912extern int nouveau_mem_init_agp(struct drm_device *); 913extern int nouveau_mem_reset_agp(struct drm_device *); 914extern void nouveau_mem_close(struct drm_device *); 915extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 916extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, 917 struct nouveau_pm_memtiming *); 918extern void nouveau_mem_timing_read(struct drm_device *, 919 struct nouveau_pm_memtiming *); 920extern int nouveau_mem_vbios_type(struct drm_device *); 921extern struct nouveau_tile_reg *nv10_mem_set_tiling( 922 struct drm_device *dev, uint32_t addr, uint32_t size, 923 uint32_t pitch, uint32_t flags); 924extern void nv10_mem_put_tile_region(struct drm_device *dev, 925 struct nouveau_tile_reg *tile, 926 struct nouveau_fence *fence); 927extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 928extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 929 930/* nouveau_notifier.c */ 931extern int nouveau_notifier_init_channel(struct nouveau_channel *); 932extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 933extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 934 int cout, uint32_t start, uint32_t end, 935 uint32_t *offset); 936extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 937extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 938 struct drm_file *); 939extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 940 struct drm_file *); 941 942/* nouveau_channel.c */ 943extern struct drm_ioctl_desc nouveau_ioctls[]; 944extern int nouveau_max_ioctl; 945extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 946extern int nouveau_channel_alloc(struct drm_device *dev, 947 struct nouveau_channel **chan, 948 struct drm_file *file_priv, 949 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 950extern struct nouveau_channel * 951nouveau_channel_get_unlocked(struct nouveau_channel *); 952extern struct nouveau_channel * 953nouveau_channel_get(struct drm_file *, int id); 954extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 955extern void nouveau_channel_put(struct nouveau_channel **); 956extern void nouveau_channel_ref(struct nouveau_channel *chan, 957 struct nouveau_channel **pchan); 958extern void nouveau_channel_idle(struct nouveau_channel *chan); 959 960/* nouveau_object.c */ 961#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 962 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 963 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 964} while (0) 965 966#define NVOBJ_ENGINE_DEL(d, e) do { \ 967 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 968 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 969} while (0) 970 971#define NVOBJ_CLASS(d, c, e) do { \ 972 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 973 if (ret) \ 974 return ret; \ 975} while (0) 976 977#define NVOBJ_MTHD(d, c, m, e) do { \ 978 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 979 if (ret) \ 980 return ret; \ 981} while (0) 982 983extern int nouveau_gpuobj_early_init(struct drm_device *); 984extern int nouveau_gpuobj_init(struct drm_device *); 985extern void nouveau_gpuobj_takedown(struct drm_device *); 986extern int nouveau_gpuobj_suspend(struct drm_device *dev); 987extern void nouveau_gpuobj_resume(struct drm_device *dev); 988extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 989extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 990 int (*exec)(struct nouveau_channel *, 991 u32 class, u32 mthd, u32 data)); 992extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 993extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 994extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 995 uint32_t vram_h, uint32_t tt_h); 996extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 997extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 998 uint32_t size, int align, uint32_t flags, 999 struct nouveau_gpuobj **); 1000extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 1001 struct nouveau_gpuobj **); 1002extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 1003 u32 size, u32 flags, 1004 struct nouveau_gpuobj **); 1005extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 1006 uint64_t offset, uint64_t size, int access, 1007 int target, struct nouveau_gpuobj **); 1008extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1009extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1010 u64 size, int target, int access, u32 type, 1011 u32 comp, struct nouveau_gpuobj **pobj); 1012extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1013 int class, u64 base, u64 size, int target, 1014 int access, u32 type, u32 comp); 1015extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1016 struct drm_file *); 1017extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1018 struct drm_file *); 1019 1020/* nouveau_irq.c */ 1021extern int nouveau_irq_init(struct drm_device *); 1022extern void nouveau_irq_fini(struct drm_device *); 1023extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1024extern void nouveau_irq_register(struct drm_device *, int status_bit, 1025 void (*)(struct drm_device *)); 1026extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1027extern void nouveau_irq_preinstall(struct drm_device *); 1028extern int nouveau_irq_postinstall(struct drm_device *); 1029extern void nouveau_irq_uninstall(struct drm_device *); 1030 1031/* nouveau_sgdma.c */ 1032extern int nouveau_sgdma_init(struct drm_device *); 1033extern void nouveau_sgdma_takedown(struct drm_device *); 1034extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1035 uint32_t offset); 1036extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1037 unsigned long size, 1038 uint32_t page_flags, 1039 struct page *dummy_read_page); 1040 1041/* nouveau_debugfs.c */ 1042#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1043extern int nouveau_debugfs_init(struct drm_minor *); 1044extern void nouveau_debugfs_takedown(struct drm_minor *); 1045extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1046extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1047#else 1048static inline int 1049nouveau_debugfs_init(struct drm_minor *minor) 1050{ 1051 return 0; 1052} 1053 1054static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1055{ 1056} 1057 1058static inline int 1059nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1060{ 1061 return 0; 1062} 1063 1064static inline void 1065nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1066{ 1067} 1068#endif 1069 1070/* nouveau_dma.c */ 1071extern void nouveau_dma_pre_init(struct nouveau_channel *); 1072extern int nouveau_dma_init(struct nouveau_channel *); 1073extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1074 1075/* nouveau_acpi.c */ 1076#define ROM_BIOS_PAGE 4096 1077#if defined(CONFIG_ACPI) 1078void nouveau_register_dsm_handler(void); 1079void nouveau_unregister_dsm_handler(void); 1080void nouveau_switcheroo_optimus_dsm(void); 1081int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1082bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1083int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1084#else 1085static inline void nouveau_register_dsm_handler(void) {} 1086static inline void nouveau_unregister_dsm_handler(void) {} 1087static inline void nouveau_switcheroo_optimus_dsm(void) {} 1088static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1089static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1090static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1091#endif 1092 1093/* nouveau_backlight.c */ 1094#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1095extern int nouveau_backlight_init(struct drm_device *); 1096extern void nouveau_backlight_exit(struct drm_device *); 1097#else 1098static inline int nouveau_backlight_init(struct drm_device *dev) 1099{ 1100 return 0; 1101} 1102 1103static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1104#endif 1105 1106/* nouveau_bios.c */ 1107extern int nouveau_bios_init(struct drm_device *); 1108extern void nouveau_bios_takedown(struct drm_device *dev); 1109extern int nouveau_run_vbios_init(struct drm_device *); 1110extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1111 struct dcb_entry *, int crtc); 1112extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1113extern struct dcb_connector_table_entry * 1114nouveau_bios_connector_entry(struct drm_device *, int index); 1115extern u32 get_pll_register(struct drm_device *, enum pll_types); 1116extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1117 struct pll_lims *); 1118extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1119 struct dcb_entry *, int crtc); 1120extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1121extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1122extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1123 bool *dl, bool *if_is_24bit); 1124extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1125 int head, int pxclk); 1126extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1127 enum LVDS_script, int pxclk); 1128bool bios_encoder_match(struct dcb_entry *, u32 hash); 1129 1130/* nouveau_mxm.c */ 1131int nouveau_mxm_init(struct drm_device *dev); 1132void nouveau_mxm_fini(struct drm_device *dev); 1133 1134/* nouveau_ttm.c */ 1135int nouveau_ttm_global_init(struct drm_nouveau_private *); 1136void nouveau_ttm_global_release(struct drm_nouveau_private *); 1137int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1138 1139/* nouveau_hdmi.c */ 1140void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1141 1142/* nouveau_dp.c */ 1143int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1144 uint8_t *data, int data_nr); 1145bool nouveau_dp_detect(struct drm_encoder *); 1146bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1147void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1148u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1149 1150/* nv04_fb.c */ 1151extern int nv04_fb_vram_init(struct drm_device *); 1152extern int nv04_fb_init(struct drm_device *); 1153extern void nv04_fb_takedown(struct drm_device *); 1154 1155/* nv10_fb.c */ 1156extern int nv10_fb_vram_init(struct drm_device *dev); 1157extern int nv1a_fb_vram_init(struct drm_device *dev); 1158extern int nv10_fb_init(struct drm_device *); 1159extern void nv10_fb_takedown(struct drm_device *); 1160extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1161 uint32_t addr, uint32_t size, 1162 uint32_t pitch, uint32_t flags); 1163extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1164extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1165 1166/* nv20_fb.c */ 1167extern int nv20_fb_vram_init(struct drm_device *dev); 1168extern int nv20_fb_init(struct drm_device *); 1169extern void nv20_fb_takedown(struct drm_device *); 1170extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1171 uint32_t addr, uint32_t size, 1172 uint32_t pitch, uint32_t flags); 1173extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1174extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1175 1176/* nv30_fb.c */ 1177extern int nv30_fb_init(struct drm_device *); 1178extern void nv30_fb_takedown(struct drm_device *); 1179extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1180 uint32_t addr, uint32_t size, 1181 uint32_t pitch, uint32_t flags); 1182extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1183 1184/* nv40_fb.c */ 1185extern int nv40_fb_vram_init(struct drm_device *dev); 1186extern int nv40_fb_init(struct drm_device *); 1187extern void nv40_fb_takedown(struct drm_device *); 1188extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1189 1190/* nv50_fb.c */ 1191extern int nv50_fb_init(struct drm_device *); 1192extern void nv50_fb_takedown(struct drm_device *); 1193extern void nv50_fb_vm_trap(struct drm_device *, int display); 1194 1195/* nvc0_fb.c */ 1196extern int nvc0_fb_init(struct drm_device *); 1197extern void nvc0_fb_takedown(struct drm_device *); 1198 1199/* nv04_fifo.c */ 1200extern int nv04_fifo_init(struct drm_device *); 1201extern void nv04_fifo_fini(struct drm_device *); 1202extern void nv04_fifo_disable(struct drm_device *); 1203extern void nv04_fifo_enable(struct drm_device *); 1204extern bool nv04_fifo_reassign(struct drm_device *, bool); 1205extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1206extern int nv04_fifo_channel_id(struct drm_device *); 1207extern int nv04_fifo_create_context(struct nouveau_channel *); 1208extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1209extern int nv04_fifo_load_context(struct nouveau_channel *); 1210extern int nv04_fifo_unload_context(struct drm_device *); 1211extern void nv04_fifo_isr(struct drm_device *); 1212 1213/* nv10_fifo.c */ 1214extern int nv10_fifo_init(struct drm_device *); 1215extern int nv10_fifo_channel_id(struct drm_device *); 1216extern int nv10_fifo_create_context(struct nouveau_channel *); 1217extern int nv10_fifo_load_context(struct nouveau_channel *); 1218extern int nv10_fifo_unload_context(struct drm_device *); 1219 1220/* nv40_fifo.c */ 1221extern int nv40_fifo_init(struct drm_device *); 1222extern int nv40_fifo_create_context(struct nouveau_channel *); 1223extern int nv40_fifo_load_context(struct nouveau_channel *); 1224extern int nv40_fifo_unload_context(struct drm_device *); 1225 1226/* nv50_fifo.c */ 1227extern int nv50_fifo_init(struct drm_device *); 1228extern void nv50_fifo_takedown(struct drm_device *); 1229extern int nv50_fifo_channel_id(struct drm_device *); 1230extern int nv50_fifo_create_context(struct nouveau_channel *); 1231extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1232extern int nv50_fifo_load_context(struct nouveau_channel *); 1233extern int nv50_fifo_unload_context(struct drm_device *); 1234extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1235 1236/* nvc0_fifo.c */ 1237extern int nvc0_fifo_init(struct drm_device *); 1238extern void nvc0_fifo_takedown(struct drm_device *); 1239extern void nvc0_fifo_disable(struct drm_device *); 1240extern void nvc0_fifo_enable(struct drm_device *); 1241extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1242extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1243extern int nvc0_fifo_channel_id(struct drm_device *); 1244extern int nvc0_fifo_create_context(struct nouveau_channel *); 1245extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1246extern int nvc0_fifo_load_context(struct nouveau_channel *); 1247extern int nvc0_fifo_unload_context(struct drm_device *); 1248 1249/* nv04_graph.c */ 1250extern int nv04_graph_create(struct drm_device *); 1251extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1252extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1253 u32 class, u32 mthd, u32 data); 1254extern struct nouveau_bitfield nv04_graph_nsource[]; 1255 1256/* nv10_graph.c */ 1257extern int nv10_graph_create(struct drm_device *); 1258extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1259extern struct nouveau_bitfield nv10_graph_intr[]; 1260extern struct nouveau_bitfield nv10_graph_nstatus[]; 1261 1262/* nv20_graph.c */ 1263extern int nv20_graph_create(struct drm_device *); 1264 1265/* nv40_graph.c */ 1266extern int nv40_graph_create(struct drm_device *); 1267extern void nv40_grctx_init(struct nouveau_grctx *); 1268 1269/* nv50_graph.c */ 1270extern int nv50_graph_create(struct drm_device *); 1271extern int nv50_grctx_init(struct nouveau_grctx *); 1272extern struct nouveau_enum nv50_data_error_names[]; 1273extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1274 1275/* nvc0_graph.c */ 1276extern int nvc0_graph_create(struct drm_device *); 1277extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1278 1279/* nv84_crypt.c */ 1280extern int nv84_crypt_create(struct drm_device *); 1281 1282/* nv98_crypt.c */ 1283extern int nv98_crypt_create(struct drm_device *dev); 1284 1285/* nva3_copy.c */ 1286extern int nva3_copy_create(struct drm_device *dev); 1287 1288/* nvc0_copy.c */ 1289extern int nvc0_copy_create(struct drm_device *dev, int engine); 1290 1291/* nv31_mpeg.c */ 1292extern int nv31_mpeg_create(struct drm_device *dev); 1293 1294/* nv50_mpeg.c */ 1295extern int nv50_mpeg_create(struct drm_device *dev); 1296 1297/* nv84_bsp.c */ 1298/* nv98_bsp.c */ 1299extern int nv84_bsp_create(struct drm_device *dev); 1300 1301/* nv84_vp.c */ 1302/* nv98_vp.c */ 1303extern int nv84_vp_create(struct drm_device *dev); 1304 1305/* nv98_ppp.c */ 1306extern int nv98_ppp_create(struct drm_device *dev); 1307 1308/* nv04_instmem.c */ 1309extern int nv04_instmem_init(struct drm_device *); 1310extern void nv04_instmem_takedown(struct drm_device *); 1311extern int nv04_instmem_suspend(struct drm_device *); 1312extern void nv04_instmem_resume(struct drm_device *); 1313extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1314 u32 size, u32 align); 1315extern void nv04_instmem_put(struct nouveau_gpuobj *); 1316extern int nv04_instmem_map(struct nouveau_gpuobj *); 1317extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1318extern void nv04_instmem_flush(struct drm_device *); 1319 1320/* nv50_instmem.c */ 1321extern int nv50_instmem_init(struct drm_device *); 1322extern void nv50_instmem_takedown(struct drm_device *); 1323extern int nv50_instmem_suspend(struct drm_device *); 1324extern void nv50_instmem_resume(struct drm_device *); 1325extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1326 u32 size, u32 align); 1327extern void nv50_instmem_put(struct nouveau_gpuobj *); 1328extern int nv50_instmem_map(struct nouveau_gpuobj *); 1329extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1330extern void nv50_instmem_flush(struct drm_device *); 1331extern void nv84_instmem_flush(struct drm_device *); 1332 1333/* nvc0_instmem.c */ 1334extern int nvc0_instmem_init(struct drm_device *); 1335extern void nvc0_instmem_takedown(struct drm_device *); 1336extern int nvc0_instmem_suspend(struct drm_device *); 1337extern void nvc0_instmem_resume(struct drm_device *); 1338 1339/* nv04_mc.c */ 1340extern int nv04_mc_init(struct drm_device *); 1341extern void nv04_mc_takedown(struct drm_device *); 1342 1343/* nv40_mc.c */ 1344extern int nv40_mc_init(struct drm_device *); 1345extern void nv40_mc_takedown(struct drm_device *); 1346 1347/* nv50_mc.c */ 1348extern int nv50_mc_init(struct drm_device *); 1349extern void nv50_mc_takedown(struct drm_device *); 1350 1351/* nv04_timer.c */ 1352extern int nv04_timer_init(struct drm_device *); 1353extern uint64_t nv04_timer_read(struct drm_device *); 1354extern void nv04_timer_takedown(struct drm_device *); 1355 1356extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1357 unsigned long arg); 1358 1359/* nv04_dac.c */ 1360extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1361extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1362extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1363extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1364extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1365 1366/* nv04_dfp.c */ 1367extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1368extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1369extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1370 int head, bool dl); 1371extern void nv04_dfp_disable(struct drm_device *dev, int head); 1372extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1373 1374/* nv04_tv.c */ 1375extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1376extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1377 1378/* nv17_tv.c */ 1379extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1380 1381/* nv04_display.c */ 1382extern int nv04_display_early_init(struct drm_device *); 1383extern void nv04_display_late_takedown(struct drm_device *); 1384extern int nv04_display_create(struct drm_device *); 1385extern void nv04_display_destroy(struct drm_device *); 1386extern int nv04_display_init(struct drm_device *); 1387extern void nv04_display_fini(struct drm_device *); 1388 1389/* nvd0_display.c */ 1390extern int nvd0_display_create(struct drm_device *); 1391extern void nvd0_display_destroy(struct drm_device *); 1392extern int nvd0_display_init(struct drm_device *); 1393extern void nvd0_display_fini(struct drm_device *); 1394struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1395void nvd0_display_flip_stop(struct drm_crtc *); 1396int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1397 struct nouveau_channel *, u32 swap_interval); 1398 1399/* nv04_crtc.c */ 1400extern int nv04_crtc_create(struct drm_device *, int index); 1401 1402/* nouveau_bo.c */ 1403extern struct ttm_bo_driver nouveau_bo_driver; 1404extern int nouveau_bo_new(struct drm_device *, int size, int align, 1405 uint32_t flags, uint32_t tile_mode, 1406 uint32_t tile_flags, struct nouveau_bo **); 1407extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1408extern int nouveau_bo_unpin(struct nouveau_bo *); 1409extern int nouveau_bo_map(struct nouveau_bo *); 1410extern void nouveau_bo_unmap(struct nouveau_bo *); 1411extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1412 uint32_t busy); 1413extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1414extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1415extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1416extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1417extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1418extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1419 bool no_wait_reserve, bool no_wait_gpu); 1420 1421extern struct nouveau_vma * 1422nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1423extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1424 struct nouveau_vma *); 1425extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1426 1427/* nouveau_fence.c */ 1428struct nouveau_fence; 1429extern int nouveau_fence_init(struct drm_device *); 1430extern void nouveau_fence_fini(struct drm_device *); 1431extern int nouveau_fence_channel_init(struct nouveau_channel *); 1432extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1433extern void nouveau_fence_update(struct nouveau_channel *); 1434extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1435 bool emit); 1436extern int nouveau_fence_emit(struct nouveau_fence *); 1437extern void nouveau_fence_work(struct nouveau_fence *fence, 1438 void (*work)(void *priv, bool signalled), 1439 void *priv); 1440struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1441 1442extern bool __nouveau_fence_signalled(void *obj, void *arg); 1443extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1444extern int __nouveau_fence_flush(void *obj, void *arg); 1445extern void __nouveau_fence_unref(void **obj); 1446extern void *__nouveau_fence_ref(void *obj); 1447 1448static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1449{ 1450 return __nouveau_fence_signalled(obj, NULL); 1451} 1452static inline int 1453nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1454{ 1455 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1456} 1457extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1458static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1459{ 1460 return __nouveau_fence_flush(obj, NULL); 1461} 1462static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1463{ 1464 __nouveau_fence_unref((void **)obj); 1465} 1466static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1467{ 1468 return __nouveau_fence_ref(obj); 1469} 1470 1471/* nouveau_gem.c */ 1472extern int nouveau_gem_new(struct drm_device *, int size, int align, 1473 uint32_t domain, uint32_t tile_mode, 1474 uint32_t tile_flags, struct nouveau_bo **); 1475extern int nouveau_gem_object_new(struct drm_gem_object *); 1476extern void nouveau_gem_object_del(struct drm_gem_object *); 1477extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1478extern void nouveau_gem_object_close(struct drm_gem_object *, 1479 struct drm_file *); 1480extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1481 struct drm_file *); 1482extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1483 struct drm_file *); 1484extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1485 struct drm_file *); 1486extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1487 struct drm_file *); 1488extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1489 struct drm_file *); 1490 1491/* nouveau_display.c */ 1492int nouveau_display_create(struct drm_device *dev); 1493void nouveau_display_destroy(struct drm_device *dev); 1494int nouveau_display_init(struct drm_device *dev); 1495void nouveau_display_fini(struct drm_device *dev); 1496int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1497void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1498int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1499 struct drm_pending_vblank_event *event); 1500int nouveau_finish_page_flip(struct nouveau_channel *, 1501 struct nouveau_page_flip_state *); 1502int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1503 struct drm_mode_create_dumb *args); 1504int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1505 uint32_t handle, uint64_t *offset); 1506int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1507 uint32_t handle); 1508 1509/* nv10_gpio.c */ 1510int nv10_gpio_init(struct drm_device *dev); 1511void nv10_gpio_fini(struct drm_device *dev); 1512int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1513int nv10_gpio_sense(struct drm_device *dev, int line); 1514void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1515 1516/* nv50_gpio.c */ 1517int nv50_gpio_init(struct drm_device *dev); 1518void nv50_gpio_fini(struct drm_device *dev); 1519int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1520int nv50_gpio_sense(struct drm_device *dev, int line); 1521void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1522int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1523int nvd0_gpio_sense(struct drm_device *dev, int line); 1524 1525/* nv50_calc.c */ 1526int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1527 int *N1, int *M1, int *N2, int *M2, int *P); 1528int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1529 int clk, int *N, int *fN, int *M, int *P); 1530 1531#ifndef ioread32_native 1532#ifdef __BIG_ENDIAN 1533#define ioread16_native ioread16be 1534#define iowrite16_native iowrite16be 1535#define ioread32_native ioread32be 1536#define iowrite32_native iowrite32be 1537#else /* def __BIG_ENDIAN */ 1538#define ioread16_native ioread16 1539#define iowrite16_native iowrite16 1540#define ioread32_native ioread32 1541#define iowrite32_native iowrite32 1542#endif /* def __BIG_ENDIAN else */ 1543#endif /* !ioread32_native */ 1544 1545/* channel control reg access */ 1546static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1547{ 1548 return ioread32_native(chan->user + reg); 1549} 1550 1551static inline void nvchan_wr32(struct nouveau_channel *chan, 1552 unsigned reg, u32 val) 1553{ 1554 iowrite32_native(val, chan->user + reg); 1555} 1556 1557/* register access */ 1558static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1559{ 1560 struct drm_nouveau_private *dev_priv = dev->dev_private; 1561 return ioread32_native(dev_priv->mmio + reg); 1562} 1563 1564static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1565{ 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 iowrite32_native(val, dev_priv->mmio + reg); 1568} 1569 1570static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1571{ 1572 u32 tmp = nv_rd32(dev, reg); 1573 nv_wr32(dev, reg, (tmp & ~mask) | val); 1574 return tmp; 1575} 1576 1577static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1578{ 1579 struct drm_nouveau_private *dev_priv = dev->dev_private; 1580 return ioread8(dev_priv->mmio + reg); 1581} 1582 1583static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1584{ 1585 struct drm_nouveau_private *dev_priv = dev->dev_private; 1586 iowrite8(val, dev_priv->mmio + reg); 1587} 1588 1589#define nv_wait(dev, reg, mask, val) \ 1590 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1591#define nv_wait_ne(dev, reg, mask, val) \ 1592 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1593#define nv_wait_cb(dev, func, data) \ 1594 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1595 1596/* PRAMIN access */ 1597static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1598{ 1599 struct drm_nouveau_private *dev_priv = dev->dev_private; 1600 return ioread32_native(dev_priv->ramin + offset); 1601} 1602 1603static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1604{ 1605 struct drm_nouveau_private *dev_priv = dev->dev_private; 1606 iowrite32_native(val, dev_priv->ramin + offset); 1607} 1608 1609/* object access */ 1610extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1611extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1612 1613/* 1614 * Logging 1615 * Argument d is (struct drm_device *). 1616 */ 1617#define NV_PRINTK(level, d, fmt, arg...) \ 1618 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1619 pci_name(d->pdev), ##arg) 1620#ifndef NV_DEBUG_NOTRACE 1621#define NV_DEBUG(d, fmt, arg...) do { \ 1622 if (drm_debug & DRM_UT_DRIVER) { \ 1623 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1624 __LINE__, ##arg); \ 1625 } \ 1626} while (0) 1627#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1628 if (drm_debug & DRM_UT_KMS) { \ 1629 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1630 __LINE__, ##arg); \ 1631 } \ 1632} while (0) 1633#else 1634#define NV_DEBUG(d, fmt, arg...) do { \ 1635 if (drm_debug & DRM_UT_DRIVER) \ 1636 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1637} while (0) 1638#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1639 if (drm_debug & DRM_UT_KMS) \ 1640 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1641} while (0) 1642#endif 1643#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1644#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1645#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1646#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1647#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1648#define NV_WARNONCE(d, fmt, arg...) do { \ 1649 static int _warned = 0; \ 1650 if (!_warned) { \ 1651 NV_WARN(d, fmt, ##arg); \ 1652 _warned = 1; \ 1653 } \ 1654} while(0) 1655 1656/* nouveau_reg_debug bitmask */ 1657enum { 1658 NOUVEAU_REG_DEBUG_MC = 0x1, 1659 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1660 NOUVEAU_REG_DEBUG_FB = 0x4, 1661 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1662 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1663 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1664 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1665 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1666 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1667 NOUVEAU_REG_DEBUG_EVO = 0x200, 1668 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1669}; 1670 1671#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1672 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1673 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1674} while (0) 1675 1676static inline bool 1677nv_two_heads(struct drm_device *dev) 1678{ 1679 struct drm_nouveau_private *dev_priv = dev->dev_private; 1680 const int impl = dev->pci_device & 0x0ff0; 1681 1682 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1683 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1684 return true; 1685 1686 return false; 1687} 1688 1689static inline bool 1690nv_gf4_disp_arch(struct drm_device *dev) 1691{ 1692 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1693} 1694 1695static inline bool 1696nv_two_reg_pll(struct drm_device *dev) 1697{ 1698 struct drm_nouveau_private *dev_priv = dev->dev_private; 1699 const int impl = dev->pci_device & 0x0ff0; 1700 1701 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1702 return true; 1703 return false; 1704} 1705 1706static inline bool 1707nv_match_device(struct drm_device *dev, unsigned device, 1708 unsigned sub_vendor, unsigned sub_device) 1709{ 1710 return dev->pdev->device == device && 1711 dev->pdev->subsystem_vendor == sub_vendor && 1712 dev->pdev->subsystem_device == sub_device; 1713} 1714 1715static inline void * 1716nv_engine(struct drm_device *dev, int engine) 1717{ 1718 struct drm_nouveau_private *dev_priv = dev->dev_private; 1719 return (void *)dev_priv->eng[engine]; 1720} 1721 1722/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1723 * helpful to determine a number of other hardware features 1724 */ 1725static inline int 1726nv44_graph_class(struct drm_device *dev) 1727{ 1728 struct drm_nouveau_private *dev_priv = dev->dev_private; 1729 1730 if ((dev_priv->chipset & 0xf0) == 0x60) 1731 return 1; 1732 1733 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1734} 1735 1736/* memory type/access flags, do not match hardware values */ 1737#define NV_MEM_ACCESS_RO 1 1738#define NV_MEM_ACCESS_WO 2 1739#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1740#define NV_MEM_ACCESS_SYS 4 1741#define NV_MEM_ACCESS_VM 8 1742 1743#define NV_MEM_TARGET_VRAM 0 1744#define NV_MEM_TARGET_PCI 1 1745#define NV_MEM_TARGET_PCI_NOSNOOP 2 1746#define NV_MEM_TARGET_VM 3 1747#define NV_MEM_TARGET_GART 4 1748 1749#define NV_MEM_TYPE_VM 0x7f 1750#define NV_MEM_COMP_VM 0x03 1751 1752/* NV_SW object class */ 1753#define NV_SW 0x0000506e 1754#define NV_SW_DMA_SEMAPHORE 0x00000060 1755#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1756#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1757#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1758#define NV_SW_YIELD 0x00000080 1759#define NV_SW_DMA_VBLSEM 0x0000018c 1760#define NV_SW_VBLSEM_OFFSET 0x00000400 1761#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1762#define NV_SW_VBLSEM_RELEASE 0x00000408 1763#define NV_SW_PAGE_FLIP 0x00000500 1764 1765#endif /* __NOUVEAU_DRV_H__ */ 1766