nouveau_drv.h revision 0cba1b7644cbcd855d0a2b2ea4d8da26fd08dec4
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_pull)(struct drm_device *dev, bool enable); 300 301 int (*channel_id)(struct drm_device *); 302 303 int (*create_context)(struct nouveau_channel *); 304 void (*destroy_context)(struct nouveau_channel *); 305 int (*load_context)(struct nouveau_channel *); 306 int (*unload_context)(struct drm_device *); 307}; 308 309struct nouveau_pgraph_object_method { 310 int id; 311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 312 uint32_t data); 313}; 314 315struct nouveau_pgraph_object_class { 316 int id; 317 bool software; 318 struct nouveau_pgraph_object_method *methods; 319}; 320 321struct nouveau_pgraph_engine { 322 struct nouveau_pgraph_object_class *grclass; 323 bool accel_blocked; 324 int grctx_size; 325 326 /* NV2x/NV3x context table (0x400780) */ 327 struct nouveau_gpuobj *ctx_table; 328 329 int (*init)(struct drm_device *); 330 void (*takedown)(struct drm_device *); 331 332 void (*fifo_access)(struct drm_device *, bool); 333 334 struct nouveau_channel *(*channel)(struct drm_device *); 335 int (*create_context)(struct nouveau_channel *); 336 void (*destroy_context)(struct nouveau_channel *); 337 int (*load_context)(struct nouveau_channel *); 338 int (*unload_context)(struct drm_device *); 339 340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 341 uint32_t size, uint32_t pitch); 342}; 343 344struct nouveau_display_engine { 345 int (*early_init)(struct drm_device *); 346 void (*late_takedown)(struct drm_device *); 347 int (*create)(struct drm_device *); 348 int (*init)(struct drm_device *); 349 void (*destroy)(struct drm_device *); 350}; 351 352struct nouveau_gpio_engine { 353 int (*init)(struct drm_device *); 354 void (*takedown)(struct drm_device *); 355 356 int (*get)(struct drm_device *, enum dcb_gpio_tag); 357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 358 359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 360}; 361 362struct nouveau_pm_voltage_level { 363 u8 voltage; 364 u8 vid; 365}; 366 367struct nouveau_pm_voltage { 368 bool supported; 369 u8 vid_mask; 370 371 struct nouveau_pm_voltage_level *level; 372 int nr_level; 373}; 374 375#define NOUVEAU_PM_MAX_LEVEL 8 376struct nouveau_pm_level { 377 struct device_attribute dev_attr; 378 char name[32]; 379 int id; 380 381 u32 core; 382 u32 memory; 383 u32 shader; 384 u32 unk05; 385 386 u8 voltage; 387 u8 fanspeed; 388 389 u16 memscript; 390}; 391 392struct nouveau_pm_temp_sensor_constants { 393 u16 offset_constant; 394 s16 offset_mult; 395 u16 offset_div; 396 u16 slope_mult; 397 u16 slope_div; 398}; 399 400struct nouveau_pm_threshold_temp { 401 s16 critical; 402 s16 down_clock; 403 s16 fan_boost; 404}; 405 406struct nouveau_pm_memtiming { 407 u32 reg_100220; 408 u32 reg_100224; 409 u32 reg_100228; 410 u32 reg_10022c; 411 u32 reg_100230; 412 u32 reg_100234; 413 u32 reg_100238; 414 u32 reg_10023c; 415}; 416 417struct nouveau_pm_memtimings { 418 bool supported; 419 struct nouveau_pm_memtiming *timing; 420 int nr_timing; 421}; 422 423struct nouveau_pm_engine { 424 struct nouveau_pm_voltage voltage; 425 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 426 int nr_perflvl; 427 struct nouveau_pm_memtimings memtimings; 428 struct nouveau_pm_temp_sensor_constants sensor_constants; 429 struct nouveau_pm_threshold_temp threshold_temp; 430 431 struct nouveau_pm_level boot; 432 struct nouveau_pm_level *cur; 433 434 struct device *hwmon; 435 436 int (*clock_get)(struct drm_device *, u32 id); 437 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 438 u32 id, int khz); 439 void (*clock_set)(struct drm_device *, void *); 440 int (*voltage_get)(struct drm_device *); 441 int (*voltage_set)(struct drm_device *, int voltage); 442 int (*fanspeed_get)(struct drm_device *); 443 int (*fanspeed_set)(struct drm_device *, int fanspeed); 444 int (*temp_get)(struct drm_device *); 445}; 446 447struct nouveau_engine { 448 struct nouveau_instmem_engine instmem; 449 struct nouveau_mc_engine mc; 450 struct nouveau_timer_engine timer; 451 struct nouveau_fb_engine fb; 452 struct nouveau_pgraph_engine graph; 453 struct nouveau_fifo_engine fifo; 454 struct nouveau_display_engine display; 455 struct nouveau_gpio_engine gpio; 456 struct nouveau_pm_engine pm; 457}; 458 459struct nouveau_pll_vals { 460 union { 461 struct { 462#ifdef __BIG_ENDIAN 463 uint8_t N1, M1, N2, M2; 464#else 465 uint8_t M1, N1, M2, N2; 466#endif 467 }; 468 struct { 469 uint16_t NM1, NM2; 470 } __attribute__((packed)); 471 }; 472 int log2P; 473 474 int refclk; 475}; 476 477enum nv04_fp_display_regs { 478 FP_DISPLAY_END, 479 FP_TOTAL, 480 FP_CRTC, 481 FP_SYNC_START, 482 FP_SYNC_END, 483 FP_VALID_START, 484 FP_VALID_END 485}; 486 487struct nv04_crtc_reg { 488 unsigned char MiscOutReg; /* */ 489 uint8_t CRTC[0xa0]; 490 uint8_t CR58[0x10]; 491 uint8_t Sequencer[5]; 492 uint8_t Graphics[9]; 493 uint8_t Attribute[21]; 494 unsigned char DAC[768]; /* Internal Colorlookuptable */ 495 496 /* PCRTC regs */ 497 uint32_t fb_start; 498 uint32_t crtc_cfg; 499 uint32_t cursor_cfg; 500 uint32_t gpio_ext; 501 uint32_t crtc_830; 502 uint32_t crtc_834; 503 uint32_t crtc_850; 504 uint32_t crtc_eng_ctrl; 505 506 /* PRAMDAC regs */ 507 uint32_t nv10_cursync; 508 struct nouveau_pll_vals pllvals; 509 uint32_t ramdac_gen_ctrl; 510 uint32_t ramdac_630; 511 uint32_t ramdac_634; 512 uint32_t tv_setup; 513 uint32_t tv_vtotal; 514 uint32_t tv_vskew; 515 uint32_t tv_vsync_delay; 516 uint32_t tv_htotal; 517 uint32_t tv_hskew; 518 uint32_t tv_hsync_delay; 519 uint32_t tv_hsync_delay2; 520 uint32_t fp_horiz_regs[7]; 521 uint32_t fp_vert_regs[7]; 522 uint32_t dither; 523 uint32_t fp_control; 524 uint32_t dither_regs[6]; 525 uint32_t fp_debug_0; 526 uint32_t fp_debug_1; 527 uint32_t fp_debug_2; 528 uint32_t fp_margin_color; 529 uint32_t ramdac_8c0; 530 uint32_t ramdac_a20; 531 uint32_t ramdac_a24; 532 uint32_t ramdac_a34; 533 uint32_t ctv_regs[38]; 534}; 535 536struct nv04_output_reg { 537 uint32_t output; 538 int head; 539}; 540 541struct nv04_mode_state { 542 uint32_t bpp; 543 uint32_t width; 544 uint32_t height; 545 uint32_t interlace; 546 uint32_t repaint0; 547 uint32_t repaint1; 548 uint32_t screen; 549 uint32_t scale; 550 uint32_t dither; 551 uint32_t extra; 552 uint32_t fifo; 553 uint32_t pixel; 554 uint32_t horiz; 555 int arbitration0; 556 int arbitration1; 557 uint32_t pll; 558 uint32_t pllB; 559 uint32_t vpll; 560 uint32_t vpll2; 561 uint32_t vpllB; 562 uint32_t vpll2B; 563 uint32_t pllsel; 564 uint32_t sel_clk; 565 uint32_t general; 566 uint32_t crtcOwner; 567 uint32_t head; 568 uint32_t head2; 569 uint32_t cursorConfig; 570 uint32_t cursor0; 571 uint32_t cursor1; 572 uint32_t cursor2; 573 uint32_t timingH; 574 uint32_t timingV; 575 uint32_t displayV; 576 uint32_t crtcSync; 577 578 struct nv04_crtc_reg crtc_reg[2]; 579}; 580 581enum nouveau_card_type { 582 NV_04 = 0x00, 583 NV_10 = 0x10, 584 NV_20 = 0x20, 585 NV_30 = 0x30, 586 NV_40 = 0x40, 587 NV_50 = 0x50, 588 NV_C0 = 0xc0, 589}; 590 591struct drm_nouveau_private { 592 struct drm_device *dev; 593 594 /* the card type, takes NV_* as values */ 595 enum nouveau_card_type card_type; 596 /* exact chipset, derived from NV_PMC_BOOT_0 */ 597 int chipset; 598 int flags; 599 600 void __iomem *mmio; 601 602 spinlock_t ramin_lock; 603 void __iomem *ramin; 604 u32 ramin_size; 605 u32 ramin_base; 606 bool ramin_available; 607 struct drm_mm ramin_heap; 608 struct list_head gpuobj_list; 609 610 struct nouveau_bo *vga_ram; 611 612 struct workqueue_struct *wq; 613 struct work_struct irq_work; 614 struct work_struct hpd_work; 615 616 struct list_head vbl_waiting; 617 618 struct { 619 struct drm_global_reference mem_global_ref; 620 struct ttm_bo_global_ref bo_global_ref; 621 struct ttm_bo_device bdev; 622 atomic_t validate_sequence; 623 } ttm; 624 625 int fifo_alloc_count; 626 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 627 628 struct nouveau_engine engine; 629 struct nouveau_channel *channel; 630 631 /* For PFIFO and PGRAPH. */ 632 spinlock_t context_switch_lock; 633 634 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 635 struct nouveau_ramht *ramht; 636 struct nouveau_gpuobj *ramfc; 637 struct nouveau_gpuobj *ramro; 638 639 uint32_t ramin_rsvd_vram; 640 641 struct { 642 enum { 643 NOUVEAU_GART_NONE = 0, 644 NOUVEAU_GART_AGP, 645 NOUVEAU_GART_SGDMA 646 } type; 647 uint64_t aper_base; 648 uint64_t aper_size; 649 uint64_t aper_free; 650 651 struct nouveau_gpuobj *sg_ctxdma; 652 struct page *sg_dummy_page; 653 dma_addr_t sg_dummy_bus; 654 } gart_info; 655 656 /* nv10-nv40 tiling regions */ 657 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 658 659 /* VRAM/fb configuration */ 660 uint64_t vram_size; 661 uint64_t vram_sys_base; 662 u32 vram_rblock_size; 663 664 uint64_t fb_phys; 665 uint64_t fb_available_size; 666 uint64_t fb_mappable_pages; 667 uint64_t fb_aper_free; 668 int fb_mtrr; 669 670 /* G8x/G9x virtual address space */ 671 uint64_t vm_gart_base; 672 uint64_t vm_gart_size; 673 uint64_t vm_vram_base; 674 uint64_t vm_vram_size; 675 uint64_t vm_end; 676 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 677 int vm_vram_pt_nr; 678 679 struct nvbios vbios; 680 681 struct nv04_mode_state mode_reg; 682 struct nv04_mode_state saved_reg; 683 uint32_t saved_vga_font[4][16384]; 684 uint32_t crtc_owner; 685 uint32_t dac_users[4]; 686 687 struct nouveau_suspend_resume { 688 uint32_t *ramin_copy; 689 } susres; 690 691 struct backlight_device *backlight; 692 693 struct nouveau_channel *evo; 694 struct { 695 struct dcb_entry *dcb; 696 u16 script; 697 u32 pclk; 698 } evo_irq; 699 700 struct { 701 struct dentry *channel_root; 702 } debugfs; 703 704 struct nouveau_fbdev *nfbdev; 705 struct apertures_struct *apertures; 706}; 707 708static inline struct drm_nouveau_private * 709nouveau_bdev(struct ttm_bo_device *bd) 710{ 711 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 712} 713 714static inline int 715nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 716{ 717 struct nouveau_bo *prev; 718 719 if (!pnvbo) 720 return -EINVAL; 721 prev = *pnvbo; 722 723 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 724 if (prev) { 725 struct ttm_buffer_object *bo = &prev->bo; 726 727 ttm_bo_unref(&bo); 728 } 729 730 return 0; 731} 732 733#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 734 struct drm_nouveau_private *nv = dev->dev_private; \ 735 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 736 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 737 DRM_CURRENTPID, (id)); \ 738 return -EPERM; \ 739 } \ 740 (ch) = nv->fifos[(id)]; \ 741} while (0) 742 743/* nouveau_drv.c */ 744extern int nouveau_agpmode; 745extern int nouveau_duallink; 746extern int nouveau_uscript_lvds; 747extern int nouveau_uscript_tmds; 748extern int nouveau_vram_pushbuf; 749extern int nouveau_vram_notify; 750extern int nouveau_fbpercrtc; 751extern int nouveau_tv_disable; 752extern char *nouveau_tv_norm; 753extern int nouveau_reg_debug; 754extern char *nouveau_vbios; 755extern int nouveau_ignorelid; 756extern int nouveau_nofbaccel; 757extern int nouveau_noaccel; 758extern int nouveau_force_post; 759extern int nouveau_override_conntype; 760extern char *nouveau_perflvl; 761extern int nouveau_perflvl_wr; 762 763extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 764extern int nouveau_pci_resume(struct pci_dev *pdev); 765 766/* nouveau_state.c */ 767extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 768extern int nouveau_load(struct drm_device *, unsigned long flags); 769extern int nouveau_firstopen(struct drm_device *); 770extern void nouveau_lastclose(struct drm_device *); 771extern int nouveau_unload(struct drm_device *); 772extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 773 struct drm_file *); 774extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 775 struct drm_file *); 776extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 777 uint32_t reg, uint32_t mask, uint32_t val); 778extern bool nouveau_wait_for_idle(struct drm_device *); 779extern int nouveau_card_init(struct drm_device *); 780 781/* nouveau_mem.c */ 782extern int nouveau_mem_vram_init(struct drm_device *); 783extern void nouveau_mem_vram_fini(struct drm_device *); 784extern int nouveau_mem_gart_init(struct drm_device *); 785extern void nouveau_mem_gart_fini(struct drm_device *); 786extern int nouveau_mem_init_agp(struct drm_device *); 787extern int nouveau_mem_reset_agp(struct drm_device *); 788extern void nouveau_mem_close(struct drm_device *); 789extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 790 uint32_t addr, 791 uint32_t size, 792 uint32_t pitch); 793extern void nv10_mem_expire_tiling(struct drm_device *dev, 794 struct nouveau_tile_reg *tile, 795 struct nouveau_fence *fence); 796extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 797 uint32_t size, uint32_t flags, 798 uint64_t phys); 799extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 800 uint32_t size); 801 802/* nouveau_notifier.c */ 803extern int nouveau_notifier_init_channel(struct nouveau_channel *); 804extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 805extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 806 int cout, uint32_t *offset); 807extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 808extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 809 struct drm_file *); 810extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 811 struct drm_file *); 812 813/* nouveau_channel.c */ 814extern struct drm_ioctl_desc nouveau_ioctls[]; 815extern int nouveau_max_ioctl; 816extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 817extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 818 int channel); 819extern int nouveau_channel_alloc(struct drm_device *dev, 820 struct nouveau_channel **chan, 821 struct drm_file *file_priv, 822 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 823extern void nouveau_channel_free(struct nouveau_channel *); 824 825/* nouveau_object.c */ 826extern int nouveau_gpuobj_early_init(struct drm_device *); 827extern int nouveau_gpuobj_init(struct drm_device *); 828extern void nouveau_gpuobj_takedown(struct drm_device *); 829extern int nouveau_gpuobj_suspend(struct drm_device *dev); 830extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 831extern void nouveau_gpuobj_resume(struct drm_device *dev); 832extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 833 uint32_t vram_h, uint32_t tt_h); 834extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 835extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 836 uint32_t size, int align, uint32_t flags, 837 struct nouveau_gpuobj **); 838extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 839 struct nouveau_gpuobj **); 840extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 841 u32 size, u32 flags, 842 struct nouveau_gpuobj **); 843extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 844 uint64_t offset, uint64_t size, int access, 845 int target, struct nouveau_gpuobj **); 846extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 847 uint64_t offset, uint64_t size, 848 int access, struct nouveau_gpuobj **, 849 uint32_t *o_ret); 850extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 851 struct nouveau_gpuobj **); 852extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 853 struct nouveau_gpuobj **); 854extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 855 struct drm_file *); 856extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 857 struct drm_file *); 858 859/* nouveau_irq.c */ 860extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 861extern void nouveau_irq_preinstall(struct drm_device *); 862extern int nouveau_irq_postinstall(struct drm_device *); 863extern void nouveau_irq_uninstall(struct drm_device *); 864 865/* nouveau_sgdma.c */ 866extern int nouveau_sgdma_init(struct drm_device *); 867extern void nouveau_sgdma_takedown(struct drm_device *); 868extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 869 uint32_t *page); 870extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 871 872/* nouveau_debugfs.c */ 873#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 874extern int nouveau_debugfs_init(struct drm_minor *); 875extern void nouveau_debugfs_takedown(struct drm_minor *); 876extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 877extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 878#else 879static inline int 880nouveau_debugfs_init(struct drm_minor *minor) 881{ 882 return 0; 883} 884 885static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 886{ 887} 888 889static inline int 890nouveau_debugfs_channel_init(struct nouveau_channel *chan) 891{ 892 return 0; 893} 894 895static inline void 896nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 897{ 898} 899#endif 900 901/* nouveau_dma.c */ 902extern void nouveau_dma_pre_init(struct nouveau_channel *); 903extern int nouveau_dma_init(struct nouveau_channel *); 904extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 905 906/* nouveau_acpi.c */ 907#define ROM_BIOS_PAGE 4096 908#if defined(CONFIG_ACPI) 909void nouveau_register_dsm_handler(void); 910void nouveau_unregister_dsm_handler(void); 911int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 912bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 913int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 914#else 915static inline void nouveau_register_dsm_handler(void) {} 916static inline void nouveau_unregister_dsm_handler(void) {} 917static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 918static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 919static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 920#endif 921 922/* nouveau_backlight.c */ 923#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 924extern int nouveau_backlight_init(struct drm_device *); 925extern void nouveau_backlight_exit(struct drm_device *); 926#else 927static inline int nouveau_backlight_init(struct drm_device *dev) 928{ 929 return 0; 930} 931 932static inline void nouveau_backlight_exit(struct drm_device *dev) { } 933#endif 934 935/* nouveau_bios.c */ 936extern int nouveau_bios_init(struct drm_device *); 937extern void nouveau_bios_takedown(struct drm_device *dev); 938extern int nouveau_run_vbios_init(struct drm_device *); 939extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 940 struct dcb_entry *); 941extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 942 enum dcb_gpio_tag); 943extern struct dcb_connector_table_entry * 944nouveau_bios_connector_entry(struct drm_device *, int index); 945extern u32 get_pll_register(struct drm_device *, enum pll_types); 946extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 947 struct pll_lims *); 948extern int nouveau_bios_run_display_table(struct drm_device *, 949 struct dcb_entry *, 950 uint32_t script, int pxclk); 951extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 952 int *length); 953extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 954extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 955extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 956 bool *dl, bool *if_is_24bit); 957extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 958 int head, int pxclk); 959extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 960 enum LVDS_script, int pxclk); 961 962/* nouveau_ttm.c */ 963int nouveau_ttm_global_init(struct drm_nouveau_private *); 964void nouveau_ttm_global_release(struct drm_nouveau_private *); 965int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 966 967/* nouveau_dp.c */ 968int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 969 uint8_t *data, int data_nr); 970bool nouveau_dp_detect(struct drm_encoder *); 971bool nouveau_dp_link_train(struct drm_encoder *); 972 973/* nv04_fb.c */ 974extern int nv04_fb_init(struct drm_device *); 975extern void nv04_fb_takedown(struct drm_device *); 976 977/* nv10_fb.c */ 978extern int nv10_fb_init(struct drm_device *); 979extern void nv10_fb_takedown(struct drm_device *); 980extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 981 uint32_t, uint32_t); 982 983/* nv30_fb.c */ 984extern int nv30_fb_init(struct drm_device *); 985extern void nv30_fb_takedown(struct drm_device *); 986 987/* nv40_fb.c */ 988extern int nv40_fb_init(struct drm_device *); 989extern void nv40_fb_takedown(struct drm_device *); 990extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 991 uint32_t, uint32_t); 992/* nv50_fb.c */ 993extern int nv50_fb_init(struct drm_device *); 994extern void nv50_fb_takedown(struct drm_device *); 995extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 996 997/* nvc0_fb.c */ 998extern int nvc0_fb_init(struct drm_device *); 999extern void nvc0_fb_takedown(struct drm_device *); 1000 1001/* nv04_fifo.c */ 1002extern int nv04_fifo_init(struct drm_device *); 1003extern void nv04_fifo_disable(struct drm_device *); 1004extern void nv04_fifo_enable(struct drm_device *); 1005extern bool nv04_fifo_reassign(struct drm_device *, bool); 1006extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1007extern int nv04_fifo_channel_id(struct drm_device *); 1008extern int nv04_fifo_create_context(struct nouveau_channel *); 1009extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1010extern int nv04_fifo_load_context(struct nouveau_channel *); 1011extern int nv04_fifo_unload_context(struct drm_device *); 1012 1013/* nv10_fifo.c */ 1014extern int nv10_fifo_init(struct drm_device *); 1015extern int nv10_fifo_channel_id(struct drm_device *); 1016extern int nv10_fifo_create_context(struct nouveau_channel *); 1017extern void nv10_fifo_destroy_context(struct nouveau_channel *); 1018extern int nv10_fifo_load_context(struct nouveau_channel *); 1019extern int nv10_fifo_unload_context(struct drm_device *); 1020 1021/* nv40_fifo.c */ 1022extern int nv40_fifo_init(struct drm_device *); 1023extern int nv40_fifo_create_context(struct nouveau_channel *); 1024extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1025extern int nv40_fifo_load_context(struct nouveau_channel *); 1026extern int nv40_fifo_unload_context(struct drm_device *); 1027 1028/* nv50_fifo.c */ 1029extern int nv50_fifo_init(struct drm_device *); 1030extern void nv50_fifo_takedown(struct drm_device *); 1031extern int nv50_fifo_channel_id(struct drm_device *); 1032extern int nv50_fifo_create_context(struct nouveau_channel *); 1033extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1034extern int nv50_fifo_load_context(struct nouveau_channel *); 1035extern int nv50_fifo_unload_context(struct drm_device *); 1036 1037/* nvc0_fifo.c */ 1038extern int nvc0_fifo_init(struct drm_device *); 1039extern void nvc0_fifo_takedown(struct drm_device *); 1040extern void nvc0_fifo_disable(struct drm_device *); 1041extern void nvc0_fifo_enable(struct drm_device *); 1042extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1043extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1044extern int nvc0_fifo_channel_id(struct drm_device *); 1045extern int nvc0_fifo_create_context(struct nouveau_channel *); 1046extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1047extern int nvc0_fifo_load_context(struct nouveau_channel *); 1048extern int nvc0_fifo_unload_context(struct drm_device *); 1049 1050/* nv04_graph.c */ 1051extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1052extern int nv04_graph_init(struct drm_device *); 1053extern void nv04_graph_takedown(struct drm_device *); 1054extern void nv04_graph_fifo_access(struct drm_device *, bool); 1055extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1056extern int nv04_graph_create_context(struct nouveau_channel *); 1057extern void nv04_graph_destroy_context(struct nouveau_channel *); 1058extern int nv04_graph_load_context(struct nouveau_channel *); 1059extern int nv04_graph_unload_context(struct drm_device *); 1060extern void nv04_graph_context_switch(struct drm_device *); 1061 1062/* nv10_graph.c */ 1063extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1064extern int nv10_graph_init(struct drm_device *); 1065extern void nv10_graph_takedown(struct drm_device *); 1066extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1067extern int nv10_graph_create_context(struct nouveau_channel *); 1068extern void nv10_graph_destroy_context(struct nouveau_channel *); 1069extern int nv10_graph_load_context(struct nouveau_channel *); 1070extern int nv10_graph_unload_context(struct drm_device *); 1071extern void nv10_graph_context_switch(struct drm_device *); 1072extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1073 uint32_t, uint32_t); 1074 1075/* nv20_graph.c */ 1076extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1077extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1078extern int nv20_graph_create_context(struct nouveau_channel *); 1079extern void nv20_graph_destroy_context(struct nouveau_channel *); 1080extern int nv20_graph_load_context(struct nouveau_channel *); 1081extern int nv20_graph_unload_context(struct drm_device *); 1082extern int nv20_graph_init(struct drm_device *); 1083extern void nv20_graph_takedown(struct drm_device *); 1084extern int nv30_graph_init(struct drm_device *); 1085extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1086 uint32_t, uint32_t); 1087 1088/* nv40_graph.c */ 1089extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1090extern int nv40_graph_init(struct drm_device *); 1091extern void nv40_graph_takedown(struct drm_device *); 1092extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1093extern int nv40_graph_create_context(struct nouveau_channel *); 1094extern void nv40_graph_destroy_context(struct nouveau_channel *); 1095extern int nv40_graph_load_context(struct nouveau_channel *); 1096extern int nv40_graph_unload_context(struct drm_device *); 1097extern void nv40_grctx_init(struct nouveau_grctx *); 1098extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1099 uint32_t, uint32_t); 1100 1101/* nv50_graph.c */ 1102extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1103extern int nv50_graph_init(struct drm_device *); 1104extern void nv50_graph_takedown(struct drm_device *); 1105extern void nv50_graph_fifo_access(struct drm_device *, bool); 1106extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1107extern int nv50_graph_create_context(struct nouveau_channel *); 1108extern void nv50_graph_destroy_context(struct nouveau_channel *); 1109extern int nv50_graph_load_context(struct nouveau_channel *); 1110extern int nv50_graph_unload_context(struct drm_device *); 1111extern void nv50_graph_context_switch(struct drm_device *); 1112extern int nv50_grctx_init(struct nouveau_grctx *); 1113 1114/* nvc0_graph.c */ 1115extern int nvc0_graph_init(struct drm_device *); 1116extern void nvc0_graph_takedown(struct drm_device *); 1117extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1118extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1119extern int nvc0_graph_create_context(struct nouveau_channel *); 1120extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1121extern int nvc0_graph_load_context(struct nouveau_channel *); 1122extern int nvc0_graph_unload_context(struct drm_device *); 1123 1124/* nv04_instmem.c */ 1125extern int nv04_instmem_init(struct drm_device *); 1126extern void nv04_instmem_takedown(struct drm_device *); 1127extern int nv04_instmem_suspend(struct drm_device *); 1128extern void nv04_instmem_resume(struct drm_device *); 1129extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1130 uint32_t *size); 1131extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1132extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1133extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1134extern void nv04_instmem_flush(struct drm_device *); 1135 1136/* nv50_instmem.c */ 1137extern int nv50_instmem_init(struct drm_device *); 1138extern void nv50_instmem_takedown(struct drm_device *); 1139extern int nv50_instmem_suspend(struct drm_device *); 1140extern void nv50_instmem_resume(struct drm_device *); 1141extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1142 uint32_t *size); 1143extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1144extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1145extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1146extern void nv50_instmem_flush(struct drm_device *); 1147extern void nv84_instmem_flush(struct drm_device *); 1148extern void nv50_vm_flush(struct drm_device *, int engine); 1149 1150/* nvc0_instmem.c */ 1151extern int nvc0_instmem_init(struct drm_device *); 1152extern void nvc0_instmem_takedown(struct drm_device *); 1153extern int nvc0_instmem_suspend(struct drm_device *); 1154extern void nvc0_instmem_resume(struct drm_device *); 1155extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1156 uint32_t *size); 1157extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1158extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1159extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1160extern void nvc0_instmem_flush(struct drm_device *); 1161 1162/* nv04_mc.c */ 1163extern int nv04_mc_init(struct drm_device *); 1164extern void nv04_mc_takedown(struct drm_device *); 1165 1166/* nv40_mc.c */ 1167extern int nv40_mc_init(struct drm_device *); 1168extern void nv40_mc_takedown(struct drm_device *); 1169 1170/* nv50_mc.c */ 1171extern int nv50_mc_init(struct drm_device *); 1172extern void nv50_mc_takedown(struct drm_device *); 1173 1174/* nv04_timer.c */ 1175extern int nv04_timer_init(struct drm_device *); 1176extern uint64_t nv04_timer_read(struct drm_device *); 1177extern void nv04_timer_takedown(struct drm_device *); 1178 1179extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1180 unsigned long arg); 1181 1182/* nv04_dac.c */ 1183extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1184extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1185extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1186extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1187extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1188 1189/* nv04_dfp.c */ 1190extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1191extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1192extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1193 int head, bool dl); 1194extern void nv04_dfp_disable(struct drm_device *dev, int head); 1195extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1196 1197/* nv04_tv.c */ 1198extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1199extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1200 1201/* nv17_tv.c */ 1202extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1203 1204/* nv04_display.c */ 1205extern int nv04_display_early_init(struct drm_device *); 1206extern void nv04_display_late_takedown(struct drm_device *); 1207extern int nv04_display_create(struct drm_device *); 1208extern int nv04_display_init(struct drm_device *); 1209extern void nv04_display_destroy(struct drm_device *); 1210 1211/* nv04_crtc.c */ 1212extern int nv04_crtc_create(struct drm_device *, int index); 1213 1214/* nouveau_bo.c */ 1215extern struct ttm_bo_driver nouveau_bo_driver; 1216extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1217 int size, int align, uint32_t flags, 1218 uint32_t tile_mode, uint32_t tile_flags, 1219 bool no_vm, bool mappable, struct nouveau_bo **); 1220extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1221extern int nouveau_bo_unpin(struct nouveau_bo *); 1222extern int nouveau_bo_map(struct nouveau_bo *); 1223extern void nouveau_bo_unmap(struct nouveau_bo *); 1224extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1225 uint32_t busy); 1226extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1227extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1228extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1229extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1230extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1231 1232/* nouveau_fence.c */ 1233struct nouveau_fence; 1234extern int nouveau_fence_init(struct nouveau_channel *); 1235extern void nouveau_fence_fini(struct nouveau_channel *); 1236extern void nouveau_fence_update(struct nouveau_channel *); 1237extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1238 bool emit); 1239extern int nouveau_fence_emit(struct nouveau_fence *); 1240struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1241extern bool nouveau_fence_signalled(void *obj, void *arg); 1242extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1243extern int nouveau_fence_flush(void *obj, void *arg); 1244extern void nouveau_fence_unref(void **obj); 1245extern void *nouveau_fence_ref(void *obj); 1246 1247/* nouveau_gem.c */ 1248extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1249 int size, int align, uint32_t flags, 1250 uint32_t tile_mode, uint32_t tile_flags, 1251 bool no_vm, bool mappable, struct nouveau_bo **); 1252extern int nouveau_gem_object_new(struct drm_gem_object *); 1253extern void nouveau_gem_object_del(struct drm_gem_object *); 1254extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1255 struct drm_file *); 1256extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1257 struct drm_file *); 1258extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1259 struct drm_file *); 1260extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1261 struct drm_file *); 1262extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1263 struct drm_file *); 1264 1265/* nv10_gpio.c */ 1266int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1267int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1268 1269/* nv50_gpio.c */ 1270int nv50_gpio_init(struct drm_device *dev); 1271int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1272int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1273void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1274 1275/* nv50_calc. */ 1276int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1277 int *N1, int *M1, int *N2, int *M2, int *P); 1278int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1279 int clk, int *N, int *fN, int *M, int *P); 1280 1281#ifndef ioread32_native 1282#ifdef __BIG_ENDIAN 1283#define ioread16_native ioread16be 1284#define iowrite16_native iowrite16be 1285#define ioread32_native ioread32be 1286#define iowrite32_native iowrite32be 1287#else /* def __BIG_ENDIAN */ 1288#define ioread16_native ioread16 1289#define iowrite16_native iowrite16 1290#define ioread32_native ioread32 1291#define iowrite32_native iowrite32 1292#endif /* def __BIG_ENDIAN else */ 1293#endif /* !ioread32_native */ 1294 1295/* channel control reg access */ 1296static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1297{ 1298 return ioread32_native(chan->user + reg); 1299} 1300 1301static inline void nvchan_wr32(struct nouveau_channel *chan, 1302 unsigned reg, u32 val) 1303{ 1304 iowrite32_native(val, chan->user + reg); 1305} 1306 1307/* register access */ 1308static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1309{ 1310 struct drm_nouveau_private *dev_priv = dev->dev_private; 1311 return ioread32_native(dev_priv->mmio + reg); 1312} 1313 1314static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1315{ 1316 struct drm_nouveau_private *dev_priv = dev->dev_private; 1317 iowrite32_native(val, dev_priv->mmio + reg); 1318} 1319 1320static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1321{ 1322 u32 tmp = nv_rd32(dev, reg); 1323 nv_wr32(dev, reg, (tmp & ~mask) | val); 1324 return tmp; 1325} 1326 1327static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1328{ 1329 struct drm_nouveau_private *dev_priv = dev->dev_private; 1330 return ioread8(dev_priv->mmio + reg); 1331} 1332 1333static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1334{ 1335 struct drm_nouveau_private *dev_priv = dev->dev_private; 1336 iowrite8(val, dev_priv->mmio + reg); 1337} 1338 1339#define nv_wait(dev, reg, mask, val) \ 1340 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1341 1342/* PRAMIN access */ 1343static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1344{ 1345 struct drm_nouveau_private *dev_priv = dev->dev_private; 1346 return ioread32_native(dev_priv->ramin + offset); 1347} 1348 1349static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1350{ 1351 struct drm_nouveau_private *dev_priv = dev->dev_private; 1352 iowrite32_native(val, dev_priv->ramin + offset); 1353} 1354 1355/* object access */ 1356extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1357extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1358 1359/* 1360 * Logging 1361 * Argument d is (struct drm_device *). 1362 */ 1363#define NV_PRINTK(level, d, fmt, arg...) \ 1364 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1365 pci_name(d->pdev), ##arg) 1366#ifndef NV_DEBUG_NOTRACE 1367#define NV_DEBUG(d, fmt, arg...) do { \ 1368 if (drm_debug & DRM_UT_DRIVER) { \ 1369 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1370 __LINE__, ##arg); \ 1371 } \ 1372} while (0) 1373#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1374 if (drm_debug & DRM_UT_KMS) { \ 1375 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1376 __LINE__, ##arg); \ 1377 } \ 1378} while (0) 1379#else 1380#define NV_DEBUG(d, fmt, arg...) do { \ 1381 if (drm_debug & DRM_UT_DRIVER) \ 1382 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1383} while (0) 1384#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1385 if (drm_debug & DRM_UT_KMS) \ 1386 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1387} while (0) 1388#endif 1389#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1390#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1391#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1392#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1393#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1394 1395/* nouveau_reg_debug bitmask */ 1396enum { 1397 NOUVEAU_REG_DEBUG_MC = 0x1, 1398 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1399 NOUVEAU_REG_DEBUG_FB = 0x4, 1400 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1401 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1402 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1403 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1404 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1405 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1406 NOUVEAU_REG_DEBUG_EVO = 0x200, 1407}; 1408 1409#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1410 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1411 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1412} while (0) 1413 1414static inline bool 1415nv_two_heads(struct drm_device *dev) 1416{ 1417 struct drm_nouveau_private *dev_priv = dev->dev_private; 1418 const int impl = dev->pci_device & 0x0ff0; 1419 1420 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1421 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1422 return true; 1423 1424 return false; 1425} 1426 1427static inline bool 1428nv_gf4_disp_arch(struct drm_device *dev) 1429{ 1430 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1431} 1432 1433static inline bool 1434nv_two_reg_pll(struct drm_device *dev) 1435{ 1436 struct drm_nouveau_private *dev_priv = dev->dev_private; 1437 const int impl = dev->pci_device & 0x0ff0; 1438 1439 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1440 return true; 1441 return false; 1442} 1443 1444static inline bool 1445nv_match_device(struct drm_device *dev, unsigned device, 1446 unsigned sub_vendor, unsigned sub_device) 1447{ 1448 return dev->pdev->device == device && 1449 dev->pdev->subsystem_vendor == sub_vendor && 1450 dev->pdev->subsystem_device == sub_device; 1451} 1452 1453#define NV_SW 0x0000506e 1454#define NV_SW_DMA_SEMAPHORE 0x00000060 1455#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1456#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1457#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1458#define NV_SW_DMA_VBLSEM 0x0000018c 1459#define NV_SW_VBLSEM_OFFSET 0x00000400 1460#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1461#define NV_SW_VBLSEM_RELEASE 0x00000408 1462 1463#endif /* __NOUVEAU_DRV_H__ */ 1464