nouveau_drv.h revision 0d87c100312ce75d9bb75a456d8a542e84a1722f
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 15 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62 63#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 64#define NV50_VM_BLOCK (512*1024*1024ULL) 65#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 66 67struct nouveau_bo { 68 struct ttm_buffer_object bo; 69 struct ttm_placement placement; 70 u32 placements[3]; 71 struct ttm_bo_kmap_obj kmap; 72 struct list_head head; 73 74 /* protected by ttm_bo_reserve() */ 75 struct drm_file *reserved_by; 76 struct list_head entry; 77 int pbbo_index; 78 79 struct nouveau_channel *channel; 80 81 bool mappable; 82 bool no_vm; 83 84 uint32_t tile_mode; 85 uint32_t tile_flags; 86 87 struct drm_gem_object *gem; 88 struct drm_file *cpu_filp; 89 int pin_refcnt; 90}; 91 92static inline struct nouveau_bo * 93nouveau_bo(struct ttm_buffer_object *bo) 94{ 95 return container_of(bo, struct nouveau_bo, bo); 96} 97 98static inline struct nouveau_bo * 99nouveau_gem_object(struct drm_gem_object *gem) 100{ 101 return gem ? gem->driver_private : NULL; 102} 103 104/* TODO: submit equivalent to TTM generic API upstream? */ 105static inline void __iomem * 106nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 107{ 108 bool is_iomem; 109 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 110 &nvbo->kmap, &is_iomem); 111 WARN_ON_ONCE(ioptr && !is_iomem); 112 return ioptr; 113} 114 115struct mem_block { 116 struct mem_block *next; 117 struct mem_block *prev; 118 uint64_t start; 119 uint64_t size; 120 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 121}; 122 123enum nouveau_flags { 124 NV_NFORCE = 0x10000000, 125 NV_NFORCE2 = 0x20000000 126}; 127 128#define NVOBJ_ENGINE_SW 0 129#define NVOBJ_ENGINE_GR 1 130#define NVOBJ_ENGINE_DISPLAY 2 131#define NVOBJ_ENGINE_INT 0xdeadbeef 132 133#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 134#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 135#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 136#define NVOBJ_FLAG_FAKE (1 << 3) 137struct nouveau_gpuobj { 138 struct list_head list; 139 140 struct nouveau_channel *im_channel; 141 struct mem_block *im_pramin; 142 struct nouveau_bo *im_backing; 143 uint32_t im_backing_start; 144 uint32_t *im_backing_suspend; 145 int im_bound; 146 147 uint32_t flags; 148 int refcount; 149 150 uint32_t engine; 151 uint32_t class; 152 153 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 154 void *priv; 155}; 156 157struct nouveau_gpuobj_ref { 158 struct list_head list; 159 160 struct nouveau_gpuobj *gpuobj; 161 uint32_t instance; 162 163 struct nouveau_channel *channel; 164 int handle; 165}; 166 167struct nouveau_channel { 168 struct drm_device *dev; 169 int id; 170 171 /* owner of this fifo */ 172 struct drm_file *file_priv; 173 /* mapping of the fifo itself */ 174 struct drm_local_map *map; 175 176 /* mapping of the regs controling the fifo */ 177 void __iomem *user; 178 uint32_t user_get; 179 uint32_t user_put; 180 181 /* Fencing */ 182 struct { 183 /* lock protects the pending list only */ 184 spinlock_t lock; 185 struct list_head pending; 186 uint32_t sequence; 187 uint32_t sequence_ack; 188 uint32_t last_sequence_irq; 189 } fence; 190 191 /* DMA push buffer */ 192 struct nouveau_gpuobj_ref *pushbuf; 193 struct nouveau_bo *pushbuf_bo; 194 uint32_t pushbuf_base; 195 196 /* Notifier memory */ 197 struct nouveau_bo *notifier_bo; 198 struct mem_block *notifier_heap; 199 200 /* PFIFO context */ 201 struct nouveau_gpuobj_ref *ramfc; 202 struct nouveau_gpuobj_ref *cache; 203 204 /* PGRAPH context */ 205 /* XXX may be merge 2 pointers as private data ??? */ 206 struct nouveau_gpuobj_ref *ramin_grctx; 207 void *pgraph_ctx; 208 209 /* NV50 VM */ 210 struct nouveau_gpuobj *vm_pd; 211 struct nouveau_gpuobj_ref *vm_gart_pt; 212 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 213 214 /* Objects */ 215 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 216 struct mem_block *ramin_heap; /* Private PRAMIN heap */ 217 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 218 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 219 220 /* GPU object info for stuff used in-kernel (mm_enabled) */ 221 uint32_t m2mf_ntfy; 222 uint32_t vram_handle; 223 uint32_t gart_handle; 224 bool accel_done; 225 226 /* Push buffer state (only for drm's channel on !mm_enabled) */ 227 struct { 228 int max; 229 int free; 230 int cur; 231 int put; 232 /* access via pushbuf_bo */ 233 } dma; 234 235 uint32_t sw_subchannel[8]; 236 237 struct { 238 struct nouveau_gpuobj *vblsem; 239 uint32_t vblsem_offset; 240 uint32_t vblsem_rval; 241 struct list_head vbl_wait; 242 } nvsw; 243 244 struct { 245 bool active; 246 char name[32]; 247 struct drm_info_list info; 248 } debugfs; 249}; 250 251struct nouveau_instmem_engine { 252 void *priv; 253 254 int (*init)(struct drm_device *dev); 255 void (*takedown)(struct drm_device *dev); 256 int (*suspend)(struct drm_device *dev); 257 void (*resume)(struct drm_device *dev); 258 259 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 260 uint32_t *size); 261 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 263 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 264 void (*prepare_access)(struct drm_device *, bool write); 265 void (*finish_access)(struct drm_device *); 266}; 267 268struct nouveau_mc_engine { 269 int (*init)(struct drm_device *dev); 270 void (*takedown)(struct drm_device *dev); 271}; 272 273struct nouveau_timer_engine { 274 int (*init)(struct drm_device *dev); 275 void (*takedown)(struct drm_device *dev); 276 uint64_t (*read)(struct drm_device *dev); 277}; 278 279struct nouveau_fb_engine { 280 int num_tiles; 281 282 int (*init)(struct drm_device *dev); 283 void (*takedown)(struct drm_device *dev); 284 285 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 286 uint32_t size, uint32_t pitch); 287}; 288 289struct nouveau_fifo_engine { 290 void *priv; 291 292 int channels; 293 294 int (*init)(struct drm_device *); 295 void (*takedown)(struct drm_device *); 296 297 void (*disable)(struct drm_device *); 298 void (*enable)(struct drm_device *); 299 bool (*reassign)(struct drm_device *, bool enable); 300 bool (*cache_flush)(struct drm_device *dev); 301 bool (*cache_pull)(struct drm_device *dev, bool enable); 302 303 int (*channel_id)(struct drm_device *); 304 305 int (*create_context)(struct nouveau_channel *); 306 void (*destroy_context)(struct nouveau_channel *); 307 int (*load_context)(struct nouveau_channel *); 308 int (*unload_context)(struct drm_device *); 309}; 310 311struct nouveau_pgraph_object_method { 312 int id; 313 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 314 uint32_t data); 315}; 316 317struct nouveau_pgraph_object_class { 318 int id; 319 bool software; 320 struct nouveau_pgraph_object_method *methods; 321}; 322 323struct nouveau_pgraph_engine { 324 struct nouveau_pgraph_object_class *grclass; 325 bool accel_blocked; 326 void *ctxprog; 327 void *ctxvals; 328 int grctx_size; 329 330 int (*init)(struct drm_device *); 331 void (*takedown)(struct drm_device *); 332 333 void (*fifo_access)(struct drm_device *, bool); 334 335 struct nouveau_channel *(*channel)(struct drm_device *); 336 int (*create_context)(struct nouveau_channel *); 337 void (*destroy_context)(struct nouveau_channel *); 338 int (*load_context)(struct nouveau_channel *); 339 int (*unload_context)(struct drm_device *); 340 341 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 342 uint32_t size, uint32_t pitch); 343}; 344 345struct nouveau_engine { 346 struct nouveau_instmem_engine instmem; 347 struct nouveau_mc_engine mc; 348 struct nouveau_timer_engine timer; 349 struct nouveau_fb_engine fb; 350 struct nouveau_pgraph_engine graph; 351 struct nouveau_fifo_engine fifo; 352}; 353 354struct nouveau_pll_vals { 355 union { 356 struct { 357#ifdef __BIG_ENDIAN 358 uint8_t N1, M1, N2, M2; 359#else 360 uint8_t M1, N1, M2, N2; 361#endif 362 }; 363 struct { 364 uint16_t NM1, NM2; 365 } __attribute__((packed)); 366 }; 367 int log2P; 368 369 int refclk; 370}; 371 372enum nv04_fp_display_regs { 373 FP_DISPLAY_END, 374 FP_TOTAL, 375 FP_CRTC, 376 FP_SYNC_START, 377 FP_SYNC_END, 378 FP_VALID_START, 379 FP_VALID_END 380}; 381 382struct nv04_crtc_reg { 383 unsigned char MiscOutReg; /* */ 384 uint8_t CRTC[0x9f]; 385 uint8_t CR58[0x10]; 386 uint8_t Sequencer[5]; 387 uint8_t Graphics[9]; 388 uint8_t Attribute[21]; 389 unsigned char DAC[768]; /* Internal Colorlookuptable */ 390 391 /* PCRTC regs */ 392 uint32_t fb_start; 393 uint32_t crtc_cfg; 394 uint32_t cursor_cfg; 395 uint32_t gpio_ext; 396 uint32_t crtc_830; 397 uint32_t crtc_834; 398 uint32_t crtc_850; 399 uint32_t crtc_eng_ctrl; 400 401 /* PRAMDAC regs */ 402 uint32_t nv10_cursync; 403 struct nouveau_pll_vals pllvals; 404 uint32_t ramdac_gen_ctrl; 405 uint32_t ramdac_630; 406 uint32_t ramdac_634; 407 uint32_t tv_setup; 408 uint32_t tv_vtotal; 409 uint32_t tv_vskew; 410 uint32_t tv_vsync_delay; 411 uint32_t tv_htotal; 412 uint32_t tv_hskew; 413 uint32_t tv_hsync_delay; 414 uint32_t tv_hsync_delay2; 415 uint32_t fp_horiz_regs[7]; 416 uint32_t fp_vert_regs[7]; 417 uint32_t dither; 418 uint32_t fp_control; 419 uint32_t dither_regs[6]; 420 uint32_t fp_debug_0; 421 uint32_t fp_debug_1; 422 uint32_t fp_debug_2; 423 uint32_t fp_margin_color; 424 uint32_t ramdac_8c0; 425 uint32_t ramdac_a20; 426 uint32_t ramdac_a24; 427 uint32_t ramdac_a34; 428 uint32_t ctv_regs[38]; 429}; 430 431struct nv04_output_reg { 432 uint32_t output; 433 int head; 434}; 435 436struct nv04_mode_state { 437 uint32_t bpp; 438 uint32_t width; 439 uint32_t height; 440 uint32_t interlace; 441 uint32_t repaint0; 442 uint32_t repaint1; 443 uint32_t screen; 444 uint32_t scale; 445 uint32_t dither; 446 uint32_t extra; 447 uint32_t fifo; 448 uint32_t pixel; 449 uint32_t horiz; 450 int arbitration0; 451 int arbitration1; 452 uint32_t pll; 453 uint32_t pllB; 454 uint32_t vpll; 455 uint32_t vpll2; 456 uint32_t vpllB; 457 uint32_t vpll2B; 458 uint32_t pllsel; 459 uint32_t sel_clk; 460 uint32_t general; 461 uint32_t crtcOwner; 462 uint32_t head; 463 uint32_t head2; 464 uint32_t cursorConfig; 465 uint32_t cursor0; 466 uint32_t cursor1; 467 uint32_t cursor2; 468 uint32_t timingH; 469 uint32_t timingV; 470 uint32_t displayV; 471 uint32_t crtcSync; 472 473 struct nv04_crtc_reg crtc_reg[2]; 474}; 475 476enum nouveau_card_type { 477 NV_04 = 0x00, 478 NV_10 = 0x10, 479 NV_20 = 0x20, 480 NV_30 = 0x30, 481 NV_40 = 0x40, 482 NV_50 = 0x50, 483}; 484 485struct drm_nouveau_private { 486 struct drm_device *dev; 487 enum { 488 NOUVEAU_CARD_INIT_DOWN, 489 NOUVEAU_CARD_INIT_DONE, 490 NOUVEAU_CARD_INIT_FAILED 491 } init_state; 492 493 /* the card type, takes NV_* as values */ 494 enum nouveau_card_type card_type; 495 /* exact chipset, derived from NV_PMC_BOOT_0 */ 496 int chipset; 497 int flags; 498 499 void __iomem *mmio; 500 void __iomem *ramin; 501 uint32_t ramin_size; 502 503 struct workqueue_struct *wq; 504 struct work_struct irq_work; 505 506 struct list_head vbl_waiting; 507 508 struct { 509 struct ttm_global_reference mem_global_ref; 510 struct ttm_bo_global_ref bo_global_ref; 511 struct ttm_bo_device bdev; 512 spinlock_t bo_list_lock; 513 struct list_head bo_list; 514 atomic_t validate_sequence; 515 } ttm; 516 517 struct fb_info *fbdev_info; 518 519 int fifo_alloc_count; 520 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 521 522 struct nouveau_engine engine; 523 struct nouveau_channel *channel; 524 525 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 526 struct nouveau_gpuobj *ramht; 527 uint32_t ramin_rsvd_vram; 528 uint32_t ramht_offset; 529 uint32_t ramht_size; 530 uint32_t ramht_bits; 531 uint32_t ramfc_offset; 532 uint32_t ramfc_size; 533 uint32_t ramro_offset; 534 uint32_t ramro_size; 535 536 /* base physical adresses */ 537 uint64_t fb_phys; 538 uint64_t fb_available_size; 539 uint64_t fb_mappable_pages; 540 uint64_t fb_aper_free; 541 542 struct { 543 enum { 544 NOUVEAU_GART_NONE = 0, 545 NOUVEAU_GART_AGP, 546 NOUVEAU_GART_SGDMA 547 } type; 548 uint64_t aper_base; 549 uint64_t aper_size; 550 uint64_t aper_free; 551 552 struct nouveau_gpuobj *sg_ctxdma; 553 struct page *sg_dummy_page; 554 dma_addr_t sg_dummy_bus; 555 556 /* nottm hack */ 557 struct drm_ttm_backend *sg_be; 558 unsigned long sg_handle; 559 } gart_info; 560 561 /* G8x/G9x virtual address space */ 562 uint64_t vm_gart_base; 563 uint64_t vm_gart_size; 564 uint64_t vm_vram_base; 565 uint64_t vm_vram_size; 566 uint64_t vm_end; 567 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 568 int vm_vram_pt_nr; 569 570 /* the mtrr covering the FB */ 571 int fb_mtrr; 572 573 struct mem_block *ramin_heap; 574 575 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ 576 uint32_t ctx_table_size; 577 struct nouveau_gpuobj_ref *ctx_table; 578 579 struct list_head gpuobj_list; 580 581 struct nvbios VBIOS; 582 struct nouveau_bios_info *vbios; 583 584 struct nv04_mode_state mode_reg; 585 struct nv04_mode_state saved_reg; 586 uint32_t saved_vga_font[4][16384]; 587 uint32_t crtc_owner; 588 uint32_t dac_users[4]; 589 590 struct nouveau_suspend_resume { 591 uint32_t fifo_mode; 592 uint32_t graph_ctx_control; 593 uint32_t graph_state; 594 uint32_t *ramin_copy; 595 uint64_t ramin_size; 596 } susres; 597 598 struct backlight_device *backlight; 599 bool acpi_dsm; 600 601 struct nouveau_channel *evo; 602 603 struct { 604 struct dentry *channel_root; 605 } debugfs; 606}; 607 608static inline struct drm_nouveau_private * 609nouveau_bdev(struct ttm_bo_device *bd) 610{ 611 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 612} 613 614static inline int 615nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 616{ 617 struct nouveau_bo *prev; 618 619 if (!pnvbo) 620 return -EINVAL; 621 prev = *pnvbo; 622 623 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 624 if (prev) { 625 struct ttm_buffer_object *bo = &prev->bo; 626 627 ttm_bo_unref(&bo); 628 } 629 630 return 0; 631} 632 633#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ 634 struct drm_nouveau_private *nv = dev->dev_private; \ 635 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ 636 NV_ERROR(dev, "called without init\n"); \ 637 return -EINVAL; \ 638 } \ 639} while (0) 640 641#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 642 struct drm_nouveau_private *nv = dev->dev_private; \ 643 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 644 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 645 DRM_CURRENTPID, (id)); \ 646 return -EPERM; \ 647 } \ 648 (ch) = nv->fifos[(id)]; \ 649} while (0) 650 651/* nouveau_drv.c */ 652extern int nouveau_noagp; 653extern int nouveau_duallink; 654extern int nouveau_uscript_lvds; 655extern int nouveau_uscript_tmds; 656extern int nouveau_vram_pushbuf; 657extern int nouveau_vram_notify; 658extern int nouveau_fbpercrtc; 659extern char *nouveau_tv_norm; 660extern int nouveau_reg_debug; 661extern char *nouveau_vbios; 662extern int nouveau_ctxfw; 663 664/* nouveau_state.c */ 665extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 666extern int nouveau_load(struct drm_device *, unsigned long flags); 667extern int nouveau_firstopen(struct drm_device *); 668extern void nouveau_lastclose(struct drm_device *); 669extern int nouveau_unload(struct drm_device *); 670extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 671 struct drm_file *); 672extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 673 struct drm_file *); 674extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 675 uint32_t reg, uint32_t mask, uint32_t val); 676extern bool nouveau_wait_for_idle(struct drm_device *); 677extern int nouveau_card_init(struct drm_device *); 678extern int nouveau_ioctl_card_init(struct drm_device *, void *data, 679 struct drm_file *); 680extern int nouveau_ioctl_suspend(struct drm_device *, void *data, 681 struct drm_file *); 682extern int nouveau_ioctl_resume(struct drm_device *, void *data, 683 struct drm_file *); 684 685/* nouveau_mem.c */ 686extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, 687 uint64_t size); 688extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, 689 uint64_t size, int align2, 690 struct drm_file *, int tail); 691extern void nouveau_mem_takedown(struct mem_block **heap); 692extern void nouveau_mem_free_block(struct mem_block *); 693extern uint64_t nouveau_mem_fb_amount(struct drm_device *); 694extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 695extern int nouveau_mem_init(struct drm_device *); 696extern int nouveau_mem_init_agp(struct drm_device *); 697extern void nouveau_mem_close(struct drm_device *); 698extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 699 uint32_t size, uint32_t flags, 700 uint64_t phys); 701extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 702 uint32_t size); 703 704/* nouveau_notifier.c */ 705extern int nouveau_notifier_init_channel(struct nouveau_channel *); 706extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 707extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 708 int cout, uint32_t *offset); 709extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 710extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 711 struct drm_file *); 712extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 713 struct drm_file *); 714 715/* nouveau_channel.c */ 716extern struct drm_ioctl_desc nouveau_ioctls[]; 717extern int nouveau_max_ioctl; 718extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 719extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 720 int channel); 721extern int nouveau_channel_alloc(struct drm_device *dev, 722 struct nouveau_channel **chan, 723 struct drm_file *file_priv, 724 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 725extern void nouveau_channel_free(struct nouveau_channel *); 726extern int nouveau_channel_idle(struct nouveau_channel *chan); 727 728/* nouveau_object.c */ 729extern int nouveau_gpuobj_early_init(struct drm_device *); 730extern int nouveau_gpuobj_init(struct drm_device *); 731extern void nouveau_gpuobj_takedown(struct drm_device *); 732extern void nouveau_gpuobj_late_takedown(struct drm_device *); 733extern int nouveau_gpuobj_suspend(struct drm_device *dev); 734extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 735extern void nouveau_gpuobj_resume(struct drm_device *dev); 736extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 737 uint32_t vram_h, uint32_t tt_h); 738extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 739extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 740 uint32_t size, int align, uint32_t flags, 741 struct nouveau_gpuobj **); 742extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 743extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 744 uint32_t handle, struct nouveau_gpuobj *, 745 struct nouveau_gpuobj_ref **); 746extern int nouveau_gpuobj_ref_del(struct drm_device *, 747 struct nouveau_gpuobj_ref **); 748extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 749 struct nouveau_gpuobj_ref **ref_ret); 750extern int nouveau_gpuobj_new_ref(struct drm_device *, 751 struct nouveau_channel *alloc_chan, 752 struct nouveau_channel *ref_chan, 753 uint32_t handle, uint32_t size, int align, 754 uint32_t flags, struct nouveau_gpuobj_ref **); 755extern int nouveau_gpuobj_new_fake(struct drm_device *, 756 uint32_t p_offset, uint32_t b_offset, 757 uint32_t size, uint32_t flags, 758 struct nouveau_gpuobj **, 759 struct nouveau_gpuobj_ref**); 760extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 761 uint64_t offset, uint64_t size, int access, 762 int target, struct nouveau_gpuobj **); 763extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 764 uint64_t offset, uint64_t size, 765 int access, struct nouveau_gpuobj **, 766 uint32_t *o_ret); 767extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 768 struct nouveau_gpuobj **); 769extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 770 struct drm_file *); 771extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 772 struct drm_file *); 773 774/* nouveau_irq.c */ 775extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 776extern void nouveau_irq_preinstall(struct drm_device *); 777extern int nouveau_irq_postinstall(struct drm_device *); 778extern void nouveau_irq_uninstall(struct drm_device *); 779 780/* nouveau_sgdma.c */ 781extern int nouveau_sgdma_init(struct drm_device *); 782extern void nouveau_sgdma_takedown(struct drm_device *); 783extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 784 uint32_t *page); 785extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 786 787/* nouveau_debugfs.c */ 788#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 789extern int nouveau_debugfs_init(struct drm_minor *); 790extern void nouveau_debugfs_takedown(struct drm_minor *); 791extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 792extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 793#else 794static inline int 795nouveau_debugfs_init(struct drm_minor *minor) 796{ 797 return 0; 798} 799 800static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 801{ 802} 803 804static inline int 805nouveau_debugfs_channel_init(struct nouveau_channel *chan) 806{ 807 return 0; 808} 809 810static inline void 811nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 812{ 813} 814#endif 815 816/* nouveau_dma.c */ 817extern int nouveau_dma_init(struct nouveau_channel *); 818extern int nouveau_dma_wait(struct nouveau_channel *, int size); 819 820/* nouveau_acpi.c */ 821#ifdef CONFIG_ACPI 822extern int nouveau_hybrid_setup(struct drm_device *dev); 823extern bool nouveau_dsm_probe(struct drm_device *dev); 824#else 825static inline int nouveau_hybrid_setup(struct drm_device *dev) 826{ 827 return 0; 828} 829static inline bool nouveau_dsm_probe(struct drm_device *dev) 830{ 831 return false; 832} 833#endif 834 835/* nouveau_backlight.c */ 836#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 837extern int nouveau_backlight_init(struct drm_device *); 838extern void nouveau_backlight_exit(struct drm_device *); 839#else 840static inline int nouveau_backlight_init(struct drm_device *dev) 841{ 842 return 0; 843} 844 845static inline void nouveau_backlight_exit(struct drm_device *dev) { } 846#endif 847 848/* nouveau_bios.c */ 849extern int nouveau_bios_init(struct drm_device *); 850extern void nouveau_bios_takedown(struct drm_device *dev); 851extern int nouveau_run_vbios_init(struct drm_device *); 852extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 853 struct dcb_entry *); 854extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 855 enum dcb_gpio_tag); 856extern struct dcb_connector_table_entry * 857nouveau_bios_connector_entry(struct drm_device *, int index); 858extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 859 struct pll_lims *); 860extern int nouveau_bios_run_display_table(struct drm_device *, 861 struct dcb_entry *, 862 uint32_t script, int pxclk); 863extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 864 int *length); 865extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 866extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 867extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 868 bool *dl, bool *if_is_24bit); 869extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 870 int head, int pxclk); 871extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 872 enum LVDS_script, int pxclk); 873 874/* nouveau_ttm.c */ 875int nouveau_ttm_global_init(struct drm_nouveau_private *); 876void nouveau_ttm_global_release(struct drm_nouveau_private *); 877int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 878 879/* nouveau_dp.c */ 880int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 881 uint8_t *data, int data_nr); 882bool nouveau_dp_detect(struct drm_encoder *); 883bool nouveau_dp_link_train(struct drm_encoder *); 884 885/* nv04_fb.c */ 886extern int nv04_fb_init(struct drm_device *); 887extern void nv04_fb_takedown(struct drm_device *); 888 889/* nv10_fb.c */ 890extern int nv10_fb_init(struct drm_device *); 891extern void nv10_fb_takedown(struct drm_device *); 892extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 893 uint32_t, uint32_t); 894 895/* nv40_fb.c */ 896extern int nv40_fb_init(struct drm_device *); 897extern void nv40_fb_takedown(struct drm_device *); 898extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 899 uint32_t, uint32_t); 900 901/* nv04_fifo.c */ 902extern int nv04_fifo_init(struct drm_device *); 903extern void nv04_fifo_disable(struct drm_device *); 904extern void nv04_fifo_enable(struct drm_device *); 905extern bool nv04_fifo_reassign(struct drm_device *, bool); 906extern bool nv04_fifo_cache_flush(struct drm_device *); 907extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 908extern int nv04_fifo_channel_id(struct drm_device *); 909extern int nv04_fifo_create_context(struct nouveau_channel *); 910extern void nv04_fifo_destroy_context(struct nouveau_channel *); 911extern int nv04_fifo_load_context(struct nouveau_channel *); 912extern int nv04_fifo_unload_context(struct drm_device *); 913 914/* nv10_fifo.c */ 915extern int nv10_fifo_init(struct drm_device *); 916extern int nv10_fifo_channel_id(struct drm_device *); 917extern int nv10_fifo_create_context(struct nouveau_channel *); 918extern void nv10_fifo_destroy_context(struct nouveau_channel *); 919extern int nv10_fifo_load_context(struct nouveau_channel *); 920extern int nv10_fifo_unload_context(struct drm_device *); 921 922/* nv40_fifo.c */ 923extern int nv40_fifo_init(struct drm_device *); 924extern int nv40_fifo_create_context(struct nouveau_channel *); 925extern void nv40_fifo_destroy_context(struct nouveau_channel *); 926extern int nv40_fifo_load_context(struct nouveau_channel *); 927extern int nv40_fifo_unload_context(struct drm_device *); 928 929/* nv50_fifo.c */ 930extern int nv50_fifo_init(struct drm_device *); 931extern void nv50_fifo_takedown(struct drm_device *); 932extern int nv50_fifo_channel_id(struct drm_device *); 933extern int nv50_fifo_create_context(struct nouveau_channel *); 934extern void nv50_fifo_destroy_context(struct nouveau_channel *); 935extern int nv50_fifo_load_context(struct nouveau_channel *); 936extern int nv50_fifo_unload_context(struct drm_device *); 937 938/* nv04_graph.c */ 939extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 940extern int nv04_graph_init(struct drm_device *); 941extern void nv04_graph_takedown(struct drm_device *); 942extern void nv04_graph_fifo_access(struct drm_device *, bool); 943extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 944extern int nv04_graph_create_context(struct nouveau_channel *); 945extern void nv04_graph_destroy_context(struct nouveau_channel *); 946extern int nv04_graph_load_context(struct nouveau_channel *); 947extern int nv04_graph_unload_context(struct drm_device *); 948extern void nv04_graph_context_switch(struct drm_device *); 949 950/* nv10_graph.c */ 951extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 952extern int nv10_graph_init(struct drm_device *); 953extern void nv10_graph_takedown(struct drm_device *); 954extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 955extern int nv10_graph_create_context(struct nouveau_channel *); 956extern void nv10_graph_destroy_context(struct nouveau_channel *); 957extern int nv10_graph_load_context(struct nouveau_channel *); 958extern int nv10_graph_unload_context(struct drm_device *); 959extern void nv10_graph_context_switch(struct drm_device *); 960extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 961 uint32_t, uint32_t); 962 963/* nv20_graph.c */ 964extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 965extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 966extern int nv20_graph_create_context(struct nouveau_channel *); 967extern void nv20_graph_destroy_context(struct nouveau_channel *); 968extern int nv20_graph_load_context(struct nouveau_channel *); 969extern int nv20_graph_unload_context(struct drm_device *); 970extern int nv20_graph_init(struct drm_device *); 971extern void nv20_graph_takedown(struct drm_device *); 972extern int nv30_graph_init(struct drm_device *); 973extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 974 uint32_t, uint32_t); 975 976/* nv40_graph.c */ 977extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 978extern int nv40_graph_init(struct drm_device *); 979extern void nv40_graph_takedown(struct drm_device *); 980extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 981extern int nv40_graph_create_context(struct nouveau_channel *); 982extern void nv40_graph_destroy_context(struct nouveau_channel *); 983extern int nv40_graph_load_context(struct nouveau_channel *); 984extern int nv40_graph_unload_context(struct drm_device *); 985extern void nv40_grctx_init(struct nouveau_grctx *); 986extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 987 uint32_t, uint32_t); 988 989/* nv50_graph.c */ 990extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 991extern int nv50_graph_init(struct drm_device *); 992extern void nv50_graph_takedown(struct drm_device *); 993extern void nv50_graph_fifo_access(struct drm_device *, bool); 994extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 995extern int nv50_graph_create_context(struct nouveau_channel *); 996extern void nv50_graph_destroy_context(struct nouveau_channel *); 997extern int nv50_graph_load_context(struct nouveau_channel *); 998extern int nv50_graph_unload_context(struct drm_device *); 999extern void nv50_graph_context_switch(struct drm_device *); 1000 1001/* nouveau_grctx.c */ 1002extern int nouveau_grctx_prog_load(struct drm_device *); 1003extern void nouveau_grctx_vals_load(struct drm_device *, 1004 struct nouveau_gpuobj *); 1005extern void nouveau_grctx_fini(struct drm_device *); 1006 1007/* nv04_instmem.c */ 1008extern int nv04_instmem_init(struct drm_device *); 1009extern void nv04_instmem_takedown(struct drm_device *); 1010extern int nv04_instmem_suspend(struct drm_device *); 1011extern void nv04_instmem_resume(struct drm_device *); 1012extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1013 uint32_t *size); 1014extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1015extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1016extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1017extern void nv04_instmem_prepare_access(struct drm_device *, bool write); 1018extern void nv04_instmem_finish_access(struct drm_device *); 1019 1020/* nv50_instmem.c */ 1021extern int nv50_instmem_init(struct drm_device *); 1022extern void nv50_instmem_takedown(struct drm_device *); 1023extern int nv50_instmem_suspend(struct drm_device *); 1024extern void nv50_instmem_resume(struct drm_device *); 1025extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1026 uint32_t *size); 1027extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1028extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1029extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1030extern void nv50_instmem_prepare_access(struct drm_device *, bool write); 1031extern void nv50_instmem_finish_access(struct drm_device *); 1032 1033/* nv04_mc.c */ 1034extern int nv04_mc_init(struct drm_device *); 1035extern void nv04_mc_takedown(struct drm_device *); 1036 1037/* nv40_mc.c */ 1038extern int nv40_mc_init(struct drm_device *); 1039extern void nv40_mc_takedown(struct drm_device *); 1040 1041/* nv50_mc.c */ 1042extern int nv50_mc_init(struct drm_device *); 1043extern void nv50_mc_takedown(struct drm_device *); 1044 1045/* nv04_timer.c */ 1046extern int nv04_timer_init(struct drm_device *); 1047extern uint64_t nv04_timer_read(struct drm_device *); 1048extern void nv04_timer_takedown(struct drm_device *); 1049 1050extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1051 unsigned long arg); 1052 1053/* nv04_dac.c */ 1054extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1055extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, 1056 struct drm_connector *connector); 1057extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1058extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1059 1060/* nv04_dfp.c */ 1061extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry); 1062extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1063extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1064 int head, bool dl); 1065extern void nv04_dfp_disable(struct drm_device *dev, int head); 1066extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1067 1068/* nv04_tv.c */ 1069extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1070extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1071 1072/* nv17_tv.c */ 1073extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1074extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, 1075 struct drm_connector *connector, 1076 uint32_t pin_mask); 1077 1078/* nv04_display.c */ 1079extern int nv04_display_create(struct drm_device *); 1080extern void nv04_display_destroy(struct drm_device *); 1081extern void nv04_display_restore(struct drm_device *); 1082 1083/* nv04_crtc.c */ 1084extern int nv04_crtc_create(struct drm_device *, int index); 1085 1086/* nouveau_bo.c */ 1087extern struct ttm_bo_driver nouveau_bo_driver; 1088extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1089 int size, int align, uint32_t flags, 1090 uint32_t tile_mode, uint32_t tile_flags, 1091 bool no_vm, bool mappable, struct nouveau_bo **); 1092extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1093extern int nouveau_bo_unpin(struct nouveau_bo *); 1094extern int nouveau_bo_map(struct nouveau_bo *); 1095extern void nouveau_bo_unmap(struct nouveau_bo *); 1096extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); 1097extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1098extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1099extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1100extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1101 1102/* nouveau_fence.c */ 1103struct nouveau_fence; 1104extern int nouveau_fence_init(struct nouveau_channel *); 1105extern void nouveau_fence_fini(struct nouveau_channel *); 1106extern void nouveau_fence_update(struct nouveau_channel *); 1107extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1108 bool emit); 1109extern int nouveau_fence_emit(struct nouveau_fence *); 1110struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1111extern bool nouveau_fence_signalled(void *obj, void *arg); 1112extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1113extern int nouveau_fence_flush(void *obj, void *arg); 1114extern void nouveau_fence_unref(void **obj); 1115extern void *nouveau_fence_ref(void *obj); 1116extern void nouveau_fence_handler(struct drm_device *dev, int channel); 1117 1118/* nouveau_gem.c */ 1119extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1120 int size, int align, uint32_t flags, 1121 uint32_t tile_mode, uint32_t tile_flags, 1122 bool no_vm, bool mappable, struct nouveau_bo **); 1123extern int nouveau_gem_object_new(struct drm_gem_object *); 1124extern void nouveau_gem_object_del(struct drm_gem_object *); 1125extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1126 struct drm_file *); 1127extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1128 struct drm_file *); 1129extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *, 1130 struct drm_file *); 1131extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *, 1132 struct drm_file *); 1133extern int nouveau_gem_ioctl_pin(struct drm_device *, void *, 1134 struct drm_file *); 1135extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *, 1136 struct drm_file *); 1137extern int nouveau_gem_ioctl_tile(struct drm_device *, void *, 1138 struct drm_file *); 1139extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1140 struct drm_file *); 1141extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1142 struct drm_file *); 1143extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1144 struct drm_file *); 1145 1146/* nv17_gpio.c */ 1147int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1148int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1149 1150#ifndef ioread32_native 1151#ifdef __BIG_ENDIAN 1152#define ioread16_native ioread16be 1153#define iowrite16_native iowrite16be 1154#define ioread32_native ioread32be 1155#define iowrite32_native iowrite32be 1156#else /* def __BIG_ENDIAN */ 1157#define ioread16_native ioread16 1158#define iowrite16_native iowrite16 1159#define ioread32_native ioread32 1160#define iowrite32_native iowrite32 1161#endif /* def __BIG_ENDIAN else */ 1162#endif /* !ioread32_native */ 1163 1164/* channel control reg access */ 1165static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1166{ 1167 return ioread32_native(chan->user + reg); 1168} 1169 1170static inline void nvchan_wr32(struct nouveau_channel *chan, 1171 unsigned reg, u32 val) 1172{ 1173 iowrite32_native(val, chan->user + reg); 1174} 1175 1176/* register access */ 1177static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1178{ 1179 struct drm_nouveau_private *dev_priv = dev->dev_private; 1180 return ioread32_native(dev_priv->mmio + reg); 1181} 1182 1183static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1184{ 1185 struct drm_nouveau_private *dev_priv = dev->dev_private; 1186 iowrite32_native(val, dev_priv->mmio + reg); 1187} 1188 1189static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1190{ 1191 struct drm_nouveau_private *dev_priv = dev->dev_private; 1192 return ioread8(dev_priv->mmio + reg); 1193} 1194 1195static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1196{ 1197 struct drm_nouveau_private *dev_priv = dev->dev_private; 1198 iowrite8(val, dev_priv->mmio + reg); 1199} 1200 1201#define nv_wait(reg, mask, val) \ 1202 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1203 1204/* PRAMIN access */ 1205static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1206{ 1207 struct drm_nouveau_private *dev_priv = dev->dev_private; 1208 return ioread32_native(dev_priv->ramin + offset); 1209} 1210 1211static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1212{ 1213 struct drm_nouveau_private *dev_priv = dev->dev_private; 1214 iowrite32_native(val, dev_priv->ramin + offset); 1215} 1216 1217/* object access */ 1218static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1219 unsigned index) 1220{ 1221 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1222} 1223 1224static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1225 unsigned index, u32 val) 1226{ 1227 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1228} 1229 1230/* 1231 * Logging 1232 * Argument d is (struct drm_device *). 1233 */ 1234#define NV_PRINTK(level, d, fmt, arg...) \ 1235 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1236 pci_name(d->pdev), ##arg) 1237#ifndef NV_DEBUG_NOTRACE 1238#define NV_DEBUG(d, fmt, arg...) do { \ 1239 if (drm_debug & DRM_UT_DRIVER) { \ 1240 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1241 __LINE__, ##arg); \ 1242 } \ 1243} while (0) 1244#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1245 if (drm_debug & DRM_UT_KMS) { \ 1246 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1247 __LINE__, ##arg); \ 1248 } \ 1249} while (0) 1250#else 1251#define NV_DEBUG(d, fmt, arg...) do { \ 1252 if (drm_debug & DRM_UT_DRIVER) \ 1253 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1254} while (0) 1255#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1256 if (drm_debug & DRM_UT_KMS) \ 1257 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1258} while (0) 1259#endif 1260#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1261#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1262#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1263#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1264#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1265 1266/* nouveau_reg_debug bitmask */ 1267enum { 1268 NOUVEAU_REG_DEBUG_MC = 0x1, 1269 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1270 NOUVEAU_REG_DEBUG_FB = 0x4, 1271 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1272 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1273 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1274 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1275 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1276 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1277 NOUVEAU_REG_DEBUG_EVO = 0x200, 1278}; 1279 1280#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1281 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1282 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1283} while (0) 1284 1285static inline bool 1286nv_two_heads(struct drm_device *dev) 1287{ 1288 struct drm_nouveau_private *dev_priv = dev->dev_private; 1289 const int impl = dev->pci_device & 0x0ff0; 1290 1291 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1292 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1293 return true; 1294 1295 return false; 1296} 1297 1298static inline bool 1299nv_gf4_disp_arch(struct drm_device *dev) 1300{ 1301 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1302} 1303 1304static inline bool 1305nv_two_reg_pll(struct drm_device *dev) 1306{ 1307 struct drm_nouveau_private *dev_priv = dev->dev_private; 1308 const int impl = dev->pci_device & 0x0ff0; 1309 1310 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1311 return true; 1312 return false; 1313} 1314 1315#define NV50_NVSW 0x0000506e 1316#define NV50_NVSW_DMA_SEMAPHORE 0x00000060 1317#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 1318#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 1319#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c 1320#define NV50_NVSW_DMA_VBLSEM 0x0000018c 1321#define NV50_NVSW_VBLSEM_OFFSET 0x00000400 1322#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 1323#define NV50_NVSW_VBLSEM_RELEASE 0x00000408 1324 1325#endif /* __NOUVEAU_DRV_H__ */ 1326