nouveau_drv.h revision 1e05415733b0d4668fbce92856fafabfa1a33333
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401}; 402 403struct nouveau_gpio_engine { 404 void *priv; 405 406 int (*init)(struct drm_device *); 407 void (*takedown)(struct drm_device *); 408 409 int (*get)(struct drm_device *, enum dcb_gpio_tag); 410 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 411 412 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 413 void (*)(void *, int), void *); 414 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 415 void (*)(void *, int), void *); 416 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 417}; 418 419struct nouveau_pm_voltage_level { 420 u32 voltage; /* microvolts */ 421 u8 vid; 422}; 423 424struct nouveau_pm_voltage { 425 bool supported; 426 u8 version; 427 u8 vid_mask; 428 429 struct nouveau_pm_voltage_level *level; 430 int nr_level; 431}; 432 433struct nouveau_pm_memtiming { 434 int id; 435 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 436 u32 reg_1; 437 u32 reg_2; 438 u32 reg_3; 439 u32 reg_4; 440 u32 reg_5; 441 u32 reg_6; 442 u32 reg_7; 443 u32 reg_8; 444 /* To be written to 0x1002c0 */ 445 u8 CL; 446 u8 WR; 447}; 448 449struct nouveau_pm_tbl_header{ 450 u8 version; 451 u8 header_len; 452 u8 entry_cnt; 453 u8 entry_len; 454}; 455 456struct nouveau_pm_tbl_entry{ 457 u8 tWR; 458 u8 tUNK_1; 459 u8 tCL; 460 u8 tRP; /* Byte 3 */ 461 u8 empty_4; 462 u8 tRAS; /* Byte 5 */ 463 u8 empty_6; 464 u8 tRFC; /* Byte 7 */ 465 u8 empty_8; 466 u8 tRC; /* Byte 9 */ 467 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 468 u8 empty_15,empty_16,empty_17; 469 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 470}; 471 472/* nouveau_mem.c */ 473void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 474 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 475 struct nouveau_pm_memtiming *timing); 476 477#define NOUVEAU_PM_MAX_LEVEL 8 478struct nouveau_pm_level { 479 struct device_attribute dev_attr; 480 char name[32]; 481 int id; 482 483 u32 core; 484 u32 memory; 485 u32 shader; 486 u32 rop; 487 u32 copy; 488 u32 daemon; 489 u32 vdec; 490 u32 unk05; /* nv50:nva3, roughly.. */ 491 u32 unka0; /* nva3:nvc0 */ 492 u32 hub01; /* nvc0- */ 493 u32 hub06; /* nvc0- */ 494 u32 hub07; /* nvc0- */ 495 496 u32 volt_min; /* microvolts */ 497 u32 volt_max; 498 u8 fanspeed; 499 500 u16 memscript; 501 struct nouveau_pm_memtiming *timing; 502}; 503 504struct nouveau_pm_temp_sensor_constants { 505 u16 offset_constant; 506 s16 offset_mult; 507 s16 offset_div; 508 s16 slope_mult; 509 s16 slope_div; 510}; 511 512struct nouveau_pm_threshold_temp { 513 s16 critical; 514 s16 down_clock; 515 s16 fan_boost; 516}; 517 518struct nouveau_pm_memtimings { 519 bool supported; 520 struct nouveau_pm_memtiming *timing; 521 int nr_timing; 522}; 523 524struct nouveau_pm_fan { 525 u32 min_duty; 526 u32 max_duty; 527 u32 pwm_freq; 528}; 529 530struct nouveau_pm_engine { 531 struct nouveau_pm_voltage voltage; 532 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 533 int nr_perflvl; 534 struct nouveau_pm_memtimings memtimings; 535 struct nouveau_pm_temp_sensor_constants sensor_constants; 536 struct nouveau_pm_threshold_temp threshold_temp; 537 struct nouveau_pm_fan fan; 538 u32 pwm_divisor; 539 540 struct nouveau_pm_level boot; 541 struct nouveau_pm_level *cur; 542 543 struct device *hwmon; 544 struct notifier_block acpi_nb; 545 546 int (*clock_get)(struct drm_device *, u32 id); 547 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 548 u32 id, int khz); 549 void (*clock_set)(struct drm_device *, void *); 550 551 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 552 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 553 void (*clocks_set)(struct drm_device *, void *); 554 555 int (*voltage_get)(struct drm_device *); 556 int (*voltage_set)(struct drm_device *, int voltage); 557 int (*pwm_get)(struct drm_device *, struct dcb_gpio_entry*, u32*, u32*); 558 int (*pwm_set)(struct drm_device *, struct dcb_gpio_entry*, u32, u32); 559 int (*temp_get)(struct drm_device *); 560}; 561 562struct nouveau_vram_engine { 563 struct nouveau_mm mm; 564 565 int (*init)(struct drm_device *); 566 void (*takedown)(struct drm_device *dev); 567 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 568 u32 type, struct nouveau_mem **); 569 void (*put)(struct drm_device *, struct nouveau_mem **); 570 571 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 572}; 573 574struct nouveau_engine { 575 struct nouveau_instmem_engine instmem; 576 struct nouveau_mc_engine mc; 577 struct nouveau_timer_engine timer; 578 struct nouveau_fb_engine fb; 579 struct nouveau_fifo_engine fifo; 580 struct nouveau_display_engine display; 581 struct nouveau_gpio_engine gpio; 582 struct nouveau_pm_engine pm; 583 struct nouveau_vram_engine vram; 584}; 585 586struct nouveau_pll_vals { 587 union { 588 struct { 589#ifdef __BIG_ENDIAN 590 uint8_t N1, M1, N2, M2; 591#else 592 uint8_t M1, N1, M2, N2; 593#endif 594 }; 595 struct { 596 uint16_t NM1, NM2; 597 } __attribute__((packed)); 598 }; 599 int log2P; 600 601 int refclk; 602}; 603 604enum nv04_fp_display_regs { 605 FP_DISPLAY_END, 606 FP_TOTAL, 607 FP_CRTC, 608 FP_SYNC_START, 609 FP_SYNC_END, 610 FP_VALID_START, 611 FP_VALID_END 612}; 613 614struct nv04_crtc_reg { 615 unsigned char MiscOutReg; 616 uint8_t CRTC[0xa0]; 617 uint8_t CR58[0x10]; 618 uint8_t Sequencer[5]; 619 uint8_t Graphics[9]; 620 uint8_t Attribute[21]; 621 unsigned char DAC[768]; 622 623 /* PCRTC regs */ 624 uint32_t fb_start; 625 uint32_t crtc_cfg; 626 uint32_t cursor_cfg; 627 uint32_t gpio_ext; 628 uint32_t crtc_830; 629 uint32_t crtc_834; 630 uint32_t crtc_850; 631 uint32_t crtc_eng_ctrl; 632 633 /* PRAMDAC regs */ 634 uint32_t nv10_cursync; 635 struct nouveau_pll_vals pllvals; 636 uint32_t ramdac_gen_ctrl; 637 uint32_t ramdac_630; 638 uint32_t ramdac_634; 639 uint32_t tv_setup; 640 uint32_t tv_vtotal; 641 uint32_t tv_vskew; 642 uint32_t tv_vsync_delay; 643 uint32_t tv_htotal; 644 uint32_t tv_hskew; 645 uint32_t tv_hsync_delay; 646 uint32_t tv_hsync_delay2; 647 uint32_t fp_horiz_regs[7]; 648 uint32_t fp_vert_regs[7]; 649 uint32_t dither; 650 uint32_t fp_control; 651 uint32_t dither_regs[6]; 652 uint32_t fp_debug_0; 653 uint32_t fp_debug_1; 654 uint32_t fp_debug_2; 655 uint32_t fp_margin_color; 656 uint32_t ramdac_8c0; 657 uint32_t ramdac_a20; 658 uint32_t ramdac_a24; 659 uint32_t ramdac_a34; 660 uint32_t ctv_regs[38]; 661}; 662 663struct nv04_output_reg { 664 uint32_t output; 665 int head; 666}; 667 668struct nv04_mode_state { 669 struct nv04_crtc_reg crtc_reg[2]; 670 uint32_t pllsel; 671 uint32_t sel_clk; 672}; 673 674enum nouveau_card_type { 675 NV_04 = 0x00, 676 NV_10 = 0x10, 677 NV_20 = 0x20, 678 NV_30 = 0x30, 679 NV_40 = 0x40, 680 NV_50 = 0x50, 681 NV_C0 = 0xc0, 682 NV_D0 = 0xd0 683}; 684 685struct drm_nouveau_private { 686 struct drm_device *dev; 687 bool noaccel; 688 689 /* the card type, takes NV_* as values */ 690 enum nouveau_card_type card_type; 691 /* exact chipset, derived from NV_PMC_BOOT_0 */ 692 int chipset; 693 int flags; 694 u32 crystal; 695 696 void __iomem *mmio; 697 698 spinlock_t ramin_lock; 699 void __iomem *ramin; 700 u32 ramin_size; 701 u32 ramin_base; 702 bool ramin_available; 703 struct drm_mm ramin_heap; 704 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 705 struct list_head gpuobj_list; 706 struct list_head classes; 707 708 struct nouveau_bo *vga_ram; 709 710 /* interrupt handling */ 711 void (*irq_handler[32])(struct drm_device *); 712 bool msi_enabled; 713 714 struct list_head vbl_waiting; 715 716 struct { 717 struct drm_global_reference mem_global_ref; 718 struct ttm_bo_global_ref bo_global_ref; 719 struct ttm_bo_device bdev; 720 atomic_t validate_sequence; 721 } ttm; 722 723 struct { 724 spinlock_t lock; 725 struct drm_mm heap; 726 struct nouveau_bo *bo; 727 } fence; 728 729 struct { 730 spinlock_t lock; 731 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 732 } channels; 733 734 struct nouveau_engine engine; 735 struct nouveau_channel *channel; 736 737 /* For PFIFO and PGRAPH. */ 738 spinlock_t context_switch_lock; 739 740 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 741 spinlock_t vm_lock; 742 743 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 744 struct nouveau_ramht *ramht; 745 struct nouveau_gpuobj *ramfc; 746 struct nouveau_gpuobj *ramro; 747 748 uint32_t ramin_rsvd_vram; 749 750 struct { 751 enum { 752 NOUVEAU_GART_NONE = 0, 753 NOUVEAU_GART_AGP, /* AGP */ 754 NOUVEAU_GART_PDMA, /* paged dma object */ 755 NOUVEAU_GART_HW /* on-chip gart/vm */ 756 } type; 757 uint64_t aper_base; 758 uint64_t aper_size; 759 uint64_t aper_free; 760 761 struct ttm_backend_func *func; 762 763 struct { 764 struct page *page; 765 dma_addr_t addr; 766 } dummy; 767 768 struct nouveau_gpuobj *sg_ctxdma; 769 } gart_info; 770 771 /* nv10-nv40 tiling regions */ 772 struct { 773 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 774 spinlock_t lock; 775 } tile; 776 777 /* VRAM/fb configuration */ 778 uint64_t vram_size; 779 uint64_t vram_sys_base; 780 781 uint64_t fb_available_size; 782 uint64_t fb_mappable_pages; 783 uint64_t fb_aper_free; 784 int fb_mtrr; 785 786 /* BAR control (NV50-) */ 787 struct nouveau_vm *bar1_vm; 788 struct nouveau_vm *bar3_vm; 789 790 /* G8x/G9x virtual address space */ 791 struct nouveau_vm *chan_vm; 792 793 struct nvbios vbios; 794 795 struct nv04_mode_state mode_reg; 796 struct nv04_mode_state saved_reg; 797 uint32_t saved_vga_font[4][16384]; 798 uint32_t crtc_owner; 799 uint32_t dac_users[4]; 800 801 struct backlight_device *backlight; 802 803 struct { 804 struct dentry *channel_root; 805 } debugfs; 806 807 struct nouveau_fbdev *nfbdev; 808 struct apertures_struct *apertures; 809}; 810 811static inline struct drm_nouveau_private * 812nouveau_private(struct drm_device *dev) 813{ 814 return dev->dev_private; 815} 816 817static inline struct drm_nouveau_private * 818nouveau_bdev(struct ttm_bo_device *bd) 819{ 820 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 821} 822 823static inline int 824nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 825{ 826 struct nouveau_bo *prev; 827 828 if (!pnvbo) 829 return -EINVAL; 830 prev = *pnvbo; 831 832 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 833 if (prev) { 834 struct ttm_buffer_object *bo = &prev->bo; 835 836 ttm_bo_unref(&bo); 837 } 838 839 return 0; 840} 841 842/* nouveau_drv.c */ 843extern int nouveau_modeset; 844extern int nouveau_agpmode; 845extern int nouveau_duallink; 846extern int nouveau_uscript_lvds; 847extern int nouveau_uscript_tmds; 848extern int nouveau_vram_pushbuf; 849extern int nouveau_vram_notify; 850extern int nouveau_fbpercrtc; 851extern int nouveau_tv_disable; 852extern char *nouveau_tv_norm; 853extern int nouveau_reg_debug; 854extern char *nouveau_vbios; 855extern int nouveau_ignorelid; 856extern int nouveau_nofbaccel; 857extern int nouveau_noaccel; 858extern int nouveau_force_post; 859extern int nouveau_override_conntype; 860extern char *nouveau_perflvl; 861extern int nouveau_perflvl_wr; 862extern int nouveau_msi; 863extern int nouveau_ctxfw; 864 865extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 866extern int nouveau_pci_resume(struct pci_dev *pdev); 867 868/* nouveau_state.c */ 869extern int nouveau_open(struct drm_device *, struct drm_file *); 870extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 871extern void nouveau_postclose(struct drm_device *, struct drm_file *); 872extern int nouveau_load(struct drm_device *, unsigned long flags); 873extern int nouveau_firstopen(struct drm_device *); 874extern void nouveau_lastclose(struct drm_device *); 875extern int nouveau_unload(struct drm_device *); 876extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 877 struct drm_file *); 878extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 879 struct drm_file *); 880extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 881 uint32_t reg, uint32_t mask, uint32_t val); 882extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 883 uint32_t reg, uint32_t mask, uint32_t val); 884extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 885 bool (*cond)(void *), void *); 886extern bool nouveau_wait_for_idle(struct drm_device *); 887extern int nouveau_card_init(struct drm_device *); 888 889/* nouveau_mem.c */ 890extern int nouveau_mem_vram_init(struct drm_device *); 891extern void nouveau_mem_vram_fini(struct drm_device *); 892extern int nouveau_mem_gart_init(struct drm_device *); 893extern void nouveau_mem_gart_fini(struct drm_device *); 894extern int nouveau_mem_init_agp(struct drm_device *); 895extern int nouveau_mem_reset_agp(struct drm_device *); 896extern void nouveau_mem_close(struct drm_device *); 897extern int nouveau_mem_detect(struct drm_device *); 898extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 899extern struct nouveau_tile_reg *nv10_mem_set_tiling( 900 struct drm_device *dev, uint32_t addr, uint32_t size, 901 uint32_t pitch, uint32_t flags); 902extern void nv10_mem_put_tile_region(struct drm_device *dev, 903 struct nouveau_tile_reg *tile, 904 struct nouveau_fence *fence); 905extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 906extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 907 908/* nouveau_notifier.c */ 909extern int nouveau_notifier_init_channel(struct nouveau_channel *); 910extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 911extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 912 int cout, uint32_t start, uint32_t end, 913 uint32_t *offset); 914extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 915extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 916 struct drm_file *); 917extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 918 struct drm_file *); 919 920/* nouveau_channel.c */ 921extern struct drm_ioctl_desc nouveau_ioctls[]; 922extern int nouveau_max_ioctl; 923extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 924extern int nouveau_channel_alloc(struct drm_device *dev, 925 struct nouveau_channel **chan, 926 struct drm_file *file_priv, 927 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 928extern struct nouveau_channel * 929nouveau_channel_get_unlocked(struct nouveau_channel *); 930extern struct nouveau_channel * 931nouveau_channel_get(struct drm_file *, int id); 932extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 933extern void nouveau_channel_put(struct nouveau_channel **); 934extern void nouveau_channel_ref(struct nouveau_channel *chan, 935 struct nouveau_channel **pchan); 936extern void nouveau_channel_idle(struct nouveau_channel *chan); 937 938/* nouveau_object.c */ 939#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 940 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 941 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 942} while (0) 943 944#define NVOBJ_ENGINE_DEL(d, e) do { \ 945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 946 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 947} while (0) 948 949#define NVOBJ_CLASS(d, c, e) do { \ 950 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 951 if (ret) \ 952 return ret; \ 953} while (0) 954 955#define NVOBJ_MTHD(d, c, m, e) do { \ 956 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 957 if (ret) \ 958 return ret; \ 959} while (0) 960 961extern int nouveau_gpuobj_early_init(struct drm_device *); 962extern int nouveau_gpuobj_init(struct drm_device *); 963extern void nouveau_gpuobj_takedown(struct drm_device *); 964extern int nouveau_gpuobj_suspend(struct drm_device *dev); 965extern void nouveau_gpuobj_resume(struct drm_device *dev); 966extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 967extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 968 int (*exec)(struct nouveau_channel *, 969 u32 class, u32 mthd, u32 data)); 970extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 971extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 972extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 973 uint32_t vram_h, uint32_t tt_h); 974extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 975extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 976 uint32_t size, int align, uint32_t flags, 977 struct nouveau_gpuobj **); 978extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 979 struct nouveau_gpuobj **); 980extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 981 u32 size, u32 flags, 982 struct nouveau_gpuobj **); 983extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 984 uint64_t offset, uint64_t size, int access, 985 int target, struct nouveau_gpuobj **); 986extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 987extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 988 u64 size, int target, int access, u32 type, 989 u32 comp, struct nouveau_gpuobj **pobj); 990extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 991 int class, u64 base, u64 size, int target, 992 int access, u32 type, u32 comp); 993extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 994 struct drm_file *); 995extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 996 struct drm_file *); 997 998/* nouveau_irq.c */ 999extern int nouveau_irq_init(struct drm_device *); 1000extern void nouveau_irq_fini(struct drm_device *); 1001extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1002extern void nouveau_irq_register(struct drm_device *, int status_bit, 1003 void (*)(struct drm_device *)); 1004extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1005extern void nouveau_irq_preinstall(struct drm_device *); 1006extern int nouveau_irq_postinstall(struct drm_device *); 1007extern void nouveau_irq_uninstall(struct drm_device *); 1008 1009/* nouveau_sgdma.c */ 1010extern int nouveau_sgdma_init(struct drm_device *); 1011extern void nouveau_sgdma_takedown(struct drm_device *); 1012extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1013 uint32_t offset); 1014extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1015 unsigned long size, 1016 uint32_t page_flags, 1017 struct page *dummy_read_page); 1018 1019/* nouveau_debugfs.c */ 1020#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1021extern int nouveau_debugfs_init(struct drm_minor *); 1022extern void nouveau_debugfs_takedown(struct drm_minor *); 1023extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1024extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1025#else 1026static inline int 1027nouveau_debugfs_init(struct drm_minor *minor) 1028{ 1029 return 0; 1030} 1031 1032static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1033{ 1034} 1035 1036static inline int 1037nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1038{ 1039 return 0; 1040} 1041 1042static inline void 1043nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1044{ 1045} 1046#endif 1047 1048/* nouveau_dma.c */ 1049extern void nouveau_dma_pre_init(struct nouveau_channel *); 1050extern int nouveau_dma_init(struct nouveau_channel *); 1051extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1052 1053/* nouveau_acpi.c */ 1054#define ROM_BIOS_PAGE 4096 1055#if defined(CONFIG_ACPI) 1056void nouveau_register_dsm_handler(void); 1057void nouveau_unregister_dsm_handler(void); 1058int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1059bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1060int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1061#else 1062static inline void nouveau_register_dsm_handler(void) {} 1063static inline void nouveau_unregister_dsm_handler(void) {} 1064static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1065static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1066static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1067#endif 1068 1069/* nouveau_backlight.c */ 1070#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1071extern int nouveau_backlight_init(struct drm_device *); 1072extern void nouveau_backlight_exit(struct drm_device *); 1073#else 1074static inline int nouveau_backlight_init(struct drm_device *dev) 1075{ 1076 return 0; 1077} 1078 1079static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1080#endif 1081 1082/* nouveau_bios.c */ 1083extern int nouveau_bios_init(struct drm_device *); 1084extern void nouveau_bios_takedown(struct drm_device *dev); 1085extern int nouveau_run_vbios_init(struct drm_device *); 1086extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1087 struct dcb_entry *, int crtc); 1088extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1089extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1090 enum dcb_gpio_tag); 1091extern struct dcb_connector_table_entry * 1092nouveau_bios_connector_entry(struct drm_device *, int index); 1093extern u32 get_pll_register(struct drm_device *, enum pll_types); 1094extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1095 struct pll_lims *); 1096extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1097 struct dcb_entry *, int crtc); 1098extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1099extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1100extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1101 bool *dl, bool *if_is_24bit); 1102extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1103 int head, int pxclk); 1104extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1105 enum LVDS_script, int pxclk); 1106bool bios_encoder_match(struct dcb_entry *, u32 hash); 1107 1108/* nouveau_ttm.c */ 1109int nouveau_ttm_global_init(struct drm_nouveau_private *); 1110void nouveau_ttm_global_release(struct drm_nouveau_private *); 1111int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1112 1113/* nouveau_dp.c */ 1114int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1115 uint8_t *data, int data_nr); 1116bool nouveau_dp_detect(struct drm_encoder *); 1117bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1118void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1119u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1120 1121/* nv04_fb.c */ 1122extern int nv04_fb_init(struct drm_device *); 1123extern void nv04_fb_takedown(struct drm_device *); 1124 1125/* nv10_fb.c */ 1126extern int nv10_fb_init(struct drm_device *); 1127extern void nv10_fb_takedown(struct drm_device *); 1128extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1129 uint32_t addr, uint32_t size, 1130 uint32_t pitch, uint32_t flags); 1131extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1132extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1133 1134/* nv30_fb.c */ 1135extern int nv30_fb_init(struct drm_device *); 1136extern void nv30_fb_takedown(struct drm_device *); 1137extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1138 uint32_t addr, uint32_t size, 1139 uint32_t pitch, uint32_t flags); 1140extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1141 1142/* nv40_fb.c */ 1143extern int nv40_fb_init(struct drm_device *); 1144extern void nv40_fb_takedown(struct drm_device *); 1145extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1146 1147/* nv50_fb.c */ 1148extern int nv50_fb_init(struct drm_device *); 1149extern void nv50_fb_takedown(struct drm_device *); 1150extern void nv50_fb_vm_trap(struct drm_device *, int display); 1151 1152/* nvc0_fb.c */ 1153extern int nvc0_fb_init(struct drm_device *); 1154extern void nvc0_fb_takedown(struct drm_device *); 1155 1156/* nv04_fifo.c */ 1157extern int nv04_fifo_init(struct drm_device *); 1158extern void nv04_fifo_fini(struct drm_device *); 1159extern void nv04_fifo_disable(struct drm_device *); 1160extern void nv04_fifo_enable(struct drm_device *); 1161extern bool nv04_fifo_reassign(struct drm_device *, bool); 1162extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1163extern int nv04_fifo_channel_id(struct drm_device *); 1164extern int nv04_fifo_create_context(struct nouveau_channel *); 1165extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1166extern int nv04_fifo_load_context(struct nouveau_channel *); 1167extern int nv04_fifo_unload_context(struct drm_device *); 1168extern void nv04_fifo_isr(struct drm_device *); 1169 1170/* nv10_fifo.c */ 1171extern int nv10_fifo_init(struct drm_device *); 1172extern int nv10_fifo_channel_id(struct drm_device *); 1173extern int nv10_fifo_create_context(struct nouveau_channel *); 1174extern int nv10_fifo_load_context(struct nouveau_channel *); 1175extern int nv10_fifo_unload_context(struct drm_device *); 1176 1177/* nv40_fifo.c */ 1178extern int nv40_fifo_init(struct drm_device *); 1179extern int nv40_fifo_create_context(struct nouveau_channel *); 1180extern int nv40_fifo_load_context(struct nouveau_channel *); 1181extern int nv40_fifo_unload_context(struct drm_device *); 1182 1183/* nv50_fifo.c */ 1184extern int nv50_fifo_init(struct drm_device *); 1185extern void nv50_fifo_takedown(struct drm_device *); 1186extern int nv50_fifo_channel_id(struct drm_device *); 1187extern int nv50_fifo_create_context(struct nouveau_channel *); 1188extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1189extern int nv50_fifo_load_context(struct nouveau_channel *); 1190extern int nv50_fifo_unload_context(struct drm_device *); 1191extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1192 1193/* nvc0_fifo.c */ 1194extern int nvc0_fifo_init(struct drm_device *); 1195extern void nvc0_fifo_takedown(struct drm_device *); 1196extern void nvc0_fifo_disable(struct drm_device *); 1197extern void nvc0_fifo_enable(struct drm_device *); 1198extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1199extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1200extern int nvc0_fifo_channel_id(struct drm_device *); 1201extern int nvc0_fifo_create_context(struct nouveau_channel *); 1202extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1203extern int nvc0_fifo_load_context(struct nouveau_channel *); 1204extern int nvc0_fifo_unload_context(struct drm_device *); 1205 1206/* nv04_graph.c */ 1207extern int nv04_graph_create(struct drm_device *); 1208extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1209extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1210 u32 class, u32 mthd, u32 data); 1211extern struct nouveau_bitfield nv04_graph_nsource[]; 1212 1213/* nv10_graph.c */ 1214extern int nv10_graph_create(struct drm_device *); 1215extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1216extern struct nouveau_bitfield nv10_graph_intr[]; 1217extern struct nouveau_bitfield nv10_graph_nstatus[]; 1218 1219/* nv20_graph.c */ 1220extern int nv20_graph_create(struct drm_device *); 1221 1222/* nv40_graph.c */ 1223extern int nv40_graph_create(struct drm_device *); 1224extern void nv40_grctx_init(struct nouveau_grctx *); 1225 1226/* nv50_graph.c */ 1227extern int nv50_graph_create(struct drm_device *); 1228extern int nv50_grctx_init(struct nouveau_grctx *); 1229extern struct nouveau_enum nv50_data_error_names[]; 1230extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1231 1232/* nvc0_graph.c */ 1233extern int nvc0_graph_create(struct drm_device *); 1234extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1235 1236/* nv84_crypt.c */ 1237extern int nv84_crypt_create(struct drm_device *); 1238 1239/* nv98_crypt.c */ 1240extern int nv98_crypt_create(struct drm_device *dev); 1241 1242/* nva3_copy.c */ 1243extern int nva3_copy_create(struct drm_device *dev); 1244 1245/* nvc0_copy.c */ 1246extern int nvc0_copy_create(struct drm_device *dev, int engine); 1247 1248/* nv31_mpeg.c */ 1249extern int nv31_mpeg_create(struct drm_device *dev); 1250 1251/* nv50_mpeg.c */ 1252extern int nv50_mpeg_create(struct drm_device *dev); 1253 1254/* nv84_bsp.c */ 1255/* nv98_bsp.c */ 1256extern int nv84_bsp_create(struct drm_device *dev); 1257 1258/* nv84_vp.c */ 1259/* nv98_vp.c */ 1260extern int nv84_vp_create(struct drm_device *dev); 1261 1262/* nv98_ppp.c */ 1263extern int nv98_ppp_create(struct drm_device *dev); 1264 1265/* nv04_instmem.c */ 1266extern int nv04_instmem_init(struct drm_device *); 1267extern void nv04_instmem_takedown(struct drm_device *); 1268extern int nv04_instmem_suspend(struct drm_device *); 1269extern void nv04_instmem_resume(struct drm_device *); 1270extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1271 u32 size, u32 align); 1272extern void nv04_instmem_put(struct nouveau_gpuobj *); 1273extern int nv04_instmem_map(struct nouveau_gpuobj *); 1274extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1275extern void nv04_instmem_flush(struct drm_device *); 1276 1277/* nv50_instmem.c */ 1278extern int nv50_instmem_init(struct drm_device *); 1279extern void nv50_instmem_takedown(struct drm_device *); 1280extern int nv50_instmem_suspend(struct drm_device *); 1281extern void nv50_instmem_resume(struct drm_device *); 1282extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1283 u32 size, u32 align); 1284extern void nv50_instmem_put(struct nouveau_gpuobj *); 1285extern int nv50_instmem_map(struct nouveau_gpuobj *); 1286extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1287extern void nv50_instmem_flush(struct drm_device *); 1288extern void nv84_instmem_flush(struct drm_device *); 1289 1290/* nvc0_instmem.c */ 1291extern int nvc0_instmem_init(struct drm_device *); 1292extern void nvc0_instmem_takedown(struct drm_device *); 1293extern int nvc0_instmem_suspend(struct drm_device *); 1294extern void nvc0_instmem_resume(struct drm_device *); 1295 1296/* nv04_mc.c */ 1297extern int nv04_mc_init(struct drm_device *); 1298extern void nv04_mc_takedown(struct drm_device *); 1299 1300/* nv40_mc.c */ 1301extern int nv40_mc_init(struct drm_device *); 1302extern void nv40_mc_takedown(struct drm_device *); 1303 1304/* nv50_mc.c */ 1305extern int nv50_mc_init(struct drm_device *); 1306extern void nv50_mc_takedown(struct drm_device *); 1307 1308/* nv04_timer.c */ 1309extern int nv04_timer_init(struct drm_device *); 1310extern uint64_t nv04_timer_read(struct drm_device *); 1311extern void nv04_timer_takedown(struct drm_device *); 1312 1313extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1314 unsigned long arg); 1315 1316/* nv04_dac.c */ 1317extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1318extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1319extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1320extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1321extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1322 1323/* nv04_dfp.c */ 1324extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1325extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1326extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1327 int head, bool dl); 1328extern void nv04_dfp_disable(struct drm_device *dev, int head); 1329extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1330 1331/* nv04_tv.c */ 1332extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1333extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1334 1335/* nv17_tv.c */ 1336extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1337 1338/* nv04_display.c */ 1339extern int nv04_display_early_init(struct drm_device *); 1340extern void nv04_display_late_takedown(struct drm_device *); 1341extern int nv04_display_create(struct drm_device *); 1342extern int nv04_display_init(struct drm_device *); 1343extern void nv04_display_destroy(struct drm_device *); 1344 1345/* nvd0_display.c */ 1346extern int nvd0_display_create(struct drm_device *); 1347extern int nvd0_display_init(struct drm_device *); 1348extern void nvd0_display_destroy(struct drm_device *); 1349 1350/* nv04_crtc.c */ 1351extern int nv04_crtc_create(struct drm_device *, int index); 1352 1353/* nouveau_bo.c */ 1354extern struct ttm_bo_driver nouveau_bo_driver; 1355extern int nouveau_bo_new(struct drm_device *, int size, int align, 1356 uint32_t flags, uint32_t tile_mode, 1357 uint32_t tile_flags, struct nouveau_bo **); 1358extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1359extern int nouveau_bo_unpin(struct nouveau_bo *); 1360extern int nouveau_bo_map(struct nouveau_bo *); 1361extern void nouveau_bo_unmap(struct nouveau_bo *); 1362extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1363 uint32_t busy); 1364extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1365extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1366extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1367extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1368extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1369extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1370 bool no_wait_reserve, bool no_wait_gpu); 1371 1372extern struct nouveau_vma * 1373nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1374extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1375 struct nouveau_vma *); 1376extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1377 1378/* nouveau_fence.c */ 1379struct nouveau_fence; 1380extern int nouveau_fence_init(struct drm_device *); 1381extern void nouveau_fence_fini(struct drm_device *); 1382extern int nouveau_fence_channel_init(struct nouveau_channel *); 1383extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1384extern void nouveau_fence_update(struct nouveau_channel *); 1385extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1386 bool emit); 1387extern int nouveau_fence_emit(struct nouveau_fence *); 1388extern void nouveau_fence_work(struct nouveau_fence *fence, 1389 void (*work)(void *priv, bool signalled), 1390 void *priv); 1391struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1392 1393extern bool __nouveau_fence_signalled(void *obj, void *arg); 1394extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1395extern int __nouveau_fence_flush(void *obj, void *arg); 1396extern void __nouveau_fence_unref(void **obj); 1397extern void *__nouveau_fence_ref(void *obj); 1398 1399static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1400{ 1401 return __nouveau_fence_signalled(obj, NULL); 1402} 1403static inline int 1404nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1405{ 1406 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1407} 1408extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1409static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1410{ 1411 return __nouveau_fence_flush(obj, NULL); 1412} 1413static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1414{ 1415 __nouveau_fence_unref((void **)obj); 1416} 1417static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1418{ 1419 return __nouveau_fence_ref(obj); 1420} 1421 1422/* nouveau_gem.c */ 1423extern int nouveau_gem_new(struct drm_device *, int size, int align, 1424 uint32_t domain, uint32_t tile_mode, 1425 uint32_t tile_flags, struct nouveau_bo **); 1426extern int nouveau_gem_object_new(struct drm_gem_object *); 1427extern void nouveau_gem_object_del(struct drm_gem_object *); 1428extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1429extern void nouveau_gem_object_close(struct drm_gem_object *, 1430 struct drm_file *); 1431extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1432 struct drm_file *); 1433extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1434 struct drm_file *); 1435extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1436 struct drm_file *); 1437extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1438 struct drm_file *); 1439extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1440 struct drm_file *); 1441 1442/* nouveau_display.c */ 1443int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1444void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1445int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1446 struct drm_pending_vblank_event *event); 1447int nouveau_finish_page_flip(struct nouveau_channel *, 1448 struct nouveau_page_flip_state *); 1449int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1450 struct drm_mode_create_dumb *args); 1451int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1452 uint32_t handle, uint64_t *offset); 1453int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1454 uint32_t handle); 1455 1456/* nv10_gpio.c */ 1457int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1458int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1459 1460/* nv50_gpio.c */ 1461int nv50_gpio_init(struct drm_device *dev); 1462void nv50_gpio_fini(struct drm_device *dev); 1463int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1464int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1465int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1466int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1467int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1468 void (*)(void *, int), void *); 1469void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1470 void (*)(void *, int), void *); 1471bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1472 1473/* nv50_calc. */ 1474int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1475 int *N1, int *M1, int *N2, int *M2, int *P); 1476int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1477 int clk, int *N, int *fN, int *M, int *P); 1478 1479#ifndef ioread32_native 1480#ifdef __BIG_ENDIAN 1481#define ioread16_native ioread16be 1482#define iowrite16_native iowrite16be 1483#define ioread32_native ioread32be 1484#define iowrite32_native iowrite32be 1485#else /* def __BIG_ENDIAN */ 1486#define ioread16_native ioread16 1487#define iowrite16_native iowrite16 1488#define ioread32_native ioread32 1489#define iowrite32_native iowrite32 1490#endif /* def __BIG_ENDIAN else */ 1491#endif /* !ioread32_native */ 1492 1493/* channel control reg access */ 1494static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1495{ 1496 return ioread32_native(chan->user + reg); 1497} 1498 1499static inline void nvchan_wr32(struct nouveau_channel *chan, 1500 unsigned reg, u32 val) 1501{ 1502 iowrite32_native(val, chan->user + reg); 1503} 1504 1505/* register access */ 1506static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1507{ 1508 struct drm_nouveau_private *dev_priv = dev->dev_private; 1509 return ioread32_native(dev_priv->mmio + reg); 1510} 1511 1512static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1513{ 1514 struct drm_nouveau_private *dev_priv = dev->dev_private; 1515 iowrite32_native(val, dev_priv->mmio + reg); 1516} 1517 1518static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1519{ 1520 u32 tmp = nv_rd32(dev, reg); 1521 nv_wr32(dev, reg, (tmp & ~mask) | val); 1522 return tmp; 1523} 1524 1525static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1526{ 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 return ioread8(dev_priv->mmio + reg); 1529} 1530 1531static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1532{ 1533 struct drm_nouveau_private *dev_priv = dev->dev_private; 1534 iowrite8(val, dev_priv->mmio + reg); 1535} 1536 1537#define nv_wait(dev, reg, mask, val) \ 1538 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1539#define nv_wait_ne(dev, reg, mask, val) \ 1540 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1541#define nv_wait_cb(dev, func, data) \ 1542 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1543 1544/* PRAMIN access */ 1545static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1546{ 1547 struct drm_nouveau_private *dev_priv = dev->dev_private; 1548 return ioread32_native(dev_priv->ramin + offset); 1549} 1550 1551static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1552{ 1553 struct drm_nouveau_private *dev_priv = dev->dev_private; 1554 iowrite32_native(val, dev_priv->ramin + offset); 1555} 1556 1557/* object access */ 1558extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1559extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1560 1561/* 1562 * Logging 1563 * Argument d is (struct drm_device *). 1564 */ 1565#define NV_PRINTK(level, d, fmt, arg...) \ 1566 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1567 pci_name(d->pdev), ##arg) 1568#ifndef NV_DEBUG_NOTRACE 1569#define NV_DEBUG(d, fmt, arg...) do { \ 1570 if (drm_debug & DRM_UT_DRIVER) { \ 1571 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1572 __LINE__, ##arg); \ 1573 } \ 1574} while (0) 1575#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1576 if (drm_debug & DRM_UT_KMS) { \ 1577 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1578 __LINE__, ##arg); \ 1579 } \ 1580} while (0) 1581#else 1582#define NV_DEBUG(d, fmt, arg...) do { \ 1583 if (drm_debug & DRM_UT_DRIVER) \ 1584 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1585} while (0) 1586#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1587 if (drm_debug & DRM_UT_KMS) \ 1588 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1589} while (0) 1590#endif 1591#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1592#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1593#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1594#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1595#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1596 1597/* nouveau_reg_debug bitmask */ 1598enum { 1599 NOUVEAU_REG_DEBUG_MC = 0x1, 1600 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1601 NOUVEAU_REG_DEBUG_FB = 0x4, 1602 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1603 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1604 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1605 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1606 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1607 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1608 NOUVEAU_REG_DEBUG_EVO = 0x200, 1609 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1610}; 1611 1612#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1613 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1614 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1615} while (0) 1616 1617static inline bool 1618nv_two_heads(struct drm_device *dev) 1619{ 1620 struct drm_nouveau_private *dev_priv = dev->dev_private; 1621 const int impl = dev->pci_device & 0x0ff0; 1622 1623 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1624 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1625 return true; 1626 1627 return false; 1628} 1629 1630static inline bool 1631nv_gf4_disp_arch(struct drm_device *dev) 1632{ 1633 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1634} 1635 1636static inline bool 1637nv_two_reg_pll(struct drm_device *dev) 1638{ 1639 struct drm_nouveau_private *dev_priv = dev->dev_private; 1640 const int impl = dev->pci_device & 0x0ff0; 1641 1642 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1643 return true; 1644 return false; 1645} 1646 1647static inline bool 1648nv_match_device(struct drm_device *dev, unsigned device, 1649 unsigned sub_vendor, unsigned sub_device) 1650{ 1651 return dev->pdev->device == device && 1652 dev->pdev->subsystem_vendor == sub_vendor && 1653 dev->pdev->subsystem_device == sub_device; 1654} 1655 1656static inline void * 1657nv_engine(struct drm_device *dev, int engine) 1658{ 1659 struct drm_nouveau_private *dev_priv = dev->dev_private; 1660 return (void *)dev_priv->eng[engine]; 1661} 1662 1663/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1664 * helpful to determine a number of other hardware features 1665 */ 1666static inline int 1667nv44_graph_class(struct drm_device *dev) 1668{ 1669 struct drm_nouveau_private *dev_priv = dev->dev_private; 1670 1671 if ((dev_priv->chipset & 0xf0) == 0x60) 1672 return 1; 1673 1674 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1675} 1676 1677/* memory type/access flags, do not match hardware values */ 1678#define NV_MEM_ACCESS_RO 1 1679#define NV_MEM_ACCESS_WO 2 1680#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1681#define NV_MEM_ACCESS_SYS 4 1682#define NV_MEM_ACCESS_VM 8 1683 1684#define NV_MEM_TARGET_VRAM 0 1685#define NV_MEM_TARGET_PCI 1 1686#define NV_MEM_TARGET_PCI_NOSNOOP 2 1687#define NV_MEM_TARGET_VM 3 1688#define NV_MEM_TARGET_GART 4 1689 1690#define NV_MEM_TYPE_VM 0x7f 1691#define NV_MEM_COMP_VM 0x03 1692 1693/* NV_SW object class */ 1694#define NV_SW 0x0000506e 1695#define NV_SW_DMA_SEMAPHORE 0x00000060 1696#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1697#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1698#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1699#define NV_SW_YIELD 0x00000080 1700#define NV_SW_DMA_VBLSEM 0x0000018c 1701#define NV_SW_VBLSEM_OFFSET 0x00000400 1702#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1703#define NV_SW_VBLSEM_RELEASE 0x00000408 1704#define NV_SW_PAGE_FLIP 0x00000500 1705 1706#endif /* __NOUVEAU_DRV_H__ */ 1707