nouveau_drv.h revision 20f63afe988a25b0a4d991e87b41f76ee14e2a84
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58struct nouveau_grctx; 59 60#define MAX_NUM_DCB_ENTRIES 16 61 62#define NOUVEAU_MAX_CHANNEL_NR 128 63#define NOUVEAU_MAX_TILE_NR 15 64 65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 66#define NV50_VM_BLOCK (512*1024*1024ULL) 67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 68 69struct nouveau_tile_reg { 70 bool used; 71 uint32_t addr; 72 uint32_t limit; 73 uint32_t pitch; 74 uint32_t zcomp; 75 struct drm_mm_node *tag_mem; 76 struct nouveau_fence *fence; 77}; 78 79struct nouveau_bo { 80 struct ttm_buffer_object bo; 81 struct ttm_placement placement; 82 u32 placements[3]; 83 u32 busy_placements[3]; 84 struct ttm_bo_kmap_obj kmap; 85 struct list_head head; 86 87 /* protected by ttm_bo_reserve() */ 88 struct drm_file *reserved_by; 89 struct list_head entry; 90 int pbbo_index; 91 bool validate_mapped; 92 93 struct nouveau_channel *channel; 94 95 bool mappable; 96 bool no_vm; 97 98 uint32_t tile_mode; 99 uint32_t tile_flags; 100 struct nouveau_tile_reg *tile; 101 102 struct drm_gem_object *gem; 103 int pin_refcnt; 104}; 105 106#define nouveau_bo_tile_layout(nvbo) \ 107 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 108 109static inline struct nouveau_bo * 110nouveau_bo(struct ttm_buffer_object *bo) 111{ 112 return container_of(bo, struct nouveau_bo, bo); 113} 114 115static inline struct nouveau_bo * 116nouveau_gem_object(struct drm_gem_object *gem) 117{ 118 return gem ? gem->driver_private : NULL; 119} 120 121/* TODO: submit equivalent to TTM generic API upstream? */ 122static inline void __iomem * 123nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 124{ 125 bool is_iomem; 126 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 127 &nvbo->kmap, &is_iomem); 128 WARN_ON_ONCE(ioptr && !is_iomem); 129 return ioptr; 130} 131 132enum nouveau_flags { 133 NV_NFORCE = 0x10000000, 134 NV_NFORCE2 = 0x20000000 135}; 136 137#define NVOBJ_ENGINE_SW 0 138#define NVOBJ_ENGINE_GR 1 139#define NVOBJ_ENGINE_PPP 2 140#define NVOBJ_ENGINE_COPY 3 141#define NVOBJ_ENGINE_VP 4 142#define NVOBJ_ENGINE_CRYPT 5 143#define NVOBJ_ENGINE_BSP 6 144#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 145#define NVOBJ_ENGINE_INT 0xdeadbeef 146 147#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 148#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 149 150#define NVOBJ_CINST_GLOBAL 0xdeadbeef 151 152struct nouveau_gpuobj { 153 struct drm_device *dev; 154 struct kref refcount; 155 struct list_head list; 156 157 void *node; 158 u32 *suspend; 159 160 uint32_t flags; 161 162 u32 size; 163 u32 pinst; 164 u32 cinst; 165 u64 vinst; 166 167 uint32_t engine; 168 uint32_t class; 169 170 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 171 void *priv; 172}; 173 174struct nouveau_page_flip_state { 175 struct list_head head; 176 struct drm_pending_vblank_event *event; 177 int crtc, bpp, pitch, x, y; 178 uint64_t offset; 179}; 180 181enum nouveau_channel_mutex_class { 182 NOUVEAU_UCHANNEL_MUTEX, 183 NOUVEAU_KCHANNEL_MUTEX 184}; 185 186struct nouveau_channel { 187 struct drm_device *dev; 188 int id; 189 190 /* references to the channel data structure */ 191 struct kref ref; 192 /* users of the hardware channel resources, the hardware 193 * context will be kicked off when it reaches zero. */ 194 atomic_t users; 195 struct mutex mutex; 196 197 /* owner of this fifo */ 198 struct drm_file *file_priv; 199 /* mapping of the fifo itself */ 200 struct drm_local_map *map; 201 202 /* mapping of the regs controling the fifo */ 203 void __iomem *user; 204 uint32_t user_get; 205 uint32_t user_put; 206 207 /* Fencing */ 208 struct { 209 /* lock protects the pending list only */ 210 spinlock_t lock; 211 struct list_head pending; 212 uint32_t sequence; 213 uint32_t sequence_ack; 214 atomic_t last_sequence_irq; 215 } fence; 216 217 /* DMA push buffer */ 218 struct nouveau_gpuobj *pushbuf; 219 struct nouveau_bo *pushbuf_bo; 220 uint32_t pushbuf_base; 221 222 /* Notifier memory */ 223 struct nouveau_bo *notifier_bo; 224 struct drm_mm notifier_heap; 225 226 /* PFIFO context */ 227 struct nouveau_gpuobj *ramfc; 228 struct nouveau_gpuobj *cache; 229 230 /* PGRAPH context */ 231 /* XXX may be merge 2 pointers as private data ??? */ 232 struct nouveau_gpuobj *ramin_grctx; 233 struct nouveau_gpuobj *crypt_ctx; 234 void *pgraph_ctx; 235 236 /* NV50 VM */ 237 struct nouveau_gpuobj *vm_pd; 238 struct nouveau_gpuobj *vm_gart_pt; 239 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 240 241 /* Objects */ 242 struct nouveau_gpuobj *ramin; /* Private instmem */ 243 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 244 struct nouveau_ramht *ramht; /* Hash table */ 245 246 /* GPU object info for stuff used in-kernel (mm_enabled) */ 247 uint32_t m2mf_ntfy; 248 uint32_t vram_handle; 249 uint32_t gart_handle; 250 bool accel_done; 251 252 /* Push buffer state (only for drm's channel on !mm_enabled) */ 253 struct { 254 int max; 255 int free; 256 int cur; 257 int put; 258 /* access via pushbuf_bo */ 259 260 int ib_base; 261 int ib_max; 262 int ib_free; 263 int ib_put; 264 } dma; 265 266 uint32_t sw_subchannel[8]; 267 268 struct { 269 struct nouveau_gpuobj *vblsem; 270 uint32_t vblsem_head; 271 uint32_t vblsem_offset; 272 uint32_t vblsem_rval; 273 struct list_head vbl_wait; 274 struct list_head flip; 275 } nvsw; 276 277 struct { 278 bool active; 279 char name[32]; 280 struct drm_info_list info; 281 } debugfs; 282}; 283 284struct nouveau_instmem_engine { 285 void *priv; 286 287 int (*init)(struct drm_device *dev); 288 void (*takedown)(struct drm_device *dev); 289 int (*suspend)(struct drm_device *dev); 290 void (*resume)(struct drm_device *dev); 291 292 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 293 void (*put)(struct nouveau_gpuobj *); 294 int (*map)(struct nouveau_gpuobj *); 295 void (*unmap)(struct nouveau_gpuobj *); 296 297 void (*flush)(struct drm_device *); 298}; 299 300struct nouveau_mc_engine { 301 int (*init)(struct drm_device *dev); 302 void (*takedown)(struct drm_device *dev); 303}; 304 305struct nouveau_timer_engine { 306 int (*init)(struct drm_device *dev); 307 void (*takedown)(struct drm_device *dev); 308 uint64_t (*read)(struct drm_device *dev); 309}; 310 311struct nouveau_fb_engine { 312 int num_tiles; 313 struct drm_mm tag_heap; 314 void *priv; 315 316 int (*init)(struct drm_device *dev); 317 void (*takedown)(struct drm_device *dev); 318 319 void (*init_tile_region)(struct drm_device *dev, int i, 320 uint32_t addr, uint32_t size, 321 uint32_t pitch, uint32_t flags); 322 void (*set_tile_region)(struct drm_device *dev, int i); 323 void (*free_tile_region)(struct drm_device *dev, int i); 324}; 325 326struct nouveau_fifo_engine { 327 int channels; 328 329 struct nouveau_gpuobj *playlist[2]; 330 int cur_playlist; 331 332 int (*init)(struct drm_device *); 333 void (*takedown)(struct drm_device *); 334 335 void (*disable)(struct drm_device *); 336 void (*enable)(struct drm_device *); 337 bool (*reassign)(struct drm_device *, bool enable); 338 bool (*cache_pull)(struct drm_device *dev, bool enable); 339 340 int (*channel_id)(struct drm_device *); 341 342 int (*create_context)(struct nouveau_channel *); 343 void (*destroy_context)(struct nouveau_channel *); 344 int (*load_context)(struct nouveau_channel *); 345 int (*unload_context)(struct drm_device *); 346 void (*tlb_flush)(struct drm_device *dev); 347}; 348 349struct nouveau_pgraph_engine { 350 bool accel_blocked; 351 bool registered; 352 int grctx_size; 353 354 /* NV2x/NV3x context table (0x400780) */ 355 struct nouveau_gpuobj *ctx_table; 356 357 int (*init)(struct drm_device *); 358 void (*takedown)(struct drm_device *); 359 360 void (*fifo_access)(struct drm_device *, bool); 361 362 struct nouveau_channel *(*channel)(struct drm_device *); 363 int (*create_context)(struct nouveau_channel *); 364 void (*destroy_context)(struct nouveau_channel *); 365 int (*load_context)(struct nouveau_channel *); 366 int (*unload_context)(struct drm_device *); 367 void (*tlb_flush)(struct drm_device *dev); 368 369 void (*set_tile_region)(struct drm_device *dev, int i); 370}; 371 372struct nouveau_display_engine { 373 int (*early_init)(struct drm_device *); 374 void (*late_takedown)(struct drm_device *); 375 int (*create)(struct drm_device *); 376 int (*init)(struct drm_device *); 377 void (*destroy)(struct drm_device *); 378}; 379 380struct nouveau_gpio_engine { 381 void *priv; 382 383 int (*init)(struct drm_device *); 384 void (*takedown)(struct drm_device *); 385 386 int (*get)(struct drm_device *, enum dcb_gpio_tag); 387 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 388 389 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 390 void (*)(void *, int), void *); 391 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 392 void (*)(void *, int), void *); 393 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 394}; 395 396struct nouveau_pm_voltage_level { 397 u8 voltage; 398 u8 vid; 399}; 400 401struct nouveau_pm_voltage { 402 bool supported; 403 u8 vid_mask; 404 405 struct nouveau_pm_voltage_level *level; 406 int nr_level; 407}; 408 409#define NOUVEAU_PM_MAX_LEVEL 8 410struct nouveau_pm_level { 411 struct device_attribute dev_attr; 412 char name[32]; 413 int id; 414 415 u32 core; 416 u32 memory; 417 u32 shader; 418 u32 unk05; 419 420 u8 voltage; 421 u8 fanspeed; 422 423 u16 memscript; 424}; 425 426struct nouveau_pm_temp_sensor_constants { 427 u16 offset_constant; 428 s16 offset_mult; 429 u16 offset_div; 430 u16 slope_mult; 431 u16 slope_div; 432}; 433 434struct nouveau_pm_threshold_temp { 435 s16 critical; 436 s16 down_clock; 437 s16 fan_boost; 438}; 439 440struct nouveau_pm_memtiming { 441 u32 reg_100220; 442 u32 reg_100224; 443 u32 reg_100228; 444 u32 reg_10022c; 445 u32 reg_100230; 446 u32 reg_100234; 447 u32 reg_100238; 448 u32 reg_10023c; 449}; 450 451struct nouveau_pm_memtimings { 452 bool supported; 453 struct nouveau_pm_memtiming *timing; 454 int nr_timing; 455}; 456 457struct nouveau_pm_engine { 458 struct nouveau_pm_voltage voltage; 459 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 460 int nr_perflvl; 461 struct nouveau_pm_memtimings memtimings; 462 struct nouveau_pm_temp_sensor_constants sensor_constants; 463 struct nouveau_pm_threshold_temp threshold_temp; 464 465 struct nouveau_pm_level boot; 466 struct nouveau_pm_level *cur; 467 468 struct device *hwmon; 469 struct notifier_block acpi_nb; 470 471 int (*clock_get)(struct drm_device *, u32 id); 472 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 473 u32 id, int khz); 474 void (*clock_set)(struct drm_device *, void *); 475 int (*voltage_get)(struct drm_device *); 476 int (*voltage_set)(struct drm_device *, int voltage); 477 int (*fanspeed_get)(struct drm_device *); 478 int (*fanspeed_set)(struct drm_device *, int fanspeed); 479 int (*temp_get)(struct drm_device *); 480}; 481 482struct nouveau_crypt_engine { 483 bool registered; 484 485 int (*init)(struct drm_device *); 486 void (*takedown)(struct drm_device *); 487 int (*create_context)(struct nouveau_channel *); 488 void (*destroy_context)(struct nouveau_channel *); 489 void (*tlb_flush)(struct drm_device *dev); 490}; 491 492struct nouveau_engine { 493 struct nouveau_instmem_engine instmem; 494 struct nouveau_mc_engine mc; 495 struct nouveau_timer_engine timer; 496 struct nouveau_fb_engine fb; 497 struct nouveau_pgraph_engine graph; 498 struct nouveau_fifo_engine fifo; 499 struct nouveau_display_engine display; 500 struct nouveau_gpio_engine gpio; 501 struct nouveau_pm_engine pm; 502 struct nouveau_crypt_engine crypt; 503}; 504 505struct nouveau_pll_vals { 506 union { 507 struct { 508#ifdef __BIG_ENDIAN 509 uint8_t N1, M1, N2, M2; 510#else 511 uint8_t M1, N1, M2, N2; 512#endif 513 }; 514 struct { 515 uint16_t NM1, NM2; 516 } __attribute__((packed)); 517 }; 518 int log2P; 519 520 int refclk; 521}; 522 523enum nv04_fp_display_regs { 524 FP_DISPLAY_END, 525 FP_TOTAL, 526 FP_CRTC, 527 FP_SYNC_START, 528 FP_SYNC_END, 529 FP_VALID_START, 530 FP_VALID_END 531}; 532 533struct nv04_crtc_reg { 534 unsigned char MiscOutReg; 535 uint8_t CRTC[0xa0]; 536 uint8_t CR58[0x10]; 537 uint8_t Sequencer[5]; 538 uint8_t Graphics[9]; 539 uint8_t Attribute[21]; 540 unsigned char DAC[768]; 541 542 /* PCRTC regs */ 543 uint32_t fb_start; 544 uint32_t crtc_cfg; 545 uint32_t cursor_cfg; 546 uint32_t gpio_ext; 547 uint32_t crtc_830; 548 uint32_t crtc_834; 549 uint32_t crtc_850; 550 uint32_t crtc_eng_ctrl; 551 552 /* PRAMDAC regs */ 553 uint32_t nv10_cursync; 554 struct nouveau_pll_vals pllvals; 555 uint32_t ramdac_gen_ctrl; 556 uint32_t ramdac_630; 557 uint32_t ramdac_634; 558 uint32_t tv_setup; 559 uint32_t tv_vtotal; 560 uint32_t tv_vskew; 561 uint32_t tv_vsync_delay; 562 uint32_t tv_htotal; 563 uint32_t tv_hskew; 564 uint32_t tv_hsync_delay; 565 uint32_t tv_hsync_delay2; 566 uint32_t fp_horiz_regs[7]; 567 uint32_t fp_vert_regs[7]; 568 uint32_t dither; 569 uint32_t fp_control; 570 uint32_t dither_regs[6]; 571 uint32_t fp_debug_0; 572 uint32_t fp_debug_1; 573 uint32_t fp_debug_2; 574 uint32_t fp_margin_color; 575 uint32_t ramdac_8c0; 576 uint32_t ramdac_a20; 577 uint32_t ramdac_a24; 578 uint32_t ramdac_a34; 579 uint32_t ctv_regs[38]; 580}; 581 582struct nv04_output_reg { 583 uint32_t output; 584 int head; 585}; 586 587struct nv04_mode_state { 588 struct nv04_crtc_reg crtc_reg[2]; 589 uint32_t pllsel; 590 uint32_t sel_clk; 591}; 592 593enum nouveau_card_type { 594 NV_04 = 0x00, 595 NV_10 = 0x10, 596 NV_20 = 0x20, 597 NV_30 = 0x30, 598 NV_40 = 0x40, 599 NV_50 = 0x50, 600 NV_C0 = 0xc0, 601}; 602 603struct drm_nouveau_private { 604 struct drm_device *dev; 605 606 /* the card type, takes NV_* as values */ 607 enum nouveau_card_type card_type; 608 /* exact chipset, derived from NV_PMC_BOOT_0 */ 609 int chipset; 610 int flags; 611 612 void __iomem *mmio; 613 614 spinlock_t ramin_lock; 615 void __iomem *ramin; 616 u32 ramin_size; 617 u32 ramin_base; 618 bool ramin_available; 619 struct drm_mm ramin_heap; 620 struct list_head gpuobj_list; 621 struct list_head classes; 622 623 struct nouveau_bo *vga_ram; 624 625 /* interrupt handling */ 626 void (*irq_handler[32])(struct drm_device *); 627 bool msi_enabled; 628 struct workqueue_struct *wq; 629 struct work_struct irq_work; 630 631 struct list_head vbl_waiting; 632 633 struct { 634 struct drm_global_reference mem_global_ref; 635 struct ttm_bo_global_ref bo_global_ref; 636 struct ttm_bo_device bdev; 637 atomic_t validate_sequence; 638 } ttm; 639 640 struct { 641 spinlock_t lock; 642 struct drm_mm heap; 643 struct nouveau_bo *bo; 644 } fence; 645 646 struct { 647 spinlock_t lock; 648 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 649 } channels; 650 651 struct nouveau_engine engine; 652 struct nouveau_channel *channel; 653 654 /* For PFIFO and PGRAPH. */ 655 spinlock_t context_switch_lock; 656 657 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 658 struct nouveau_ramht *ramht; 659 struct nouveau_gpuobj *ramfc; 660 struct nouveau_gpuobj *ramro; 661 662 uint32_t ramin_rsvd_vram; 663 664 struct { 665 enum { 666 NOUVEAU_GART_NONE = 0, 667 NOUVEAU_GART_AGP, 668 NOUVEAU_GART_SGDMA 669 } type; 670 uint64_t aper_base; 671 uint64_t aper_size; 672 uint64_t aper_free; 673 674 struct nouveau_gpuobj *sg_ctxdma; 675 struct page *sg_dummy_page; 676 dma_addr_t sg_dummy_bus; 677 } gart_info; 678 679 /* nv10-nv40 tiling regions */ 680 struct { 681 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 682 spinlock_t lock; 683 } tile; 684 685 /* VRAM/fb configuration */ 686 uint64_t vram_size; 687 uint64_t vram_sys_base; 688 u32 vram_rblock_size; 689 690 uint64_t fb_phys; 691 uint64_t fb_available_size; 692 uint64_t fb_mappable_pages; 693 uint64_t fb_aper_free; 694 int fb_mtrr; 695 696 /* G8x/G9x virtual address space */ 697 uint64_t vm_gart_base; 698 uint64_t vm_gart_size; 699 uint64_t vm_vram_base; 700 uint64_t vm_vram_size; 701 uint64_t vm_end; 702 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 703 int vm_vram_pt_nr; 704 705 struct nvbios vbios; 706 707 struct nv04_mode_state mode_reg; 708 struct nv04_mode_state saved_reg; 709 uint32_t saved_vga_font[4][16384]; 710 uint32_t crtc_owner; 711 uint32_t dac_users[4]; 712 713 struct nouveau_suspend_resume { 714 uint32_t *ramin_copy; 715 } susres; 716 717 struct backlight_device *backlight; 718 719 struct nouveau_channel *evo; 720 u32 evo_alloc; 721 struct { 722 struct dcb_entry *dcb; 723 u16 script; 724 u32 pclk; 725 } evo_irq; 726 727 struct { 728 struct dentry *channel_root; 729 } debugfs; 730 731 struct nouveau_fbdev *nfbdev; 732 struct apertures_struct *apertures; 733}; 734 735static inline struct drm_nouveau_private * 736nouveau_private(struct drm_device *dev) 737{ 738 return dev->dev_private; 739} 740 741static inline struct drm_nouveau_private * 742nouveau_bdev(struct ttm_bo_device *bd) 743{ 744 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 745} 746 747static inline int 748nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 749{ 750 struct nouveau_bo *prev; 751 752 if (!pnvbo) 753 return -EINVAL; 754 prev = *pnvbo; 755 756 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 757 if (prev) { 758 struct ttm_buffer_object *bo = &prev->bo; 759 760 ttm_bo_unref(&bo); 761 } 762 763 return 0; 764} 765 766/* nouveau_drv.c */ 767extern int nouveau_agpmode; 768extern int nouveau_duallink; 769extern int nouveau_uscript_lvds; 770extern int nouveau_uscript_tmds; 771extern int nouveau_vram_pushbuf; 772extern int nouveau_vram_notify; 773extern int nouveau_fbpercrtc; 774extern int nouveau_tv_disable; 775extern char *nouveau_tv_norm; 776extern int nouveau_reg_debug; 777extern char *nouveau_vbios; 778extern int nouveau_ignorelid; 779extern int nouveau_nofbaccel; 780extern int nouveau_noaccel; 781extern int nouveau_force_post; 782extern int nouveau_override_conntype; 783extern char *nouveau_perflvl; 784extern int nouveau_perflvl_wr; 785extern int nouveau_msi; 786 787extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 788extern int nouveau_pci_resume(struct pci_dev *pdev); 789 790/* nouveau_state.c */ 791extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 792extern int nouveau_load(struct drm_device *, unsigned long flags); 793extern int nouveau_firstopen(struct drm_device *); 794extern void nouveau_lastclose(struct drm_device *); 795extern int nouveau_unload(struct drm_device *); 796extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 797 struct drm_file *); 798extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 799 struct drm_file *); 800extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 801 uint32_t reg, uint32_t mask, uint32_t val); 802extern bool nouveau_wait_for_idle(struct drm_device *); 803extern int nouveau_card_init(struct drm_device *); 804 805/* nouveau_mem.c */ 806extern int nouveau_mem_vram_init(struct drm_device *); 807extern void nouveau_mem_vram_fini(struct drm_device *); 808extern int nouveau_mem_gart_init(struct drm_device *); 809extern void nouveau_mem_gart_fini(struct drm_device *); 810extern int nouveau_mem_init_agp(struct drm_device *); 811extern int nouveau_mem_reset_agp(struct drm_device *); 812extern void nouveau_mem_close(struct drm_device *); 813extern struct nouveau_tile_reg *nv10_mem_set_tiling( 814 struct drm_device *dev, uint32_t addr, uint32_t size, 815 uint32_t pitch, uint32_t flags); 816extern void nv10_mem_put_tile_region(struct drm_device *dev, 817 struct nouveau_tile_reg *tile, 818 struct nouveau_fence *fence); 819extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 820 uint32_t size, uint32_t flags, 821 uint64_t phys); 822extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 823 uint32_t size); 824 825/* nouveau_notifier.c */ 826extern int nouveau_notifier_init_channel(struct nouveau_channel *); 827extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 828extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 829 int cout, uint32_t *offset); 830extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 831extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 832 struct drm_file *); 833extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 834 struct drm_file *); 835 836/* nouveau_channel.c */ 837extern struct drm_ioctl_desc nouveau_ioctls[]; 838extern int nouveau_max_ioctl; 839extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 840extern int nouveau_channel_alloc(struct drm_device *dev, 841 struct nouveau_channel **chan, 842 struct drm_file *file_priv, 843 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 844extern struct nouveau_channel * 845nouveau_channel_get_unlocked(struct nouveau_channel *); 846extern struct nouveau_channel * 847nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 848extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 849extern void nouveau_channel_put(struct nouveau_channel **); 850extern void nouveau_channel_ref(struct nouveau_channel *chan, 851 struct nouveau_channel **pchan); 852 853/* nouveau_object.c */ 854#define NVOBJ_CLASS(d,c,e) do { \ 855 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 856 if (ret) \ 857 return ret; \ 858} while(0) 859 860#define NVOBJ_MTHD(d,c,m,e) do { \ 861 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 862 if (ret) \ 863 return ret; \ 864} while(0) 865 866extern int nouveau_gpuobj_early_init(struct drm_device *); 867extern int nouveau_gpuobj_init(struct drm_device *); 868extern void nouveau_gpuobj_takedown(struct drm_device *); 869extern int nouveau_gpuobj_suspend(struct drm_device *dev); 870extern void nouveau_gpuobj_resume(struct drm_device *dev); 871extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 872extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 873 int (*exec)(struct nouveau_channel *, 874 u32 class, u32 mthd, u32 data)); 875extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 876extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 877extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 878 uint32_t vram_h, uint32_t tt_h); 879extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 880extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 881 uint32_t size, int align, uint32_t flags, 882 struct nouveau_gpuobj **); 883extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 884 struct nouveau_gpuobj **); 885extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 886 u32 size, u32 flags, 887 struct nouveau_gpuobj **); 888extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 889 uint64_t offset, uint64_t size, int access, 890 int target, struct nouveau_gpuobj **); 891extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 892 uint64_t offset, uint64_t size, 893 int access, struct nouveau_gpuobj **, 894 uint32_t *o_ret); 895extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 896 struct nouveau_gpuobj **); 897extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 898 struct drm_file *); 899extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 900 struct drm_file *); 901 902/* nouveau_irq.c */ 903extern int nouveau_irq_init(struct drm_device *); 904extern void nouveau_irq_fini(struct drm_device *); 905extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 906extern void nouveau_irq_register(struct drm_device *, int status_bit, 907 void (*)(struct drm_device *)); 908extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 909extern void nouveau_irq_preinstall(struct drm_device *); 910extern int nouveau_irq_postinstall(struct drm_device *); 911extern void nouveau_irq_uninstall(struct drm_device *); 912 913/* nouveau_sgdma.c */ 914extern int nouveau_sgdma_init(struct drm_device *); 915extern void nouveau_sgdma_takedown(struct drm_device *); 916extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 917 uint32_t *page); 918extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 919 920/* nouveau_debugfs.c */ 921#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 922extern int nouveau_debugfs_init(struct drm_minor *); 923extern void nouveau_debugfs_takedown(struct drm_minor *); 924extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 925extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 926#else 927static inline int 928nouveau_debugfs_init(struct drm_minor *minor) 929{ 930 return 0; 931} 932 933static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 934{ 935} 936 937static inline int 938nouveau_debugfs_channel_init(struct nouveau_channel *chan) 939{ 940 return 0; 941} 942 943static inline void 944nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 945{ 946} 947#endif 948 949/* nouveau_dma.c */ 950extern void nouveau_dma_pre_init(struct nouveau_channel *); 951extern int nouveau_dma_init(struct nouveau_channel *); 952extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 953 954/* nouveau_acpi.c */ 955#define ROM_BIOS_PAGE 4096 956#if defined(CONFIG_ACPI) 957void nouveau_register_dsm_handler(void); 958void nouveau_unregister_dsm_handler(void); 959int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 960bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 961int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 962#else 963static inline void nouveau_register_dsm_handler(void) {} 964static inline void nouveau_unregister_dsm_handler(void) {} 965static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 966static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 967static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 968#endif 969 970/* nouveau_backlight.c */ 971#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 972extern int nouveau_backlight_init(struct drm_device *); 973extern void nouveau_backlight_exit(struct drm_device *); 974#else 975static inline int nouveau_backlight_init(struct drm_device *dev) 976{ 977 return 0; 978} 979 980static inline void nouveau_backlight_exit(struct drm_device *dev) { } 981#endif 982 983/* nouveau_bios.c */ 984extern int nouveau_bios_init(struct drm_device *); 985extern void nouveau_bios_takedown(struct drm_device *dev); 986extern int nouveau_run_vbios_init(struct drm_device *); 987extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 988 struct dcb_entry *); 989extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 990 enum dcb_gpio_tag); 991extern struct dcb_connector_table_entry * 992nouveau_bios_connector_entry(struct drm_device *, int index); 993extern u32 get_pll_register(struct drm_device *, enum pll_types); 994extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 995 struct pll_lims *); 996extern int nouveau_bios_run_display_table(struct drm_device *, 997 struct dcb_entry *, 998 uint32_t script, int pxclk); 999extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1000 int *length); 1001extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1002extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1003extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1004 bool *dl, bool *if_is_24bit); 1005extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1006 int head, int pxclk); 1007extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1008 enum LVDS_script, int pxclk); 1009 1010/* nouveau_ttm.c */ 1011int nouveau_ttm_global_init(struct drm_nouveau_private *); 1012void nouveau_ttm_global_release(struct drm_nouveau_private *); 1013int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1014 1015/* nouveau_dp.c */ 1016int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1017 uint8_t *data, int data_nr); 1018bool nouveau_dp_detect(struct drm_encoder *); 1019bool nouveau_dp_link_train(struct drm_encoder *); 1020 1021/* nv04_fb.c */ 1022extern int nv04_fb_init(struct drm_device *); 1023extern void nv04_fb_takedown(struct drm_device *); 1024 1025/* nv10_fb.c */ 1026extern int nv10_fb_init(struct drm_device *); 1027extern void nv10_fb_takedown(struct drm_device *); 1028extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1029 uint32_t addr, uint32_t size, 1030 uint32_t pitch, uint32_t flags); 1031extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1032extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1033 1034/* nv30_fb.c */ 1035extern int nv30_fb_init(struct drm_device *); 1036extern void nv30_fb_takedown(struct drm_device *); 1037extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1038 uint32_t addr, uint32_t size, 1039 uint32_t pitch, uint32_t flags); 1040extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1041 1042/* nv40_fb.c */ 1043extern int nv40_fb_init(struct drm_device *); 1044extern void nv40_fb_takedown(struct drm_device *); 1045extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1046 1047/* nv50_fb.c */ 1048extern int nv50_fb_init(struct drm_device *); 1049extern void nv50_fb_takedown(struct drm_device *); 1050extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1051 1052/* nvc0_fb.c */ 1053extern int nvc0_fb_init(struct drm_device *); 1054extern void nvc0_fb_takedown(struct drm_device *); 1055 1056/* nv04_fifo.c */ 1057extern int nv04_fifo_init(struct drm_device *); 1058extern void nv04_fifo_fini(struct drm_device *); 1059extern void nv04_fifo_disable(struct drm_device *); 1060extern void nv04_fifo_enable(struct drm_device *); 1061extern bool nv04_fifo_reassign(struct drm_device *, bool); 1062extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1063extern int nv04_fifo_channel_id(struct drm_device *); 1064extern int nv04_fifo_create_context(struct nouveau_channel *); 1065extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1066extern int nv04_fifo_load_context(struct nouveau_channel *); 1067extern int nv04_fifo_unload_context(struct drm_device *); 1068extern void nv04_fifo_isr(struct drm_device *); 1069 1070/* nv10_fifo.c */ 1071extern int nv10_fifo_init(struct drm_device *); 1072extern int nv10_fifo_channel_id(struct drm_device *); 1073extern int nv10_fifo_create_context(struct nouveau_channel *); 1074extern int nv10_fifo_load_context(struct nouveau_channel *); 1075extern int nv10_fifo_unload_context(struct drm_device *); 1076 1077/* nv40_fifo.c */ 1078extern int nv40_fifo_init(struct drm_device *); 1079extern int nv40_fifo_create_context(struct nouveau_channel *); 1080extern int nv40_fifo_load_context(struct nouveau_channel *); 1081extern int nv40_fifo_unload_context(struct drm_device *); 1082 1083/* nv50_fifo.c */ 1084extern int nv50_fifo_init(struct drm_device *); 1085extern void nv50_fifo_takedown(struct drm_device *); 1086extern int nv50_fifo_channel_id(struct drm_device *); 1087extern int nv50_fifo_create_context(struct nouveau_channel *); 1088extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1089extern int nv50_fifo_load_context(struct nouveau_channel *); 1090extern int nv50_fifo_unload_context(struct drm_device *); 1091extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1092 1093/* nvc0_fifo.c */ 1094extern int nvc0_fifo_init(struct drm_device *); 1095extern void nvc0_fifo_takedown(struct drm_device *); 1096extern void nvc0_fifo_disable(struct drm_device *); 1097extern void nvc0_fifo_enable(struct drm_device *); 1098extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1099extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1100extern int nvc0_fifo_channel_id(struct drm_device *); 1101extern int nvc0_fifo_create_context(struct nouveau_channel *); 1102extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1103extern int nvc0_fifo_load_context(struct nouveau_channel *); 1104extern int nvc0_fifo_unload_context(struct drm_device *); 1105 1106/* nv04_graph.c */ 1107extern int nv04_graph_init(struct drm_device *); 1108extern void nv04_graph_takedown(struct drm_device *); 1109extern void nv04_graph_fifo_access(struct drm_device *, bool); 1110extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1111extern int nv04_graph_create_context(struct nouveau_channel *); 1112extern void nv04_graph_destroy_context(struct nouveau_channel *); 1113extern int nv04_graph_load_context(struct nouveau_channel *); 1114extern int nv04_graph_unload_context(struct drm_device *); 1115extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1116 u32 class, u32 mthd, u32 data); 1117extern struct nouveau_bitfield nv04_graph_nsource[]; 1118 1119/* nv10_graph.c */ 1120extern int nv10_graph_init(struct drm_device *); 1121extern void nv10_graph_takedown(struct drm_device *); 1122extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1123extern int nv10_graph_create_context(struct nouveau_channel *); 1124extern void nv10_graph_destroy_context(struct nouveau_channel *); 1125extern int nv10_graph_load_context(struct nouveau_channel *); 1126extern int nv10_graph_unload_context(struct drm_device *); 1127extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1128extern struct nouveau_bitfield nv10_graph_intr[]; 1129extern struct nouveau_bitfield nv10_graph_nstatus[]; 1130 1131/* nv20_graph.c */ 1132extern int nv20_graph_create_context(struct nouveau_channel *); 1133extern void nv20_graph_destroy_context(struct nouveau_channel *); 1134extern int nv20_graph_load_context(struct nouveau_channel *); 1135extern int nv20_graph_unload_context(struct drm_device *); 1136extern int nv20_graph_init(struct drm_device *); 1137extern void nv20_graph_takedown(struct drm_device *); 1138extern int nv30_graph_init(struct drm_device *); 1139extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1140 1141/* nv40_graph.c */ 1142extern int nv40_graph_init(struct drm_device *); 1143extern void nv40_graph_takedown(struct drm_device *); 1144extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1145extern int nv40_graph_create_context(struct nouveau_channel *); 1146extern void nv40_graph_destroy_context(struct nouveau_channel *); 1147extern int nv40_graph_load_context(struct nouveau_channel *); 1148extern int nv40_graph_unload_context(struct drm_device *); 1149extern void nv40_grctx_init(struct nouveau_grctx *); 1150extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1151 1152/* nv50_graph.c */ 1153extern int nv50_graph_init(struct drm_device *); 1154extern void nv50_graph_takedown(struct drm_device *); 1155extern void nv50_graph_fifo_access(struct drm_device *, bool); 1156extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1157extern int nv50_graph_create_context(struct nouveau_channel *); 1158extern void nv50_graph_destroy_context(struct nouveau_channel *); 1159extern int nv50_graph_load_context(struct nouveau_channel *); 1160extern int nv50_graph_unload_context(struct drm_device *); 1161extern int nv50_grctx_init(struct nouveau_grctx *); 1162extern void nv50_graph_tlb_flush(struct drm_device *dev); 1163extern void nv86_graph_tlb_flush(struct drm_device *dev); 1164 1165/* nvc0_graph.c */ 1166extern int nvc0_graph_init(struct drm_device *); 1167extern void nvc0_graph_takedown(struct drm_device *); 1168extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1169extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1170extern int nvc0_graph_create_context(struct nouveau_channel *); 1171extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1172extern int nvc0_graph_load_context(struct nouveau_channel *); 1173extern int nvc0_graph_unload_context(struct drm_device *); 1174 1175/* nv84_crypt.c */ 1176extern int nv84_crypt_init(struct drm_device *dev); 1177extern void nv84_crypt_fini(struct drm_device *dev); 1178extern int nv84_crypt_create_context(struct nouveau_channel *); 1179extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1180extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1181 1182/* nv04_instmem.c */ 1183extern int nv04_instmem_init(struct drm_device *); 1184extern void nv04_instmem_takedown(struct drm_device *); 1185extern int nv04_instmem_suspend(struct drm_device *); 1186extern void nv04_instmem_resume(struct drm_device *); 1187extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1188extern void nv04_instmem_put(struct nouveau_gpuobj *); 1189extern int nv04_instmem_map(struct nouveau_gpuobj *); 1190extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1191extern void nv04_instmem_flush(struct drm_device *); 1192 1193/* nv50_instmem.c */ 1194extern int nv50_instmem_init(struct drm_device *); 1195extern void nv50_instmem_takedown(struct drm_device *); 1196extern int nv50_instmem_suspend(struct drm_device *); 1197extern void nv50_instmem_resume(struct drm_device *); 1198extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1199extern void nv50_instmem_put(struct nouveau_gpuobj *); 1200extern int nv50_instmem_map(struct nouveau_gpuobj *); 1201extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1202extern void nv50_instmem_flush(struct drm_device *); 1203extern void nv84_instmem_flush(struct drm_device *); 1204extern void nv50_vm_flush(struct drm_device *, int engine); 1205 1206/* nvc0_instmem.c */ 1207extern int nvc0_instmem_init(struct drm_device *); 1208extern void nvc0_instmem_takedown(struct drm_device *); 1209extern int nvc0_instmem_suspend(struct drm_device *); 1210extern void nvc0_instmem_resume(struct drm_device *); 1211extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1212extern void nvc0_instmem_put(struct nouveau_gpuobj *); 1213extern int nvc0_instmem_map(struct nouveau_gpuobj *); 1214extern void nvc0_instmem_unmap(struct nouveau_gpuobj *); 1215extern void nvc0_instmem_flush(struct drm_device *); 1216 1217/* nv04_mc.c */ 1218extern int nv04_mc_init(struct drm_device *); 1219extern void nv04_mc_takedown(struct drm_device *); 1220 1221/* nv40_mc.c */ 1222extern int nv40_mc_init(struct drm_device *); 1223extern void nv40_mc_takedown(struct drm_device *); 1224 1225/* nv50_mc.c */ 1226extern int nv50_mc_init(struct drm_device *); 1227extern void nv50_mc_takedown(struct drm_device *); 1228 1229/* nv04_timer.c */ 1230extern int nv04_timer_init(struct drm_device *); 1231extern uint64_t nv04_timer_read(struct drm_device *); 1232extern void nv04_timer_takedown(struct drm_device *); 1233 1234extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1235 unsigned long arg); 1236 1237/* nv04_dac.c */ 1238extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1239extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1240extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1241extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1242extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1243 1244/* nv04_dfp.c */ 1245extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1246extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1247extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1248 int head, bool dl); 1249extern void nv04_dfp_disable(struct drm_device *dev, int head); 1250extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1251 1252/* nv04_tv.c */ 1253extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1254extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1255 1256/* nv17_tv.c */ 1257extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1258 1259/* nv04_display.c */ 1260extern int nv04_display_early_init(struct drm_device *); 1261extern void nv04_display_late_takedown(struct drm_device *); 1262extern int nv04_display_create(struct drm_device *); 1263extern int nv04_display_init(struct drm_device *); 1264extern void nv04_display_destroy(struct drm_device *); 1265 1266/* nv04_crtc.c */ 1267extern int nv04_crtc_create(struct drm_device *, int index); 1268 1269/* nouveau_bo.c */ 1270extern struct ttm_bo_driver nouveau_bo_driver; 1271extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1272 int size, int align, uint32_t flags, 1273 uint32_t tile_mode, uint32_t tile_flags, 1274 bool no_vm, bool mappable, struct nouveau_bo **); 1275extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1276extern int nouveau_bo_unpin(struct nouveau_bo *); 1277extern int nouveau_bo_map(struct nouveau_bo *); 1278extern void nouveau_bo_unmap(struct nouveau_bo *); 1279extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1280 uint32_t busy); 1281extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1282extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1283extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1284extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1285extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1286 1287/* nouveau_fence.c */ 1288struct nouveau_fence; 1289extern int nouveau_fence_init(struct drm_device *); 1290extern void nouveau_fence_fini(struct drm_device *); 1291extern int nouveau_fence_channel_init(struct nouveau_channel *); 1292extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1293extern void nouveau_fence_update(struct nouveau_channel *); 1294extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1295 bool emit); 1296extern int nouveau_fence_emit(struct nouveau_fence *); 1297extern void nouveau_fence_work(struct nouveau_fence *fence, 1298 void (*work)(void *priv, bool signalled), 1299 void *priv); 1300struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1301 1302extern bool __nouveau_fence_signalled(void *obj, void *arg); 1303extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1304extern int __nouveau_fence_flush(void *obj, void *arg); 1305extern void __nouveau_fence_unref(void **obj); 1306extern void *__nouveau_fence_ref(void *obj); 1307 1308static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1309{ 1310 return __nouveau_fence_signalled(obj, NULL); 1311} 1312static inline int 1313nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1314{ 1315 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1316} 1317extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1318static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1319{ 1320 return __nouveau_fence_flush(obj, NULL); 1321} 1322static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1323{ 1324 __nouveau_fence_unref((void **)obj); 1325} 1326static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1327{ 1328 return __nouveau_fence_ref(obj); 1329} 1330 1331/* nouveau_gem.c */ 1332extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1333 int size, int align, uint32_t flags, 1334 uint32_t tile_mode, uint32_t tile_flags, 1335 bool no_vm, bool mappable, struct nouveau_bo **); 1336extern int nouveau_gem_object_new(struct drm_gem_object *); 1337extern void nouveau_gem_object_del(struct drm_gem_object *); 1338extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1339 struct drm_file *); 1340extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1341 struct drm_file *); 1342extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1343 struct drm_file *); 1344extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1345 struct drm_file *); 1346extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1347 struct drm_file *); 1348 1349/* nouveau_display.c */ 1350int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1351void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1352int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1353 struct drm_pending_vblank_event *event); 1354int nouveau_finish_page_flip(struct nouveau_channel *, 1355 struct nouveau_page_flip_state *); 1356 1357/* nv10_gpio.c */ 1358int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1359int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1360 1361/* nv50_gpio.c */ 1362int nv50_gpio_init(struct drm_device *dev); 1363void nv50_gpio_fini(struct drm_device *dev); 1364int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1365int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1366int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1367 void (*)(void *, int), void *); 1368void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1369 void (*)(void *, int), void *); 1370bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1371 1372/* nv50_calc. */ 1373int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1374 int *N1, int *M1, int *N2, int *M2, int *P); 1375int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1376 int clk, int *N, int *fN, int *M, int *P); 1377 1378#ifndef ioread32_native 1379#ifdef __BIG_ENDIAN 1380#define ioread16_native ioread16be 1381#define iowrite16_native iowrite16be 1382#define ioread32_native ioread32be 1383#define iowrite32_native iowrite32be 1384#else /* def __BIG_ENDIAN */ 1385#define ioread16_native ioread16 1386#define iowrite16_native iowrite16 1387#define ioread32_native ioread32 1388#define iowrite32_native iowrite32 1389#endif /* def __BIG_ENDIAN else */ 1390#endif /* !ioread32_native */ 1391 1392/* channel control reg access */ 1393static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1394{ 1395 return ioread32_native(chan->user + reg); 1396} 1397 1398static inline void nvchan_wr32(struct nouveau_channel *chan, 1399 unsigned reg, u32 val) 1400{ 1401 iowrite32_native(val, chan->user + reg); 1402} 1403 1404/* register access */ 1405static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1406{ 1407 struct drm_nouveau_private *dev_priv = dev->dev_private; 1408 return ioread32_native(dev_priv->mmio + reg); 1409} 1410 1411static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1412{ 1413 struct drm_nouveau_private *dev_priv = dev->dev_private; 1414 iowrite32_native(val, dev_priv->mmio + reg); 1415} 1416 1417static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1418{ 1419 u32 tmp = nv_rd32(dev, reg); 1420 nv_wr32(dev, reg, (tmp & ~mask) | val); 1421 return tmp; 1422} 1423 1424static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1425{ 1426 struct drm_nouveau_private *dev_priv = dev->dev_private; 1427 return ioread8(dev_priv->mmio + reg); 1428} 1429 1430static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1431{ 1432 struct drm_nouveau_private *dev_priv = dev->dev_private; 1433 iowrite8(val, dev_priv->mmio + reg); 1434} 1435 1436#define nv_wait(dev, reg, mask, val) \ 1437 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1438 1439/* PRAMIN access */ 1440static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1441{ 1442 struct drm_nouveau_private *dev_priv = dev->dev_private; 1443 return ioread32_native(dev_priv->ramin + offset); 1444} 1445 1446static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1447{ 1448 struct drm_nouveau_private *dev_priv = dev->dev_private; 1449 iowrite32_native(val, dev_priv->ramin + offset); 1450} 1451 1452/* object access */ 1453extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1454extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1455 1456/* 1457 * Logging 1458 * Argument d is (struct drm_device *). 1459 */ 1460#define NV_PRINTK(level, d, fmt, arg...) \ 1461 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1462 pci_name(d->pdev), ##arg) 1463#ifndef NV_DEBUG_NOTRACE 1464#define NV_DEBUG(d, fmt, arg...) do { \ 1465 if (drm_debug & DRM_UT_DRIVER) { \ 1466 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1467 __LINE__, ##arg); \ 1468 } \ 1469} while (0) 1470#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1471 if (drm_debug & DRM_UT_KMS) { \ 1472 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1473 __LINE__, ##arg); \ 1474 } \ 1475} while (0) 1476#else 1477#define NV_DEBUG(d, fmt, arg...) do { \ 1478 if (drm_debug & DRM_UT_DRIVER) \ 1479 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1480} while (0) 1481#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1482 if (drm_debug & DRM_UT_KMS) \ 1483 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1484} while (0) 1485#endif 1486#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1487#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1488#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1489#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1490#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1491 1492/* nouveau_reg_debug bitmask */ 1493enum { 1494 NOUVEAU_REG_DEBUG_MC = 0x1, 1495 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1496 NOUVEAU_REG_DEBUG_FB = 0x4, 1497 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1498 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1499 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1500 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1501 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1502 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1503 NOUVEAU_REG_DEBUG_EVO = 0x200, 1504}; 1505 1506#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1507 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1508 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1509} while (0) 1510 1511static inline bool 1512nv_two_heads(struct drm_device *dev) 1513{ 1514 struct drm_nouveau_private *dev_priv = dev->dev_private; 1515 const int impl = dev->pci_device & 0x0ff0; 1516 1517 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1518 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1519 return true; 1520 1521 return false; 1522} 1523 1524static inline bool 1525nv_gf4_disp_arch(struct drm_device *dev) 1526{ 1527 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1528} 1529 1530static inline bool 1531nv_two_reg_pll(struct drm_device *dev) 1532{ 1533 struct drm_nouveau_private *dev_priv = dev->dev_private; 1534 const int impl = dev->pci_device & 0x0ff0; 1535 1536 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1537 return true; 1538 return false; 1539} 1540 1541static inline bool 1542nv_match_device(struct drm_device *dev, unsigned device, 1543 unsigned sub_vendor, unsigned sub_device) 1544{ 1545 return dev->pdev->device == device && 1546 dev->pdev->subsystem_vendor == sub_vendor && 1547 dev->pdev->subsystem_device == sub_device; 1548} 1549 1550#define NV_SW 0x0000506e 1551#define NV_SW_DMA_SEMAPHORE 0x00000060 1552#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1553#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1554#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1555#define NV_SW_YIELD 0x00000080 1556#define NV_SW_DMA_VBLSEM 0x0000018c 1557#define NV_SW_VBLSEM_OFFSET 0x00000400 1558#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1559#define NV_SW_VBLSEM_RELEASE 0x00000408 1560#define NV_SW_PAGE_FLIP 0x00000500 1561 1562#endif /* __NOUVEAU_DRV_H__ */ 1563