nouveau_drv.h revision 2228c6fe04ddc303e90c05dd9430539fbcd8fa18
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 433 u32 reg_1; 434 u32 reg_2; 435 u32 reg_3; 436 u32 reg_4; 437 u32 reg_5; 438 u32 reg_6; 439 u32 reg_7; 440 u32 reg_8; 441 /* To be written to 0x1002c0 */ 442 u8 CL; 443 u8 WR; 444}; 445 446struct nouveau_pm_tbl_header{ 447 u8 version; 448 u8 header_len; 449 u8 entry_cnt; 450 u8 entry_len; 451}; 452 453struct nouveau_pm_tbl_entry{ 454 u8 tWR; 455 u8 tUNK_1; 456 u8 tCL; 457 u8 tRP; /* Byte 3 */ 458 u8 empty_4; 459 u8 tRAS; /* Byte 5 */ 460 u8 empty_6; 461 u8 tRFC; /* Byte 7 */ 462 u8 empty_8; 463 u8 tRC; /* Byte 9 */ 464 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 465 u8 empty_15,empty_16,empty_17; 466 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 467}; 468 469/* nouveau_mem.c */ 470void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 471 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 472 struct nouveau_pm_memtiming *timing); 473 474#define NOUVEAU_PM_MAX_LEVEL 8 475struct nouveau_pm_level { 476 struct device_attribute dev_attr; 477 char name[32]; 478 int id; 479 480 u32 core; 481 u32 memory; 482 u32 shader; 483 u32 rop; 484 u32 copy; 485 u32 daemon; 486 u32 vdec; 487 u32 unk05; /* nv50:nva3, roughly.. */ 488 u32 unka0; /* nva3:nvc0 */ 489 u32 hub01; /* nvc0- */ 490 u32 hub06; /* nvc0- */ 491 u32 hub07; /* nvc0- */ 492 493 u32 volt_min; /* microvolts */ 494 u32 volt_max; 495 u8 fanspeed; 496 497 u16 memscript; 498 struct nouveau_pm_memtiming *timing; 499}; 500 501struct nouveau_pm_temp_sensor_constants { 502 u16 offset_constant; 503 s16 offset_mult; 504 s16 offset_div; 505 s16 slope_mult; 506 s16 slope_div; 507}; 508 509struct nouveau_pm_threshold_temp { 510 s16 critical; 511 s16 down_clock; 512 s16 fan_boost; 513}; 514 515struct nouveau_pm_memtimings { 516 bool supported; 517 struct nouveau_pm_memtiming *timing; 518 int nr_timing; 519}; 520 521struct nouveau_pm_engine { 522 struct nouveau_pm_voltage voltage; 523 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 524 int nr_perflvl; 525 struct nouveau_pm_memtimings memtimings; 526 struct nouveau_pm_temp_sensor_constants sensor_constants; 527 struct nouveau_pm_threshold_temp threshold_temp; 528 529 struct nouveau_pm_level boot; 530 struct nouveau_pm_level *cur; 531 532 struct device *hwmon; 533 struct notifier_block acpi_nb; 534 535 int (*clock_get)(struct drm_device *, u32 id); 536 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 537 u32 id, int khz); 538 void (*clock_set)(struct drm_device *, void *); 539 540 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 541 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 542 void (*clocks_set)(struct drm_device *, void *); 543 544 int (*voltage_get)(struct drm_device *); 545 int (*voltage_set)(struct drm_device *, int voltage); 546 int (*fanspeed_get)(struct drm_device *); 547 int (*fanspeed_set)(struct drm_device *, int fanspeed); 548 int (*temp_get)(struct drm_device *); 549}; 550 551struct nouveau_vram_engine { 552 struct nouveau_mm mm; 553 554 int (*init)(struct drm_device *); 555 void (*takedown)(struct drm_device *dev); 556 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 557 u32 type, struct nouveau_mem **); 558 void (*put)(struct drm_device *, struct nouveau_mem **); 559 560 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 561}; 562 563struct nouveau_engine { 564 struct nouveau_instmem_engine instmem; 565 struct nouveau_mc_engine mc; 566 struct nouveau_timer_engine timer; 567 struct nouveau_fb_engine fb; 568 struct nouveau_fifo_engine fifo; 569 struct nouveau_display_engine display; 570 struct nouveau_gpio_engine gpio; 571 struct nouveau_pm_engine pm; 572 struct nouveau_vram_engine vram; 573}; 574 575struct nouveau_pll_vals { 576 union { 577 struct { 578#ifdef __BIG_ENDIAN 579 uint8_t N1, M1, N2, M2; 580#else 581 uint8_t M1, N1, M2, N2; 582#endif 583 }; 584 struct { 585 uint16_t NM1, NM2; 586 } __attribute__((packed)); 587 }; 588 int log2P; 589 590 int refclk; 591}; 592 593enum nv04_fp_display_regs { 594 FP_DISPLAY_END, 595 FP_TOTAL, 596 FP_CRTC, 597 FP_SYNC_START, 598 FP_SYNC_END, 599 FP_VALID_START, 600 FP_VALID_END 601}; 602 603struct nv04_crtc_reg { 604 unsigned char MiscOutReg; 605 uint8_t CRTC[0xa0]; 606 uint8_t CR58[0x10]; 607 uint8_t Sequencer[5]; 608 uint8_t Graphics[9]; 609 uint8_t Attribute[21]; 610 unsigned char DAC[768]; 611 612 /* PCRTC regs */ 613 uint32_t fb_start; 614 uint32_t crtc_cfg; 615 uint32_t cursor_cfg; 616 uint32_t gpio_ext; 617 uint32_t crtc_830; 618 uint32_t crtc_834; 619 uint32_t crtc_850; 620 uint32_t crtc_eng_ctrl; 621 622 /* PRAMDAC regs */ 623 uint32_t nv10_cursync; 624 struct nouveau_pll_vals pllvals; 625 uint32_t ramdac_gen_ctrl; 626 uint32_t ramdac_630; 627 uint32_t ramdac_634; 628 uint32_t tv_setup; 629 uint32_t tv_vtotal; 630 uint32_t tv_vskew; 631 uint32_t tv_vsync_delay; 632 uint32_t tv_htotal; 633 uint32_t tv_hskew; 634 uint32_t tv_hsync_delay; 635 uint32_t tv_hsync_delay2; 636 uint32_t fp_horiz_regs[7]; 637 uint32_t fp_vert_regs[7]; 638 uint32_t dither; 639 uint32_t fp_control; 640 uint32_t dither_regs[6]; 641 uint32_t fp_debug_0; 642 uint32_t fp_debug_1; 643 uint32_t fp_debug_2; 644 uint32_t fp_margin_color; 645 uint32_t ramdac_8c0; 646 uint32_t ramdac_a20; 647 uint32_t ramdac_a24; 648 uint32_t ramdac_a34; 649 uint32_t ctv_regs[38]; 650}; 651 652struct nv04_output_reg { 653 uint32_t output; 654 int head; 655}; 656 657struct nv04_mode_state { 658 struct nv04_crtc_reg crtc_reg[2]; 659 uint32_t pllsel; 660 uint32_t sel_clk; 661}; 662 663enum nouveau_card_type { 664 NV_04 = 0x00, 665 NV_10 = 0x10, 666 NV_20 = 0x20, 667 NV_30 = 0x30, 668 NV_40 = 0x40, 669 NV_50 = 0x50, 670 NV_C0 = 0xc0, 671 NV_D0 = 0xd0 672}; 673 674struct drm_nouveau_private { 675 struct drm_device *dev; 676 bool noaccel; 677 678 /* the card type, takes NV_* as values */ 679 enum nouveau_card_type card_type; 680 /* exact chipset, derived from NV_PMC_BOOT_0 */ 681 int chipset; 682 int flags; 683 684 void __iomem *mmio; 685 686 spinlock_t ramin_lock; 687 void __iomem *ramin; 688 u32 ramin_size; 689 u32 ramin_base; 690 bool ramin_available; 691 struct drm_mm ramin_heap; 692 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 693 struct list_head gpuobj_list; 694 struct list_head classes; 695 696 struct nouveau_bo *vga_ram; 697 698 /* interrupt handling */ 699 void (*irq_handler[32])(struct drm_device *); 700 bool msi_enabled; 701 702 struct list_head vbl_waiting; 703 704 struct { 705 struct drm_global_reference mem_global_ref; 706 struct ttm_bo_global_ref bo_global_ref; 707 struct ttm_bo_device bdev; 708 atomic_t validate_sequence; 709 } ttm; 710 711 struct { 712 spinlock_t lock; 713 struct drm_mm heap; 714 struct nouveau_bo *bo; 715 } fence; 716 717 struct { 718 spinlock_t lock; 719 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 720 } channels; 721 722 struct nouveau_engine engine; 723 struct nouveau_channel *channel; 724 725 /* For PFIFO and PGRAPH. */ 726 spinlock_t context_switch_lock; 727 728 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 729 spinlock_t vm_lock; 730 731 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 732 struct nouveau_ramht *ramht; 733 struct nouveau_gpuobj *ramfc; 734 struct nouveau_gpuobj *ramro; 735 736 uint32_t ramin_rsvd_vram; 737 738 struct { 739 enum { 740 NOUVEAU_GART_NONE = 0, 741 NOUVEAU_GART_AGP, /* AGP */ 742 NOUVEAU_GART_PDMA, /* paged dma object */ 743 NOUVEAU_GART_HW /* on-chip gart/vm */ 744 } type; 745 uint64_t aper_base; 746 uint64_t aper_size; 747 uint64_t aper_free; 748 749 struct ttm_backend_func *func; 750 751 struct { 752 struct page *page; 753 dma_addr_t addr; 754 } dummy; 755 756 struct nouveau_gpuobj *sg_ctxdma; 757 } gart_info; 758 759 /* nv10-nv40 tiling regions */ 760 struct { 761 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 762 spinlock_t lock; 763 } tile; 764 765 /* VRAM/fb configuration */ 766 uint64_t vram_size; 767 uint64_t vram_sys_base; 768 769 uint64_t fb_available_size; 770 uint64_t fb_mappable_pages; 771 uint64_t fb_aper_free; 772 int fb_mtrr; 773 774 /* BAR control (NV50-) */ 775 struct nouveau_vm *bar1_vm; 776 struct nouveau_vm *bar3_vm; 777 778 /* G8x/G9x virtual address space */ 779 struct nouveau_vm *chan_vm; 780 781 struct nvbios vbios; 782 783 struct nv04_mode_state mode_reg; 784 struct nv04_mode_state saved_reg; 785 uint32_t saved_vga_font[4][16384]; 786 uint32_t crtc_owner; 787 uint32_t dac_users[4]; 788 789 struct backlight_device *backlight; 790 791 struct { 792 struct dentry *channel_root; 793 } debugfs; 794 795 struct nouveau_fbdev *nfbdev; 796 struct apertures_struct *apertures; 797}; 798 799static inline struct drm_nouveau_private * 800nouveau_private(struct drm_device *dev) 801{ 802 return dev->dev_private; 803} 804 805static inline struct drm_nouveau_private * 806nouveau_bdev(struct ttm_bo_device *bd) 807{ 808 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 809} 810 811static inline int 812nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 813{ 814 struct nouveau_bo *prev; 815 816 if (!pnvbo) 817 return -EINVAL; 818 prev = *pnvbo; 819 820 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 821 if (prev) { 822 struct ttm_buffer_object *bo = &prev->bo; 823 824 ttm_bo_unref(&bo); 825 } 826 827 return 0; 828} 829 830/* nouveau_drv.c */ 831extern int nouveau_modeset; 832extern int nouveau_agpmode; 833extern int nouveau_duallink; 834extern int nouveau_uscript_lvds; 835extern int nouveau_uscript_tmds; 836extern int nouveau_vram_pushbuf; 837extern int nouveau_vram_notify; 838extern int nouveau_fbpercrtc; 839extern int nouveau_tv_disable; 840extern char *nouveau_tv_norm; 841extern int nouveau_reg_debug; 842extern char *nouveau_vbios; 843extern int nouveau_ignorelid; 844extern int nouveau_nofbaccel; 845extern int nouveau_noaccel; 846extern int nouveau_force_post; 847extern int nouveau_override_conntype; 848extern char *nouveau_perflvl; 849extern int nouveau_perflvl_wr; 850extern int nouveau_msi; 851extern int nouveau_ctxfw; 852 853extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 854extern int nouveau_pci_resume(struct pci_dev *pdev); 855 856/* nouveau_state.c */ 857extern int nouveau_open(struct drm_device *, struct drm_file *); 858extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 859extern void nouveau_postclose(struct drm_device *, struct drm_file *); 860extern int nouveau_load(struct drm_device *, unsigned long flags); 861extern int nouveau_firstopen(struct drm_device *); 862extern void nouveau_lastclose(struct drm_device *); 863extern int nouveau_unload(struct drm_device *); 864extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 865 struct drm_file *); 866extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 867 struct drm_file *); 868extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 869 uint32_t reg, uint32_t mask, uint32_t val); 870extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 871 uint32_t reg, uint32_t mask, uint32_t val); 872extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 873 bool (*cond)(void *), void *); 874extern bool nouveau_wait_for_idle(struct drm_device *); 875extern int nouveau_card_init(struct drm_device *); 876 877/* nouveau_mem.c */ 878extern int nouveau_mem_vram_init(struct drm_device *); 879extern void nouveau_mem_vram_fini(struct drm_device *); 880extern int nouveau_mem_gart_init(struct drm_device *); 881extern void nouveau_mem_gart_fini(struct drm_device *); 882extern int nouveau_mem_init_agp(struct drm_device *); 883extern int nouveau_mem_reset_agp(struct drm_device *); 884extern void nouveau_mem_close(struct drm_device *); 885extern int nouveau_mem_detect(struct drm_device *); 886extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 887extern struct nouveau_tile_reg *nv10_mem_set_tiling( 888 struct drm_device *dev, uint32_t addr, uint32_t size, 889 uint32_t pitch, uint32_t flags); 890extern void nv10_mem_put_tile_region(struct drm_device *dev, 891 struct nouveau_tile_reg *tile, 892 struct nouveau_fence *fence); 893extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 894extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 895 896/* nouveau_notifier.c */ 897extern int nouveau_notifier_init_channel(struct nouveau_channel *); 898extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 899extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 900 int cout, uint32_t start, uint32_t end, 901 uint32_t *offset); 902extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 903extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 904 struct drm_file *); 905extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 906 struct drm_file *); 907 908/* nouveau_channel.c */ 909extern struct drm_ioctl_desc nouveau_ioctls[]; 910extern int nouveau_max_ioctl; 911extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 912extern int nouveau_channel_alloc(struct drm_device *dev, 913 struct nouveau_channel **chan, 914 struct drm_file *file_priv, 915 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 916extern struct nouveau_channel * 917nouveau_channel_get_unlocked(struct nouveau_channel *); 918extern struct nouveau_channel * 919nouveau_channel_get(struct drm_file *, int id); 920extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 921extern void nouveau_channel_put(struct nouveau_channel **); 922extern void nouveau_channel_ref(struct nouveau_channel *chan, 923 struct nouveau_channel **pchan); 924extern void nouveau_channel_idle(struct nouveau_channel *chan); 925 926/* nouveau_object.c */ 927#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 928 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 929 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 930} while (0) 931 932#define NVOBJ_ENGINE_DEL(d, e) do { \ 933 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 934 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 935} while (0) 936 937#define NVOBJ_CLASS(d, c, e) do { \ 938 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 939 if (ret) \ 940 return ret; \ 941} while (0) 942 943#define NVOBJ_MTHD(d, c, m, e) do { \ 944 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 945 if (ret) \ 946 return ret; \ 947} while (0) 948 949extern int nouveau_gpuobj_early_init(struct drm_device *); 950extern int nouveau_gpuobj_init(struct drm_device *); 951extern void nouveau_gpuobj_takedown(struct drm_device *); 952extern int nouveau_gpuobj_suspend(struct drm_device *dev); 953extern void nouveau_gpuobj_resume(struct drm_device *dev); 954extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 955extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 956 int (*exec)(struct nouveau_channel *, 957 u32 class, u32 mthd, u32 data)); 958extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 959extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 960extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 961 uint32_t vram_h, uint32_t tt_h); 962extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 963extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 964 uint32_t size, int align, uint32_t flags, 965 struct nouveau_gpuobj **); 966extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 967 struct nouveau_gpuobj **); 968extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 969 u32 size, u32 flags, 970 struct nouveau_gpuobj **); 971extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 972 uint64_t offset, uint64_t size, int access, 973 int target, struct nouveau_gpuobj **); 974extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 975extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 976 u64 size, int target, int access, u32 type, 977 u32 comp, struct nouveau_gpuobj **pobj); 978extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 979 int class, u64 base, u64 size, int target, 980 int access, u32 type, u32 comp); 981extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 982 struct drm_file *); 983extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 984 struct drm_file *); 985 986/* nouveau_irq.c */ 987extern int nouveau_irq_init(struct drm_device *); 988extern void nouveau_irq_fini(struct drm_device *); 989extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 990extern void nouveau_irq_register(struct drm_device *, int status_bit, 991 void (*)(struct drm_device *)); 992extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 993extern void nouveau_irq_preinstall(struct drm_device *); 994extern int nouveau_irq_postinstall(struct drm_device *); 995extern void nouveau_irq_uninstall(struct drm_device *); 996 997/* nouveau_sgdma.c */ 998extern int nouveau_sgdma_init(struct drm_device *); 999extern void nouveau_sgdma_takedown(struct drm_device *); 1000extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1001 uint32_t offset); 1002extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 1003 1004/* nouveau_debugfs.c */ 1005#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1006extern int nouveau_debugfs_init(struct drm_minor *); 1007extern void nouveau_debugfs_takedown(struct drm_minor *); 1008extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1009extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1010#else 1011static inline int 1012nouveau_debugfs_init(struct drm_minor *minor) 1013{ 1014 return 0; 1015} 1016 1017static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1018{ 1019} 1020 1021static inline int 1022nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1023{ 1024 return 0; 1025} 1026 1027static inline void 1028nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1029{ 1030} 1031#endif 1032 1033/* nouveau_dma.c */ 1034extern void nouveau_dma_pre_init(struct nouveau_channel *); 1035extern int nouveau_dma_init(struct nouveau_channel *); 1036extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1037 1038/* nouveau_acpi.c */ 1039#define ROM_BIOS_PAGE 4096 1040#if defined(CONFIG_ACPI) 1041void nouveau_register_dsm_handler(void); 1042void nouveau_unregister_dsm_handler(void); 1043int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1044bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1045int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1046#else 1047static inline void nouveau_register_dsm_handler(void) {} 1048static inline void nouveau_unregister_dsm_handler(void) {} 1049static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1050static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1051static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1052#endif 1053 1054/* nouveau_backlight.c */ 1055#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1056extern int nouveau_backlight_init(struct drm_connector *); 1057extern void nouveau_backlight_exit(struct drm_connector *); 1058#else 1059static inline int nouveau_backlight_init(struct drm_connector *dev) 1060{ 1061 return 0; 1062} 1063 1064static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1065#endif 1066 1067/* nouveau_bios.c */ 1068extern int nouveau_bios_init(struct drm_device *); 1069extern void nouveau_bios_takedown(struct drm_device *dev); 1070extern int nouveau_run_vbios_init(struct drm_device *); 1071extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1072 struct dcb_entry *, int crtc); 1073extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1074 enum dcb_gpio_tag); 1075extern struct dcb_connector_table_entry * 1076nouveau_bios_connector_entry(struct drm_device *, int index); 1077extern u32 get_pll_register(struct drm_device *, enum pll_types); 1078extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1079 struct pll_lims *); 1080extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1081 struct dcb_entry *, int crtc); 1082extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1083 int *length); 1084extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1085extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1086extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1087 bool *dl, bool *if_is_24bit); 1088extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1089 int head, int pxclk); 1090extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1091 enum LVDS_script, int pxclk); 1092 1093/* nouveau_ttm.c */ 1094int nouveau_ttm_global_init(struct drm_nouveau_private *); 1095void nouveau_ttm_global_release(struct drm_nouveau_private *); 1096int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1097 1098/* nouveau_dp.c */ 1099int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1100 uint8_t *data, int data_nr); 1101bool nouveau_dp_detect(struct drm_encoder *); 1102bool nouveau_dp_link_train(struct drm_encoder *); 1103 1104/* nv04_fb.c */ 1105extern int nv04_fb_init(struct drm_device *); 1106extern void nv04_fb_takedown(struct drm_device *); 1107 1108/* nv10_fb.c */ 1109extern int nv10_fb_init(struct drm_device *); 1110extern void nv10_fb_takedown(struct drm_device *); 1111extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1112 uint32_t addr, uint32_t size, 1113 uint32_t pitch, uint32_t flags); 1114extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1115extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1116 1117/* nv30_fb.c */ 1118extern int nv30_fb_init(struct drm_device *); 1119extern void nv30_fb_takedown(struct drm_device *); 1120extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1121 uint32_t addr, uint32_t size, 1122 uint32_t pitch, uint32_t flags); 1123extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1124 1125/* nv40_fb.c */ 1126extern int nv40_fb_init(struct drm_device *); 1127extern void nv40_fb_takedown(struct drm_device *); 1128extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1129 1130/* nv50_fb.c */ 1131extern int nv50_fb_init(struct drm_device *); 1132extern void nv50_fb_takedown(struct drm_device *); 1133extern void nv50_fb_vm_trap(struct drm_device *, int display); 1134 1135/* nvc0_fb.c */ 1136extern int nvc0_fb_init(struct drm_device *); 1137extern void nvc0_fb_takedown(struct drm_device *); 1138 1139/* nv04_fifo.c */ 1140extern int nv04_fifo_init(struct drm_device *); 1141extern void nv04_fifo_fini(struct drm_device *); 1142extern void nv04_fifo_disable(struct drm_device *); 1143extern void nv04_fifo_enable(struct drm_device *); 1144extern bool nv04_fifo_reassign(struct drm_device *, bool); 1145extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1146extern int nv04_fifo_channel_id(struct drm_device *); 1147extern int nv04_fifo_create_context(struct nouveau_channel *); 1148extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1149extern int nv04_fifo_load_context(struct nouveau_channel *); 1150extern int nv04_fifo_unload_context(struct drm_device *); 1151extern void nv04_fifo_isr(struct drm_device *); 1152 1153/* nv10_fifo.c */ 1154extern int nv10_fifo_init(struct drm_device *); 1155extern int nv10_fifo_channel_id(struct drm_device *); 1156extern int nv10_fifo_create_context(struct nouveau_channel *); 1157extern int nv10_fifo_load_context(struct nouveau_channel *); 1158extern int nv10_fifo_unload_context(struct drm_device *); 1159 1160/* nv40_fifo.c */ 1161extern int nv40_fifo_init(struct drm_device *); 1162extern int nv40_fifo_create_context(struct nouveau_channel *); 1163extern int nv40_fifo_load_context(struct nouveau_channel *); 1164extern int nv40_fifo_unload_context(struct drm_device *); 1165 1166/* nv50_fifo.c */ 1167extern int nv50_fifo_init(struct drm_device *); 1168extern void nv50_fifo_takedown(struct drm_device *); 1169extern int nv50_fifo_channel_id(struct drm_device *); 1170extern int nv50_fifo_create_context(struct nouveau_channel *); 1171extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1172extern int nv50_fifo_load_context(struct nouveau_channel *); 1173extern int nv50_fifo_unload_context(struct drm_device *); 1174extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1175 1176/* nvc0_fifo.c */ 1177extern int nvc0_fifo_init(struct drm_device *); 1178extern void nvc0_fifo_takedown(struct drm_device *); 1179extern void nvc0_fifo_disable(struct drm_device *); 1180extern void nvc0_fifo_enable(struct drm_device *); 1181extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1182extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1183extern int nvc0_fifo_channel_id(struct drm_device *); 1184extern int nvc0_fifo_create_context(struct nouveau_channel *); 1185extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1186extern int nvc0_fifo_load_context(struct nouveau_channel *); 1187extern int nvc0_fifo_unload_context(struct drm_device *); 1188 1189/* nv04_graph.c */ 1190extern int nv04_graph_create(struct drm_device *); 1191extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1192extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1193 u32 class, u32 mthd, u32 data); 1194extern struct nouveau_bitfield nv04_graph_nsource[]; 1195 1196/* nv10_graph.c */ 1197extern int nv10_graph_create(struct drm_device *); 1198extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1199extern struct nouveau_bitfield nv10_graph_intr[]; 1200extern struct nouveau_bitfield nv10_graph_nstatus[]; 1201 1202/* nv20_graph.c */ 1203extern int nv20_graph_create(struct drm_device *); 1204 1205/* nv40_graph.c */ 1206extern int nv40_graph_create(struct drm_device *); 1207extern void nv40_grctx_init(struct nouveau_grctx *); 1208 1209/* nv50_graph.c */ 1210extern int nv50_graph_create(struct drm_device *); 1211extern int nv50_grctx_init(struct nouveau_grctx *); 1212extern struct nouveau_enum nv50_data_error_names[]; 1213extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1214 1215/* nvc0_graph.c */ 1216extern int nvc0_graph_create(struct drm_device *); 1217extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1218 1219/* nv84_crypt.c */ 1220extern int nv84_crypt_create(struct drm_device *); 1221 1222/* nva3_copy.c */ 1223extern int nva3_copy_create(struct drm_device *dev); 1224 1225/* nvc0_copy.c */ 1226extern int nvc0_copy_create(struct drm_device *dev, int engine); 1227 1228/* nv31_mpeg.c */ 1229extern int nv31_mpeg_create(struct drm_device *dev); 1230 1231/* nv50_mpeg.c */ 1232extern int nv50_mpeg_create(struct drm_device *dev); 1233 1234/* nv04_instmem.c */ 1235extern int nv04_instmem_init(struct drm_device *); 1236extern void nv04_instmem_takedown(struct drm_device *); 1237extern int nv04_instmem_suspend(struct drm_device *); 1238extern void nv04_instmem_resume(struct drm_device *); 1239extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1240 u32 size, u32 align); 1241extern void nv04_instmem_put(struct nouveau_gpuobj *); 1242extern int nv04_instmem_map(struct nouveau_gpuobj *); 1243extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1244extern void nv04_instmem_flush(struct drm_device *); 1245 1246/* nv50_instmem.c */ 1247extern int nv50_instmem_init(struct drm_device *); 1248extern void nv50_instmem_takedown(struct drm_device *); 1249extern int nv50_instmem_suspend(struct drm_device *); 1250extern void nv50_instmem_resume(struct drm_device *); 1251extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1252 u32 size, u32 align); 1253extern void nv50_instmem_put(struct nouveau_gpuobj *); 1254extern int nv50_instmem_map(struct nouveau_gpuobj *); 1255extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1256extern void nv50_instmem_flush(struct drm_device *); 1257extern void nv84_instmem_flush(struct drm_device *); 1258 1259/* nvc0_instmem.c */ 1260extern int nvc0_instmem_init(struct drm_device *); 1261extern void nvc0_instmem_takedown(struct drm_device *); 1262extern int nvc0_instmem_suspend(struct drm_device *); 1263extern void nvc0_instmem_resume(struct drm_device *); 1264 1265/* nv04_mc.c */ 1266extern int nv04_mc_init(struct drm_device *); 1267extern void nv04_mc_takedown(struct drm_device *); 1268 1269/* nv40_mc.c */ 1270extern int nv40_mc_init(struct drm_device *); 1271extern void nv40_mc_takedown(struct drm_device *); 1272 1273/* nv50_mc.c */ 1274extern int nv50_mc_init(struct drm_device *); 1275extern void nv50_mc_takedown(struct drm_device *); 1276 1277/* nv04_timer.c */ 1278extern int nv04_timer_init(struct drm_device *); 1279extern uint64_t nv04_timer_read(struct drm_device *); 1280extern void nv04_timer_takedown(struct drm_device *); 1281 1282extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1283 unsigned long arg); 1284 1285/* nv04_dac.c */ 1286extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1287extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1288extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1289extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1290extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1291 1292/* nv04_dfp.c */ 1293extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1294extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1295extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1296 int head, bool dl); 1297extern void nv04_dfp_disable(struct drm_device *dev, int head); 1298extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1299 1300/* nv04_tv.c */ 1301extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1302extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1303 1304/* nv17_tv.c */ 1305extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1306 1307/* nv04_display.c */ 1308extern int nv04_display_early_init(struct drm_device *); 1309extern void nv04_display_late_takedown(struct drm_device *); 1310extern int nv04_display_create(struct drm_device *); 1311extern int nv04_display_init(struct drm_device *); 1312extern void nv04_display_destroy(struct drm_device *); 1313 1314/* nvd0_display.c */ 1315extern int nvd0_display_create(struct drm_device *); 1316extern int nvd0_display_init(struct drm_device *); 1317extern void nvd0_display_destroy(struct drm_device *); 1318 1319/* nv04_crtc.c */ 1320extern int nv04_crtc_create(struct drm_device *, int index); 1321 1322/* nouveau_bo.c */ 1323extern struct ttm_bo_driver nouveau_bo_driver; 1324extern int nouveau_bo_new(struct drm_device *, int size, int align, 1325 uint32_t flags, uint32_t tile_mode, 1326 uint32_t tile_flags, struct nouveau_bo **); 1327extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1328extern int nouveau_bo_unpin(struct nouveau_bo *); 1329extern int nouveau_bo_map(struct nouveau_bo *); 1330extern void nouveau_bo_unmap(struct nouveau_bo *); 1331extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1332 uint32_t busy); 1333extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1334extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1335extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1336extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1337extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1338extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1339 bool no_wait_reserve, bool no_wait_gpu); 1340 1341extern struct nouveau_vma * 1342nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1343extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1344 struct nouveau_vma *); 1345extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1346 1347/* nouveau_fence.c */ 1348struct nouveau_fence; 1349extern int nouveau_fence_init(struct drm_device *); 1350extern void nouveau_fence_fini(struct drm_device *); 1351extern int nouveau_fence_channel_init(struct nouveau_channel *); 1352extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1353extern void nouveau_fence_update(struct nouveau_channel *); 1354extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1355 bool emit); 1356extern int nouveau_fence_emit(struct nouveau_fence *); 1357extern void nouveau_fence_work(struct nouveau_fence *fence, 1358 void (*work)(void *priv, bool signalled), 1359 void *priv); 1360struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1361 1362extern bool __nouveau_fence_signalled(void *obj, void *arg); 1363extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1364extern int __nouveau_fence_flush(void *obj, void *arg); 1365extern void __nouveau_fence_unref(void **obj); 1366extern void *__nouveau_fence_ref(void *obj); 1367 1368static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1369{ 1370 return __nouveau_fence_signalled(obj, NULL); 1371} 1372static inline int 1373nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1374{ 1375 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1376} 1377extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1378static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1379{ 1380 return __nouveau_fence_flush(obj, NULL); 1381} 1382static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1383{ 1384 __nouveau_fence_unref((void **)obj); 1385} 1386static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1387{ 1388 return __nouveau_fence_ref(obj); 1389} 1390 1391/* nouveau_gem.c */ 1392extern int nouveau_gem_new(struct drm_device *, int size, int align, 1393 uint32_t domain, uint32_t tile_mode, 1394 uint32_t tile_flags, struct nouveau_bo **); 1395extern int nouveau_gem_object_new(struct drm_gem_object *); 1396extern void nouveau_gem_object_del(struct drm_gem_object *); 1397extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1398extern void nouveau_gem_object_close(struct drm_gem_object *, 1399 struct drm_file *); 1400extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1401 struct drm_file *); 1402extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1403 struct drm_file *); 1404extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1405 struct drm_file *); 1406extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1407 struct drm_file *); 1408extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1409 struct drm_file *); 1410 1411/* nouveau_display.c */ 1412int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1413void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1414int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1415 struct drm_pending_vblank_event *event); 1416int nouveau_finish_page_flip(struct nouveau_channel *, 1417 struct nouveau_page_flip_state *); 1418 1419/* nv10_gpio.c */ 1420int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1421int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1422 1423/* nv50_gpio.c */ 1424int nv50_gpio_init(struct drm_device *dev); 1425void nv50_gpio_fini(struct drm_device *dev); 1426int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1427int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1428int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1429int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1430int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1431 void (*)(void *, int), void *); 1432void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1433 void (*)(void *, int), void *); 1434bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1435 1436/* nv50_calc. */ 1437int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1438 int *N1, int *M1, int *N2, int *M2, int *P); 1439int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1440 int clk, int *N, int *fN, int *M, int *P); 1441 1442#ifndef ioread32_native 1443#ifdef __BIG_ENDIAN 1444#define ioread16_native ioread16be 1445#define iowrite16_native iowrite16be 1446#define ioread32_native ioread32be 1447#define iowrite32_native iowrite32be 1448#else /* def __BIG_ENDIAN */ 1449#define ioread16_native ioread16 1450#define iowrite16_native iowrite16 1451#define ioread32_native ioread32 1452#define iowrite32_native iowrite32 1453#endif /* def __BIG_ENDIAN else */ 1454#endif /* !ioread32_native */ 1455 1456/* channel control reg access */ 1457static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1458{ 1459 return ioread32_native(chan->user + reg); 1460} 1461 1462static inline void nvchan_wr32(struct nouveau_channel *chan, 1463 unsigned reg, u32 val) 1464{ 1465 iowrite32_native(val, chan->user + reg); 1466} 1467 1468/* register access */ 1469static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1470{ 1471 struct drm_nouveau_private *dev_priv = dev->dev_private; 1472 return ioread32_native(dev_priv->mmio + reg); 1473} 1474 1475static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1476{ 1477 struct drm_nouveau_private *dev_priv = dev->dev_private; 1478 iowrite32_native(val, dev_priv->mmio + reg); 1479} 1480 1481static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1482{ 1483 u32 tmp = nv_rd32(dev, reg); 1484 nv_wr32(dev, reg, (tmp & ~mask) | val); 1485 return tmp; 1486} 1487 1488static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1489{ 1490 struct drm_nouveau_private *dev_priv = dev->dev_private; 1491 return ioread8(dev_priv->mmio + reg); 1492} 1493 1494static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1495{ 1496 struct drm_nouveau_private *dev_priv = dev->dev_private; 1497 iowrite8(val, dev_priv->mmio + reg); 1498} 1499 1500#define nv_wait(dev, reg, mask, val) \ 1501 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1502#define nv_wait_ne(dev, reg, mask, val) \ 1503 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1504#define nv_wait_cb(dev, func, data) \ 1505 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1506 1507/* PRAMIN access */ 1508static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1509{ 1510 struct drm_nouveau_private *dev_priv = dev->dev_private; 1511 return ioread32_native(dev_priv->ramin + offset); 1512} 1513 1514static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1515{ 1516 struct drm_nouveau_private *dev_priv = dev->dev_private; 1517 iowrite32_native(val, dev_priv->ramin + offset); 1518} 1519 1520/* object access */ 1521extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1522extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1523 1524/* 1525 * Logging 1526 * Argument d is (struct drm_device *). 1527 */ 1528#define NV_PRINTK(level, d, fmt, arg...) \ 1529 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1530 pci_name(d->pdev), ##arg) 1531#ifndef NV_DEBUG_NOTRACE 1532#define NV_DEBUG(d, fmt, arg...) do { \ 1533 if (drm_debug & DRM_UT_DRIVER) { \ 1534 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1535 __LINE__, ##arg); \ 1536 } \ 1537} while (0) 1538#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1539 if (drm_debug & DRM_UT_KMS) { \ 1540 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1541 __LINE__, ##arg); \ 1542 } \ 1543} while (0) 1544#else 1545#define NV_DEBUG(d, fmt, arg...) do { \ 1546 if (drm_debug & DRM_UT_DRIVER) \ 1547 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1548} while (0) 1549#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1550 if (drm_debug & DRM_UT_KMS) \ 1551 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1552} while (0) 1553#endif 1554#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1555#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1556#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1557#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1558#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1559 1560/* nouveau_reg_debug bitmask */ 1561enum { 1562 NOUVEAU_REG_DEBUG_MC = 0x1, 1563 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1564 NOUVEAU_REG_DEBUG_FB = 0x4, 1565 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1566 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1567 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1568 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1569 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1570 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1571 NOUVEAU_REG_DEBUG_EVO = 0x200, 1572}; 1573 1574#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1575 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1576 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1577} while (0) 1578 1579static inline bool 1580nv_two_heads(struct drm_device *dev) 1581{ 1582 struct drm_nouveau_private *dev_priv = dev->dev_private; 1583 const int impl = dev->pci_device & 0x0ff0; 1584 1585 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1586 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1587 return true; 1588 1589 return false; 1590} 1591 1592static inline bool 1593nv_gf4_disp_arch(struct drm_device *dev) 1594{ 1595 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1596} 1597 1598static inline bool 1599nv_two_reg_pll(struct drm_device *dev) 1600{ 1601 struct drm_nouveau_private *dev_priv = dev->dev_private; 1602 const int impl = dev->pci_device & 0x0ff0; 1603 1604 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1605 return true; 1606 return false; 1607} 1608 1609static inline bool 1610nv_match_device(struct drm_device *dev, unsigned device, 1611 unsigned sub_vendor, unsigned sub_device) 1612{ 1613 return dev->pdev->device == device && 1614 dev->pdev->subsystem_vendor == sub_vendor && 1615 dev->pdev->subsystem_device == sub_device; 1616} 1617 1618static inline void * 1619nv_engine(struct drm_device *dev, int engine) 1620{ 1621 struct drm_nouveau_private *dev_priv = dev->dev_private; 1622 return (void *)dev_priv->eng[engine]; 1623} 1624 1625/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1626 * helpful to determine a number of other hardware features 1627 */ 1628static inline int 1629nv44_graph_class(struct drm_device *dev) 1630{ 1631 struct drm_nouveau_private *dev_priv = dev->dev_private; 1632 1633 if ((dev_priv->chipset & 0xf0) == 0x60) 1634 return 1; 1635 1636 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1637} 1638 1639/* memory type/access flags, do not match hardware values */ 1640#define NV_MEM_ACCESS_RO 1 1641#define NV_MEM_ACCESS_WO 2 1642#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1643#define NV_MEM_ACCESS_SYS 4 1644#define NV_MEM_ACCESS_VM 8 1645 1646#define NV_MEM_TARGET_VRAM 0 1647#define NV_MEM_TARGET_PCI 1 1648#define NV_MEM_TARGET_PCI_NOSNOOP 2 1649#define NV_MEM_TARGET_VM 3 1650#define NV_MEM_TARGET_GART 4 1651 1652#define NV_MEM_TYPE_VM 0x7f 1653#define NV_MEM_COMP_VM 0x03 1654 1655/* NV_SW object class */ 1656#define NV_SW 0x0000506e 1657#define NV_SW_DMA_SEMAPHORE 0x00000060 1658#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1659#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1660#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1661#define NV_SW_YIELD 0x00000080 1662#define NV_SW_DMA_VBLSEM 0x0000018c 1663#define NV_SW_VBLSEM_OFFSET 0x00000400 1664#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1665#define NV_SW_VBLSEM_RELEASE 0x00000408 1666#define NV_SW_PAGE_FLIP 0x00000500 1667 1668#endif /* __NOUVEAU_DRV_H__ */ 1669