nouveau_drv.h revision 25c53c1068a804c6b51f86e937cebab6274dc056
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435/* Exclusive upper limits */ 436#define NV_MEM_CL_DDR2_MAX 8 437#define NV_MEM_WR_DDR2_MAX 9 438#define NV_MEM_CL_DDR3_MAX 17 439#define NV_MEM_WR_DDR3_MAX 17 440#define NV_MEM_CL_GDDR3_MAX 16 441#define NV_MEM_WR_GDDR3_MAX 18 442#define NV_MEM_CL_GDDR5_MAX 21 443#define NV_MEM_WR_GDDR5_MAX 20 444 445struct nouveau_pm_memtiming { 446 int id; 447 448 u32 reg[9]; 449 u32 mr[4]; 450 451 u8 tCWL; 452 453 u8 odt; 454 u8 drive_strength; 455}; 456 457struct nouveau_pm_tbl_header { 458 u8 version; 459 u8 header_len; 460 u8 entry_cnt; 461 u8 entry_len; 462}; 463 464struct nouveau_pm_tbl_entry { 465 u8 tWR; 466 u8 tWTR; 467 u8 tCL; 468 u8 tRC; 469 u8 empty_4; 470 u8 tRFC; /* Byte 5 */ 471 u8 empty_6; 472 u8 tRAS; /* Byte 7 */ 473 u8 empty_8; 474 u8 tRP; /* Byte 9 */ 475 u8 tRCDRD; 476 u8 tRCDWR; 477 u8 tRRD; 478 u8 tUNK_13; 479 u8 RAM_FT1; /* 14, a bitmask of random RAM features */ 480 u8 empty_15; 481 u8 tUNK_16; 482 u8 empty_17; 483 u8 tUNK_18; 484 u8 tCWL; 485 u8 tUNK_20, tUNK_21; 486}; 487 488struct nouveau_pm_profile; 489struct nouveau_pm_profile_func { 490 void (*destroy)(struct nouveau_pm_profile *); 491 void (*init)(struct nouveau_pm_profile *); 492 void (*fini)(struct nouveau_pm_profile *); 493 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); 494}; 495 496struct nouveau_pm_profile { 497 const struct nouveau_pm_profile_func *func; 498 struct list_head head; 499 char name[8]; 500}; 501 502#define NOUVEAU_PM_MAX_LEVEL 8 503struct nouveau_pm_level { 504 struct nouveau_pm_profile profile; 505 struct device_attribute dev_attr; 506 char name[32]; 507 int id; 508 509 struct nouveau_pm_memtiming timing; 510 u32 memory; 511 u16 memscript; 512 513 u32 core; 514 u32 shader; 515 u32 rop; 516 u32 copy; 517 u32 daemon; 518 u32 vdec; 519 u32 dom6; 520 u32 unka0; /* nva3:nvc0 */ 521 u32 hub01; /* nvc0- */ 522 u32 hub06; /* nvc0- */ 523 u32 hub07; /* nvc0- */ 524 525 u32 volt_min; /* microvolts */ 526 u32 volt_max; 527 u8 fanspeed; 528}; 529 530struct nouveau_pm_temp_sensor_constants { 531 u16 offset_constant; 532 s16 offset_mult; 533 s16 offset_div; 534 s16 slope_mult; 535 s16 slope_div; 536}; 537 538struct nouveau_pm_threshold_temp { 539 s16 critical; 540 s16 down_clock; 541 s16 fan_boost; 542}; 543 544struct nouveau_pm_fan { 545 u32 percent; 546 u32 min_duty; 547 u32 max_duty; 548 u32 pwm_freq; 549 u32 pwm_divisor; 550}; 551 552struct nouveau_pm_engine { 553 struct nouveau_pm_voltage voltage; 554 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 555 int nr_perflvl; 556 struct nouveau_pm_temp_sensor_constants sensor_constants; 557 struct nouveau_pm_threshold_temp threshold_temp; 558 struct nouveau_pm_fan fan; 559 560 struct nouveau_pm_profile *profile_ac; 561 struct nouveau_pm_profile *profile_dc; 562 struct nouveau_pm_profile *profile; 563 struct list_head profiles; 564 565 struct nouveau_pm_level boot; 566 struct nouveau_pm_level *cur; 567 568 struct device *hwmon; 569 struct notifier_block acpi_nb; 570 571 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 572 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 573 int (*clocks_set)(struct drm_device *, void *); 574 575 int (*voltage_get)(struct drm_device *); 576 int (*voltage_set)(struct drm_device *, int voltage); 577 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 578 int (*pwm_set)(struct drm_device *, int line, u32, u32); 579 int (*temp_get)(struct drm_device *); 580}; 581 582struct nouveau_vram_engine { 583 struct nouveau_mm mm; 584 585 int (*init)(struct drm_device *); 586 void (*takedown)(struct drm_device *dev); 587 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 588 u32 type, struct nouveau_mem **); 589 void (*put)(struct drm_device *, struct nouveau_mem **); 590 591 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 592}; 593 594struct nouveau_engine { 595 struct nouveau_instmem_engine instmem; 596 struct nouveau_mc_engine mc; 597 struct nouveau_timer_engine timer; 598 struct nouveau_fb_engine fb; 599 struct nouveau_fifo_engine fifo; 600 struct nouveau_display_engine display; 601 struct nouveau_gpio_engine gpio; 602 struct nouveau_pm_engine pm; 603 struct nouveau_vram_engine vram; 604}; 605 606struct nouveau_pll_vals { 607 union { 608 struct { 609#ifdef __BIG_ENDIAN 610 uint8_t N1, M1, N2, M2; 611#else 612 uint8_t M1, N1, M2, N2; 613#endif 614 }; 615 struct { 616 uint16_t NM1, NM2; 617 } __attribute__((packed)); 618 }; 619 int log2P; 620 621 int refclk; 622}; 623 624enum nv04_fp_display_regs { 625 FP_DISPLAY_END, 626 FP_TOTAL, 627 FP_CRTC, 628 FP_SYNC_START, 629 FP_SYNC_END, 630 FP_VALID_START, 631 FP_VALID_END 632}; 633 634struct nv04_crtc_reg { 635 unsigned char MiscOutReg; 636 uint8_t CRTC[0xa0]; 637 uint8_t CR58[0x10]; 638 uint8_t Sequencer[5]; 639 uint8_t Graphics[9]; 640 uint8_t Attribute[21]; 641 unsigned char DAC[768]; 642 643 /* PCRTC regs */ 644 uint32_t fb_start; 645 uint32_t crtc_cfg; 646 uint32_t cursor_cfg; 647 uint32_t gpio_ext; 648 uint32_t crtc_830; 649 uint32_t crtc_834; 650 uint32_t crtc_850; 651 uint32_t crtc_eng_ctrl; 652 653 /* PRAMDAC regs */ 654 uint32_t nv10_cursync; 655 struct nouveau_pll_vals pllvals; 656 uint32_t ramdac_gen_ctrl; 657 uint32_t ramdac_630; 658 uint32_t ramdac_634; 659 uint32_t tv_setup; 660 uint32_t tv_vtotal; 661 uint32_t tv_vskew; 662 uint32_t tv_vsync_delay; 663 uint32_t tv_htotal; 664 uint32_t tv_hskew; 665 uint32_t tv_hsync_delay; 666 uint32_t tv_hsync_delay2; 667 uint32_t fp_horiz_regs[7]; 668 uint32_t fp_vert_regs[7]; 669 uint32_t dither; 670 uint32_t fp_control; 671 uint32_t dither_regs[6]; 672 uint32_t fp_debug_0; 673 uint32_t fp_debug_1; 674 uint32_t fp_debug_2; 675 uint32_t fp_margin_color; 676 uint32_t ramdac_8c0; 677 uint32_t ramdac_a20; 678 uint32_t ramdac_a24; 679 uint32_t ramdac_a34; 680 uint32_t ctv_regs[38]; 681}; 682 683struct nv04_output_reg { 684 uint32_t output; 685 int head; 686}; 687 688struct nv04_mode_state { 689 struct nv04_crtc_reg crtc_reg[2]; 690 uint32_t pllsel; 691 uint32_t sel_clk; 692}; 693 694enum nouveau_card_type { 695 NV_04 = 0x00, 696 NV_10 = 0x10, 697 NV_20 = 0x20, 698 NV_30 = 0x30, 699 NV_40 = 0x40, 700 NV_50 = 0x50, 701 NV_C0 = 0xc0, 702 NV_D0 = 0xd0 703}; 704 705struct drm_nouveau_private { 706 struct drm_device *dev; 707 bool noaccel; 708 709 /* the card type, takes NV_* as values */ 710 enum nouveau_card_type card_type; 711 /* exact chipset, derived from NV_PMC_BOOT_0 */ 712 int chipset; 713 int flags; 714 u32 crystal; 715 716 void __iomem *mmio; 717 718 spinlock_t ramin_lock; 719 void __iomem *ramin; 720 u32 ramin_size; 721 u32 ramin_base; 722 bool ramin_available; 723 struct drm_mm ramin_heap; 724 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 725 struct list_head gpuobj_list; 726 struct list_head classes; 727 728 struct nouveau_bo *vga_ram; 729 730 /* interrupt handling */ 731 void (*irq_handler[32])(struct drm_device *); 732 bool msi_enabled; 733 734 struct list_head vbl_waiting; 735 736 struct { 737 struct drm_global_reference mem_global_ref; 738 struct ttm_bo_global_ref bo_global_ref; 739 struct ttm_bo_device bdev; 740 atomic_t validate_sequence; 741 } ttm; 742 743 struct { 744 spinlock_t lock; 745 struct drm_mm heap; 746 struct nouveau_bo *bo; 747 } fence; 748 749 struct { 750 spinlock_t lock; 751 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 752 } channels; 753 754 struct nouveau_engine engine; 755 struct nouveau_channel *channel; 756 757 /* For PFIFO and PGRAPH. */ 758 spinlock_t context_switch_lock; 759 760 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 761 spinlock_t vm_lock; 762 763 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 764 struct nouveau_ramht *ramht; 765 struct nouveau_gpuobj *ramfc; 766 struct nouveau_gpuobj *ramro; 767 768 uint32_t ramin_rsvd_vram; 769 770 struct { 771 enum { 772 NOUVEAU_GART_NONE = 0, 773 NOUVEAU_GART_AGP, /* AGP */ 774 NOUVEAU_GART_PDMA, /* paged dma object */ 775 NOUVEAU_GART_HW /* on-chip gart/vm */ 776 } type; 777 uint64_t aper_base; 778 uint64_t aper_size; 779 uint64_t aper_free; 780 781 struct ttm_backend_func *func; 782 783 struct { 784 struct page *page; 785 dma_addr_t addr; 786 } dummy; 787 788 struct nouveau_gpuobj *sg_ctxdma; 789 } gart_info; 790 791 /* nv10-nv40 tiling regions */ 792 struct { 793 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 794 spinlock_t lock; 795 } tile; 796 797 /* VRAM/fb configuration */ 798 enum { 799 NV_MEM_TYPE_UNKNOWN = 0, 800 NV_MEM_TYPE_STOLEN, 801 NV_MEM_TYPE_SGRAM, 802 NV_MEM_TYPE_SDRAM, 803 NV_MEM_TYPE_DDR1, 804 NV_MEM_TYPE_DDR2, 805 NV_MEM_TYPE_DDR3, 806 NV_MEM_TYPE_GDDR2, 807 NV_MEM_TYPE_GDDR3, 808 NV_MEM_TYPE_GDDR4, 809 NV_MEM_TYPE_GDDR5 810 } vram_type; 811 uint64_t vram_size; 812 uint64_t vram_sys_base; 813 bool vram_rank_B; 814 815 uint64_t fb_available_size; 816 uint64_t fb_mappable_pages; 817 uint64_t fb_aper_free; 818 int fb_mtrr; 819 820 /* BAR control (NV50-) */ 821 struct nouveau_vm *bar1_vm; 822 struct nouveau_vm *bar3_vm; 823 824 /* G8x/G9x virtual address space */ 825 struct nouveau_vm *chan_vm; 826 827 struct nvbios vbios; 828 u8 *mxms; 829 struct list_head i2c_ports; 830 831 struct nv04_mode_state mode_reg; 832 struct nv04_mode_state saved_reg; 833 uint32_t saved_vga_font[4][16384]; 834 uint32_t crtc_owner; 835 uint32_t dac_users[4]; 836 837 struct backlight_device *backlight; 838 839 struct { 840 struct dentry *channel_root; 841 } debugfs; 842 843 struct nouveau_fbdev *nfbdev; 844 struct apertures_struct *apertures; 845}; 846 847static inline struct drm_nouveau_private * 848nouveau_private(struct drm_device *dev) 849{ 850 return dev->dev_private; 851} 852 853static inline struct drm_nouveau_private * 854nouveau_bdev(struct ttm_bo_device *bd) 855{ 856 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 857} 858 859static inline int 860nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 861{ 862 struct nouveau_bo *prev; 863 864 if (!pnvbo) 865 return -EINVAL; 866 prev = *pnvbo; 867 868 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 869 if (prev) { 870 struct ttm_buffer_object *bo = &prev->bo; 871 872 ttm_bo_unref(&bo); 873 } 874 875 return 0; 876} 877 878/* nouveau_drv.c */ 879extern int nouveau_modeset; 880extern int nouveau_agpmode; 881extern int nouveau_duallink; 882extern int nouveau_uscript_lvds; 883extern int nouveau_uscript_tmds; 884extern int nouveau_vram_pushbuf; 885extern int nouveau_vram_notify; 886extern char *nouveau_vram_type; 887extern int nouveau_fbpercrtc; 888extern int nouveau_tv_disable; 889extern char *nouveau_tv_norm; 890extern int nouveau_reg_debug; 891extern char *nouveau_vbios; 892extern int nouveau_ignorelid; 893extern int nouveau_nofbaccel; 894extern int nouveau_noaccel; 895extern int nouveau_force_post; 896extern int nouveau_override_conntype; 897extern char *nouveau_perflvl; 898extern int nouveau_perflvl_wr; 899extern int nouveau_msi; 900extern int nouveau_ctxfw; 901extern int nouveau_mxmdcb; 902 903extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 904extern int nouveau_pci_resume(struct pci_dev *pdev); 905 906/* nouveau_state.c */ 907extern int nouveau_open(struct drm_device *, struct drm_file *); 908extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 909extern void nouveau_postclose(struct drm_device *, struct drm_file *); 910extern int nouveau_load(struct drm_device *, unsigned long flags); 911extern int nouveau_firstopen(struct drm_device *); 912extern void nouveau_lastclose(struct drm_device *); 913extern int nouveau_unload(struct drm_device *); 914extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 915 struct drm_file *); 916extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 917 struct drm_file *); 918extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 919 uint32_t reg, uint32_t mask, uint32_t val); 920extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 921 uint32_t reg, uint32_t mask, uint32_t val); 922extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 923 bool (*cond)(void *), void *); 924extern bool nouveau_wait_for_idle(struct drm_device *); 925extern int nouveau_card_init(struct drm_device *); 926 927/* nouveau_mem.c */ 928extern int nouveau_mem_vram_init(struct drm_device *); 929extern void nouveau_mem_vram_fini(struct drm_device *); 930extern int nouveau_mem_gart_init(struct drm_device *); 931extern void nouveau_mem_gart_fini(struct drm_device *); 932extern int nouveau_mem_init_agp(struct drm_device *); 933extern int nouveau_mem_reset_agp(struct drm_device *); 934extern void nouveau_mem_close(struct drm_device *); 935extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 936extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, 937 struct nouveau_pm_memtiming *); 938extern void nouveau_mem_timing_read(struct drm_device *, 939 struct nouveau_pm_memtiming *); 940extern int nouveau_mem_vbios_type(struct drm_device *); 941extern struct nouveau_tile_reg *nv10_mem_set_tiling( 942 struct drm_device *dev, uint32_t addr, uint32_t size, 943 uint32_t pitch, uint32_t flags); 944extern void nv10_mem_put_tile_region(struct drm_device *dev, 945 struct nouveau_tile_reg *tile, 946 struct nouveau_fence *fence); 947extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 948extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 949 950/* nouveau_notifier.c */ 951extern int nouveau_notifier_init_channel(struct nouveau_channel *); 952extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 953extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 954 int cout, uint32_t start, uint32_t end, 955 uint32_t *offset); 956extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 957extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 958 struct drm_file *); 959extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 960 struct drm_file *); 961 962/* nouveau_channel.c */ 963extern struct drm_ioctl_desc nouveau_ioctls[]; 964extern int nouveau_max_ioctl; 965extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 966extern int nouveau_channel_alloc(struct drm_device *dev, 967 struct nouveau_channel **chan, 968 struct drm_file *file_priv, 969 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 970extern struct nouveau_channel * 971nouveau_channel_get_unlocked(struct nouveau_channel *); 972extern struct nouveau_channel * 973nouveau_channel_get(struct drm_file *, int id); 974extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 975extern void nouveau_channel_put(struct nouveau_channel **); 976extern void nouveau_channel_ref(struct nouveau_channel *chan, 977 struct nouveau_channel **pchan); 978extern void nouveau_channel_idle(struct nouveau_channel *chan); 979 980/* nouveau_object.c */ 981#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 982 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 983 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 984} while (0) 985 986#define NVOBJ_ENGINE_DEL(d, e) do { \ 987 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 988 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 989} while (0) 990 991#define NVOBJ_CLASS(d, c, e) do { \ 992 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 993 if (ret) \ 994 return ret; \ 995} while (0) 996 997#define NVOBJ_MTHD(d, c, m, e) do { \ 998 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 999 if (ret) \ 1000 return ret; \ 1001} while (0) 1002 1003extern int nouveau_gpuobj_early_init(struct drm_device *); 1004extern int nouveau_gpuobj_init(struct drm_device *); 1005extern void nouveau_gpuobj_takedown(struct drm_device *); 1006extern int nouveau_gpuobj_suspend(struct drm_device *dev); 1007extern void nouveau_gpuobj_resume(struct drm_device *dev); 1008extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 1009extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 1010 int (*exec)(struct nouveau_channel *, 1011 u32 class, u32 mthd, u32 data)); 1012extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 1013extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 1014extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 1015 uint32_t vram_h, uint32_t tt_h); 1016extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 1017extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 1018 uint32_t size, int align, uint32_t flags, 1019 struct nouveau_gpuobj **); 1020extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 1021 struct nouveau_gpuobj **); 1022extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 1023 u32 size, u32 flags, 1024 struct nouveau_gpuobj **); 1025extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 1026 uint64_t offset, uint64_t size, int access, 1027 int target, struct nouveau_gpuobj **); 1028extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1029extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1030 u64 size, int target, int access, u32 type, 1031 u32 comp, struct nouveau_gpuobj **pobj); 1032extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1033 int class, u64 base, u64 size, int target, 1034 int access, u32 type, u32 comp); 1035extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1036 struct drm_file *); 1037extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1038 struct drm_file *); 1039 1040/* nouveau_irq.c */ 1041extern int nouveau_irq_init(struct drm_device *); 1042extern void nouveau_irq_fini(struct drm_device *); 1043extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1044extern void nouveau_irq_register(struct drm_device *, int status_bit, 1045 void (*)(struct drm_device *)); 1046extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1047extern void nouveau_irq_preinstall(struct drm_device *); 1048extern int nouveau_irq_postinstall(struct drm_device *); 1049extern void nouveau_irq_uninstall(struct drm_device *); 1050 1051/* nouveau_sgdma.c */ 1052extern int nouveau_sgdma_init(struct drm_device *); 1053extern void nouveau_sgdma_takedown(struct drm_device *); 1054extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1055 uint32_t offset); 1056extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1057 unsigned long size, 1058 uint32_t page_flags, 1059 struct page *dummy_read_page); 1060 1061/* nouveau_debugfs.c */ 1062#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1063extern int nouveau_debugfs_init(struct drm_minor *); 1064extern void nouveau_debugfs_takedown(struct drm_minor *); 1065extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1066extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1067#else 1068static inline int 1069nouveau_debugfs_init(struct drm_minor *minor) 1070{ 1071 return 0; 1072} 1073 1074static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1075{ 1076} 1077 1078static inline int 1079nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1080{ 1081 return 0; 1082} 1083 1084static inline void 1085nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1086{ 1087} 1088#endif 1089 1090/* nouveau_dma.c */ 1091extern void nouveau_dma_pre_init(struct nouveau_channel *); 1092extern int nouveau_dma_init(struct nouveau_channel *); 1093extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1094 1095/* nouveau_acpi.c */ 1096#define ROM_BIOS_PAGE 4096 1097#if defined(CONFIG_ACPI) 1098void nouveau_register_dsm_handler(void); 1099void nouveau_unregister_dsm_handler(void); 1100void nouveau_switcheroo_optimus_dsm(void); 1101int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1102bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1103int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1104#else 1105static inline void nouveau_register_dsm_handler(void) {} 1106static inline void nouveau_unregister_dsm_handler(void) {} 1107static inline void nouveau_switcheroo_optimus_dsm(void) {} 1108static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1109static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1110static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1111#endif 1112 1113/* nouveau_backlight.c */ 1114#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1115extern int nouveau_backlight_init(struct drm_device *); 1116extern void nouveau_backlight_exit(struct drm_device *); 1117#else 1118static inline int nouveau_backlight_init(struct drm_device *dev) 1119{ 1120 return 0; 1121} 1122 1123static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1124#endif 1125 1126/* nouveau_bios.c */ 1127extern int nouveau_bios_init(struct drm_device *); 1128extern void nouveau_bios_takedown(struct drm_device *dev); 1129extern int nouveau_run_vbios_init(struct drm_device *); 1130extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1131 struct dcb_entry *, int crtc); 1132extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1133extern struct dcb_connector_table_entry * 1134nouveau_bios_connector_entry(struct drm_device *, int index); 1135extern u32 get_pll_register(struct drm_device *, enum pll_types); 1136extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1137 struct pll_lims *); 1138extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1139 struct dcb_entry *, int crtc); 1140extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1141extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1142extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1143 bool *dl, bool *if_is_24bit); 1144extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1145 int head, int pxclk); 1146extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1147 enum LVDS_script, int pxclk); 1148bool bios_encoder_match(struct dcb_entry *, u32 hash); 1149 1150/* nouveau_mxm.c */ 1151int nouveau_mxm_init(struct drm_device *dev); 1152void nouveau_mxm_fini(struct drm_device *dev); 1153 1154/* nouveau_ttm.c */ 1155int nouveau_ttm_global_init(struct drm_nouveau_private *); 1156void nouveau_ttm_global_release(struct drm_nouveau_private *); 1157int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1158 1159/* nouveau_hdmi.c */ 1160void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1161 1162/* nouveau_dp.c */ 1163int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1164 uint8_t *data, int data_nr); 1165bool nouveau_dp_detect(struct drm_encoder *); 1166bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1167void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1168u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1169 1170/* nv04_fb.c */ 1171extern int nv04_fb_vram_init(struct drm_device *); 1172extern int nv04_fb_init(struct drm_device *); 1173extern void nv04_fb_takedown(struct drm_device *); 1174 1175/* nv10_fb.c */ 1176extern int nv10_fb_vram_init(struct drm_device *dev); 1177extern int nv1a_fb_vram_init(struct drm_device *dev); 1178extern int nv10_fb_init(struct drm_device *); 1179extern void nv10_fb_takedown(struct drm_device *); 1180extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1181 uint32_t addr, uint32_t size, 1182 uint32_t pitch, uint32_t flags); 1183extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1184extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1185 1186/* nv20_fb.c */ 1187extern int nv20_fb_vram_init(struct drm_device *dev); 1188extern int nv20_fb_init(struct drm_device *); 1189extern void nv20_fb_takedown(struct drm_device *); 1190extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1191 uint32_t addr, uint32_t size, 1192 uint32_t pitch, uint32_t flags); 1193extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1194extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1195 1196/* nv30_fb.c */ 1197extern int nv30_fb_init(struct drm_device *); 1198extern void nv30_fb_takedown(struct drm_device *); 1199extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1200 uint32_t addr, uint32_t size, 1201 uint32_t pitch, uint32_t flags); 1202extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1203 1204/* nv40_fb.c */ 1205extern int nv40_fb_vram_init(struct drm_device *dev); 1206extern int nv40_fb_init(struct drm_device *); 1207extern void nv40_fb_takedown(struct drm_device *); 1208extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1209 1210/* nv50_fb.c */ 1211extern int nv50_fb_init(struct drm_device *); 1212extern void nv50_fb_takedown(struct drm_device *); 1213extern void nv50_fb_vm_trap(struct drm_device *, int display); 1214 1215/* nvc0_fb.c */ 1216extern int nvc0_fb_init(struct drm_device *); 1217extern void nvc0_fb_takedown(struct drm_device *); 1218 1219/* nv04_fifo.c */ 1220extern int nv04_fifo_init(struct drm_device *); 1221extern void nv04_fifo_fini(struct drm_device *); 1222extern void nv04_fifo_disable(struct drm_device *); 1223extern void nv04_fifo_enable(struct drm_device *); 1224extern bool nv04_fifo_reassign(struct drm_device *, bool); 1225extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1226extern int nv04_fifo_channel_id(struct drm_device *); 1227extern int nv04_fifo_create_context(struct nouveau_channel *); 1228extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1229extern int nv04_fifo_load_context(struct nouveau_channel *); 1230extern int nv04_fifo_unload_context(struct drm_device *); 1231extern void nv04_fifo_isr(struct drm_device *); 1232 1233/* nv10_fifo.c */ 1234extern int nv10_fifo_init(struct drm_device *); 1235extern int nv10_fifo_channel_id(struct drm_device *); 1236extern int nv10_fifo_create_context(struct nouveau_channel *); 1237extern int nv10_fifo_load_context(struct nouveau_channel *); 1238extern int nv10_fifo_unload_context(struct drm_device *); 1239 1240/* nv40_fifo.c */ 1241extern int nv40_fifo_init(struct drm_device *); 1242extern int nv40_fifo_create_context(struct nouveau_channel *); 1243extern int nv40_fifo_load_context(struct nouveau_channel *); 1244extern int nv40_fifo_unload_context(struct drm_device *); 1245 1246/* nv50_fifo.c */ 1247extern int nv50_fifo_init(struct drm_device *); 1248extern void nv50_fifo_takedown(struct drm_device *); 1249extern int nv50_fifo_channel_id(struct drm_device *); 1250extern int nv50_fifo_create_context(struct nouveau_channel *); 1251extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1252extern int nv50_fifo_load_context(struct nouveau_channel *); 1253extern int nv50_fifo_unload_context(struct drm_device *); 1254extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1255 1256/* nvc0_fifo.c */ 1257extern int nvc0_fifo_init(struct drm_device *); 1258extern void nvc0_fifo_takedown(struct drm_device *); 1259extern void nvc0_fifo_disable(struct drm_device *); 1260extern void nvc0_fifo_enable(struct drm_device *); 1261extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1262extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1263extern int nvc0_fifo_channel_id(struct drm_device *); 1264extern int nvc0_fifo_create_context(struct nouveau_channel *); 1265extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1266extern int nvc0_fifo_load_context(struct nouveau_channel *); 1267extern int nvc0_fifo_unload_context(struct drm_device *); 1268 1269/* nv04_graph.c */ 1270extern int nv04_graph_create(struct drm_device *); 1271extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1272extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1273 u32 class, u32 mthd, u32 data); 1274extern struct nouveau_bitfield nv04_graph_nsource[]; 1275 1276/* nv10_graph.c */ 1277extern int nv10_graph_create(struct drm_device *); 1278extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1279extern struct nouveau_bitfield nv10_graph_intr[]; 1280extern struct nouveau_bitfield nv10_graph_nstatus[]; 1281 1282/* nv20_graph.c */ 1283extern int nv20_graph_create(struct drm_device *); 1284 1285/* nv40_graph.c */ 1286extern int nv40_graph_create(struct drm_device *); 1287extern void nv40_grctx_init(struct nouveau_grctx *); 1288 1289/* nv50_graph.c */ 1290extern int nv50_graph_create(struct drm_device *); 1291extern int nv50_grctx_init(struct nouveau_grctx *); 1292extern struct nouveau_enum nv50_data_error_names[]; 1293extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1294 1295/* nvc0_graph.c */ 1296extern int nvc0_graph_create(struct drm_device *); 1297extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1298 1299/* nv84_crypt.c */ 1300extern int nv84_crypt_create(struct drm_device *); 1301 1302/* nv98_crypt.c */ 1303extern int nv98_crypt_create(struct drm_device *dev); 1304 1305/* nva3_copy.c */ 1306extern int nva3_copy_create(struct drm_device *dev); 1307 1308/* nvc0_copy.c */ 1309extern int nvc0_copy_create(struct drm_device *dev, int engine); 1310 1311/* nv31_mpeg.c */ 1312extern int nv31_mpeg_create(struct drm_device *dev); 1313 1314/* nv50_mpeg.c */ 1315extern int nv50_mpeg_create(struct drm_device *dev); 1316 1317/* nv84_bsp.c */ 1318/* nv98_bsp.c */ 1319extern int nv84_bsp_create(struct drm_device *dev); 1320 1321/* nv84_vp.c */ 1322/* nv98_vp.c */ 1323extern int nv84_vp_create(struct drm_device *dev); 1324 1325/* nv98_ppp.c */ 1326extern int nv98_ppp_create(struct drm_device *dev); 1327 1328/* nv04_instmem.c */ 1329extern int nv04_instmem_init(struct drm_device *); 1330extern void nv04_instmem_takedown(struct drm_device *); 1331extern int nv04_instmem_suspend(struct drm_device *); 1332extern void nv04_instmem_resume(struct drm_device *); 1333extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1334 u32 size, u32 align); 1335extern void nv04_instmem_put(struct nouveau_gpuobj *); 1336extern int nv04_instmem_map(struct nouveau_gpuobj *); 1337extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1338extern void nv04_instmem_flush(struct drm_device *); 1339 1340/* nv50_instmem.c */ 1341extern int nv50_instmem_init(struct drm_device *); 1342extern void nv50_instmem_takedown(struct drm_device *); 1343extern int nv50_instmem_suspend(struct drm_device *); 1344extern void nv50_instmem_resume(struct drm_device *); 1345extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1346 u32 size, u32 align); 1347extern void nv50_instmem_put(struct nouveau_gpuobj *); 1348extern int nv50_instmem_map(struct nouveau_gpuobj *); 1349extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1350extern void nv50_instmem_flush(struct drm_device *); 1351extern void nv84_instmem_flush(struct drm_device *); 1352 1353/* nvc0_instmem.c */ 1354extern int nvc0_instmem_init(struct drm_device *); 1355extern void nvc0_instmem_takedown(struct drm_device *); 1356extern int nvc0_instmem_suspend(struct drm_device *); 1357extern void nvc0_instmem_resume(struct drm_device *); 1358 1359/* nv04_mc.c */ 1360extern int nv04_mc_init(struct drm_device *); 1361extern void nv04_mc_takedown(struct drm_device *); 1362 1363/* nv40_mc.c */ 1364extern int nv40_mc_init(struct drm_device *); 1365extern void nv40_mc_takedown(struct drm_device *); 1366 1367/* nv50_mc.c */ 1368extern int nv50_mc_init(struct drm_device *); 1369extern void nv50_mc_takedown(struct drm_device *); 1370 1371/* nv04_timer.c */ 1372extern int nv04_timer_init(struct drm_device *); 1373extern uint64_t nv04_timer_read(struct drm_device *); 1374extern void nv04_timer_takedown(struct drm_device *); 1375 1376extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1377 unsigned long arg); 1378 1379/* nv04_dac.c */ 1380extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1381extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1382extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1383extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1384extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1385 1386/* nv04_dfp.c */ 1387extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1388extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1389extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1390 int head, bool dl); 1391extern void nv04_dfp_disable(struct drm_device *dev, int head); 1392extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1393 1394/* nv04_tv.c */ 1395extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1396extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1397 1398/* nv17_tv.c */ 1399extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1400 1401/* nv04_display.c */ 1402extern int nv04_display_early_init(struct drm_device *); 1403extern void nv04_display_late_takedown(struct drm_device *); 1404extern int nv04_display_create(struct drm_device *); 1405extern void nv04_display_destroy(struct drm_device *); 1406extern int nv04_display_init(struct drm_device *); 1407extern void nv04_display_fini(struct drm_device *); 1408 1409/* nvd0_display.c */ 1410extern int nvd0_display_create(struct drm_device *); 1411extern void nvd0_display_destroy(struct drm_device *); 1412extern int nvd0_display_init(struct drm_device *); 1413extern void nvd0_display_fini(struct drm_device *); 1414struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1415void nvd0_display_flip_stop(struct drm_crtc *); 1416int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1417 struct nouveau_channel *, u32 swap_interval); 1418 1419/* nv04_crtc.c */ 1420extern int nv04_crtc_create(struct drm_device *, int index); 1421 1422/* nouveau_bo.c */ 1423extern struct ttm_bo_driver nouveau_bo_driver; 1424extern int nouveau_bo_new(struct drm_device *, int size, int align, 1425 uint32_t flags, uint32_t tile_mode, 1426 uint32_t tile_flags, struct nouveau_bo **); 1427extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1428extern int nouveau_bo_unpin(struct nouveau_bo *); 1429extern int nouveau_bo_map(struct nouveau_bo *); 1430extern void nouveau_bo_unmap(struct nouveau_bo *); 1431extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1432 uint32_t busy); 1433extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1434extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1435extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1436extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1437extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1438extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1439 bool no_wait_reserve, bool no_wait_gpu); 1440 1441extern struct nouveau_vma * 1442nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1443extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1444 struct nouveau_vma *); 1445extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1446 1447/* nouveau_fence.c */ 1448struct nouveau_fence; 1449extern int nouveau_fence_init(struct drm_device *); 1450extern void nouveau_fence_fini(struct drm_device *); 1451extern int nouveau_fence_channel_init(struct nouveau_channel *); 1452extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1453extern void nouveau_fence_update(struct nouveau_channel *); 1454extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1455 bool emit); 1456extern int nouveau_fence_emit(struct nouveau_fence *); 1457extern void nouveau_fence_work(struct nouveau_fence *fence, 1458 void (*work)(void *priv, bool signalled), 1459 void *priv); 1460struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1461 1462extern bool __nouveau_fence_signalled(void *obj, void *arg); 1463extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1464extern int __nouveau_fence_flush(void *obj, void *arg); 1465extern void __nouveau_fence_unref(void **obj); 1466extern void *__nouveau_fence_ref(void *obj); 1467 1468static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1469{ 1470 return __nouveau_fence_signalled(obj, NULL); 1471} 1472static inline int 1473nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1474{ 1475 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1476} 1477extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1478static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1479{ 1480 return __nouveau_fence_flush(obj, NULL); 1481} 1482static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1483{ 1484 __nouveau_fence_unref((void **)obj); 1485} 1486static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1487{ 1488 return __nouveau_fence_ref(obj); 1489} 1490 1491/* nouveau_gem.c */ 1492extern int nouveau_gem_new(struct drm_device *, int size, int align, 1493 uint32_t domain, uint32_t tile_mode, 1494 uint32_t tile_flags, struct nouveau_bo **); 1495extern int nouveau_gem_object_new(struct drm_gem_object *); 1496extern void nouveau_gem_object_del(struct drm_gem_object *); 1497extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1498extern void nouveau_gem_object_close(struct drm_gem_object *, 1499 struct drm_file *); 1500extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1501 struct drm_file *); 1502extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1503 struct drm_file *); 1504extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1505 struct drm_file *); 1506extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1507 struct drm_file *); 1508extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1509 struct drm_file *); 1510 1511/* nouveau_display.c */ 1512int nouveau_display_create(struct drm_device *dev); 1513void nouveau_display_destroy(struct drm_device *dev); 1514int nouveau_display_init(struct drm_device *dev); 1515void nouveau_display_fini(struct drm_device *dev); 1516int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1517void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1518int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1519 struct drm_pending_vblank_event *event); 1520int nouveau_finish_page_flip(struct nouveau_channel *, 1521 struct nouveau_page_flip_state *); 1522int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1523 struct drm_mode_create_dumb *args); 1524int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1525 uint32_t handle, uint64_t *offset); 1526int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1527 uint32_t handle); 1528 1529/* nv10_gpio.c */ 1530int nv10_gpio_init(struct drm_device *dev); 1531void nv10_gpio_fini(struct drm_device *dev); 1532int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1533int nv10_gpio_sense(struct drm_device *dev, int line); 1534void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1535 1536/* nv50_gpio.c */ 1537int nv50_gpio_init(struct drm_device *dev); 1538void nv50_gpio_fini(struct drm_device *dev); 1539int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1540int nv50_gpio_sense(struct drm_device *dev, int line); 1541void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1542int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1543int nvd0_gpio_sense(struct drm_device *dev, int line); 1544 1545/* nv50_calc.c */ 1546int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1547 int *N1, int *M1, int *N2, int *M2, int *P); 1548int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1549 int clk, int *N, int *fN, int *M, int *P); 1550 1551#ifndef ioread32_native 1552#ifdef __BIG_ENDIAN 1553#define ioread16_native ioread16be 1554#define iowrite16_native iowrite16be 1555#define ioread32_native ioread32be 1556#define iowrite32_native iowrite32be 1557#else /* def __BIG_ENDIAN */ 1558#define ioread16_native ioread16 1559#define iowrite16_native iowrite16 1560#define ioread32_native ioread32 1561#define iowrite32_native iowrite32 1562#endif /* def __BIG_ENDIAN else */ 1563#endif /* !ioread32_native */ 1564 1565/* channel control reg access */ 1566static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1567{ 1568 return ioread32_native(chan->user + reg); 1569} 1570 1571static inline void nvchan_wr32(struct nouveau_channel *chan, 1572 unsigned reg, u32 val) 1573{ 1574 iowrite32_native(val, chan->user + reg); 1575} 1576 1577/* register access */ 1578static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1579{ 1580 struct drm_nouveau_private *dev_priv = dev->dev_private; 1581 return ioread32_native(dev_priv->mmio + reg); 1582} 1583 1584static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1585{ 1586 struct drm_nouveau_private *dev_priv = dev->dev_private; 1587 iowrite32_native(val, dev_priv->mmio + reg); 1588} 1589 1590static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1591{ 1592 u32 tmp = nv_rd32(dev, reg); 1593 nv_wr32(dev, reg, (tmp & ~mask) | val); 1594 return tmp; 1595} 1596 1597static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1598{ 1599 struct drm_nouveau_private *dev_priv = dev->dev_private; 1600 return ioread8(dev_priv->mmio + reg); 1601} 1602 1603static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1604{ 1605 struct drm_nouveau_private *dev_priv = dev->dev_private; 1606 iowrite8(val, dev_priv->mmio + reg); 1607} 1608 1609#define nv_wait(dev, reg, mask, val) \ 1610 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1611#define nv_wait_ne(dev, reg, mask, val) \ 1612 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1613#define nv_wait_cb(dev, func, data) \ 1614 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1615 1616/* PRAMIN access */ 1617static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1618{ 1619 struct drm_nouveau_private *dev_priv = dev->dev_private; 1620 return ioread32_native(dev_priv->ramin + offset); 1621} 1622 1623static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1624{ 1625 struct drm_nouveau_private *dev_priv = dev->dev_private; 1626 iowrite32_native(val, dev_priv->ramin + offset); 1627} 1628 1629/* object access */ 1630extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1631extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1632 1633/* 1634 * Logging 1635 * Argument d is (struct drm_device *). 1636 */ 1637#define NV_PRINTK(level, d, fmt, arg...) \ 1638 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1639 pci_name(d->pdev), ##arg) 1640#ifndef NV_DEBUG_NOTRACE 1641#define NV_DEBUG(d, fmt, arg...) do { \ 1642 if (drm_debug & DRM_UT_DRIVER) { \ 1643 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1644 __LINE__, ##arg); \ 1645 } \ 1646} while (0) 1647#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1648 if (drm_debug & DRM_UT_KMS) { \ 1649 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1650 __LINE__, ##arg); \ 1651 } \ 1652} while (0) 1653#else 1654#define NV_DEBUG(d, fmt, arg...) do { \ 1655 if (drm_debug & DRM_UT_DRIVER) \ 1656 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1657} while (0) 1658#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1659 if (drm_debug & DRM_UT_KMS) \ 1660 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1661} while (0) 1662#endif 1663#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1664#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1665#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1666#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1667#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1668#define NV_WARNONCE(d, fmt, arg...) do { \ 1669 static int _warned = 0; \ 1670 if (!_warned) { \ 1671 NV_WARN(d, fmt, ##arg); \ 1672 _warned = 1; \ 1673 } \ 1674} while(0) 1675 1676/* nouveau_reg_debug bitmask */ 1677enum { 1678 NOUVEAU_REG_DEBUG_MC = 0x1, 1679 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1680 NOUVEAU_REG_DEBUG_FB = 0x4, 1681 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1682 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1683 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1684 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1685 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1686 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1687 NOUVEAU_REG_DEBUG_EVO = 0x200, 1688 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1689}; 1690 1691#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1692 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1693 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1694} while (0) 1695 1696static inline bool 1697nv_two_heads(struct drm_device *dev) 1698{ 1699 struct drm_nouveau_private *dev_priv = dev->dev_private; 1700 const int impl = dev->pci_device & 0x0ff0; 1701 1702 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1703 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1704 return true; 1705 1706 return false; 1707} 1708 1709static inline bool 1710nv_gf4_disp_arch(struct drm_device *dev) 1711{ 1712 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1713} 1714 1715static inline bool 1716nv_two_reg_pll(struct drm_device *dev) 1717{ 1718 struct drm_nouveau_private *dev_priv = dev->dev_private; 1719 const int impl = dev->pci_device & 0x0ff0; 1720 1721 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1722 return true; 1723 return false; 1724} 1725 1726static inline bool 1727nv_match_device(struct drm_device *dev, unsigned device, 1728 unsigned sub_vendor, unsigned sub_device) 1729{ 1730 return dev->pdev->device == device && 1731 dev->pdev->subsystem_vendor == sub_vendor && 1732 dev->pdev->subsystem_device == sub_device; 1733} 1734 1735static inline void * 1736nv_engine(struct drm_device *dev, int engine) 1737{ 1738 struct drm_nouveau_private *dev_priv = dev->dev_private; 1739 return (void *)dev_priv->eng[engine]; 1740} 1741 1742/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1743 * helpful to determine a number of other hardware features 1744 */ 1745static inline int 1746nv44_graph_class(struct drm_device *dev) 1747{ 1748 struct drm_nouveau_private *dev_priv = dev->dev_private; 1749 1750 if ((dev_priv->chipset & 0xf0) == 0x60) 1751 return 1; 1752 1753 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1754} 1755 1756/* memory type/access flags, do not match hardware values */ 1757#define NV_MEM_ACCESS_RO 1 1758#define NV_MEM_ACCESS_WO 2 1759#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1760#define NV_MEM_ACCESS_SYS 4 1761#define NV_MEM_ACCESS_VM 8 1762 1763#define NV_MEM_TARGET_VRAM 0 1764#define NV_MEM_TARGET_PCI 1 1765#define NV_MEM_TARGET_PCI_NOSNOOP 2 1766#define NV_MEM_TARGET_VM 3 1767#define NV_MEM_TARGET_GART 4 1768 1769#define NV_MEM_TYPE_VM 0x7f 1770#define NV_MEM_COMP_VM 0x03 1771 1772/* NV_SW object class */ 1773#define NV_SW 0x0000506e 1774#define NV_SW_DMA_SEMAPHORE 0x00000060 1775#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1776#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1777#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1778#define NV_SW_YIELD 0x00000080 1779#define NV_SW_DMA_VBLSEM 0x0000018c 1780#define NV_SW_VBLSEM_OFFSET 0x00000400 1781#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1782#define NV_SW_VBLSEM_RELEASE 0x00000408 1783#define NV_SW_PAGE_FLIP 0x00000500 1784 1785#endif /* __NOUVEAU_DRV_H__ */ 1786