nouveau_drv.h revision 27100ac95a8eee0b083e46bfa67b229ac641d28c
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct list_head vma_list; 117 unsigned page_shift; 118 119 uint32_t tile_mode; 120 uint32_t tile_flags; 121 struct nouveau_tile_reg *tile; 122 123 struct drm_gem_object *gem; 124 int pin_refcnt; 125}; 126 127#define nouveau_bo_tile_layout(nvbo) \ 128 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 129 130static inline struct nouveau_bo * 131nouveau_bo(struct ttm_buffer_object *bo) 132{ 133 return container_of(bo, struct nouveau_bo, bo); 134} 135 136static inline struct nouveau_bo * 137nouveau_gem_object(struct drm_gem_object *gem) 138{ 139 return gem ? gem->driver_private : NULL; 140} 141 142/* TODO: submit equivalent to TTM generic API upstream? */ 143static inline void __iomem * 144nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 145{ 146 bool is_iomem; 147 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 148 &nvbo->kmap, &is_iomem); 149 WARN_ON_ONCE(ioptr && !is_iomem); 150 return ioptr; 151} 152 153enum nouveau_flags { 154 NV_NFORCE = 0x10000000, 155 NV_NFORCE2 = 0x20000000 156}; 157 158#define NVOBJ_ENGINE_SW 0 159#define NVOBJ_ENGINE_GR 1 160#define NVOBJ_ENGINE_CRYPT 2 161#define NVOBJ_ENGINE_COPY0 3 162#define NVOBJ_ENGINE_COPY1 4 163#define NVOBJ_ENGINE_MPEG 5 164#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 165#define NVOBJ_ENGINE_BSP 6 166#define NVOBJ_ENGINE_VP 7 167#define NVOBJ_ENGINE_DISPLAY 15 168#define NVOBJ_ENGINE_NR 16 169 170#define NVOBJ_FLAG_DONT_MAP (1 << 0) 171#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 172#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 173#define NVOBJ_FLAG_VM (1 << 3) 174#define NVOBJ_FLAG_VM_USER (1 << 4) 175 176#define NVOBJ_CINST_GLOBAL 0xdeadbeef 177 178struct nouveau_gpuobj { 179 struct drm_device *dev; 180 struct kref refcount; 181 struct list_head list; 182 183 void *node; 184 u32 *suspend; 185 186 uint32_t flags; 187 188 u32 size; 189 u32 pinst; /* PRAMIN BAR offset */ 190 u32 cinst; /* Channel offset */ 191 u64 vinst; /* VRAM address */ 192 u64 linst; /* VM address */ 193 194 uint32_t engine; 195 uint32_t class; 196 197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 198 void *priv; 199}; 200 201struct nouveau_page_flip_state { 202 struct list_head head; 203 struct drm_pending_vblank_event *event; 204 int crtc, bpp, pitch, x, y; 205 uint64_t offset; 206}; 207 208enum nouveau_channel_mutex_class { 209 NOUVEAU_UCHANNEL_MUTEX, 210 NOUVEAU_KCHANNEL_MUTEX 211}; 212 213struct nouveau_channel { 214 struct drm_device *dev; 215 struct list_head list; 216 int id; 217 218 /* references to the channel data structure */ 219 struct kref ref; 220 /* users of the hardware channel resources, the hardware 221 * context will be kicked off when it reaches zero. */ 222 atomic_t users; 223 struct mutex mutex; 224 225 /* owner of this fifo */ 226 struct drm_file *file_priv; 227 /* mapping of the fifo itself */ 228 struct drm_local_map *map; 229 230 /* mapping of the regs controlling the fifo */ 231 void __iomem *user; 232 uint32_t user_get; 233 uint32_t user_get_hi; 234 uint32_t user_put; 235 236 /* Fencing */ 237 struct { 238 /* lock protects the pending list only */ 239 spinlock_t lock; 240 struct list_head pending; 241 uint32_t sequence; 242 uint32_t sequence_ack; 243 atomic_t last_sequence_irq; 244 struct nouveau_vma vma; 245 } fence; 246 247 /* DMA push buffer */ 248 struct nouveau_gpuobj *pushbuf; 249 struct nouveau_bo *pushbuf_bo; 250 struct nouveau_vma pushbuf_vma; 251 uint64_t pushbuf_base; 252 253 /* Notifier memory */ 254 struct nouveau_bo *notifier_bo; 255 struct nouveau_vma notifier_vma; 256 struct drm_mm notifier_heap; 257 258 /* PFIFO context */ 259 struct nouveau_gpuobj *ramfc; 260 struct nouveau_gpuobj *cache; 261 void *fifo_priv; 262 263 /* Execution engine contexts */ 264 void *engctx[NVOBJ_ENGINE_NR]; 265 266 /* NV50 VM */ 267 struct nouveau_vm *vm; 268 struct nouveau_gpuobj *vm_pd; 269 270 /* Objects */ 271 struct nouveau_gpuobj *ramin; /* Private instmem */ 272 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 273 struct nouveau_ramht *ramht; /* Hash table */ 274 275 /* GPU object info for stuff used in-kernel (mm_enabled) */ 276 uint32_t m2mf_ntfy; 277 uint32_t vram_handle; 278 uint32_t gart_handle; 279 bool accel_done; 280 281 /* Push buffer state (only for drm's channel on !mm_enabled) */ 282 struct { 283 int max; 284 int free; 285 int cur; 286 int put; 287 /* access via pushbuf_bo */ 288 289 int ib_base; 290 int ib_max; 291 int ib_free; 292 int ib_put; 293 } dma; 294 295 uint32_t sw_subchannel[8]; 296 297 struct nouveau_vma dispc_vma[4]; 298 struct { 299 struct nouveau_gpuobj *vblsem; 300 uint32_t vblsem_head; 301 uint32_t vblsem_offset; 302 uint32_t vblsem_rval; 303 struct list_head vbl_wait; 304 struct list_head flip; 305 } nvsw; 306 307 struct { 308 bool active; 309 char name[32]; 310 struct drm_info_list info; 311 } debugfs; 312}; 313 314struct nouveau_exec_engine { 315 void (*destroy)(struct drm_device *, int engine); 316 int (*init)(struct drm_device *, int engine); 317 int (*fini)(struct drm_device *, int engine, bool suspend); 318 int (*context_new)(struct nouveau_channel *, int engine); 319 void (*context_del)(struct nouveau_channel *, int engine); 320 int (*object_new)(struct nouveau_channel *, int engine, 321 u32 handle, u16 class); 322 void (*set_tile_region)(struct drm_device *dev, int i); 323 void (*tlb_flush)(struct drm_device *, int engine); 324}; 325 326struct nouveau_instmem_engine { 327 void *priv; 328 329 int (*init)(struct drm_device *dev); 330 void (*takedown)(struct drm_device *dev); 331 int (*suspend)(struct drm_device *dev); 332 void (*resume)(struct drm_device *dev); 333 334 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 335 u32 size, u32 align); 336 void (*put)(struct nouveau_gpuobj *); 337 int (*map)(struct nouveau_gpuobj *); 338 void (*unmap)(struct nouveau_gpuobj *); 339 340 void (*flush)(struct drm_device *); 341}; 342 343struct nouveau_mc_engine { 344 int (*init)(struct drm_device *dev); 345 void (*takedown)(struct drm_device *dev); 346}; 347 348struct nouveau_timer_engine { 349 int (*init)(struct drm_device *dev); 350 void (*takedown)(struct drm_device *dev); 351 uint64_t (*read)(struct drm_device *dev); 352}; 353 354struct nouveau_fb_engine { 355 int num_tiles; 356 struct drm_mm tag_heap; 357 void *priv; 358 359 int (*init)(struct drm_device *dev); 360 void (*takedown)(struct drm_device *dev); 361 362 void (*init_tile_region)(struct drm_device *dev, int i, 363 uint32_t addr, uint32_t size, 364 uint32_t pitch, uint32_t flags); 365 void (*set_tile_region)(struct drm_device *dev, int i); 366 void (*free_tile_region)(struct drm_device *dev, int i); 367}; 368 369struct nouveau_fifo_engine { 370 void *priv; 371 int channels; 372 373 struct nouveau_gpuobj *playlist[2]; 374 int cur_playlist; 375 376 int (*init)(struct drm_device *); 377 void (*takedown)(struct drm_device *); 378 379 void (*disable)(struct drm_device *); 380 void (*enable)(struct drm_device *); 381 bool (*reassign)(struct drm_device *, bool enable); 382 bool (*cache_pull)(struct drm_device *dev, bool enable); 383 384 int (*channel_id)(struct drm_device *); 385 386 int (*create_context)(struct nouveau_channel *); 387 void (*destroy_context)(struct nouveau_channel *); 388 int (*load_context)(struct nouveau_channel *); 389 int (*unload_context)(struct drm_device *); 390 void (*tlb_flush)(struct drm_device *dev); 391}; 392 393struct nouveau_display_engine { 394 void *priv; 395 int (*early_init)(struct drm_device *); 396 void (*late_takedown)(struct drm_device *); 397 int (*create)(struct drm_device *); 398 void (*destroy)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*fini)(struct drm_device *); 401 402 struct drm_property *dithering_mode; 403 struct drm_property *dithering_depth; 404 struct drm_property *underscan_property; 405 struct drm_property *underscan_hborder_property; 406 struct drm_property *underscan_vborder_property; 407 /* not really hue and saturation: */ 408 struct drm_property *vibrant_hue_property; 409 struct drm_property *color_vibrance_property; 410}; 411 412struct nouveau_gpio_engine { 413 spinlock_t lock; 414 struct list_head isr; 415 int (*init)(struct drm_device *); 416 void (*fini)(struct drm_device *); 417 int (*drive)(struct drm_device *, int line, int dir, int out); 418 int (*sense)(struct drm_device *, int line); 419 void (*irq_enable)(struct drm_device *, int line, bool); 420}; 421 422struct nouveau_pm_voltage_level { 423 u32 voltage; /* microvolts */ 424 u8 vid; 425}; 426 427struct nouveau_pm_voltage { 428 bool supported; 429 u8 version; 430 u8 vid_mask; 431 432 struct nouveau_pm_voltage_level *level; 433 int nr_level; 434}; 435 436/* Exclusive upper limits */ 437#define NV_MEM_CL_DDR2_MAX 8 438#define NV_MEM_WR_DDR2_MAX 9 439#define NV_MEM_CL_DDR3_MAX 17 440#define NV_MEM_WR_DDR3_MAX 17 441#define NV_MEM_CL_GDDR3_MAX 16 442#define NV_MEM_WR_GDDR3_MAX 18 443#define NV_MEM_CL_GDDR5_MAX 21 444#define NV_MEM_WR_GDDR5_MAX 20 445 446struct nouveau_pm_memtiming { 447 int id; 448 449 u32 reg[9]; 450 u32 mr[4]; 451 452 u8 tCWL; 453 454 u8 odt; 455 u8 drive_strength; 456}; 457 458struct nouveau_pm_tbl_header { 459 u8 version; 460 u8 header_len; 461 u8 entry_cnt; 462 u8 entry_len; 463}; 464 465struct nouveau_pm_tbl_entry { 466 u8 tWR; 467 u8 tWTR; 468 u8 tCL; 469 u8 tRC; 470 u8 empty_4; 471 u8 tRFC; /* Byte 5 */ 472 u8 empty_6; 473 u8 tRAS; /* Byte 7 */ 474 u8 empty_8; 475 u8 tRP; /* Byte 9 */ 476 u8 tRCDRD; 477 u8 tRCDWR; 478 u8 tRRD; 479 u8 tUNK_13; 480 u8 RAM_FT1; /* 14, a bitmask of random RAM features */ 481 u8 empty_15; 482 u8 tUNK_16; 483 u8 empty_17; 484 u8 tUNK_18; 485 u8 tCWL; 486 u8 tUNK_20, tUNK_21; 487}; 488 489struct nouveau_pm_profile; 490struct nouveau_pm_profile_func { 491 void (*destroy)(struct nouveau_pm_profile *); 492 void (*init)(struct nouveau_pm_profile *); 493 void (*fini)(struct nouveau_pm_profile *); 494 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); 495}; 496 497struct nouveau_pm_profile { 498 const struct nouveau_pm_profile_func *func; 499 struct list_head head; 500 char name[8]; 501}; 502 503#define NOUVEAU_PM_MAX_LEVEL 8 504struct nouveau_pm_level { 505 struct nouveau_pm_profile profile; 506 struct device_attribute dev_attr; 507 char name[32]; 508 int id; 509 510 struct nouveau_pm_memtiming timing; 511 u32 memory; 512 u16 memscript; 513 514 u32 core; 515 u32 shader; 516 u32 rop; 517 u32 copy; 518 u32 daemon; 519 u32 vdec; 520 u32 dom6; 521 u32 unka0; /* nva3:nvc0 */ 522 u32 hub01; /* nvc0- */ 523 u32 hub06; /* nvc0- */ 524 u32 hub07; /* nvc0- */ 525 526 u32 volt_min; /* microvolts */ 527 u32 volt_max; 528 u8 fanspeed; 529}; 530 531struct nouveau_pm_temp_sensor_constants { 532 u16 offset_constant; 533 s16 offset_mult; 534 s16 offset_div; 535 s16 slope_mult; 536 s16 slope_div; 537}; 538 539struct nouveau_pm_threshold_temp { 540 s16 critical; 541 s16 down_clock; 542 s16 fan_boost; 543}; 544 545struct nouveau_pm_fan { 546 u32 percent; 547 u32 min_duty; 548 u32 max_duty; 549 u32 pwm_freq; 550 u32 pwm_divisor; 551}; 552 553struct nouveau_pm_engine { 554 struct nouveau_pm_voltage voltage; 555 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 556 int nr_perflvl; 557 struct nouveau_pm_temp_sensor_constants sensor_constants; 558 struct nouveau_pm_threshold_temp threshold_temp; 559 struct nouveau_pm_fan fan; 560 561 struct nouveau_pm_profile *profile_ac; 562 struct nouveau_pm_profile *profile_dc; 563 struct nouveau_pm_profile *profile; 564 struct list_head profiles; 565 566 struct nouveau_pm_level boot; 567 struct nouveau_pm_level *cur; 568 569 struct device *hwmon; 570 struct notifier_block acpi_nb; 571 572 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 573 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 574 int (*clocks_set)(struct drm_device *, void *); 575 576 int (*voltage_get)(struct drm_device *); 577 int (*voltage_set)(struct drm_device *, int voltage); 578 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 579 int (*pwm_set)(struct drm_device *, int line, u32, u32); 580 int (*temp_get)(struct drm_device *); 581}; 582 583struct nouveau_vram_engine { 584 struct nouveau_mm mm; 585 586 int (*init)(struct drm_device *); 587 void (*takedown)(struct drm_device *dev); 588 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 589 u32 type, struct nouveau_mem **); 590 void (*put)(struct drm_device *, struct nouveau_mem **); 591 592 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 593}; 594 595struct nouveau_engine { 596 struct nouveau_instmem_engine instmem; 597 struct nouveau_mc_engine mc; 598 struct nouveau_timer_engine timer; 599 struct nouveau_fb_engine fb; 600 struct nouveau_fifo_engine fifo; 601 struct nouveau_display_engine display; 602 struct nouveau_gpio_engine gpio; 603 struct nouveau_pm_engine pm; 604 struct nouveau_vram_engine vram; 605}; 606 607struct nouveau_pll_vals { 608 union { 609 struct { 610#ifdef __BIG_ENDIAN 611 uint8_t N1, M1, N2, M2; 612#else 613 uint8_t M1, N1, M2, N2; 614#endif 615 }; 616 struct { 617 uint16_t NM1, NM2; 618 } __attribute__((packed)); 619 }; 620 int log2P; 621 622 int refclk; 623}; 624 625enum nv04_fp_display_regs { 626 FP_DISPLAY_END, 627 FP_TOTAL, 628 FP_CRTC, 629 FP_SYNC_START, 630 FP_SYNC_END, 631 FP_VALID_START, 632 FP_VALID_END 633}; 634 635struct nv04_crtc_reg { 636 unsigned char MiscOutReg; 637 uint8_t CRTC[0xa0]; 638 uint8_t CR58[0x10]; 639 uint8_t Sequencer[5]; 640 uint8_t Graphics[9]; 641 uint8_t Attribute[21]; 642 unsigned char DAC[768]; 643 644 /* PCRTC regs */ 645 uint32_t fb_start; 646 uint32_t crtc_cfg; 647 uint32_t cursor_cfg; 648 uint32_t gpio_ext; 649 uint32_t crtc_830; 650 uint32_t crtc_834; 651 uint32_t crtc_850; 652 uint32_t crtc_eng_ctrl; 653 654 /* PRAMDAC regs */ 655 uint32_t nv10_cursync; 656 struct nouveau_pll_vals pllvals; 657 uint32_t ramdac_gen_ctrl; 658 uint32_t ramdac_630; 659 uint32_t ramdac_634; 660 uint32_t tv_setup; 661 uint32_t tv_vtotal; 662 uint32_t tv_vskew; 663 uint32_t tv_vsync_delay; 664 uint32_t tv_htotal; 665 uint32_t tv_hskew; 666 uint32_t tv_hsync_delay; 667 uint32_t tv_hsync_delay2; 668 uint32_t fp_horiz_regs[7]; 669 uint32_t fp_vert_regs[7]; 670 uint32_t dither; 671 uint32_t fp_control; 672 uint32_t dither_regs[6]; 673 uint32_t fp_debug_0; 674 uint32_t fp_debug_1; 675 uint32_t fp_debug_2; 676 uint32_t fp_margin_color; 677 uint32_t ramdac_8c0; 678 uint32_t ramdac_a20; 679 uint32_t ramdac_a24; 680 uint32_t ramdac_a34; 681 uint32_t ctv_regs[38]; 682}; 683 684struct nv04_output_reg { 685 uint32_t output; 686 int head; 687}; 688 689struct nv04_mode_state { 690 struct nv04_crtc_reg crtc_reg[2]; 691 uint32_t pllsel; 692 uint32_t sel_clk; 693}; 694 695enum nouveau_card_type { 696 NV_04 = 0x04, 697 NV_10 = 0x10, 698 NV_20 = 0x20, 699 NV_30 = 0x30, 700 NV_40 = 0x40, 701 NV_50 = 0x50, 702 NV_C0 = 0xc0, 703 NV_D0 = 0xd0, 704}; 705 706struct drm_nouveau_private { 707 struct drm_device *dev; 708 bool noaccel; 709 710 /* the card type, takes NV_* as values */ 711 enum nouveau_card_type card_type; 712 /* exact chipset, derived from NV_PMC_BOOT_0 */ 713 int chipset; 714 int flags; 715 u32 crystal; 716 717 void __iomem *mmio; 718 719 spinlock_t ramin_lock; 720 void __iomem *ramin; 721 u32 ramin_size; 722 u32 ramin_base; 723 bool ramin_available; 724 struct drm_mm ramin_heap; 725 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 726 struct list_head gpuobj_list; 727 struct list_head classes; 728 729 struct nouveau_bo *vga_ram; 730 731 /* interrupt handling */ 732 void (*irq_handler[32])(struct drm_device *); 733 bool msi_enabled; 734 735 struct list_head vbl_waiting; 736 737 struct { 738 struct drm_global_reference mem_global_ref; 739 struct ttm_bo_global_ref bo_global_ref; 740 struct ttm_bo_device bdev; 741 atomic_t validate_sequence; 742 } ttm; 743 744 struct { 745 spinlock_t lock; 746 struct drm_mm heap; 747 struct nouveau_bo *bo; 748 } fence; 749 750 struct { 751 spinlock_t lock; 752 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 753 } channels; 754 755 struct nouveau_engine engine; 756 struct nouveau_channel *channel; 757 758 /* For PFIFO and PGRAPH. */ 759 spinlock_t context_switch_lock; 760 761 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 762 spinlock_t vm_lock; 763 764 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 765 struct nouveau_ramht *ramht; 766 struct nouveau_gpuobj *ramfc; 767 struct nouveau_gpuobj *ramro; 768 769 uint32_t ramin_rsvd_vram; 770 771 struct { 772 enum { 773 NOUVEAU_GART_NONE = 0, 774 NOUVEAU_GART_AGP, /* AGP */ 775 NOUVEAU_GART_PDMA, /* paged dma object */ 776 NOUVEAU_GART_HW /* on-chip gart/vm */ 777 } type; 778 uint64_t aper_base; 779 uint64_t aper_size; 780 uint64_t aper_free; 781 782 struct ttm_backend_func *func; 783 784 struct { 785 struct page *page; 786 dma_addr_t addr; 787 } dummy; 788 789 struct nouveau_gpuobj *sg_ctxdma; 790 } gart_info; 791 792 /* nv10-nv40 tiling regions */ 793 struct { 794 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 795 spinlock_t lock; 796 } tile; 797 798 /* VRAM/fb configuration */ 799 enum { 800 NV_MEM_TYPE_UNKNOWN = 0, 801 NV_MEM_TYPE_STOLEN, 802 NV_MEM_TYPE_SGRAM, 803 NV_MEM_TYPE_SDRAM, 804 NV_MEM_TYPE_DDR1, 805 NV_MEM_TYPE_DDR2, 806 NV_MEM_TYPE_DDR3, 807 NV_MEM_TYPE_GDDR2, 808 NV_MEM_TYPE_GDDR3, 809 NV_MEM_TYPE_GDDR4, 810 NV_MEM_TYPE_GDDR5 811 } vram_type; 812 uint64_t vram_size; 813 uint64_t vram_sys_base; 814 bool vram_rank_B; 815 816 uint64_t fb_available_size; 817 uint64_t fb_mappable_pages; 818 uint64_t fb_aper_free; 819 int fb_mtrr; 820 821 /* BAR control (NV50-) */ 822 struct nouveau_vm *bar1_vm; 823 struct nouveau_vm *bar3_vm; 824 825 /* G8x/G9x virtual address space */ 826 struct nouveau_vm *chan_vm; 827 828 struct nvbios vbios; 829 u8 *mxms; 830 struct list_head i2c_ports; 831 832 struct nv04_mode_state mode_reg; 833 struct nv04_mode_state saved_reg; 834 uint32_t saved_vga_font[4][16384]; 835 uint32_t crtc_owner; 836 uint32_t dac_users[4]; 837 838 struct backlight_device *backlight; 839 840 struct { 841 struct dentry *channel_root; 842 } debugfs; 843 844 struct nouveau_fbdev *nfbdev; 845 struct apertures_struct *apertures; 846}; 847 848static inline struct drm_nouveau_private * 849nouveau_private(struct drm_device *dev) 850{ 851 return dev->dev_private; 852} 853 854static inline struct drm_nouveau_private * 855nouveau_bdev(struct ttm_bo_device *bd) 856{ 857 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 858} 859 860static inline int 861nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 862{ 863 struct nouveau_bo *prev; 864 865 if (!pnvbo) 866 return -EINVAL; 867 prev = *pnvbo; 868 869 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 870 if (prev) { 871 struct ttm_buffer_object *bo = &prev->bo; 872 873 ttm_bo_unref(&bo); 874 } 875 876 return 0; 877} 878 879/* nouveau_drv.c */ 880extern int nouveau_modeset; 881extern int nouveau_agpmode; 882extern int nouveau_duallink; 883extern int nouveau_uscript_lvds; 884extern int nouveau_uscript_tmds; 885extern int nouveau_vram_pushbuf; 886extern int nouveau_vram_notify; 887extern char *nouveau_vram_type; 888extern int nouveau_fbpercrtc; 889extern int nouveau_tv_disable; 890extern char *nouveau_tv_norm; 891extern int nouveau_reg_debug; 892extern char *nouveau_vbios; 893extern int nouveau_ignorelid; 894extern int nouveau_nofbaccel; 895extern int nouveau_noaccel; 896extern int nouveau_force_post; 897extern int nouveau_override_conntype; 898extern char *nouveau_perflvl; 899extern int nouveau_perflvl_wr; 900extern int nouveau_msi; 901extern int nouveau_ctxfw; 902extern int nouveau_mxmdcb; 903 904extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 905extern int nouveau_pci_resume(struct pci_dev *pdev); 906 907/* nouveau_state.c */ 908extern int nouveau_open(struct drm_device *, struct drm_file *); 909extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 910extern void nouveau_postclose(struct drm_device *, struct drm_file *); 911extern int nouveau_load(struct drm_device *, unsigned long flags); 912extern int nouveau_firstopen(struct drm_device *); 913extern void nouveau_lastclose(struct drm_device *); 914extern int nouveau_unload(struct drm_device *); 915extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 916 struct drm_file *); 917extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 918 struct drm_file *); 919extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 920 uint32_t reg, uint32_t mask, uint32_t val); 921extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 922 uint32_t reg, uint32_t mask, uint32_t val); 923extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 924 bool (*cond)(void *), void *); 925extern bool nouveau_wait_for_idle(struct drm_device *); 926extern int nouveau_card_init(struct drm_device *); 927 928/* nouveau_mem.c */ 929extern int nouveau_mem_vram_init(struct drm_device *); 930extern void nouveau_mem_vram_fini(struct drm_device *); 931extern int nouveau_mem_gart_init(struct drm_device *); 932extern void nouveau_mem_gart_fini(struct drm_device *); 933extern int nouveau_mem_init_agp(struct drm_device *); 934extern int nouveau_mem_reset_agp(struct drm_device *); 935extern void nouveau_mem_close(struct drm_device *); 936extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 937extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, 938 struct nouveau_pm_memtiming *); 939extern void nouveau_mem_timing_read(struct drm_device *, 940 struct nouveau_pm_memtiming *); 941extern int nouveau_mem_vbios_type(struct drm_device *); 942extern struct nouveau_tile_reg *nv10_mem_set_tiling( 943 struct drm_device *dev, uint32_t addr, uint32_t size, 944 uint32_t pitch, uint32_t flags); 945extern void nv10_mem_put_tile_region(struct drm_device *dev, 946 struct nouveau_tile_reg *tile, 947 struct nouveau_fence *fence); 948extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 949extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 950 951/* nouveau_notifier.c */ 952extern int nouveau_notifier_init_channel(struct nouveau_channel *); 953extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 954extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 955 int cout, uint32_t start, uint32_t end, 956 uint32_t *offset); 957extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 958extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 959 struct drm_file *); 960extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 961 struct drm_file *); 962 963/* nouveau_channel.c */ 964extern struct drm_ioctl_desc nouveau_ioctls[]; 965extern int nouveau_max_ioctl; 966extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 967extern int nouveau_channel_alloc(struct drm_device *dev, 968 struct nouveau_channel **chan, 969 struct drm_file *file_priv, 970 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 971extern struct nouveau_channel * 972nouveau_channel_get_unlocked(struct nouveau_channel *); 973extern struct nouveau_channel * 974nouveau_channel_get(struct drm_file *, int id); 975extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 976extern void nouveau_channel_put(struct nouveau_channel **); 977extern void nouveau_channel_ref(struct nouveau_channel *chan, 978 struct nouveau_channel **pchan); 979extern void nouveau_channel_idle(struct nouveau_channel *chan); 980 981/* nouveau_object.c */ 982#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 983 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 984 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 985} while (0) 986 987#define NVOBJ_ENGINE_DEL(d, e) do { \ 988 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 989 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 990} while (0) 991 992#define NVOBJ_CLASS(d, c, e) do { \ 993 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 994 if (ret) \ 995 return ret; \ 996} while (0) 997 998#define NVOBJ_MTHD(d, c, m, e) do { \ 999 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 1000 if (ret) \ 1001 return ret; \ 1002} while (0) 1003 1004extern int nouveau_gpuobj_early_init(struct drm_device *); 1005extern int nouveau_gpuobj_init(struct drm_device *); 1006extern void nouveau_gpuobj_takedown(struct drm_device *); 1007extern int nouveau_gpuobj_suspend(struct drm_device *dev); 1008extern void nouveau_gpuobj_resume(struct drm_device *dev); 1009extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 1010extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 1011 int (*exec)(struct nouveau_channel *, 1012 u32 class, u32 mthd, u32 data)); 1013extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 1014extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 1015extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 1016 uint32_t vram_h, uint32_t tt_h); 1017extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 1018extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 1019 uint32_t size, int align, uint32_t flags, 1020 struct nouveau_gpuobj **); 1021extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 1022 struct nouveau_gpuobj **); 1023extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 1024 u32 size, u32 flags, 1025 struct nouveau_gpuobj **); 1026extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 1027 uint64_t offset, uint64_t size, int access, 1028 int target, struct nouveau_gpuobj **); 1029extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1030extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1031 u64 size, int target, int access, u32 type, 1032 u32 comp, struct nouveau_gpuobj **pobj); 1033extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1034 int class, u64 base, u64 size, int target, 1035 int access, u32 type, u32 comp); 1036extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1037 struct drm_file *); 1038extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1039 struct drm_file *); 1040 1041/* nouveau_irq.c */ 1042extern int nouveau_irq_init(struct drm_device *); 1043extern void nouveau_irq_fini(struct drm_device *); 1044extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1045extern void nouveau_irq_register(struct drm_device *, int status_bit, 1046 void (*)(struct drm_device *)); 1047extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1048extern void nouveau_irq_preinstall(struct drm_device *); 1049extern int nouveau_irq_postinstall(struct drm_device *); 1050extern void nouveau_irq_uninstall(struct drm_device *); 1051 1052/* nouveau_sgdma.c */ 1053extern int nouveau_sgdma_init(struct drm_device *); 1054extern void nouveau_sgdma_takedown(struct drm_device *); 1055extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1056 uint32_t offset); 1057extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1058 unsigned long size, 1059 uint32_t page_flags, 1060 struct page *dummy_read_page); 1061 1062/* nouveau_debugfs.c */ 1063#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1064extern int nouveau_debugfs_init(struct drm_minor *); 1065extern void nouveau_debugfs_takedown(struct drm_minor *); 1066extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1067extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1068#else 1069static inline int 1070nouveau_debugfs_init(struct drm_minor *minor) 1071{ 1072 return 0; 1073} 1074 1075static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1076{ 1077} 1078 1079static inline int 1080nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1081{ 1082 return 0; 1083} 1084 1085static inline void 1086nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1087{ 1088} 1089#endif 1090 1091/* nouveau_dma.c */ 1092extern void nouveau_dma_init(struct nouveau_channel *); 1093extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1094 1095/* nouveau_acpi.c */ 1096#define ROM_BIOS_PAGE 4096 1097#if defined(CONFIG_ACPI) 1098void nouveau_register_dsm_handler(void); 1099void nouveau_unregister_dsm_handler(void); 1100void nouveau_switcheroo_optimus_dsm(void); 1101int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1102bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1103int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1104#else 1105static inline void nouveau_register_dsm_handler(void) {} 1106static inline void nouveau_unregister_dsm_handler(void) {} 1107static inline void nouveau_switcheroo_optimus_dsm(void) {} 1108static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1109static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1110static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1111#endif 1112 1113/* nouveau_backlight.c */ 1114#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1115extern int nouveau_backlight_init(struct drm_device *); 1116extern void nouveau_backlight_exit(struct drm_device *); 1117#else 1118static inline int nouveau_backlight_init(struct drm_device *dev) 1119{ 1120 return 0; 1121} 1122 1123static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1124#endif 1125 1126/* nouveau_bios.c */ 1127extern int nouveau_bios_init(struct drm_device *); 1128extern void nouveau_bios_takedown(struct drm_device *dev); 1129extern int nouveau_run_vbios_init(struct drm_device *); 1130extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1131 struct dcb_entry *, int crtc); 1132extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1133extern struct dcb_connector_table_entry * 1134nouveau_bios_connector_entry(struct drm_device *, int index); 1135extern u32 get_pll_register(struct drm_device *, enum pll_types); 1136extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1137 struct pll_lims *); 1138extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1139 struct dcb_entry *, int crtc); 1140extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1141extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1142extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1143 bool *dl, bool *if_is_24bit); 1144extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1145 int head, int pxclk); 1146extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1147 enum LVDS_script, int pxclk); 1148bool bios_encoder_match(struct dcb_entry *, u32 hash); 1149 1150/* nouveau_mxm.c */ 1151int nouveau_mxm_init(struct drm_device *dev); 1152void nouveau_mxm_fini(struct drm_device *dev); 1153 1154/* nouveau_ttm.c */ 1155int nouveau_ttm_global_init(struct drm_nouveau_private *); 1156void nouveau_ttm_global_release(struct drm_nouveau_private *); 1157int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1158 1159/* nouveau_hdmi.c */ 1160void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1161 1162/* nv04_fb.c */ 1163extern int nv04_fb_vram_init(struct drm_device *); 1164extern int nv04_fb_init(struct drm_device *); 1165extern void nv04_fb_takedown(struct drm_device *); 1166 1167/* nv10_fb.c */ 1168extern int nv10_fb_vram_init(struct drm_device *dev); 1169extern int nv1a_fb_vram_init(struct drm_device *dev); 1170extern int nv10_fb_init(struct drm_device *); 1171extern void nv10_fb_takedown(struct drm_device *); 1172extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1173 uint32_t addr, uint32_t size, 1174 uint32_t pitch, uint32_t flags); 1175extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1176extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1177 1178/* nv20_fb.c */ 1179extern int nv20_fb_vram_init(struct drm_device *dev); 1180extern int nv20_fb_init(struct drm_device *); 1181extern void nv20_fb_takedown(struct drm_device *); 1182extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1183 uint32_t addr, uint32_t size, 1184 uint32_t pitch, uint32_t flags); 1185extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1186extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1187 1188/* nv30_fb.c */ 1189extern int nv30_fb_init(struct drm_device *); 1190extern void nv30_fb_takedown(struct drm_device *); 1191extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1192 uint32_t addr, uint32_t size, 1193 uint32_t pitch, uint32_t flags); 1194extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1195 1196/* nv40_fb.c */ 1197extern int nv40_fb_vram_init(struct drm_device *dev); 1198extern int nv40_fb_init(struct drm_device *); 1199extern void nv40_fb_takedown(struct drm_device *); 1200extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1201 1202/* nv50_fb.c */ 1203extern int nv50_fb_init(struct drm_device *); 1204extern void nv50_fb_takedown(struct drm_device *); 1205extern void nv50_fb_vm_trap(struct drm_device *, int display); 1206 1207/* nvc0_fb.c */ 1208extern int nvc0_fb_init(struct drm_device *); 1209extern void nvc0_fb_takedown(struct drm_device *); 1210 1211/* nv04_fifo.c */ 1212extern int nv04_fifo_init(struct drm_device *); 1213extern void nv04_fifo_fini(struct drm_device *); 1214extern void nv04_fifo_disable(struct drm_device *); 1215extern void nv04_fifo_enable(struct drm_device *); 1216extern bool nv04_fifo_reassign(struct drm_device *, bool); 1217extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1218extern int nv04_fifo_channel_id(struct drm_device *); 1219extern int nv04_fifo_create_context(struct nouveau_channel *); 1220extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1221extern int nv04_fifo_load_context(struct nouveau_channel *); 1222extern int nv04_fifo_unload_context(struct drm_device *); 1223extern void nv04_fifo_isr(struct drm_device *); 1224 1225/* nv10_fifo.c */ 1226extern int nv10_fifo_init(struct drm_device *); 1227extern int nv10_fifo_channel_id(struct drm_device *); 1228extern int nv10_fifo_create_context(struct nouveau_channel *); 1229extern int nv10_fifo_load_context(struct nouveau_channel *); 1230extern int nv10_fifo_unload_context(struct drm_device *); 1231 1232/* nv40_fifo.c */ 1233extern int nv40_fifo_init(struct drm_device *); 1234extern int nv40_fifo_create_context(struct nouveau_channel *); 1235extern int nv40_fifo_load_context(struct nouveau_channel *); 1236extern int nv40_fifo_unload_context(struct drm_device *); 1237 1238/* nv50_fifo.c */ 1239extern int nv50_fifo_init(struct drm_device *); 1240extern void nv50_fifo_takedown(struct drm_device *); 1241extern int nv50_fifo_channel_id(struct drm_device *); 1242extern int nv50_fifo_create_context(struct nouveau_channel *); 1243extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1244extern int nv50_fifo_load_context(struct nouveau_channel *); 1245extern int nv50_fifo_unload_context(struct drm_device *); 1246extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1247 1248/* nvc0_fifo.c */ 1249extern int nvc0_fifo_init(struct drm_device *); 1250extern void nvc0_fifo_takedown(struct drm_device *); 1251extern void nvc0_fifo_disable(struct drm_device *); 1252extern void nvc0_fifo_enable(struct drm_device *); 1253extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1254extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1255extern int nvc0_fifo_channel_id(struct drm_device *); 1256extern int nvc0_fifo_create_context(struct nouveau_channel *); 1257extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1258extern int nvc0_fifo_load_context(struct nouveau_channel *); 1259extern int nvc0_fifo_unload_context(struct drm_device *); 1260 1261/* nv04_graph.c */ 1262extern int nv04_graph_create(struct drm_device *); 1263extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1264extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1265 u32 class, u32 mthd, u32 data); 1266extern struct nouveau_bitfield nv04_graph_nsource[]; 1267 1268/* nv10_graph.c */ 1269extern int nv10_graph_create(struct drm_device *); 1270extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1271extern struct nouveau_bitfield nv10_graph_intr[]; 1272extern struct nouveau_bitfield nv10_graph_nstatus[]; 1273 1274/* nv20_graph.c */ 1275extern int nv20_graph_create(struct drm_device *); 1276 1277/* nv40_graph.c */ 1278extern int nv40_graph_create(struct drm_device *); 1279extern void nv40_grctx_init(struct nouveau_grctx *); 1280 1281/* nv50_graph.c */ 1282extern int nv50_graph_create(struct drm_device *); 1283extern int nv50_grctx_init(struct nouveau_grctx *); 1284extern struct nouveau_enum nv50_data_error_names[]; 1285extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1286 1287/* nvc0_graph.c */ 1288extern int nvc0_graph_create(struct drm_device *); 1289extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1290 1291/* nv84_crypt.c */ 1292extern int nv84_crypt_create(struct drm_device *); 1293 1294/* nv98_crypt.c */ 1295extern int nv98_crypt_create(struct drm_device *dev); 1296 1297/* nva3_copy.c */ 1298extern int nva3_copy_create(struct drm_device *dev); 1299 1300/* nvc0_copy.c */ 1301extern int nvc0_copy_create(struct drm_device *dev, int engine); 1302 1303/* nv31_mpeg.c */ 1304extern int nv31_mpeg_create(struct drm_device *dev); 1305 1306/* nv50_mpeg.c */ 1307extern int nv50_mpeg_create(struct drm_device *dev); 1308 1309/* nv84_bsp.c */ 1310/* nv98_bsp.c */ 1311extern int nv84_bsp_create(struct drm_device *dev); 1312 1313/* nv84_vp.c */ 1314/* nv98_vp.c */ 1315extern int nv84_vp_create(struct drm_device *dev); 1316 1317/* nv98_ppp.c */ 1318extern int nv98_ppp_create(struct drm_device *dev); 1319 1320/* nv04_instmem.c */ 1321extern int nv04_instmem_init(struct drm_device *); 1322extern void nv04_instmem_takedown(struct drm_device *); 1323extern int nv04_instmem_suspend(struct drm_device *); 1324extern void nv04_instmem_resume(struct drm_device *); 1325extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1326 u32 size, u32 align); 1327extern void nv04_instmem_put(struct nouveau_gpuobj *); 1328extern int nv04_instmem_map(struct nouveau_gpuobj *); 1329extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1330extern void nv04_instmem_flush(struct drm_device *); 1331 1332/* nv50_instmem.c */ 1333extern int nv50_instmem_init(struct drm_device *); 1334extern void nv50_instmem_takedown(struct drm_device *); 1335extern int nv50_instmem_suspend(struct drm_device *); 1336extern void nv50_instmem_resume(struct drm_device *); 1337extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1338 u32 size, u32 align); 1339extern void nv50_instmem_put(struct nouveau_gpuobj *); 1340extern int nv50_instmem_map(struct nouveau_gpuobj *); 1341extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1342extern void nv50_instmem_flush(struct drm_device *); 1343extern void nv84_instmem_flush(struct drm_device *); 1344 1345/* nvc0_instmem.c */ 1346extern int nvc0_instmem_init(struct drm_device *); 1347extern void nvc0_instmem_takedown(struct drm_device *); 1348extern int nvc0_instmem_suspend(struct drm_device *); 1349extern void nvc0_instmem_resume(struct drm_device *); 1350 1351/* nv04_mc.c */ 1352extern int nv04_mc_init(struct drm_device *); 1353extern void nv04_mc_takedown(struct drm_device *); 1354 1355/* nv40_mc.c */ 1356extern int nv40_mc_init(struct drm_device *); 1357extern void nv40_mc_takedown(struct drm_device *); 1358 1359/* nv50_mc.c */ 1360extern int nv50_mc_init(struct drm_device *); 1361extern void nv50_mc_takedown(struct drm_device *); 1362 1363/* nv04_timer.c */ 1364extern int nv04_timer_init(struct drm_device *); 1365extern uint64_t nv04_timer_read(struct drm_device *); 1366extern void nv04_timer_takedown(struct drm_device *); 1367 1368extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1369 unsigned long arg); 1370 1371/* nv04_dac.c */ 1372extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1373extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1374extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1375extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1376extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1377 1378/* nv04_dfp.c */ 1379extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1380extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1381extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1382 int head, bool dl); 1383extern void nv04_dfp_disable(struct drm_device *dev, int head); 1384extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1385 1386/* nv04_tv.c */ 1387extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1388extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1389 1390/* nv17_tv.c */ 1391extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1392 1393/* nv04_display.c */ 1394extern int nv04_display_early_init(struct drm_device *); 1395extern void nv04_display_late_takedown(struct drm_device *); 1396extern int nv04_display_create(struct drm_device *); 1397extern void nv04_display_destroy(struct drm_device *); 1398extern int nv04_display_init(struct drm_device *); 1399extern void nv04_display_fini(struct drm_device *); 1400 1401/* nvd0_display.c */ 1402extern int nvd0_display_create(struct drm_device *); 1403extern void nvd0_display_destroy(struct drm_device *); 1404extern int nvd0_display_init(struct drm_device *); 1405extern void nvd0_display_fini(struct drm_device *); 1406struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1407void nvd0_display_flip_stop(struct drm_crtc *); 1408int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1409 struct nouveau_channel *, u32 swap_interval); 1410 1411/* nv04_crtc.c */ 1412extern int nv04_crtc_create(struct drm_device *, int index); 1413 1414/* nouveau_bo.c */ 1415extern struct ttm_bo_driver nouveau_bo_driver; 1416extern int nouveau_bo_new(struct drm_device *, int size, int align, 1417 uint32_t flags, uint32_t tile_mode, 1418 uint32_t tile_flags, struct nouveau_bo **); 1419extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1420extern int nouveau_bo_unpin(struct nouveau_bo *); 1421extern int nouveau_bo_map(struct nouveau_bo *); 1422extern void nouveau_bo_unmap(struct nouveau_bo *); 1423extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1424 uint32_t busy); 1425extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1426extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1427extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1428extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1429extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1430extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1431 bool no_wait_reserve, bool no_wait_gpu); 1432 1433extern struct nouveau_vma * 1434nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1435extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1436 struct nouveau_vma *); 1437extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1438 1439/* nouveau_fence.c */ 1440struct nouveau_fence; 1441extern int nouveau_fence_init(struct drm_device *); 1442extern void nouveau_fence_fini(struct drm_device *); 1443extern int nouveau_fence_channel_init(struct nouveau_channel *); 1444extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1445extern void nouveau_fence_update(struct nouveau_channel *); 1446extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1447 bool emit); 1448extern int nouveau_fence_emit(struct nouveau_fence *); 1449extern void nouveau_fence_work(struct nouveau_fence *fence, 1450 void (*work)(void *priv, bool signalled), 1451 void *priv); 1452struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1453 1454extern bool __nouveau_fence_signalled(void *obj, void *arg); 1455extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1456extern int __nouveau_fence_flush(void *obj, void *arg); 1457extern void __nouveau_fence_unref(void **obj); 1458extern void *__nouveau_fence_ref(void *obj); 1459 1460static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1461{ 1462 return __nouveau_fence_signalled(obj, NULL); 1463} 1464static inline int 1465nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1466{ 1467 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1468} 1469extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1470static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1471{ 1472 return __nouveau_fence_flush(obj, NULL); 1473} 1474static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1475{ 1476 __nouveau_fence_unref((void **)obj); 1477} 1478static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1479{ 1480 return __nouveau_fence_ref(obj); 1481} 1482 1483/* nouveau_gem.c */ 1484extern int nouveau_gem_new(struct drm_device *, int size, int align, 1485 uint32_t domain, uint32_t tile_mode, 1486 uint32_t tile_flags, struct nouveau_bo **); 1487extern int nouveau_gem_object_new(struct drm_gem_object *); 1488extern void nouveau_gem_object_del(struct drm_gem_object *); 1489extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1490extern void nouveau_gem_object_close(struct drm_gem_object *, 1491 struct drm_file *); 1492extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1493 struct drm_file *); 1494extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1495 struct drm_file *); 1496extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1497 struct drm_file *); 1498extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1499 struct drm_file *); 1500extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1501 struct drm_file *); 1502 1503/* nouveau_display.c */ 1504int nouveau_display_create(struct drm_device *dev); 1505void nouveau_display_destroy(struct drm_device *dev); 1506int nouveau_display_init(struct drm_device *dev); 1507void nouveau_display_fini(struct drm_device *dev); 1508int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1509void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1510int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1511 struct drm_pending_vblank_event *event); 1512int nouveau_finish_page_flip(struct nouveau_channel *, 1513 struct nouveau_page_flip_state *); 1514int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1515 struct drm_mode_create_dumb *args); 1516int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1517 uint32_t handle, uint64_t *offset); 1518int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1519 uint32_t handle); 1520 1521/* nv10_gpio.c */ 1522int nv10_gpio_init(struct drm_device *dev); 1523void nv10_gpio_fini(struct drm_device *dev); 1524int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1525int nv10_gpio_sense(struct drm_device *dev, int line); 1526void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1527 1528/* nv50_gpio.c */ 1529int nv50_gpio_init(struct drm_device *dev); 1530void nv50_gpio_fini(struct drm_device *dev); 1531int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1532int nv50_gpio_sense(struct drm_device *dev, int line); 1533void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1534int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1535int nvd0_gpio_sense(struct drm_device *dev, int line); 1536 1537/* nv50_calc.c */ 1538int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1539 int *N1, int *M1, int *N2, int *M2, int *P); 1540int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1541 int clk, int *N, int *fN, int *M, int *P); 1542 1543#ifndef ioread32_native 1544#ifdef __BIG_ENDIAN 1545#define ioread16_native ioread16be 1546#define iowrite16_native iowrite16be 1547#define ioread32_native ioread32be 1548#define iowrite32_native iowrite32be 1549#else /* def __BIG_ENDIAN */ 1550#define ioread16_native ioread16 1551#define iowrite16_native iowrite16 1552#define ioread32_native ioread32 1553#define iowrite32_native iowrite32 1554#endif /* def __BIG_ENDIAN else */ 1555#endif /* !ioread32_native */ 1556 1557/* channel control reg access */ 1558static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1559{ 1560 return ioread32_native(chan->user + reg); 1561} 1562 1563static inline void nvchan_wr32(struct nouveau_channel *chan, 1564 unsigned reg, u32 val) 1565{ 1566 iowrite32_native(val, chan->user + reg); 1567} 1568 1569/* register access */ 1570static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1571{ 1572 struct drm_nouveau_private *dev_priv = dev->dev_private; 1573 return ioread32_native(dev_priv->mmio + reg); 1574} 1575 1576static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1577{ 1578 struct drm_nouveau_private *dev_priv = dev->dev_private; 1579 iowrite32_native(val, dev_priv->mmio + reg); 1580} 1581 1582static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1583{ 1584 u32 tmp = nv_rd32(dev, reg); 1585 nv_wr32(dev, reg, (tmp & ~mask) | val); 1586 return tmp; 1587} 1588 1589static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1590{ 1591 struct drm_nouveau_private *dev_priv = dev->dev_private; 1592 return ioread8(dev_priv->mmio + reg); 1593} 1594 1595static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1596{ 1597 struct drm_nouveau_private *dev_priv = dev->dev_private; 1598 iowrite8(val, dev_priv->mmio + reg); 1599} 1600 1601#define nv_wait(dev, reg, mask, val) \ 1602 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1603#define nv_wait_ne(dev, reg, mask, val) \ 1604 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1605#define nv_wait_cb(dev, func, data) \ 1606 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1607 1608/* PRAMIN access */ 1609static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1610{ 1611 struct drm_nouveau_private *dev_priv = dev->dev_private; 1612 return ioread32_native(dev_priv->ramin + offset); 1613} 1614 1615static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1616{ 1617 struct drm_nouveau_private *dev_priv = dev->dev_private; 1618 iowrite32_native(val, dev_priv->ramin + offset); 1619} 1620 1621/* object access */ 1622extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1623extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1624 1625/* 1626 * Logging 1627 * Argument d is (struct drm_device *). 1628 */ 1629#define NV_PRINTK(level, d, fmt, arg...) \ 1630 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1631 pci_name(d->pdev), ##arg) 1632#ifndef NV_DEBUG_NOTRACE 1633#define NV_DEBUG(d, fmt, arg...) do { \ 1634 if (drm_debug & DRM_UT_DRIVER) { \ 1635 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1636 __LINE__, ##arg); \ 1637 } \ 1638} while (0) 1639#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1640 if (drm_debug & DRM_UT_KMS) { \ 1641 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1642 __LINE__, ##arg); \ 1643 } \ 1644} while (0) 1645#else 1646#define NV_DEBUG(d, fmt, arg...) do { \ 1647 if (drm_debug & DRM_UT_DRIVER) \ 1648 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1649} while (0) 1650#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1651 if (drm_debug & DRM_UT_KMS) \ 1652 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1653} while (0) 1654#endif 1655#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1656#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1657#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1658#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1659#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1660#define NV_WARNONCE(d, fmt, arg...) do { \ 1661 static int _warned = 0; \ 1662 if (!_warned) { \ 1663 NV_WARN(d, fmt, ##arg); \ 1664 _warned = 1; \ 1665 } \ 1666} while(0) 1667 1668/* nouveau_reg_debug bitmask */ 1669enum { 1670 NOUVEAU_REG_DEBUG_MC = 0x1, 1671 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1672 NOUVEAU_REG_DEBUG_FB = 0x4, 1673 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1674 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1675 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1676 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1677 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1678 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1679 NOUVEAU_REG_DEBUG_EVO = 0x200, 1680 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1681}; 1682 1683#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1684 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1685 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1686} while (0) 1687 1688static inline bool 1689nv_two_heads(struct drm_device *dev) 1690{ 1691 struct drm_nouveau_private *dev_priv = dev->dev_private; 1692 const int impl = dev->pci_device & 0x0ff0; 1693 1694 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1695 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1696 return true; 1697 1698 return false; 1699} 1700 1701static inline bool 1702nv_gf4_disp_arch(struct drm_device *dev) 1703{ 1704 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1705} 1706 1707static inline bool 1708nv_two_reg_pll(struct drm_device *dev) 1709{ 1710 struct drm_nouveau_private *dev_priv = dev->dev_private; 1711 const int impl = dev->pci_device & 0x0ff0; 1712 1713 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1714 return true; 1715 return false; 1716} 1717 1718static inline bool 1719nv_match_device(struct drm_device *dev, unsigned device, 1720 unsigned sub_vendor, unsigned sub_device) 1721{ 1722 return dev->pdev->device == device && 1723 dev->pdev->subsystem_vendor == sub_vendor && 1724 dev->pdev->subsystem_device == sub_device; 1725} 1726 1727static inline void * 1728nv_engine(struct drm_device *dev, int engine) 1729{ 1730 struct drm_nouveau_private *dev_priv = dev->dev_private; 1731 return (void *)dev_priv->eng[engine]; 1732} 1733 1734/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1735 * helpful to determine a number of other hardware features 1736 */ 1737static inline int 1738nv44_graph_class(struct drm_device *dev) 1739{ 1740 struct drm_nouveau_private *dev_priv = dev->dev_private; 1741 1742 if ((dev_priv->chipset & 0xf0) == 0x60) 1743 return 1; 1744 1745 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1746} 1747 1748/* memory type/access flags, do not match hardware values */ 1749#define NV_MEM_ACCESS_RO 1 1750#define NV_MEM_ACCESS_WO 2 1751#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1752#define NV_MEM_ACCESS_SYS 4 1753#define NV_MEM_ACCESS_VM 8 1754#define NV_MEM_ACCESS_NOSNOOP 16 1755 1756#define NV_MEM_TARGET_VRAM 0 1757#define NV_MEM_TARGET_PCI 1 1758#define NV_MEM_TARGET_PCI_NOSNOOP 2 1759#define NV_MEM_TARGET_VM 3 1760#define NV_MEM_TARGET_GART 4 1761 1762#define NV_MEM_TYPE_VM 0x7f 1763#define NV_MEM_COMP_VM 0x03 1764 1765/* FIFO methods */ 1766#define NV01_SUBCHAN_OBJECT 0x00000000 1767#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 1768#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 1769#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 1770#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c 1771#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 1772#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 1773#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 1774#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020 1775#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 1776#define NV10_SUBCHAN_REF_CNT 0x00000050 1777#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054 1778#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 1779#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 1780#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 1781#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c 1782#define NV40_SUBCHAN_YIELD 0x00000080 1783 1784/* NV_SW object class */ 1785#define NV_SW 0x0000506e 1786#define NV_SW_DMA_VBLSEM 0x0000018c 1787#define NV_SW_VBLSEM_OFFSET 0x00000400 1788#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1789#define NV_SW_VBLSEM_RELEASE 0x00000408 1790#define NV_SW_PAGE_FLIP 0x00000500 1791 1792#endif /* __NOUVEAU_DRV_H__ */ 1793