nouveau_drv.h revision 2730723bbc4a8b289fa536fc3555e15947da09c1
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR		"Stephane Marchesin"
29#define DRIVER_EMAIL		"dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME		"nouveau"
32#define DRIVER_DESC		"nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE		"20090420"
34
35#define DRIVER_MAJOR		0
36#define DRIVER_MINOR		0
37#define DRIVER_PATCHLEVEL	16
38
39#define NOUVEAU_FAMILY   0x0000FFFF
40#define NOUVEAU_FLAGS    0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49	struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
57struct nouveau_grctx;
58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
62#define NOUVEAU_MAX_TILE_NR 15
63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK    (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR  (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68struct nouveau_tile_reg {
69	struct nouveau_fence *fence;
70	uint32_t addr;
71	uint32_t size;
72	bool used;
73};
74
75struct nouveau_bo {
76	struct ttm_buffer_object bo;
77	struct ttm_placement placement;
78	u32 placements[3];
79	u32 busy_placements[3];
80	struct ttm_bo_kmap_obj kmap;
81	struct list_head head;
82
83	/* protected by ttm_bo_reserve() */
84	struct drm_file *reserved_by;
85	struct list_head entry;
86	int pbbo_index;
87	bool validate_mapped;
88
89	struct nouveau_channel *channel;
90
91	bool mappable;
92	bool no_vm;
93
94	uint32_t tile_mode;
95	uint32_t tile_flags;
96	struct nouveau_tile_reg *tile;
97
98	struct drm_gem_object *gem;
99	struct drm_file *cpu_filp;
100	int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106	return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112	return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119	bool is_iomem;
120	void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121						&nvbo->kmap, &is_iomem);
122	WARN_ON_ONCE(ioptr && !is_iomem);
123	return ioptr;
124}
125
126enum nouveau_flags {
127	NV_NFORCE   = 0x10000000,
128	NV_NFORCE2  = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW		0
132#define NVOBJ_ENGINE_GR		1
133#define NVOBJ_ENGINE_DISPLAY	2
134#define NVOBJ_ENGINE_INT	0xdeadbeef
135
136#define NVOBJ_FLAG_ZERO_ALLOC		(1 << 1)
137#define NVOBJ_FLAG_ZERO_FREE		(1 << 2)
138struct nouveau_gpuobj {
139	struct drm_device *dev;
140	struct kref refcount;
141	struct list_head list;
142
143	struct drm_mm_node *im_pramin;
144	struct nouveau_bo *im_backing;
145	uint32_t *im_backing_suspend;
146	int im_bound;
147
148	uint32_t flags;
149
150	u32 size;
151	u32 pinst;
152	u32 cinst;
153	u64 vinst;
154
155	uint32_t engine;
156	uint32_t class;
157
158	void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
159	void *priv;
160};
161
162struct nouveau_channel {
163	struct drm_device *dev;
164	int id;
165
166	/* owner of this fifo */
167	struct drm_file *file_priv;
168	/* mapping of the fifo itself */
169	struct drm_local_map *map;
170
171	/* mapping of the regs controling the fifo */
172	void __iomem *user;
173	uint32_t user_get;
174	uint32_t user_put;
175
176	/* Fencing */
177	struct {
178		/* lock protects the pending list only */
179		spinlock_t lock;
180		struct list_head pending;
181		uint32_t sequence;
182		uint32_t sequence_ack;
183		atomic_t last_sequence_irq;
184	} fence;
185
186	/* DMA push buffer */
187	struct nouveau_gpuobj *pushbuf;
188	struct nouveau_bo     *pushbuf_bo;
189	uint32_t               pushbuf_base;
190
191	/* Notifier memory */
192	struct nouveau_bo *notifier_bo;
193	struct drm_mm notifier_heap;
194
195	/* PFIFO context */
196	struct nouveau_gpuobj *ramfc;
197	struct nouveau_gpuobj *cache;
198
199	/* PGRAPH context */
200	/* XXX may be merge 2 pointers as private data ??? */
201	struct nouveau_gpuobj *ramin_grctx;
202	void *pgraph_ctx;
203
204	/* NV50 VM */
205	struct nouveau_gpuobj *vm_pd;
206	struct nouveau_gpuobj *vm_gart_pt;
207	struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
208
209	/* Objects */
210	struct nouveau_gpuobj *ramin; /* Private instmem */
211	struct drm_mm          ramin_heap; /* Private PRAMIN heap */
212	struct nouveau_ramht  *ramht; /* Hash table */
213
214	/* GPU object info for stuff used in-kernel (mm_enabled) */
215	uint32_t m2mf_ntfy;
216	uint32_t vram_handle;
217	uint32_t gart_handle;
218	bool accel_done;
219
220	/* Push buffer state (only for drm's channel on !mm_enabled) */
221	struct {
222		int max;
223		int free;
224		int cur;
225		int put;
226		/* access via pushbuf_bo */
227
228		int ib_base;
229		int ib_max;
230		int ib_free;
231		int ib_put;
232	} dma;
233
234	uint32_t sw_subchannel[8];
235
236	struct {
237		struct nouveau_gpuobj *vblsem;
238		uint32_t vblsem_offset;
239		uint32_t vblsem_rval;
240		struct list_head vbl_wait;
241	} nvsw;
242
243	struct {
244		bool active;
245		char name[32];
246		struct drm_info_list info;
247	} debugfs;
248};
249
250struct nouveau_instmem_engine {
251	void	*priv;
252
253	int	(*init)(struct drm_device *dev);
254	void	(*takedown)(struct drm_device *dev);
255	int	(*suspend)(struct drm_device *dev);
256	void	(*resume)(struct drm_device *dev);
257
258	int	(*populate)(struct drm_device *, struct nouveau_gpuobj *,
259			    uint32_t *size);
260	void	(*clear)(struct drm_device *, struct nouveau_gpuobj *);
261	int	(*bind)(struct drm_device *, struct nouveau_gpuobj *);
262	int	(*unbind)(struct drm_device *, struct nouveau_gpuobj *);
263	void	(*flush)(struct drm_device *);
264};
265
266struct nouveau_mc_engine {
267	int  (*init)(struct drm_device *dev);
268	void (*takedown)(struct drm_device *dev);
269};
270
271struct nouveau_timer_engine {
272	int      (*init)(struct drm_device *dev);
273	void     (*takedown)(struct drm_device *dev);
274	uint64_t (*read)(struct drm_device *dev);
275};
276
277struct nouveau_fb_engine {
278	int num_tiles;
279
280	int  (*init)(struct drm_device *dev);
281	void (*takedown)(struct drm_device *dev);
282
283	void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
284				 uint32_t size, uint32_t pitch);
285};
286
287struct nouveau_fifo_engine {
288	int  channels;
289
290	struct nouveau_gpuobj *playlist[2];
291	int cur_playlist;
292
293	int  (*init)(struct drm_device *);
294	void (*takedown)(struct drm_device *);
295
296	void (*disable)(struct drm_device *);
297	void (*enable)(struct drm_device *);
298	bool (*reassign)(struct drm_device *, bool enable);
299	bool (*cache_pull)(struct drm_device *dev, bool enable);
300
301	int  (*channel_id)(struct drm_device *);
302
303	int  (*create_context)(struct nouveau_channel *);
304	void (*destroy_context)(struct nouveau_channel *);
305	int  (*load_context)(struct nouveau_channel *);
306	int  (*unload_context)(struct drm_device *);
307};
308
309struct nouveau_pgraph_object_method {
310	int id;
311	int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
312		      uint32_t data);
313};
314
315struct nouveau_pgraph_object_class {
316	int id;
317	bool software;
318	struct nouveau_pgraph_object_method *methods;
319};
320
321struct nouveau_pgraph_engine {
322	struct nouveau_pgraph_object_class *grclass;
323	bool accel_blocked;
324	int grctx_size;
325
326	/* NV2x/NV3x context table (0x400780) */
327	struct nouveau_gpuobj *ctx_table;
328
329	int  (*init)(struct drm_device *);
330	void (*takedown)(struct drm_device *);
331
332	void (*fifo_access)(struct drm_device *, bool);
333
334	struct nouveau_channel *(*channel)(struct drm_device *);
335	int  (*create_context)(struct nouveau_channel *);
336	void (*destroy_context)(struct nouveau_channel *);
337	int  (*load_context)(struct nouveau_channel *);
338	int  (*unload_context)(struct drm_device *);
339
340	void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
341				  uint32_t size, uint32_t pitch);
342};
343
344struct nouveau_display_engine {
345	int (*early_init)(struct drm_device *);
346	void (*late_takedown)(struct drm_device *);
347	int (*create)(struct drm_device *);
348	int (*init)(struct drm_device *);
349	void (*destroy)(struct drm_device *);
350};
351
352struct nouveau_gpio_engine {
353	int  (*init)(struct drm_device *);
354	void (*takedown)(struct drm_device *);
355
356	int  (*get)(struct drm_device *, enum dcb_gpio_tag);
357	int  (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
358
359	void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
360};
361
362struct nouveau_pm_voltage_level {
363	u8 voltage;
364	u8 vid;
365};
366
367struct nouveau_pm_voltage {
368	bool supported;
369	u8 vid_mask;
370
371	struct nouveau_pm_voltage_level *level;
372	int nr_level;
373};
374
375#define NOUVEAU_PM_MAX_LEVEL 8
376struct nouveau_pm_level {
377	struct device_attribute dev_attr;
378	char name[32];
379	int id;
380
381	u32 core;
382	u32 memory;
383	u32 shader;
384	u32 unk05;
385
386	u8 voltage;
387	u8 fanspeed;
388
389	u16 memscript;
390};
391
392struct nouveau_pm_temp_sensor_constants {
393	u16 offset_constant;
394	s16 offset_mult;
395	u16 offset_div;
396	u16 slope_mult;
397	u16 slope_div;
398};
399
400struct nouveau_pm_threshold_temp {
401	s16 critical;
402	s16 down_clock;
403	s16 fan_boost;
404};
405
406struct nouveau_pm_memtiming {
407	u32 reg_100220;
408	u32 reg_100224;
409	u32 reg_100228;
410	u32 reg_10022c;
411	u32 reg_100230;
412	u32 reg_100234;
413	u32 reg_100238;
414	u32 reg_10023c;
415};
416
417struct nouveau_pm_memtimings {
418	bool supported;
419	struct nouveau_pm_memtiming *timing;
420	int nr_timing;
421};
422
423struct nouveau_pm_engine {
424	struct nouveau_pm_voltage voltage;
425	struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
426	int nr_perflvl;
427	struct nouveau_pm_memtimings memtimings;
428	struct nouveau_pm_temp_sensor_constants sensor_constants;
429	struct nouveau_pm_threshold_temp threshold_temp;
430
431	struct nouveau_pm_level boot;
432	struct nouveau_pm_level *cur;
433
434	struct device *hwmon;
435
436	int (*clock_get)(struct drm_device *, u32 id);
437	void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
438			   u32 id, int khz);
439	void (*clock_set)(struct drm_device *, void *);
440	int (*voltage_get)(struct drm_device *);
441	int (*voltage_set)(struct drm_device *, int voltage);
442	int (*fanspeed_get)(struct drm_device *);
443	int (*fanspeed_set)(struct drm_device *, int fanspeed);
444	int (*temp_get)(struct drm_device *);
445};
446
447struct nouveau_engine {
448	struct nouveau_instmem_engine instmem;
449	struct nouveau_mc_engine      mc;
450	struct nouveau_timer_engine   timer;
451	struct nouveau_fb_engine      fb;
452	struct nouveau_pgraph_engine  graph;
453	struct nouveau_fifo_engine    fifo;
454	struct nouveau_display_engine display;
455	struct nouveau_gpio_engine    gpio;
456	struct nouveau_pm_engine      pm;
457};
458
459struct nouveau_pll_vals {
460	union {
461		struct {
462#ifdef __BIG_ENDIAN
463			uint8_t N1, M1, N2, M2;
464#else
465			uint8_t M1, N1, M2, N2;
466#endif
467		};
468		struct {
469			uint16_t NM1, NM2;
470		} __attribute__((packed));
471	};
472	int log2P;
473
474	int refclk;
475};
476
477enum nv04_fp_display_regs {
478	FP_DISPLAY_END,
479	FP_TOTAL,
480	FP_CRTC,
481	FP_SYNC_START,
482	FP_SYNC_END,
483	FP_VALID_START,
484	FP_VALID_END
485};
486
487struct nv04_crtc_reg {
488	unsigned char MiscOutReg;     /* */
489	uint8_t CRTC[0xa0];
490	uint8_t CR58[0x10];
491	uint8_t Sequencer[5];
492	uint8_t Graphics[9];
493	uint8_t Attribute[21];
494	unsigned char DAC[768];       /* Internal Colorlookuptable */
495
496	/* PCRTC regs */
497	uint32_t fb_start;
498	uint32_t crtc_cfg;
499	uint32_t cursor_cfg;
500	uint32_t gpio_ext;
501	uint32_t crtc_830;
502	uint32_t crtc_834;
503	uint32_t crtc_850;
504	uint32_t crtc_eng_ctrl;
505
506	/* PRAMDAC regs */
507	uint32_t nv10_cursync;
508	struct nouveau_pll_vals pllvals;
509	uint32_t ramdac_gen_ctrl;
510	uint32_t ramdac_630;
511	uint32_t ramdac_634;
512	uint32_t tv_setup;
513	uint32_t tv_vtotal;
514	uint32_t tv_vskew;
515	uint32_t tv_vsync_delay;
516	uint32_t tv_htotal;
517	uint32_t tv_hskew;
518	uint32_t tv_hsync_delay;
519	uint32_t tv_hsync_delay2;
520	uint32_t fp_horiz_regs[7];
521	uint32_t fp_vert_regs[7];
522	uint32_t dither;
523	uint32_t fp_control;
524	uint32_t dither_regs[6];
525	uint32_t fp_debug_0;
526	uint32_t fp_debug_1;
527	uint32_t fp_debug_2;
528	uint32_t fp_margin_color;
529	uint32_t ramdac_8c0;
530	uint32_t ramdac_a20;
531	uint32_t ramdac_a24;
532	uint32_t ramdac_a34;
533	uint32_t ctv_regs[38];
534};
535
536struct nv04_output_reg {
537	uint32_t output;
538	int head;
539};
540
541struct nv04_mode_state {
542	uint32_t bpp;
543	uint32_t width;
544	uint32_t height;
545	uint32_t interlace;
546	uint32_t repaint0;
547	uint32_t repaint1;
548	uint32_t screen;
549	uint32_t scale;
550	uint32_t dither;
551	uint32_t extra;
552	uint32_t fifo;
553	uint32_t pixel;
554	uint32_t horiz;
555	int arbitration0;
556	int arbitration1;
557	uint32_t pll;
558	uint32_t pllB;
559	uint32_t vpll;
560	uint32_t vpll2;
561	uint32_t vpllB;
562	uint32_t vpll2B;
563	uint32_t pllsel;
564	uint32_t sel_clk;
565	uint32_t general;
566	uint32_t crtcOwner;
567	uint32_t head;
568	uint32_t head2;
569	uint32_t cursorConfig;
570	uint32_t cursor0;
571	uint32_t cursor1;
572	uint32_t cursor2;
573	uint32_t timingH;
574	uint32_t timingV;
575	uint32_t displayV;
576	uint32_t crtcSync;
577
578	struct nv04_crtc_reg crtc_reg[2];
579};
580
581enum nouveau_card_type {
582	NV_04      = 0x00,
583	NV_10      = 0x10,
584	NV_20      = 0x20,
585	NV_30      = 0x30,
586	NV_40      = 0x40,
587	NV_50      = 0x50,
588	NV_C0      = 0xc0,
589};
590
591struct drm_nouveau_private {
592	struct drm_device *dev;
593
594	/* the card type, takes NV_* as values */
595	enum nouveau_card_type card_type;
596	/* exact chipset, derived from NV_PMC_BOOT_0 */
597	int chipset;
598	int flags;
599
600	void __iomem *mmio;
601
602	spinlock_t ramin_lock;
603	void __iomem *ramin;
604	u32 ramin_size;
605	u32 ramin_base;
606	bool ramin_available;
607	struct drm_mm ramin_heap;
608	struct list_head gpuobj_list;
609
610	struct nouveau_bo *vga_ram;
611
612	struct workqueue_struct *wq;
613	struct work_struct irq_work;
614	struct work_struct hpd_work;
615
616	struct list_head vbl_waiting;
617
618	struct {
619		struct drm_global_reference mem_global_ref;
620		struct ttm_bo_global_ref bo_global_ref;
621		struct ttm_bo_device bdev;
622		atomic_t validate_sequence;
623	} ttm;
624
625	int fifo_alloc_count;
626	struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
627
628	struct nouveau_engine engine;
629	struct nouveau_channel *channel;
630
631	/* For PFIFO and PGRAPH. */
632	spinlock_t context_switch_lock;
633
634	/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
635	struct nouveau_ramht  *ramht;
636	struct nouveau_gpuobj *ramfc;
637	struct nouveau_gpuobj *ramro;
638
639	uint32_t ramin_rsvd_vram;
640
641	struct {
642		enum {
643			NOUVEAU_GART_NONE = 0,
644			NOUVEAU_GART_AGP,
645			NOUVEAU_GART_SGDMA
646		} type;
647		uint64_t aper_base;
648		uint64_t aper_size;
649		uint64_t aper_free;
650
651		struct nouveau_gpuobj *sg_ctxdma;
652		struct page *sg_dummy_page;
653		dma_addr_t sg_dummy_bus;
654	} gart_info;
655
656	/* nv10-nv40 tiling regions */
657	struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
658
659	/* VRAM/fb configuration */
660	uint64_t vram_size;
661	uint64_t vram_sys_base;
662	u32 vram_rblock_size;
663
664	uint64_t fb_phys;
665	uint64_t fb_available_size;
666	uint64_t fb_mappable_pages;
667	uint64_t fb_aper_free;
668	int fb_mtrr;
669
670	/* G8x/G9x virtual address space */
671	uint64_t vm_gart_base;
672	uint64_t vm_gart_size;
673	uint64_t vm_vram_base;
674	uint64_t vm_vram_size;
675	uint64_t vm_end;
676	struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
677	int vm_vram_pt_nr;
678
679	struct nvbios vbios;
680
681	struct nv04_mode_state mode_reg;
682	struct nv04_mode_state saved_reg;
683	uint32_t saved_vga_font[4][16384];
684	uint32_t crtc_owner;
685	uint32_t dac_users[4];
686
687	struct nouveau_suspend_resume {
688		uint32_t *ramin_copy;
689	} susres;
690
691	struct backlight_device *backlight;
692
693	struct nouveau_channel *evo;
694	struct {
695		struct dcb_entry *dcb;
696		u16 script;
697		u32 pclk;
698	} evo_irq;
699
700	struct {
701		struct dentry *channel_root;
702	} debugfs;
703
704	struct nouveau_fbdev *nfbdev;
705	struct apertures_struct *apertures;
706};
707
708static inline struct drm_nouveau_private *
709nouveau_private(struct drm_device *dev)
710{
711	return dev->dev_private;
712}
713
714static inline struct drm_nouveau_private *
715nouveau_bdev(struct ttm_bo_device *bd)
716{
717	return container_of(bd, struct drm_nouveau_private, ttm.bdev);
718}
719
720static inline int
721nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
722{
723	struct nouveau_bo *prev;
724
725	if (!pnvbo)
726		return -EINVAL;
727	prev = *pnvbo;
728
729	*pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
730	if (prev) {
731		struct ttm_buffer_object *bo = &prev->bo;
732
733		ttm_bo_unref(&bo);
734	}
735
736	return 0;
737}
738
739#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do {    \
740	struct drm_nouveau_private *nv = dev->dev_private;       \
741	if (!nouveau_channel_owner(dev, (cl), (id))) {           \
742		NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
743			 DRM_CURRENTPID, (id));                  \
744		return -EPERM;                                   \
745	}                                                        \
746	(ch) = nv->fifos[(id)];                                  \
747} while (0)
748
749/* nouveau_drv.c */
750extern int nouveau_agpmode;
751extern int nouveau_duallink;
752extern int nouveau_uscript_lvds;
753extern int nouveau_uscript_tmds;
754extern int nouveau_vram_pushbuf;
755extern int nouveau_vram_notify;
756extern int nouveau_fbpercrtc;
757extern int nouveau_tv_disable;
758extern char *nouveau_tv_norm;
759extern int nouveau_reg_debug;
760extern char *nouveau_vbios;
761extern int nouveau_ignorelid;
762extern int nouveau_nofbaccel;
763extern int nouveau_noaccel;
764extern int nouveau_force_post;
765extern int nouveau_override_conntype;
766extern char *nouveau_perflvl;
767extern int nouveau_perflvl_wr;
768
769extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
770extern int nouveau_pci_resume(struct pci_dev *pdev);
771
772/* nouveau_state.c */
773extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
774extern int  nouveau_load(struct drm_device *, unsigned long flags);
775extern int  nouveau_firstopen(struct drm_device *);
776extern void nouveau_lastclose(struct drm_device *);
777extern int  nouveau_unload(struct drm_device *);
778extern int  nouveau_ioctl_getparam(struct drm_device *, void *data,
779				   struct drm_file *);
780extern int  nouveau_ioctl_setparam(struct drm_device *, void *data,
781				   struct drm_file *);
782extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
783			       uint32_t reg, uint32_t mask, uint32_t val);
784extern bool nouveau_wait_for_idle(struct drm_device *);
785extern int  nouveau_card_init(struct drm_device *);
786
787/* nouveau_mem.c */
788extern int  nouveau_mem_vram_init(struct drm_device *);
789extern void nouveau_mem_vram_fini(struct drm_device *);
790extern int  nouveau_mem_gart_init(struct drm_device *);
791extern void nouveau_mem_gart_fini(struct drm_device *);
792extern int  nouveau_mem_init_agp(struct drm_device *);
793extern int  nouveau_mem_reset_agp(struct drm_device *);
794extern void nouveau_mem_close(struct drm_device *);
795extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
796						    uint32_t addr,
797						    uint32_t size,
798						    uint32_t pitch);
799extern void nv10_mem_expire_tiling(struct drm_device *dev,
800				   struct nouveau_tile_reg *tile,
801				   struct nouveau_fence *fence);
802extern int  nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
803				    uint32_t size, uint32_t flags,
804				    uint64_t phys);
805extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
806			       uint32_t size);
807
808/* nouveau_notifier.c */
809extern int  nouveau_notifier_init_channel(struct nouveau_channel *);
810extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
811extern int  nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
812				   int cout, uint32_t *offset);
813extern int  nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
814extern int  nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
815					 struct drm_file *);
816extern int  nouveau_ioctl_notifier_free(struct drm_device *, void *data,
817					struct drm_file *);
818
819/* nouveau_channel.c */
820extern struct drm_ioctl_desc nouveau_ioctls[];
821extern int nouveau_max_ioctl;
822extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
823extern int  nouveau_channel_owner(struct drm_device *, struct drm_file *,
824				  int channel);
825extern int  nouveau_channel_alloc(struct drm_device *dev,
826				  struct nouveau_channel **chan,
827				  struct drm_file *file_priv,
828				  uint32_t fb_ctxdma, uint32_t tt_ctxdma);
829extern void nouveau_channel_free(struct nouveau_channel *);
830
831/* nouveau_object.c */
832extern int  nouveau_gpuobj_early_init(struct drm_device *);
833extern int  nouveau_gpuobj_init(struct drm_device *);
834extern void nouveau_gpuobj_takedown(struct drm_device *);
835extern int  nouveau_gpuobj_suspend(struct drm_device *dev);
836extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
837extern void nouveau_gpuobj_resume(struct drm_device *dev);
838extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
839				       uint32_t vram_h, uint32_t tt_h);
840extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
841extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
842			      uint32_t size, int align, uint32_t flags,
843			      struct nouveau_gpuobj **);
844extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
845			       struct nouveau_gpuobj **);
846extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
847				   u32 size, u32 flags,
848				   struct nouveau_gpuobj **);
849extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
850				  uint64_t offset, uint64_t size, int access,
851				  int target, struct nouveau_gpuobj **);
852extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
853				       uint64_t offset, uint64_t size,
854				       int access, struct nouveau_gpuobj **,
855				       uint32_t *o_ret);
856extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
857				 struct nouveau_gpuobj **);
858extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
859				 struct nouveau_gpuobj **);
860extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
861				     struct drm_file *);
862extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
863				     struct drm_file *);
864
865/* nouveau_irq.c */
866extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
867extern void        nouveau_irq_preinstall(struct drm_device *);
868extern int         nouveau_irq_postinstall(struct drm_device *);
869extern void        nouveau_irq_uninstall(struct drm_device *);
870
871/* nouveau_sgdma.c */
872extern int nouveau_sgdma_init(struct drm_device *);
873extern void nouveau_sgdma_takedown(struct drm_device *);
874extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
875				  uint32_t *page);
876extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
877
878/* nouveau_debugfs.c */
879#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
880extern int  nouveau_debugfs_init(struct drm_minor *);
881extern void nouveau_debugfs_takedown(struct drm_minor *);
882extern int  nouveau_debugfs_channel_init(struct nouveau_channel *);
883extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
884#else
885static inline int
886nouveau_debugfs_init(struct drm_minor *minor)
887{
888	return 0;
889}
890
891static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
892{
893}
894
895static inline int
896nouveau_debugfs_channel_init(struct nouveau_channel *chan)
897{
898	return 0;
899}
900
901static inline void
902nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
903{
904}
905#endif
906
907/* nouveau_dma.c */
908extern void nouveau_dma_pre_init(struct nouveau_channel *);
909extern int  nouveau_dma_init(struct nouveau_channel *);
910extern int  nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
911
912/* nouveau_acpi.c */
913#define ROM_BIOS_PAGE 4096
914#if defined(CONFIG_ACPI)
915void nouveau_register_dsm_handler(void);
916void nouveau_unregister_dsm_handler(void);
917int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
918bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
919int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
920#else
921static inline void nouveau_register_dsm_handler(void) {}
922static inline void nouveau_unregister_dsm_handler(void) {}
923static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
924static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
925static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
926#endif
927
928/* nouveau_backlight.c */
929#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
930extern int nouveau_backlight_init(struct drm_device *);
931extern void nouveau_backlight_exit(struct drm_device *);
932#else
933static inline int nouveau_backlight_init(struct drm_device *dev)
934{
935	return 0;
936}
937
938static inline void nouveau_backlight_exit(struct drm_device *dev) { }
939#endif
940
941/* nouveau_bios.c */
942extern int nouveau_bios_init(struct drm_device *);
943extern void nouveau_bios_takedown(struct drm_device *dev);
944extern int nouveau_run_vbios_init(struct drm_device *);
945extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
946					struct dcb_entry *);
947extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
948						      enum dcb_gpio_tag);
949extern struct dcb_connector_table_entry *
950nouveau_bios_connector_entry(struct drm_device *, int index);
951extern u32 get_pll_register(struct drm_device *, enum pll_types);
952extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
953			  struct pll_lims *);
954extern int nouveau_bios_run_display_table(struct drm_device *,
955					  struct dcb_entry *,
956					  uint32_t script, int pxclk);
957extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
958				   int *length);
959extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
960extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
961extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
962					 bool *dl, bool *if_is_24bit);
963extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
964			  int head, int pxclk);
965extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
966			    enum LVDS_script, int pxclk);
967
968/* nouveau_ttm.c */
969int nouveau_ttm_global_init(struct drm_nouveau_private *);
970void nouveau_ttm_global_release(struct drm_nouveau_private *);
971int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
972
973/* nouveau_dp.c */
974int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
975		     uint8_t *data, int data_nr);
976bool nouveau_dp_detect(struct drm_encoder *);
977bool nouveau_dp_link_train(struct drm_encoder *);
978
979/* nv04_fb.c */
980extern int  nv04_fb_init(struct drm_device *);
981extern void nv04_fb_takedown(struct drm_device *);
982
983/* nv10_fb.c */
984extern int  nv10_fb_init(struct drm_device *);
985extern void nv10_fb_takedown(struct drm_device *);
986extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
987				      uint32_t, uint32_t);
988
989/* nv30_fb.c */
990extern int  nv30_fb_init(struct drm_device *);
991extern void nv30_fb_takedown(struct drm_device *);
992
993/* nv40_fb.c */
994extern int  nv40_fb_init(struct drm_device *);
995extern void nv40_fb_takedown(struct drm_device *);
996extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
997				      uint32_t, uint32_t);
998/* nv50_fb.c */
999extern int  nv50_fb_init(struct drm_device *);
1000extern void nv50_fb_takedown(struct drm_device *);
1001extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1002
1003/* nvc0_fb.c */
1004extern int  nvc0_fb_init(struct drm_device *);
1005extern void nvc0_fb_takedown(struct drm_device *);
1006
1007/* nv04_fifo.c */
1008extern int  nv04_fifo_init(struct drm_device *);
1009extern void nv04_fifo_disable(struct drm_device *);
1010extern void nv04_fifo_enable(struct drm_device *);
1011extern bool nv04_fifo_reassign(struct drm_device *, bool);
1012extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1013extern int  nv04_fifo_channel_id(struct drm_device *);
1014extern int  nv04_fifo_create_context(struct nouveau_channel *);
1015extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1016extern int  nv04_fifo_load_context(struct nouveau_channel *);
1017extern int  nv04_fifo_unload_context(struct drm_device *);
1018
1019/* nv10_fifo.c */
1020extern int  nv10_fifo_init(struct drm_device *);
1021extern int  nv10_fifo_channel_id(struct drm_device *);
1022extern int  nv10_fifo_create_context(struct nouveau_channel *);
1023extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1024extern int  nv10_fifo_load_context(struct nouveau_channel *);
1025extern int  nv10_fifo_unload_context(struct drm_device *);
1026
1027/* nv40_fifo.c */
1028extern int  nv40_fifo_init(struct drm_device *);
1029extern int  nv40_fifo_create_context(struct nouveau_channel *);
1030extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1031extern int  nv40_fifo_load_context(struct nouveau_channel *);
1032extern int  nv40_fifo_unload_context(struct drm_device *);
1033
1034/* nv50_fifo.c */
1035extern int  nv50_fifo_init(struct drm_device *);
1036extern void nv50_fifo_takedown(struct drm_device *);
1037extern int  nv50_fifo_channel_id(struct drm_device *);
1038extern int  nv50_fifo_create_context(struct nouveau_channel *);
1039extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1040extern int  nv50_fifo_load_context(struct nouveau_channel *);
1041extern int  nv50_fifo_unload_context(struct drm_device *);
1042
1043/* nvc0_fifo.c */
1044extern int  nvc0_fifo_init(struct drm_device *);
1045extern void nvc0_fifo_takedown(struct drm_device *);
1046extern void nvc0_fifo_disable(struct drm_device *);
1047extern void nvc0_fifo_enable(struct drm_device *);
1048extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1049extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1050extern int  nvc0_fifo_channel_id(struct drm_device *);
1051extern int  nvc0_fifo_create_context(struct nouveau_channel *);
1052extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1053extern int  nvc0_fifo_load_context(struct nouveau_channel *);
1054extern int  nvc0_fifo_unload_context(struct drm_device *);
1055
1056/* nv04_graph.c */
1057extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1058extern int  nv04_graph_init(struct drm_device *);
1059extern void nv04_graph_takedown(struct drm_device *);
1060extern void nv04_graph_fifo_access(struct drm_device *, bool);
1061extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1062extern int  nv04_graph_create_context(struct nouveau_channel *);
1063extern void nv04_graph_destroy_context(struct nouveau_channel *);
1064extern int  nv04_graph_load_context(struct nouveau_channel *);
1065extern int  nv04_graph_unload_context(struct drm_device *);
1066extern void nv04_graph_context_switch(struct drm_device *);
1067
1068/* nv10_graph.c */
1069extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1070extern int  nv10_graph_init(struct drm_device *);
1071extern void nv10_graph_takedown(struct drm_device *);
1072extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1073extern int  nv10_graph_create_context(struct nouveau_channel *);
1074extern void nv10_graph_destroy_context(struct nouveau_channel *);
1075extern int  nv10_graph_load_context(struct nouveau_channel *);
1076extern int  nv10_graph_unload_context(struct drm_device *);
1077extern void nv10_graph_context_switch(struct drm_device *);
1078extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1079					 uint32_t, uint32_t);
1080
1081/* nv20_graph.c */
1082extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1083extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1084extern int  nv20_graph_create_context(struct nouveau_channel *);
1085extern void nv20_graph_destroy_context(struct nouveau_channel *);
1086extern int  nv20_graph_load_context(struct nouveau_channel *);
1087extern int  nv20_graph_unload_context(struct drm_device *);
1088extern int  nv20_graph_init(struct drm_device *);
1089extern void nv20_graph_takedown(struct drm_device *);
1090extern int  nv30_graph_init(struct drm_device *);
1091extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1092					 uint32_t, uint32_t);
1093
1094/* nv40_graph.c */
1095extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1096extern int  nv40_graph_init(struct drm_device *);
1097extern void nv40_graph_takedown(struct drm_device *);
1098extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1099extern int  nv40_graph_create_context(struct nouveau_channel *);
1100extern void nv40_graph_destroy_context(struct nouveau_channel *);
1101extern int  nv40_graph_load_context(struct nouveau_channel *);
1102extern int  nv40_graph_unload_context(struct drm_device *);
1103extern void nv40_grctx_init(struct nouveau_grctx *);
1104extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1105					 uint32_t, uint32_t);
1106
1107/* nv50_graph.c */
1108extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1109extern int  nv50_graph_init(struct drm_device *);
1110extern void nv50_graph_takedown(struct drm_device *);
1111extern void nv50_graph_fifo_access(struct drm_device *, bool);
1112extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1113extern int  nv50_graph_create_context(struct nouveau_channel *);
1114extern void nv50_graph_destroy_context(struct nouveau_channel *);
1115extern int  nv50_graph_load_context(struct nouveau_channel *);
1116extern int  nv50_graph_unload_context(struct drm_device *);
1117extern void nv50_graph_context_switch(struct drm_device *);
1118extern int  nv50_grctx_init(struct nouveau_grctx *);
1119
1120/* nvc0_graph.c */
1121extern int  nvc0_graph_init(struct drm_device *);
1122extern void nvc0_graph_takedown(struct drm_device *);
1123extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1124extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1125extern int  nvc0_graph_create_context(struct nouveau_channel *);
1126extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1127extern int  nvc0_graph_load_context(struct nouveau_channel *);
1128extern int  nvc0_graph_unload_context(struct drm_device *);
1129
1130/* nv04_instmem.c */
1131extern int  nv04_instmem_init(struct drm_device *);
1132extern void nv04_instmem_takedown(struct drm_device *);
1133extern int  nv04_instmem_suspend(struct drm_device *);
1134extern void nv04_instmem_resume(struct drm_device *);
1135extern int  nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1136				  uint32_t *size);
1137extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1138extern int  nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1139extern int  nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1140extern void nv04_instmem_flush(struct drm_device *);
1141
1142/* nv50_instmem.c */
1143extern int  nv50_instmem_init(struct drm_device *);
1144extern void nv50_instmem_takedown(struct drm_device *);
1145extern int  nv50_instmem_suspend(struct drm_device *);
1146extern void nv50_instmem_resume(struct drm_device *);
1147extern int  nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1148				  uint32_t *size);
1149extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1150extern int  nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1151extern int  nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1152extern void nv50_instmem_flush(struct drm_device *);
1153extern void nv84_instmem_flush(struct drm_device *);
1154extern void nv50_vm_flush(struct drm_device *, int engine);
1155
1156/* nvc0_instmem.c */
1157extern int  nvc0_instmem_init(struct drm_device *);
1158extern void nvc0_instmem_takedown(struct drm_device *);
1159extern int  nvc0_instmem_suspend(struct drm_device *);
1160extern void nvc0_instmem_resume(struct drm_device *);
1161extern int  nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1162				  uint32_t *size);
1163extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1164extern int  nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1165extern int  nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1166extern void nvc0_instmem_flush(struct drm_device *);
1167
1168/* nv04_mc.c */
1169extern int  nv04_mc_init(struct drm_device *);
1170extern void nv04_mc_takedown(struct drm_device *);
1171
1172/* nv40_mc.c */
1173extern int  nv40_mc_init(struct drm_device *);
1174extern void nv40_mc_takedown(struct drm_device *);
1175
1176/* nv50_mc.c */
1177extern int  nv50_mc_init(struct drm_device *);
1178extern void nv50_mc_takedown(struct drm_device *);
1179
1180/* nv04_timer.c */
1181extern int  nv04_timer_init(struct drm_device *);
1182extern uint64_t nv04_timer_read(struct drm_device *);
1183extern void nv04_timer_takedown(struct drm_device *);
1184
1185extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1186				 unsigned long arg);
1187
1188/* nv04_dac.c */
1189extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1190extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1191extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1192extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1193extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1194
1195/* nv04_dfp.c */
1196extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1197extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1198extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1199			       int head, bool dl);
1200extern void nv04_dfp_disable(struct drm_device *dev, int head);
1201extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1202
1203/* nv04_tv.c */
1204extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1205extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1206
1207/* nv17_tv.c */
1208extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1209
1210/* nv04_display.c */
1211extern int nv04_display_early_init(struct drm_device *);
1212extern void nv04_display_late_takedown(struct drm_device *);
1213extern int nv04_display_create(struct drm_device *);
1214extern int nv04_display_init(struct drm_device *);
1215extern void nv04_display_destroy(struct drm_device *);
1216
1217/* nv04_crtc.c */
1218extern int nv04_crtc_create(struct drm_device *, int index);
1219
1220/* nouveau_bo.c */
1221extern struct ttm_bo_driver nouveau_bo_driver;
1222extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1223			  int size, int align, uint32_t flags,
1224			  uint32_t tile_mode, uint32_t tile_flags,
1225			  bool no_vm, bool mappable, struct nouveau_bo **);
1226extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1227extern int nouveau_bo_unpin(struct nouveau_bo *);
1228extern int nouveau_bo_map(struct nouveau_bo *);
1229extern void nouveau_bo_unmap(struct nouveau_bo *);
1230extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1231				     uint32_t busy);
1232extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1233extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1234extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1235extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1236extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
1237
1238/* nouveau_fence.c */
1239struct nouveau_fence;
1240extern int nouveau_fence_channel_init(struct nouveau_channel *);
1241extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1242extern void nouveau_fence_update(struct nouveau_channel *);
1243extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1244			     bool emit);
1245extern int nouveau_fence_emit(struct nouveau_fence *);
1246struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1247extern bool nouveau_fence_signalled(void *obj, void *arg);
1248extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1249extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1250extern int nouveau_fence_flush(void *obj, void *arg);
1251extern void nouveau_fence_unref(void **obj);
1252extern void *nouveau_fence_ref(void *obj);
1253
1254/* nouveau_gem.c */
1255extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1256			   int size, int align, uint32_t flags,
1257			   uint32_t tile_mode, uint32_t tile_flags,
1258			   bool no_vm, bool mappable, struct nouveau_bo **);
1259extern int nouveau_gem_object_new(struct drm_gem_object *);
1260extern void nouveau_gem_object_del(struct drm_gem_object *);
1261extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1262				 struct drm_file *);
1263extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1264				     struct drm_file *);
1265extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1266				      struct drm_file *);
1267extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1268				      struct drm_file *);
1269extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1270				  struct drm_file *);
1271
1272/* nv10_gpio.c */
1273int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1274int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1275
1276/* nv50_gpio.c */
1277int nv50_gpio_init(struct drm_device *dev);
1278int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1279int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1280void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1281
1282/* nv50_calc. */
1283int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1284		  int *N1, int *M1, int *N2, int *M2, int *P);
1285int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1286		   int clk, int *N, int *fN, int *M, int *P);
1287
1288#ifndef ioread32_native
1289#ifdef __BIG_ENDIAN
1290#define ioread16_native ioread16be
1291#define iowrite16_native iowrite16be
1292#define ioread32_native  ioread32be
1293#define iowrite32_native iowrite32be
1294#else /* def __BIG_ENDIAN */
1295#define ioread16_native ioread16
1296#define iowrite16_native iowrite16
1297#define ioread32_native  ioread32
1298#define iowrite32_native iowrite32
1299#endif /* def __BIG_ENDIAN else */
1300#endif /* !ioread32_native */
1301
1302/* channel control reg access */
1303static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1304{
1305	return ioread32_native(chan->user + reg);
1306}
1307
1308static inline void nvchan_wr32(struct nouveau_channel *chan,
1309							unsigned reg, u32 val)
1310{
1311	iowrite32_native(val, chan->user + reg);
1312}
1313
1314/* register access */
1315static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1316{
1317	struct drm_nouveau_private *dev_priv = dev->dev_private;
1318	return ioread32_native(dev_priv->mmio + reg);
1319}
1320
1321static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1322{
1323	struct drm_nouveau_private *dev_priv = dev->dev_private;
1324	iowrite32_native(val, dev_priv->mmio + reg);
1325}
1326
1327static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1328{
1329	u32 tmp = nv_rd32(dev, reg);
1330	nv_wr32(dev, reg, (tmp & ~mask) | val);
1331	return tmp;
1332}
1333
1334static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1335{
1336	struct drm_nouveau_private *dev_priv = dev->dev_private;
1337	return ioread8(dev_priv->mmio + reg);
1338}
1339
1340static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1341{
1342	struct drm_nouveau_private *dev_priv = dev->dev_private;
1343	iowrite8(val, dev_priv->mmio + reg);
1344}
1345
1346#define nv_wait(dev, reg, mask, val) \
1347	nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1348
1349/* PRAMIN access */
1350static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1351{
1352	struct drm_nouveau_private *dev_priv = dev->dev_private;
1353	return ioread32_native(dev_priv->ramin + offset);
1354}
1355
1356static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1357{
1358	struct drm_nouveau_private *dev_priv = dev->dev_private;
1359	iowrite32_native(val, dev_priv->ramin + offset);
1360}
1361
1362/* object access */
1363extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1364extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1365
1366/*
1367 * Logging
1368 * Argument d is (struct drm_device *).
1369 */
1370#define NV_PRINTK(level, d, fmt, arg...) \
1371	printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1372					pci_name(d->pdev), ##arg)
1373#ifndef NV_DEBUG_NOTRACE
1374#define NV_DEBUG(d, fmt, arg...) do {                                          \
1375	if (drm_debug & DRM_UT_DRIVER) {                                       \
1376		NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
1377			  __LINE__, ##arg);                                    \
1378	}                                                                      \
1379} while (0)
1380#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
1381	if (drm_debug & DRM_UT_KMS) {                                          \
1382		NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
1383			  __LINE__, ##arg);                                    \
1384	}                                                                      \
1385} while (0)
1386#else
1387#define NV_DEBUG(d, fmt, arg...) do {                                          \
1388	if (drm_debug & DRM_UT_DRIVER)                                         \
1389		NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
1390} while (0)
1391#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
1392	if (drm_debug & DRM_UT_KMS)                                            \
1393		NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
1394} while (0)
1395#endif
1396#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1397#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1398#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1399#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1400#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1401
1402/* nouveau_reg_debug bitmask */
1403enum {
1404	NOUVEAU_REG_DEBUG_MC             = 0x1,
1405	NOUVEAU_REG_DEBUG_VIDEO          = 0x2,
1406	NOUVEAU_REG_DEBUG_FB             = 0x4,
1407	NOUVEAU_REG_DEBUG_EXTDEV         = 0x8,
1408	NOUVEAU_REG_DEBUG_CRTC           = 0x10,
1409	NOUVEAU_REG_DEBUG_RAMDAC         = 0x20,
1410	NOUVEAU_REG_DEBUG_VGACRTC        = 0x40,
1411	NOUVEAU_REG_DEBUG_RMVIO          = 0x80,
1412	NOUVEAU_REG_DEBUG_VGAATTR        = 0x100,
1413	NOUVEAU_REG_DEBUG_EVO            = 0x200,
1414};
1415
1416#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1417	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1418		NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1419} while (0)
1420
1421static inline bool
1422nv_two_heads(struct drm_device *dev)
1423{
1424	struct drm_nouveau_private *dev_priv = dev->dev_private;
1425	const int impl = dev->pci_device & 0x0ff0;
1426
1427	if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1428	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1429		return true;
1430
1431	return false;
1432}
1433
1434static inline bool
1435nv_gf4_disp_arch(struct drm_device *dev)
1436{
1437	return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1438}
1439
1440static inline bool
1441nv_two_reg_pll(struct drm_device *dev)
1442{
1443	struct drm_nouveau_private *dev_priv = dev->dev_private;
1444	const int impl = dev->pci_device & 0x0ff0;
1445
1446	if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1447		return true;
1448	return false;
1449}
1450
1451static inline bool
1452nv_match_device(struct drm_device *dev, unsigned device,
1453		unsigned sub_vendor, unsigned sub_device)
1454{
1455	return dev->pdev->device == device &&
1456		dev->pdev->subsystem_vendor == sub_vendor &&
1457		dev->pdev->subsystem_device == sub_device;
1458}
1459
1460#define NV_SW                                                        0x0000506e
1461#define NV_SW_DMA_SEMAPHORE                                          0x00000060
1462#define NV_SW_SEMAPHORE_OFFSET                                       0x00000064
1463#define NV_SW_SEMAPHORE_ACQUIRE                                      0x00000068
1464#define NV_SW_SEMAPHORE_RELEASE                                      0x0000006c
1465#define NV_SW_DMA_VBLSEM                                             0x0000018c
1466#define NV_SW_VBLSEM_OFFSET                                          0x00000400
1467#define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
1468#define NV_SW_VBLSEM_RELEASE                                         0x00000408
1469
1470#endif /* __NOUVEAU_DRV_H__ */
1471