nouveau_drv.h revision 2d7b919c9b0ca3df1da2498bb0cede25ddd97e00
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_PPP 2 154#define NVOBJ_ENGINE_COPY 3 155#define NVOBJ_ENGINE_VP 4 156#define NVOBJ_ENGINE_CRYPT 5 157#define NVOBJ_ENGINE_BSP 6 158#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 159#define NVOBJ_ENGINE_INT 0xdeadbeef 160 161#define NVOBJ_FLAG_DONT_MAP (1 << 0) 162#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 163#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 164#define NVOBJ_FLAG_VM (1 << 3) 165#define NVOBJ_FLAG_VM_USER (1 << 4) 166 167#define NVOBJ_CINST_GLOBAL 0xdeadbeef 168 169struct nouveau_gpuobj { 170 struct drm_device *dev; 171 struct kref refcount; 172 struct list_head list; 173 174 void *node; 175 u32 *suspend; 176 177 uint32_t flags; 178 179 u32 size; 180 u32 pinst; 181 u32 cinst; 182 u64 vinst; 183 184 uint32_t engine; 185 uint32_t class; 186 187 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 188 void *priv; 189}; 190 191struct nouveau_page_flip_state { 192 struct list_head head; 193 struct drm_pending_vblank_event *event; 194 int crtc, bpp, pitch, x, y; 195 uint64_t offset; 196}; 197 198enum nouveau_channel_mutex_class { 199 NOUVEAU_UCHANNEL_MUTEX, 200 NOUVEAU_KCHANNEL_MUTEX 201}; 202 203struct nouveau_channel { 204 struct drm_device *dev; 205 int id; 206 207 /* references to the channel data structure */ 208 struct kref ref; 209 /* users of the hardware channel resources, the hardware 210 * context will be kicked off when it reaches zero. */ 211 atomic_t users; 212 struct mutex mutex; 213 214 /* owner of this fifo */ 215 struct drm_file *file_priv; 216 /* mapping of the fifo itself */ 217 struct drm_local_map *map; 218 219 /* mapping of the regs controlling the fifo */ 220 void __iomem *user; 221 uint32_t user_get; 222 uint32_t user_put; 223 224 /* Fencing */ 225 struct { 226 /* lock protects the pending list only */ 227 spinlock_t lock; 228 struct list_head pending; 229 uint32_t sequence; 230 uint32_t sequence_ack; 231 atomic_t last_sequence_irq; 232 } fence; 233 234 /* DMA push buffer */ 235 struct nouveau_gpuobj *pushbuf; 236 struct nouveau_bo *pushbuf_bo; 237 uint32_t pushbuf_base; 238 239 /* Notifier memory */ 240 struct nouveau_bo *notifier_bo; 241 struct drm_mm notifier_heap; 242 243 /* PFIFO context */ 244 struct nouveau_gpuobj *ramfc; 245 struct nouveau_gpuobj *cache; 246 void *fifo_priv; 247 248 /* PGRAPH context */ 249 /* XXX may be merge 2 pointers as private data ??? */ 250 struct nouveau_gpuobj *ramin_grctx; 251 struct nouveau_gpuobj *crypt_ctx; 252 void *pgraph_ctx; 253 254 /* NV50 VM */ 255 struct nouveau_vm *vm; 256 struct nouveau_gpuobj *vm_pd; 257 258 /* Objects */ 259 struct nouveau_gpuobj *ramin; /* Private instmem */ 260 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 261 struct nouveau_ramht *ramht; /* Hash table */ 262 263 /* GPU object info for stuff used in-kernel (mm_enabled) */ 264 uint32_t m2mf_ntfy; 265 uint32_t vram_handle; 266 uint32_t gart_handle; 267 bool accel_done; 268 269 /* Push buffer state (only for drm's channel on !mm_enabled) */ 270 struct { 271 int max; 272 int free; 273 int cur; 274 int put; 275 /* access via pushbuf_bo */ 276 277 int ib_base; 278 int ib_max; 279 int ib_free; 280 int ib_put; 281 } dma; 282 283 uint32_t sw_subchannel[8]; 284 285 struct { 286 struct nouveau_gpuobj *vblsem; 287 uint32_t vblsem_head; 288 uint32_t vblsem_offset; 289 uint32_t vblsem_rval; 290 struct list_head vbl_wait; 291 struct list_head flip; 292 } nvsw; 293 294 struct { 295 bool active; 296 char name[32]; 297 struct drm_info_list info; 298 } debugfs; 299}; 300 301struct nouveau_instmem_engine { 302 void *priv; 303 304 int (*init)(struct drm_device *dev); 305 void (*takedown)(struct drm_device *dev); 306 int (*suspend)(struct drm_device *dev); 307 void (*resume)(struct drm_device *dev); 308 309 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 310 void (*put)(struct nouveau_gpuobj *); 311 int (*map)(struct nouveau_gpuobj *); 312 void (*unmap)(struct nouveau_gpuobj *); 313 314 void (*flush)(struct drm_device *); 315}; 316 317struct nouveau_mc_engine { 318 int (*init)(struct drm_device *dev); 319 void (*takedown)(struct drm_device *dev); 320}; 321 322struct nouveau_timer_engine { 323 int (*init)(struct drm_device *dev); 324 void (*takedown)(struct drm_device *dev); 325 uint64_t (*read)(struct drm_device *dev); 326}; 327 328struct nouveau_fb_engine { 329 int num_tiles; 330 struct drm_mm tag_heap; 331 void *priv; 332 333 int (*init)(struct drm_device *dev); 334 void (*takedown)(struct drm_device *dev); 335 336 void (*init_tile_region)(struct drm_device *dev, int i, 337 uint32_t addr, uint32_t size, 338 uint32_t pitch, uint32_t flags); 339 void (*set_tile_region)(struct drm_device *dev, int i); 340 void (*free_tile_region)(struct drm_device *dev, int i); 341}; 342 343struct nouveau_fifo_engine { 344 void *priv; 345 int channels; 346 347 struct nouveau_gpuobj *playlist[2]; 348 int cur_playlist; 349 350 int (*init)(struct drm_device *); 351 void (*takedown)(struct drm_device *); 352 353 void (*disable)(struct drm_device *); 354 void (*enable)(struct drm_device *); 355 bool (*reassign)(struct drm_device *, bool enable); 356 bool (*cache_pull)(struct drm_device *dev, bool enable); 357 358 int (*channel_id)(struct drm_device *); 359 360 int (*create_context)(struct nouveau_channel *); 361 void (*destroy_context)(struct nouveau_channel *); 362 int (*load_context)(struct nouveau_channel *); 363 int (*unload_context)(struct drm_device *); 364 void (*tlb_flush)(struct drm_device *dev); 365}; 366 367struct nouveau_pgraph_engine { 368 bool accel_blocked; 369 bool registered; 370 int grctx_size; 371 void *priv; 372 373 /* NV2x/NV3x context table (0x400780) */ 374 struct nouveau_gpuobj *ctx_table; 375 376 int (*init)(struct drm_device *); 377 void (*takedown)(struct drm_device *); 378 379 void (*fifo_access)(struct drm_device *, bool); 380 381 struct nouveau_channel *(*channel)(struct drm_device *); 382 int (*create_context)(struct nouveau_channel *); 383 void (*destroy_context)(struct nouveau_channel *); 384 int (*load_context)(struct nouveau_channel *); 385 int (*unload_context)(struct drm_device *); 386 int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class); 387 void (*tlb_flush)(struct drm_device *dev); 388 389 void (*set_tile_region)(struct drm_device *dev, int i); 390}; 391 392struct nouveau_display_engine { 393 void *priv; 394 int (*early_init)(struct drm_device *); 395 void (*late_takedown)(struct drm_device *); 396 int (*create)(struct drm_device *); 397 int (*init)(struct drm_device *); 398 void (*destroy)(struct drm_device *); 399}; 400 401struct nouveau_gpio_engine { 402 void *priv; 403 404 int (*init)(struct drm_device *); 405 void (*takedown)(struct drm_device *); 406 407 int (*get)(struct drm_device *, enum dcb_gpio_tag); 408 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 409 410 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 411 void (*)(void *, int), void *); 412 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 413 void (*)(void *, int), void *); 414 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 415}; 416 417struct nouveau_pm_voltage_level { 418 u8 voltage; 419 u8 vid; 420}; 421 422struct nouveau_pm_voltage { 423 bool supported; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430#define NOUVEAU_PM_MAX_LEVEL 8 431struct nouveau_pm_level { 432 struct device_attribute dev_attr; 433 char name[32]; 434 int id; 435 436 u32 core; 437 u32 memory; 438 u32 shader; 439 u32 unk05; 440 441 u8 voltage; 442 u8 fanspeed; 443 444 u16 memscript; 445}; 446 447struct nouveau_pm_temp_sensor_constants { 448 u16 offset_constant; 449 s16 offset_mult; 450 u16 offset_div; 451 u16 slope_mult; 452 u16 slope_div; 453}; 454 455struct nouveau_pm_threshold_temp { 456 s16 critical; 457 s16 down_clock; 458 s16 fan_boost; 459}; 460 461struct nouveau_pm_memtiming { 462 u32 reg_100220; 463 u32 reg_100224; 464 u32 reg_100228; 465 u32 reg_10022c; 466 u32 reg_100230; 467 u32 reg_100234; 468 u32 reg_100238; 469 u32 reg_10023c; 470 u32 reg_100240; 471}; 472 473struct nouveau_pm_memtimings { 474 bool supported; 475 struct nouveau_pm_memtiming *timing; 476 int nr_timing; 477}; 478 479struct nouveau_pm_engine { 480 struct nouveau_pm_voltage voltage; 481 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 482 int nr_perflvl; 483 struct nouveau_pm_memtimings memtimings; 484 struct nouveau_pm_temp_sensor_constants sensor_constants; 485 struct nouveau_pm_threshold_temp threshold_temp; 486 487 struct nouveau_pm_level boot; 488 struct nouveau_pm_level *cur; 489 490 struct device *hwmon; 491 struct notifier_block acpi_nb; 492 493 int (*clock_get)(struct drm_device *, u32 id); 494 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 495 u32 id, int khz); 496 void (*clock_set)(struct drm_device *, void *); 497 int (*voltage_get)(struct drm_device *); 498 int (*voltage_set)(struct drm_device *, int voltage); 499 int (*fanspeed_get)(struct drm_device *); 500 int (*fanspeed_set)(struct drm_device *, int fanspeed); 501 int (*temp_get)(struct drm_device *); 502}; 503 504struct nouveau_crypt_engine { 505 bool registered; 506 507 int (*init)(struct drm_device *); 508 void (*takedown)(struct drm_device *); 509 int (*create_context)(struct nouveau_channel *); 510 void (*destroy_context)(struct nouveau_channel *); 511 int (*object_new)(struct nouveau_channel *, u32 handle, u16 class); 512 void (*tlb_flush)(struct drm_device *dev); 513}; 514 515struct nouveau_vram_engine { 516 int (*init)(struct drm_device *); 517 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 518 u32 type, struct nouveau_mem **); 519 void (*put)(struct drm_device *, struct nouveau_mem **); 520 521 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 522}; 523 524struct nouveau_engine { 525 struct nouveau_instmem_engine instmem; 526 struct nouveau_mc_engine mc; 527 struct nouveau_timer_engine timer; 528 struct nouveau_fb_engine fb; 529 struct nouveau_pgraph_engine graph; 530 struct nouveau_fifo_engine fifo; 531 struct nouveau_display_engine display; 532 struct nouveau_gpio_engine gpio; 533 struct nouveau_pm_engine pm; 534 struct nouveau_crypt_engine crypt; 535 struct nouveau_vram_engine vram; 536}; 537 538struct nouveau_pll_vals { 539 union { 540 struct { 541#ifdef __BIG_ENDIAN 542 uint8_t N1, M1, N2, M2; 543#else 544 uint8_t M1, N1, M2, N2; 545#endif 546 }; 547 struct { 548 uint16_t NM1, NM2; 549 } __attribute__((packed)); 550 }; 551 int log2P; 552 553 int refclk; 554}; 555 556enum nv04_fp_display_regs { 557 FP_DISPLAY_END, 558 FP_TOTAL, 559 FP_CRTC, 560 FP_SYNC_START, 561 FP_SYNC_END, 562 FP_VALID_START, 563 FP_VALID_END 564}; 565 566struct nv04_crtc_reg { 567 unsigned char MiscOutReg; 568 uint8_t CRTC[0xa0]; 569 uint8_t CR58[0x10]; 570 uint8_t Sequencer[5]; 571 uint8_t Graphics[9]; 572 uint8_t Attribute[21]; 573 unsigned char DAC[768]; 574 575 /* PCRTC regs */ 576 uint32_t fb_start; 577 uint32_t crtc_cfg; 578 uint32_t cursor_cfg; 579 uint32_t gpio_ext; 580 uint32_t crtc_830; 581 uint32_t crtc_834; 582 uint32_t crtc_850; 583 uint32_t crtc_eng_ctrl; 584 585 /* PRAMDAC regs */ 586 uint32_t nv10_cursync; 587 struct nouveau_pll_vals pllvals; 588 uint32_t ramdac_gen_ctrl; 589 uint32_t ramdac_630; 590 uint32_t ramdac_634; 591 uint32_t tv_setup; 592 uint32_t tv_vtotal; 593 uint32_t tv_vskew; 594 uint32_t tv_vsync_delay; 595 uint32_t tv_htotal; 596 uint32_t tv_hskew; 597 uint32_t tv_hsync_delay; 598 uint32_t tv_hsync_delay2; 599 uint32_t fp_horiz_regs[7]; 600 uint32_t fp_vert_regs[7]; 601 uint32_t dither; 602 uint32_t fp_control; 603 uint32_t dither_regs[6]; 604 uint32_t fp_debug_0; 605 uint32_t fp_debug_1; 606 uint32_t fp_debug_2; 607 uint32_t fp_margin_color; 608 uint32_t ramdac_8c0; 609 uint32_t ramdac_a20; 610 uint32_t ramdac_a24; 611 uint32_t ramdac_a34; 612 uint32_t ctv_regs[38]; 613}; 614 615struct nv04_output_reg { 616 uint32_t output; 617 int head; 618}; 619 620struct nv04_mode_state { 621 struct nv04_crtc_reg crtc_reg[2]; 622 uint32_t pllsel; 623 uint32_t sel_clk; 624}; 625 626enum nouveau_card_type { 627 NV_04 = 0x00, 628 NV_10 = 0x10, 629 NV_20 = 0x20, 630 NV_30 = 0x30, 631 NV_40 = 0x40, 632 NV_50 = 0x50, 633 NV_C0 = 0xc0, 634}; 635 636struct drm_nouveau_private { 637 struct drm_device *dev; 638 639 /* the card type, takes NV_* as values */ 640 enum nouveau_card_type card_type; 641 /* exact chipset, derived from NV_PMC_BOOT_0 */ 642 int chipset; 643 int stepping; 644 int flags; 645 646 void __iomem *mmio; 647 648 spinlock_t ramin_lock; 649 void __iomem *ramin; 650 u32 ramin_size; 651 u32 ramin_base; 652 bool ramin_available; 653 struct drm_mm ramin_heap; 654 struct list_head gpuobj_list; 655 struct list_head classes; 656 657 struct nouveau_bo *vga_ram; 658 659 /* interrupt handling */ 660 void (*irq_handler[32])(struct drm_device *); 661 bool msi_enabled; 662 663 struct list_head vbl_waiting; 664 665 struct { 666 struct drm_global_reference mem_global_ref; 667 struct ttm_bo_global_ref bo_global_ref; 668 struct ttm_bo_device bdev; 669 atomic_t validate_sequence; 670 } ttm; 671 672 struct { 673 spinlock_t lock; 674 struct drm_mm heap; 675 struct nouveau_bo *bo; 676 } fence; 677 678 struct { 679 spinlock_t lock; 680 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 681 } channels; 682 683 struct nouveau_engine engine; 684 struct nouveau_channel *channel; 685 686 /* For PFIFO and PGRAPH. */ 687 spinlock_t context_switch_lock; 688 689 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 690 spinlock_t vm_lock; 691 692 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 693 struct nouveau_ramht *ramht; 694 struct nouveau_gpuobj *ramfc; 695 struct nouveau_gpuobj *ramro; 696 697 uint32_t ramin_rsvd_vram; 698 699 struct { 700 enum { 701 NOUVEAU_GART_NONE = 0, 702 NOUVEAU_GART_AGP, /* AGP */ 703 NOUVEAU_GART_PDMA, /* paged dma object */ 704 NOUVEAU_GART_HW /* on-chip gart/vm */ 705 } type; 706 uint64_t aper_base; 707 uint64_t aper_size; 708 uint64_t aper_free; 709 710 struct ttm_backend_func *func; 711 712 struct { 713 struct page *page; 714 dma_addr_t addr; 715 } dummy; 716 717 struct nouveau_gpuobj *sg_ctxdma; 718 } gart_info; 719 720 /* nv10-nv40 tiling regions */ 721 struct { 722 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 723 spinlock_t lock; 724 } tile; 725 726 /* VRAM/fb configuration */ 727 uint64_t vram_size; 728 uint64_t vram_sys_base; 729 u32 vram_rblock_size; 730 731 uint64_t fb_phys; 732 uint64_t fb_available_size; 733 uint64_t fb_mappable_pages; 734 uint64_t fb_aper_free; 735 int fb_mtrr; 736 737 /* BAR control (NV50-) */ 738 struct nouveau_vm *bar1_vm; 739 struct nouveau_vm *bar3_vm; 740 741 /* G8x/G9x virtual address space */ 742 struct nouveau_vm *chan_vm; 743 744 struct nvbios vbios; 745 746 struct nv04_mode_state mode_reg; 747 struct nv04_mode_state saved_reg; 748 uint32_t saved_vga_font[4][16384]; 749 uint32_t crtc_owner; 750 uint32_t dac_users[4]; 751 752 struct backlight_device *backlight; 753 754 struct { 755 struct dentry *channel_root; 756 } debugfs; 757 758 struct nouveau_fbdev *nfbdev; 759 struct apertures_struct *apertures; 760}; 761 762static inline struct drm_nouveau_private * 763nouveau_private(struct drm_device *dev) 764{ 765 return dev->dev_private; 766} 767 768static inline struct drm_nouveau_private * 769nouveau_bdev(struct ttm_bo_device *bd) 770{ 771 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 772} 773 774static inline int 775nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 776{ 777 struct nouveau_bo *prev; 778 779 if (!pnvbo) 780 return -EINVAL; 781 prev = *pnvbo; 782 783 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 784 if (prev) { 785 struct ttm_buffer_object *bo = &prev->bo; 786 787 ttm_bo_unref(&bo); 788 } 789 790 return 0; 791} 792 793/* nouveau_drv.c */ 794extern int nouveau_agpmode; 795extern int nouveau_duallink; 796extern int nouveau_uscript_lvds; 797extern int nouveau_uscript_tmds; 798extern int nouveau_vram_pushbuf; 799extern int nouveau_vram_notify; 800extern int nouveau_fbpercrtc; 801extern int nouveau_tv_disable; 802extern char *nouveau_tv_norm; 803extern int nouveau_reg_debug; 804extern char *nouveau_vbios; 805extern int nouveau_ignorelid; 806extern int nouveau_nofbaccel; 807extern int nouveau_noaccel; 808extern int nouveau_force_post; 809extern int nouveau_override_conntype; 810extern char *nouveau_perflvl; 811extern int nouveau_perflvl_wr; 812extern int nouveau_msi; 813 814extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 815extern int nouveau_pci_resume(struct pci_dev *pdev); 816 817/* nouveau_state.c */ 818extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 819extern int nouveau_load(struct drm_device *, unsigned long flags); 820extern int nouveau_firstopen(struct drm_device *); 821extern void nouveau_lastclose(struct drm_device *); 822extern int nouveau_unload(struct drm_device *); 823extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 824 struct drm_file *); 825extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 826 struct drm_file *); 827extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 828 uint32_t reg, uint32_t mask, uint32_t val); 829extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 830 uint32_t reg, uint32_t mask, uint32_t val); 831extern bool nouveau_wait_for_idle(struct drm_device *); 832extern int nouveau_card_init(struct drm_device *); 833 834/* nouveau_mem.c */ 835extern int nouveau_mem_vram_init(struct drm_device *); 836extern void nouveau_mem_vram_fini(struct drm_device *); 837extern int nouveau_mem_gart_init(struct drm_device *); 838extern void nouveau_mem_gart_fini(struct drm_device *); 839extern int nouveau_mem_init_agp(struct drm_device *); 840extern int nouveau_mem_reset_agp(struct drm_device *); 841extern void nouveau_mem_close(struct drm_device *); 842extern int nouveau_mem_detect(struct drm_device *); 843extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 844extern struct nouveau_tile_reg *nv10_mem_set_tiling( 845 struct drm_device *dev, uint32_t addr, uint32_t size, 846 uint32_t pitch, uint32_t flags); 847extern void nv10_mem_put_tile_region(struct drm_device *dev, 848 struct nouveau_tile_reg *tile, 849 struct nouveau_fence *fence); 850extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 851extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 852 853/* nouveau_notifier.c */ 854extern int nouveau_notifier_init_channel(struct nouveau_channel *); 855extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 856extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 857 int cout, uint32_t start, uint32_t end, 858 uint32_t *offset); 859extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 860extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 861 struct drm_file *); 862extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 863 struct drm_file *); 864 865/* nouveau_channel.c */ 866extern struct drm_ioctl_desc nouveau_ioctls[]; 867extern int nouveau_max_ioctl; 868extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 869extern int nouveau_channel_alloc(struct drm_device *dev, 870 struct nouveau_channel **chan, 871 struct drm_file *file_priv, 872 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 873extern struct nouveau_channel * 874nouveau_channel_get_unlocked(struct nouveau_channel *); 875extern struct nouveau_channel * 876nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 877extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 878extern void nouveau_channel_put(struct nouveau_channel **); 879extern void nouveau_channel_ref(struct nouveau_channel *chan, 880 struct nouveau_channel **pchan); 881extern void nouveau_channel_idle(struct nouveau_channel *chan); 882 883/* nouveau_object.c */ 884#define NVOBJ_CLASS(d, c, e) do { \ 885 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 886 if (ret) \ 887 return ret; \ 888} while (0) 889 890#define NVOBJ_MTHD(d, c, m, e) do { \ 891 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 892 if (ret) \ 893 return ret; \ 894} while (0) 895 896extern int nouveau_gpuobj_early_init(struct drm_device *); 897extern int nouveau_gpuobj_init(struct drm_device *); 898extern void nouveau_gpuobj_takedown(struct drm_device *); 899extern int nouveau_gpuobj_suspend(struct drm_device *dev); 900extern void nouveau_gpuobj_resume(struct drm_device *dev); 901extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 902extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 903 int (*exec)(struct nouveau_channel *, 904 u32 class, u32 mthd, u32 data)); 905extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 906extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 907extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 908 uint32_t vram_h, uint32_t tt_h); 909extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 910extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 911 uint32_t size, int align, uint32_t flags, 912 struct nouveau_gpuobj **); 913extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 914 struct nouveau_gpuobj **); 915extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 916 u32 size, u32 flags, 917 struct nouveau_gpuobj **); 918extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 919 uint64_t offset, uint64_t size, int access, 920 int target, struct nouveau_gpuobj **); 921extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 922extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 923 u64 size, int target, int access, u32 type, 924 u32 comp, struct nouveau_gpuobj **pobj); 925extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 926 int class, u64 base, u64 size, int target, 927 int access, u32 type, u32 comp); 928extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 929 struct drm_file *); 930extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 931 struct drm_file *); 932 933/* nouveau_irq.c */ 934extern int nouveau_irq_init(struct drm_device *); 935extern void nouveau_irq_fini(struct drm_device *); 936extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 937extern void nouveau_irq_register(struct drm_device *, int status_bit, 938 void (*)(struct drm_device *)); 939extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 940extern void nouveau_irq_preinstall(struct drm_device *); 941extern int nouveau_irq_postinstall(struct drm_device *); 942extern void nouveau_irq_uninstall(struct drm_device *); 943 944/* nouveau_sgdma.c */ 945extern int nouveau_sgdma_init(struct drm_device *); 946extern void nouveau_sgdma_takedown(struct drm_device *); 947extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 948 uint32_t offset); 949extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 950 951/* nouveau_debugfs.c */ 952#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 953extern int nouveau_debugfs_init(struct drm_minor *); 954extern void nouveau_debugfs_takedown(struct drm_minor *); 955extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 956extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 957#else 958static inline int 959nouveau_debugfs_init(struct drm_minor *minor) 960{ 961 return 0; 962} 963 964static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 965{ 966} 967 968static inline int 969nouveau_debugfs_channel_init(struct nouveau_channel *chan) 970{ 971 return 0; 972} 973 974static inline void 975nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 976{ 977} 978#endif 979 980/* nouveau_dma.c */ 981extern void nouveau_dma_pre_init(struct nouveau_channel *); 982extern int nouveau_dma_init(struct nouveau_channel *); 983extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 984 985/* nouveau_acpi.c */ 986#define ROM_BIOS_PAGE 4096 987#if defined(CONFIG_ACPI) 988void nouveau_register_dsm_handler(void); 989void nouveau_unregister_dsm_handler(void); 990int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 991bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 992int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 993#else 994static inline void nouveau_register_dsm_handler(void) {} 995static inline void nouveau_unregister_dsm_handler(void) {} 996static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 997static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 998static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 999#endif 1000 1001/* nouveau_backlight.c */ 1002#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1003extern int nouveau_backlight_init(struct drm_connector *); 1004extern void nouveau_backlight_exit(struct drm_connector *); 1005#else 1006static inline int nouveau_backlight_init(struct drm_connector *dev) 1007{ 1008 return 0; 1009} 1010 1011static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1012#endif 1013 1014/* nouveau_bios.c */ 1015extern int nouveau_bios_init(struct drm_device *); 1016extern void nouveau_bios_takedown(struct drm_device *dev); 1017extern int nouveau_run_vbios_init(struct drm_device *); 1018extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1019 struct dcb_entry *); 1020extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1021 enum dcb_gpio_tag); 1022extern struct dcb_connector_table_entry * 1023nouveau_bios_connector_entry(struct drm_device *, int index); 1024extern u32 get_pll_register(struct drm_device *, enum pll_types); 1025extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1026 struct pll_lims *); 1027extern int nouveau_bios_run_display_table(struct drm_device *, 1028 struct dcb_entry *, 1029 uint32_t script, int pxclk); 1030extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1031 int *length); 1032extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1033extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1034extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1035 bool *dl, bool *if_is_24bit); 1036extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1037 int head, int pxclk); 1038extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1039 enum LVDS_script, int pxclk); 1040 1041/* nouveau_ttm.c */ 1042int nouveau_ttm_global_init(struct drm_nouveau_private *); 1043void nouveau_ttm_global_release(struct drm_nouveau_private *); 1044int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1045 1046/* nouveau_dp.c */ 1047int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1048 uint8_t *data, int data_nr); 1049bool nouveau_dp_detect(struct drm_encoder *); 1050bool nouveau_dp_link_train(struct drm_encoder *); 1051 1052/* nv04_fb.c */ 1053extern int nv04_fb_init(struct drm_device *); 1054extern void nv04_fb_takedown(struct drm_device *); 1055 1056/* nv10_fb.c */ 1057extern int nv10_fb_init(struct drm_device *); 1058extern void nv10_fb_takedown(struct drm_device *); 1059extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1060 uint32_t addr, uint32_t size, 1061 uint32_t pitch, uint32_t flags); 1062extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1063extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1064 1065/* nv30_fb.c */ 1066extern int nv30_fb_init(struct drm_device *); 1067extern void nv30_fb_takedown(struct drm_device *); 1068extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1069 uint32_t addr, uint32_t size, 1070 uint32_t pitch, uint32_t flags); 1071extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1072 1073/* nv40_fb.c */ 1074extern int nv40_fb_init(struct drm_device *); 1075extern void nv40_fb_takedown(struct drm_device *); 1076extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1077 1078/* nv50_fb.c */ 1079extern int nv50_fb_init(struct drm_device *); 1080extern void nv50_fb_takedown(struct drm_device *); 1081extern void nv50_fb_vm_trap(struct drm_device *, int display); 1082 1083/* nvc0_fb.c */ 1084extern int nvc0_fb_init(struct drm_device *); 1085extern void nvc0_fb_takedown(struct drm_device *); 1086 1087/* nv04_fifo.c */ 1088extern int nv04_fifo_init(struct drm_device *); 1089extern void nv04_fifo_fini(struct drm_device *); 1090extern void nv04_fifo_disable(struct drm_device *); 1091extern void nv04_fifo_enable(struct drm_device *); 1092extern bool nv04_fifo_reassign(struct drm_device *, bool); 1093extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1094extern int nv04_fifo_channel_id(struct drm_device *); 1095extern int nv04_fifo_create_context(struct nouveau_channel *); 1096extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1097extern int nv04_fifo_load_context(struct nouveau_channel *); 1098extern int nv04_fifo_unload_context(struct drm_device *); 1099extern void nv04_fifo_isr(struct drm_device *); 1100 1101/* nv10_fifo.c */ 1102extern int nv10_fifo_init(struct drm_device *); 1103extern int nv10_fifo_channel_id(struct drm_device *); 1104extern int nv10_fifo_create_context(struct nouveau_channel *); 1105extern int nv10_fifo_load_context(struct nouveau_channel *); 1106extern int nv10_fifo_unload_context(struct drm_device *); 1107 1108/* nv40_fifo.c */ 1109extern int nv40_fifo_init(struct drm_device *); 1110extern int nv40_fifo_create_context(struct nouveau_channel *); 1111extern int nv40_fifo_load_context(struct nouveau_channel *); 1112extern int nv40_fifo_unload_context(struct drm_device *); 1113 1114/* nv50_fifo.c */ 1115extern int nv50_fifo_init(struct drm_device *); 1116extern void nv50_fifo_takedown(struct drm_device *); 1117extern int nv50_fifo_channel_id(struct drm_device *); 1118extern int nv50_fifo_create_context(struct nouveau_channel *); 1119extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1120extern int nv50_fifo_load_context(struct nouveau_channel *); 1121extern int nv50_fifo_unload_context(struct drm_device *); 1122extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1123 1124/* nvc0_fifo.c */ 1125extern int nvc0_fifo_init(struct drm_device *); 1126extern void nvc0_fifo_takedown(struct drm_device *); 1127extern void nvc0_fifo_disable(struct drm_device *); 1128extern void nvc0_fifo_enable(struct drm_device *); 1129extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1130extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1131extern int nvc0_fifo_channel_id(struct drm_device *); 1132extern int nvc0_fifo_create_context(struct nouveau_channel *); 1133extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1134extern int nvc0_fifo_load_context(struct nouveau_channel *); 1135extern int nvc0_fifo_unload_context(struct drm_device *); 1136 1137/* nv04_graph.c */ 1138extern int nv04_graph_init(struct drm_device *); 1139extern void nv04_graph_takedown(struct drm_device *); 1140extern void nv04_graph_fifo_access(struct drm_device *, bool); 1141extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1142extern int nv04_graph_create_context(struct nouveau_channel *); 1143extern void nv04_graph_destroy_context(struct nouveau_channel *); 1144extern int nv04_graph_load_context(struct nouveau_channel *); 1145extern int nv04_graph_unload_context(struct drm_device *); 1146extern int nv04_graph_object_new(struct nouveau_channel *, u32, u16); 1147extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1148 u32 class, u32 mthd, u32 data); 1149extern struct nouveau_bitfield nv04_graph_nsource[]; 1150 1151/* nv10_graph.c */ 1152extern int nv10_graph_init(struct drm_device *); 1153extern void nv10_graph_takedown(struct drm_device *); 1154extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1155extern int nv10_graph_create_context(struct nouveau_channel *); 1156extern void nv10_graph_destroy_context(struct nouveau_channel *); 1157extern int nv10_graph_load_context(struct nouveau_channel *); 1158extern int nv10_graph_unload_context(struct drm_device *); 1159extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1160extern struct nouveau_bitfield nv10_graph_intr[]; 1161extern struct nouveau_bitfield nv10_graph_nstatus[]; 1162 1163/* nv20_graph.c */ 1164extern int nv20_graph_create_context(struct nouveau_channel *); 1165extern void nv20_graph_destroy_context(struct nouveau_channel *); 1166extern int nv20_graph_load_context(struct nouveau_channel *); 1167extern int nv20_graph_unload_context(struct drm_device *); 1168extern int nv20_graph_init(struct drm_device *); 1169extern void nv20_graph_takedown(struct drm_device *); 1170extern int nv30_graph_init(struct drm_device *); 1171extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1172 1173/* nv40_graph.c */ 1174extern int nv40_graph_init(struct drm_device *); 1175extern void nv40_graph_takedown(struct drm_device *); 1176extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1177extern int nv40_graph_create_context(struct nouveau_channel *); 1178extern void nv40_graph_destroy_context(struct nouveau_channel *); 1179extern int nv40_graph_load_context(struct nouveau_channel *); 1180extern int nv40_graph_unload_context(struct drm_device *); 1181extern int nv40_graph_object_new(struct nouveau_channel *, u32, u16); 1182extern void nv40_grctx_init(struct nouveau_grctx *); 1183extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1184 1185/* nv50_graph.c */ 1186extern int nv50_graph_init(struct drm_device *); 1187extern void nv50_graph_takedown(struct drm_device *); 1188extern void nv50_graph_fifo_access(struct drm_device *, bool); 1189extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1190extern int nv50_graph_create_context(struct nouveau_channel *); 1191extern void nv50_graph_destroy_context(struct nouveau_channel *); 1192extern int nv50_graph_load_context(struct nouveau_channel *); 1193extern int nv50_graph_unload_context(struct drm_device *); 1194extern int nv50_graph_object_new(struct nouveau_channel *, u32, u16); 1195extern int nv50_grctx_init(struct nouveau_grctx *); 1196extern void nv50_graph_tlb_flush(struct drm_device *dev); 1197extern void nv84_graph_tlb_flush(struct drm_device *dev); 1198extern struct nouveau_enum nv50_data_error_names[]; 1199 1200/* nvc0_graph.c */ 1201extern int nvc0_graph_init(struct drm_device *); 1202extern void nvc0_graph_takedown(struct drm_device *); 1203extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1204extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1205extern int nvc0_graph_create_context(struct nouveau_channel *); 1206extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1207extern int nvc0_graph_load_context(struct nouveau_channel *); 1208extern int nvc0_graph_unload_context(struct drm_device *); 1209extern int nvc0_graph_object_new(struct nouveau_channel *, u32, u16); 1210 1211/* nv84_crypt.c */ 1212extern int nv84_crypt_init(struct drm_device *dev); 1213extern void nv84_crypt_fini(struct drm_device *dev); 1214extern int nv84_crypt_create_context(struct nouveau_channel *); 1215extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1216extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1217extern int nv84_crypt_object_new(struct nouveau_channel *, u32, u16); 1218 1219/* nv04_instmem.c */ 1220extern int nv04_instmem_init(struct drm_device *); 1221extern void nv04_instmem_takedown(struct drm_device *); 1222extern int nv04_instmem_suspend(struct drm_device *); 1223extern void nv04_instmem_resume(struct drm_device *); 1224extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1225extern void nv04_instmem_put(struct nouveau_gpuobj *); 1226extern int nv04_instmem_map(struct nouveau_gpuobj *); 1227extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1228extern void nv04_instmem_flush(struct drm_device *); 1229 1230/* nv50_instmem.c */ 1231extern int nv50_instmem_init(struct drm_device *); 1232extern void nv50_instmem_takedown(struct drm_device *); 1233extern int nv50_instmem_suspend(struct drm_device *); 1234extern void nv50_instmem_resume(struct drm_device *); 1235extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1236extern void nv50_instmem_put(struct nouveau_gpuobj *); 1237extern int nv50_instmem_map(struct nouveau_gpuobj *); 1238extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1239extern void nv50_instmem_flush(struct drm_device *); 1240extern void nv84_instmem_flush(struct drm_device *); 1241 1242/* nvc0_instmem.c */ 1243extern int nvc0_instmem_init(struct drm_device *); 1244extern void nvc0_instmem_takedown(struct drm_device *); 1245extern int nvc0_instmem_suspend(struct drm_device *); 1246extern void nvc0_instmem_resume(struct drm_device *); 1247 1248/* nv04_mc.c */ 1249extern int nv04_mc_init(struct drm_device *); 1250extern void nv04_mc_takedown(struct drm_device *); 1251 1252/* nv40_mc.c */ 1253extern int nv40_mc_init(struct drm_device *); 1254extern void nv40_mc_takedown(struct drm_device *); 1255 1256/* nv50_mc.c */ 1257extern int nv50_mc_init(struct drm_device *); 1258extern void nv50_mc_takedown(struct drm_device *); 1259 1260/* nv04_timer.c */ 1261extern int nv04_timer_init(struct drm_device *); 1262extern uint64_t nv04_timer_read(struct drm_device *); 1263extern void nv04_timer_takedown(struct drm_device *); 1264 1265extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1266 unsigned long arg); 1267 1268/* nv04_dac.c */ 1269extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1270extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1271extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1272extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1273extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1274 1275/* nv04_dfp.c */ 1276extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1277extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1278extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1279 int head, bool dl); 1280extern void nv04_dfp_disable(struct drm_device *dev, int head); 1281extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1282 1283/* nv04_tv.c */ 1284extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1285extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1286 1287/* nv17_tv.c */ 1288extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1289 1290/* nv04_display.c */ 1291extern int nv04_display_early_init(struct drm_device *); 1292extern void nv04_display_late_takedown(struct drm_device *); 1293extern int nv04_display_create(struct drm_device *); 1294extern int nv04_display_init(struct drm_device *); 1295extern void nv04_display_destroy(struct drm_device *); 1296 1297/* nv04_crtc.c */ 1298extern int nv04_crtc_create(struct drm_device *, int index); 1299 1300/* nouveau_bo.c */ 1301extern struct ttm_bo_driver nouveau_bo_driver; 1302extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1303 int size, int align, uint32_t flags, 1304 uint32_t tile_mode, uint32_t tile_flags, 1305 struct nouveau_bo **); 1306extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1307extern int nouveau_bo_unpin(struct nouveau_bo *); 1308extern int nouveau_bo_map(struct nouveau_bo *); 1309extern void nouveau_bo_unmap(struct nouveau_bo *); 1310extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1311 uint32_t busy); 1312extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1313extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1314extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1315extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1316extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1317extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1318 bool no_wait_reserve, bool no_wait_gpu); 1319 1320/* nouveau_fence.c */ 1321struct nouveau_fence; 1322extern int nouveau_fence_init(struct drm_device *); 1323extern void nouveau_fence_fini(struct drm_device *); 1324extern int nouveau_fence_channel_init(struct nouveau_channel *); 1325extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1326extern void nouveau_fence_update(struct nouveau_channel *); 1327extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1328 bool emit); 1329extern int nouveau_fence_emit(struct nouveau_fence *); 1330extern void nouveau_fence_work(struct nouveau_fence *fence, 1331 void (*work)(void *priv, bool signalled), 1332 void *priv); 1333struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1334 1335extern bool __nouveau_fence_signalled(void *obj, void *arg); 1336extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1337extern int __nouveau_fence_flush(void *obj, void *arg); 1338extern void __nouveau_fence_unref(void **obj); 1339extern void *__nouveau_fence_ref(void *obj); 1340 1341static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1342{ 1343 return __nouveau_fence_signalled(obj, NULL); 1344} 1345static inline int 1346nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1347{ 1348 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1349} 1350extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1351static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1352{ 1353 return __nouveau_fence_flush(obj, NULL); 1354} 1355static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1356{ 1357 __nouveau_fence_unref((void **)obj); 1358} 1359static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1360{ 1361 return __nouveau_fence_ref(obj); 1362} 1363 1364/* nouveau_gem.c */ 1365extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1366 int size, int align, uint32_t domain, 1367 uint32_t tile_mode, uint32_t tile_flags, 1368 struct nouveau_bo **); 1369extern int nouveau_gem_object_new(struct drm_gem_object *); 1370extern void nouveau_gem_object_del(struct drm_gem_object *); 1371extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1372 struct drm_file *); 1373extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1374 struct drm_file *); 1375extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1376 struct drm_file *); 1377extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1378 struct drm_file *); 1379extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1380 struct drm_file *); 1381 1382/* nouveau_display.c */ 1383int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1384void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1385int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1386 struct drm_pending_vblank_event *event); 1387int nouveau_finish_page_flip(struct nouveau_channel *, 1388 struct nouveau_page_flip_state *); 1389 1390/* nv10_gpio.c */ 1391int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1392int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1393 1394/* nv50_gpio.c */ 1395int nv50_gpio_init(struct drm_device *dev); 1396void nv50_gpio_fini(struct drm_device *dev); 1397int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1398int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1399int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1400 void (*)(void *, int), void *); 1401void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1402 void (*)(void *, int), void *); 1403bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1404 1405/* nv50_calc. */ 1406int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1407 int *N1, int *M1, int *N2, int *M2, int *P); 1408int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1409 int clk, int *N, int *fN, int *M, int *P); 1410 1411#ifndef ioread32_native 1412#ifdef __BIG_ENDIAN 1413#define ioread16_native ioread16be 1414#define iowrite16_native iowrite16be 1415#define ioread32_native ioread32be 1416#define iowrite32_native iowrite32be 1417#else /* def __BIG_ENDIAN */ 1418#define ioread16_native ioread16 1419#define iowrite16_native iowrite16 1420#define ioread32_native ioread32 1421#define iowrite32_native iowrite32 1422#endif /* def __BIG_ENDIAN else */ 1423#endif /* !ioread32_native */ 1424 1425/* channel control reg access */ 1426static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1427{ 1428 return ioread32_native(chan->user + reg); 1429} 1430 1431static inline void nvchan_wr32(struct nouveau_channel *chan, 1432 unsigned reg, u32 val) 1433{ 1434 iowrite32_native(val, chan->user + reg); 1435} 1436 1437/* register access */ 1438static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 return ioread32_native(dev_priv->mmio + reg); 1442} 1443 1444static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1445{ 1446 struct drm_nouveau_private *dev_priv = dev->dev_private; 1447 iowrite32_native(val, dev_priv->mmio + reg); 1448} 1449 1450static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1451{ 1452 u32 tmp = nv_rd32(dev, reg); 1453 nv_wr32(dev, reg, (tmp & ~mask) | val); 1454 return tmp; 1455} 1456 1457static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1458{ 1459 struct drm_nouveau_private *dev_priv = dev->dev_private; 1460 return ioread8(dev_priv->mmio + reg); 1461} 1462 1463static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1464{ 1465 struct drm_nouveau_private *dev_priv = dev->dev_private; 1466 iowrite8(val, dev_priv->mmio + reg); 1467} 1468 1469#define nv_wait(dev, reg, mask, val) \ 1470 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1471#define nv_wait_ne(dev, reg, mask, val) \ 1472 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1473 1474/* PRAMIN access */ 1475static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1476{ 1477 struct drm_nouveau_private *dev_priv = dev->dev_private; 1478 return ioread32_native(dev_priv->ramin + offset); 1479} 1480 1481static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1482{ 1483 struct drm_nouveau_private *dev_priv = dev->dev_private; 1484 iowrite32_native(val, dev_priv->ramin + offset); 1485} 1486 1487/* object access */ 1488extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1489extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1490 1491/* 1492 * Logging 1493 * Argument d is (struct drm_device *). 1494 */ 1495#define NV_PRINTK(level, d, fmt, arg...) \ 1496 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1497 pci_name(d->pdev), ##arg) 1498#ifndef NV_DEBUG_NOTRACE 1499#define NV_DEBUG(d, fmt, arg...) do { \ 1500 if (drm_debug & DRM_UT_DRIVER) { \ 1501 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1502 __LINE__, ##arg); \ 1503 } \ 1504} while (0) 1505#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1506 if (drm_debug & DRM_UT_KMS) { \ 1507 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1508 __LINE__, ##arg); \ 1509 } \ 1510} while (0) 1511#else 1512#define NV_DEBUG(d, fmt, arg...) do { \ 1513 if (drm_debug & DRM_UT_DRIVER) \ 1514 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1515} while (0) 1516#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1517 if (drm_debug & DRM_UT_KMS) \ 1518 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1519} while (0) 1520#endif 1521#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1522#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1523#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1524#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1525#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1526 1527/* nouveau_reg_debug bitmask */ 1528enum { 1529 NOUVEAU_REG_DEBUG_MC = 0x1, 1530 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1531 NOUVEAU_REG_DEBUG_FB = 0x4, 1532 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1533 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1534 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1535 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1536 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1537 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1538 NOUVEAU_REG_DEBUG_EVO = 0x200, 1539}; 1540 1541#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1542 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1543 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1544} while (0) 1545 1546static inline bool 1547nv_two_heads(struct drm_device *dev) 1548{ 1549 struct drm_nouveau_private *dev_priv = dev->dev_private; 1550 const int impl = dev->pci_device & 0x0ff0; 1551 1552 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1553 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1554 return true; 1555 1556 return false; 1557} 1558 1559static inline bool 1560nv_gf4_disp_arch(struct drm_device *dev) 1561{ 1562 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1563} 1564 1565static inline bool 1566nv_two_reg_pll(struct drm_device *dev) 1567{ 1568 struct drm_nouveau_private *dev_priv = dev->dev_private; 1569 const int impl = dev->pci_device & 0x0ff0; 1570 1571 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1572 return true; 1573 return false; 1574} 1575 1576static inline bool 1577nv_match_device(struct drm_device *dev, unsigned device, 1578 unsigned sub_vendor, unsigned sub_device) 1579{ 1580 return dev->pdev->device == device && 1581 dev->pdev->subsystem_vendor == sub_vendor && 1582 dev->pdev->subsystem_device == sub_device; 1583} 1584 1585/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1586 * helpful to determine a number of other hardware features 1587 */ 1588static inline int 1589nv44_graph_class(struct drm_device *dev) 1590{ 1591 struct drm_nouveau_private *dev_priv = dev->dev_private; 1592 1593 if ((dev_priv->chipset & 0xf0) == 0x60) 1594 return 1; 1595 1596 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1597} 1598 1599/* memory type/access flags, do not match hardware values */ 1600#define NV_MEM_ACCESS_RO 1 1601#define NV_MEM_ACCESS_WO 2 1602#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1603#define NV_MEM_ACCESS_SYS 4 1604#define NV_MEM_ACCESS_VM 8 1605 1606#define NV_MEM_TARGET_VRAM 0 1607#define NV_MEM_TARGET_PCI 1 1608#define NV_MEM_TARGET_PCI_NOSNOOP 2 1609#define NV_MEM_TARGET_VM 3 1610#define NV_MEM_TARGET_GART 4 1611 1612#define NV_MEM_TYPE_VM 0x7f 1613#define NV_MEM_COMP_VM 0x03 1614 1615/* NV_SW object class */ 1616#define NV_SW 0x0000506e 1617#define NV_SW_DMA_SEMAPHORE 0x00000060 1618#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1619#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1620#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1621#define NV_SW_YIELD 0x00000080 1622#define NV_SW_DMA_VBLSEM 0x0000018c 1623#define NV_SW_VBLSEM_OFFSET 0x00000400 1624#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1625#define NV_SW_VBLSEM_RELEASE 0x00000408 1626#define NV_SW_PAGE_FLIP 0x00000500 1627 1628#endif /* __NOUVEAU_DRV_H__ */ 1629