nouveau_drv.h revision 2e9733ff7d4f1c7185bea16041f532d6142ca40a
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_100220; 433 u32 reg_100224; 434 u32 reg_100228; 435 u32 reg_10022c; 436 u32 reg_100230; 437 u32 reg_100234; 438 u32 reg_100238; 439 u32 reg_10023c; 440 u32 reg_100240; 441}; 442 443#define NOUVEAU_PM_MAX_LEVEL 8 444struct nouveau_pm_level { 445 struct device_attribute dev_attr; 446 char name[32]; 447 int id; 448 449 u32 core; 450 u32 memory; 451 u32 shader; 452 u32 rop; 453 u32 copy; 454 u32 daemon; 455 u32 vdec; 456 u32 unk05; /* nv50:nva3, roughly.. */ 457 u32 unka0; /* nva3:nvc0 */ 458 u32 hub01; /* nvc0- */ 459 u32 hub06; /* nvc0- */ 460 u32 hub07; /* nvc0- */ 461 462 u32 volt_min; /* microvolts */ 463 u32 volt_max; 464 u8 fanspeed; 465 466 u16 memscript; 467 struct nouveau_pm_memtiming *timing; 468}; 469 470struct nouveau_pm_temp_sensor_constants { 471 u16 offset_constant; 472 s16 offset_mult; 473 s16 offset_div; 474 s16 slope_mult; 475 s16 slope_div; 476}; 477 478struct nouveau_pm_threshold_temp { 479 s16 critical; 480 s16 down_clock; 481 s16 fan_boost; 482}; 483 484struct nouveau_pm_memtimings { 485 bool supported; 486 struct nouveau_pm_memtiming *timing; 487 int nr_timing; 488}; 489 490struct nouveau_pm_engine { 491 struct nouveau_pm_voltage voltage; 492 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 493 int nr_perflvl; 494 struct nouveau_pm_memtimings memtimings; 495 struct nouveau_pm_temp_sensor_constants sensor_constants; 496 struct nouveau_pm_threshold_temp threshold_temp; 497 498 struct nouveau_pm_level boot; 499 struct nouveau_pm_level *cur; 500 501 struct device *hwmon; 502 struct notifier_block acpi_nb; 503 504 int (*clock_get)(struct drm_device *, u32 id); 505 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 506 u32 id, int khz); 507 void (*clock_set)(struct drm_device *, void *); 508 509 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 510 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 511 void (*clocks_set)(struct drm_device *, void *); 512 513 int (*voltage_get)(struct drm_device *); 514 int (*voltage_set)(struct drm_device *, int voltage); 515 int (*fanspeed_get)(struct drm_device *); 516 int (*fanspeed_set)(struct drm_device *, int fanspeed); 517 int (*temp_get)(struct drm_device *); 518}; 519 520struct nouveau_vram_engine { 521 struct nouveau_mm mm; 522 523 int (*init)(struct drm_device *); 524 void (*takedown)(struct drm_device *dev); 525 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 526 u32 type, struct nouveau_mem **); 527 void (*put)(struct drm_device *, struct nouveau_mem **); 528 529 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 530}; 531 532struct nouveau_engine { 533 struct nouveau_instmem_engine instmem; 534 struct nouveau_mc_engine mc; 535 struct nouveau_timer_engine timer; 536 struct nouveau_fb_engine fb; 537 struct nouveau_fifo_engine fifo; 538 struct nouveau_display_engine display; 539 struct nouveau_gpio_engine gpio; 540 struct nouveau_pm_engine pm; 541 struct nouveau_vram_engine vram; 542}; 543 544struct nouveau_pll_vals { 545 union { 546 struct { 547#ifdef __BIG_ENDIAN 548 uint8_t N1, M1, N2, M2; 549#else 550 uint8_t M1, N1, M2, N2; 551#endif 552 }; 553 struct { 554 uint16_t NM1, NM2; 555 } __attribute__((packed)); 556 }; 557 int log2P; 558 559 int refclk; 560}; 561 562enum nv04_fp_display_regs { 563 FP_DISPLAY_END, 564 FP_TOTAL, 565 FP_CRTC, 566 FP_SYNC_START, 567 FP_SYNC_END, 568 FP_VALID_START, 569 FP_VALID_END 570}; 571 572struct nv04_crtc_reg { 573 unsigned char MiscOutReg; 574 uint8_t CRTC[0xa0]; 575 uint8_t CR58[0x10]; 576 uint8_t Sequencer[5]; 577 uint8_t Graphics[9]; 578 uint8_t Attribute[21]; 579 unsigned char DAC[768]; 580 581 /* PCRTC regs */ 582 uint32_t fb_start; 583 uint32_t crtc_cfg; 584 uint32_t cursor_cfg; 585 uint32_t gpio_ext; 586 uint32_t crtc_830; 587 uint32_t crtc_834; 588 uint32_t crtc_850; 589 uint32_t crtc_eng_ctrl; 590 591 /* PRAMDAC regs */ 592 uint32_t nv10_cursync; 593 struct nouveau_pll_vals pllvals; 594 uint32_t ramdac_gen_ctrl; 595 uint32_t ramdac_630; 596 uint32_t ramdac_634; 597 uint32_t tv_setup; 598 uint32_t tv_vtotal; 599 uint32_t tv_vskew; 600 uint32_t tv_vsync_delay; 601 uint32_t tv_htotal; 602 uint32_t tv_hskew; 603 uint32_t tv_hsync_delay; 604 uint32_t tv_hsync_delay2; 605 uint32_t fp_horiz_regs[7]; 606 uint32_t fp_vert_regs[7]; 607 uint32_t dither; 608 uint32_t fp_control; 609 uint32_t dither_regs[6]; 610 uint32_t fp_debug_0; 611 uint32_t fp_debug_1; 612 uint32_t fp_debug_2; 613 uint32_t fp_margin_color; 614 uint32_t ramdac_8c0; 615 uint32_t ramdac_a20; 616 uint32_t ramdac_a24; 617 uint32_t ramdac_a34; 618 uint32_t ctv_regs[38]; 619}; 620 621struct nv04_output_reg { 622 uint32_t output; 623 int head; 624}; 625 626struct nv04_mode_state { 627 struct nv04_crtc_reg crtc_reg[2]; 628 uint32_t pllsel; 629 uint32_t sel_clk; 630}; 631 632enum nouveau_card_type { 633 NV_04 = 0x00, 634 NV_10 = 0x10, 635 NV_20 = 0x20, 636 NV_30 = 0x30, 637 NV_40 = 0x40, 638 NV_50 = 0x50, 639 NV_C0 = 0xc0, 640 NV_D0 = 0xd0 641}; 642 643struct drm_nouveau_private { 644 struct drm_device *dev; 645 bool noaccel; 646 647 /* the card type, takes NV_* as values */ 648 enum nouveau_card_type card_type; 649 /* exact chipset, derived from NV_PMC_BOOT_0 */ 650 int chipset; 651 int stepping; 652 int flags; 653 654 void __iomem *mmio; 655 656 spinlock_t ramin_lock; 657 void __iomem *ramin; 658 u32 ramin_size; 659 u32 ramin_base; 660 bool ramin_available; 661 struct drm_mm ramin_heap; 662 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 663 struct list_head gpuobj_list; 664 struct list_head classes; 665 666 struct nouveau_bo *vga_ram; 667 668 /* interrupt handling */ 669 void (*irq_handler[32])(struct drm_device *); 670 bool msi_enabled; 671 672 struct list_head vbl_waiting; 673 674 struct { 675 struct drm_global_reference mem_global_ref; 676 struct ttm_bo_global_ref bo_global_ref; 677 struct ttm_bo_device bdev; 678 atomic_t validate_sequence; 679 } ttm; 680 681 struct { 682 spinlock_t lock; 683 struct drm_mm heap; 684 struct nouveau_bo *bo; 685 } fence; 686 687 struct { 688 spinlock_t lock; 689 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 690 } channels; 691 692 struct nouveau_engine engine; 693 struct nouveau_channel *channel; 694 695 /* For PFIFO and PGRAPH. */ 696 spinlock_t context_switch_lock; 697 698 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 699 spinlock_t vm_lock; 700 701 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 702 struct nouveau_ramht *ramht; 703 struct nouveau_gpuobj *ramfc; 704 struct nouveau_gpuobj *ramro; 705 706 uint32_t ramin_rsvd_vram; 707 708 struct { 709 enum { 710 NOUVEAU_GART_NONE = 0, 711 NOUVEAU_GART_AGP, /* AGP */ 712 NOUVEAU_GART_PDMA, /* paged dma object */ 713 NOUVEAU_GART_HW /* on-chip gart/vm */ 714 } type; 715 uint64_t aper_base; 716 uint64_t aper_size; 717 uint64_t aper_free; 718 719 struct ttm_backend_func *func; 720 721 struct { 722 struct page *page; 723 dma_addr_t addr; 724 } dummy; 725 726 struct nouveau_gpuobj *sg_ctxdma; 727 } gart_info; 728 729 /* nv10-nv40 tiling regions */ 730 struct { 731 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 732 spinlock_t lock; 733 } tile; 734 735 /* VRAM/fb configuration */ 736 uint64_t vram_size; 737 uint64_t vram_sys_base; 738 739 uint64_t fb_phys; 740 uint64_t fb_available_size; 741 uint64_t fb_mappable_pages; 742 uint64_t fb_aper_free; 743 int fb_mtrr; 744 745 /* BAR control (NV50-) */ 746 struct nouveau_vm *bar1_vm; 747 struct nouveau_vm *bar3_vm; 748 749 /* G8x/G9x virtual address space */ 750 struct nouveau_vm *chan_vm; 751 752 struct nvbios vbios; 753 754 struct nv04_mode_state mode_reg; 755 struct nv04_mode_state saved_reg; 756 uint32_t saved_vga_font[4][16384]; 757 uint32_t crtc_owner; 758 uint32_t dac_users[4]; 759 760 struct backlight_device *backlight; 761 762 struct { 763 struct dentry *channel_root; 764 } debugfs; 765 766 struct nouveau_fbdev *nfbdev; 767 struct apertures_struct *apertures; 768}; 769 770static inline struct drm_nouveau_private * 771nouveau_private(struct drm_device *dev) 772{ 773 return dev->dev_private; 774} 775 776static inline struct drm_nouveau_private * 777nouveau_bdev(struct ttm_bo_device *bd) 778{ 779 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 780} 781 782static inline int 783nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 784{ 785 struct nouveau_bo *prev; 786 787 if (!pnvbo) 788 return -EINVAL; 789 prev = *pnvbo; 790 791 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 792 if (prev) { 793 struct ttm_buffer_object *bo = &prev->bo; 794 795 ttm_bo_unref(&bo); 796 } 797 798 return 0; 799} 800 801/* nouveau_drv.c */ 802extern int nouveau_agpmode; 803extern int nouveau_duallink; 804extern int nouveau_uscript_lvds; 805extern int nouveau_uscript_tmds; 806extern int nouveau_vram_pushbuf; 807extern int nouveau_vram_notify; 808extern int nouveau_fbpercrtc; 809extern int nouveau_tv_disable; 810extern char *nouveau_tv_norm; 811extern int nouveau_reg_debug; 812extern char *nouveau_vbios; 813extern int nouveau_ignorelid; 814extern int nouveau_nofbaccel; 815extern int nouveau_noaccel; 816extern int nouveau_force_post; 817extern int nouveau_override_conntype; 818extern char *nouveau_perflvl; 819extern int nouveau_perflvl_wr; 820extern int nouveau_msi; 821extern int nouveau_ctxfw; 822 823extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 824extern int nouveau_pci_resume(struct pci_dev *pdev); 825 826/* nouveau_state.c */ 827extern int nouveau_open(struct drm_device *, struct drm_file *); 828extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 829extern void nouveau_postclose(struct drm_device *, struct drm_file *); 830extern int nouveau_load(struct drm_device *, unsigned long flags); 831extern int nouveau_firstopen(struct drm_device *); 832extern void nouveau_lastclose(struct drm_device *); 833extern int nouveau_unload(struct drm_device *); 834extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 835 struct drm_file *); 836extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 837 struct drm_file *); 838extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 839 uint32_t reg, uint32_t mask, uint32_t val); 840extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 841 uint32_t reg, uint32_t mask, uint32_t val); 842extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 843 bool (*cond)(void *), void *); 844extern bool nouveau_wait_for_idle(struct drm_device *); 845extern int nouveau_card_init(struct drm_device *); 846 847/* nouveau_mem.c */ 848extern int nouveau_mem_vram_init(struct drm_device *); 849extern void nouveau_mem_vram_fini(struct drm_device *); 850extern int nouveau_mem_gart_init(struct drm_device *); 851extern void nouveau_mem_gart_fini(struct drm_device *); 852extern int nouveau_mem_init_agp(struct drm_device *); 853extern int nouveau_mem_reset_agp(struct drm_device *); 854extern void nouveau_mem_close(struct drm_device *); 855extern int nouveau_mem_detect(struct drm_device *); 856extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 857extern struct nouveau_tile_reg *nv10_mem_set_tiling( 858 struct drm_device *dev, uint32_t addr, uint32_t size, 859 uint32_t pitch, uint32_t flags); 860extern void nv10_mem_put_tile_region(struct drm_device *dev, 861 struct nouveau_tile_reg *tile, 862 struct nouveau_fence *fence); 863extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 864extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 865 866/* nouveau_notifier.c */ 867extern int nouveau_notifier_init_channel(struct nouveau_channel *); 868extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 869extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 870 int cout, uint32_t start, uint32_t end, 871 uint32_t *offset); 872extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 873extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 874 struct drm_file *); 875extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 876 struct drm_file *); 877 878/* nouveau_channel.c */ 879extern struct drm_ioctl_desc nouveau_ioctls[]; 880extern int nouveau_max_ioctl; 881extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 882extern int nouveau_channel_alloc(struct drm_device *dev, 883 struct nouveau_channel **chan, 884 struct drm_file *file_priv, 885 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 886extern struct nouveau_channel * 887nouveau_channel_get_unlocked(struct nouveau_channel *); 888extern struct nouveau_channel * 889nouveau_channel_get(struct drm_file *, int id); 890extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 891extern void nouveau_channel_put(struct nouveau_channel **); 892extern void nouveau_channel_ref(struct nouveau_channel *chan, 893 struct nouveau_channel **pchan); 894extern void nouveau_channel_idle(struct nouveau_channel *chan); 895 896/* nouveau_object.c */ 897#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 898 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 899 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 900} while (0) 901 902#define NVOBJ_ENGINE_DEL(d, e) do { \ 903 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 904 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 905} while (0) 906 907#define NVOBJ_CLASS(d, c, e) do { \ 908 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 909 if (ret) \ 910 return ret; \ 911} while (0) 912 913#define NVOBJ_MTHD(d, c, m, e) do { \ 914 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 915 if (ret) \ 916 return ret; \ 917} while (0) 918 919extern int nouveau_gpuobj_early_init(struct drm_device *); 920extern int nouveau_gpuobj_init(struct drm_device *); 921extern void nouveau_gpuobj_takedown(struct drm_device *); 922extern int nouveau_gpuobj_suspend(struct drm_device *dev); 923extern void nouveau_gpuobj_resume(struct drm_device *dev); 924extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 925extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 926 int (*exec)(struct nouveau_channel *, 927 u32 class, u32 mthd, u32 data)); 928extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 929extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 930extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 931 uint32_t vram_h, uint32_t tt_h); 932extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 933extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 934 uint32_t size, int align, uint32_t flags, 935 struct nouveau_gpuobj **); 936extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 937 struct nouveau_gpuobj **); 938extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 939 u32 size, u32 flags, 940 struct nouveau_gpuobj **); 941extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 942 uint64_t offset, uint64_t size, int access, 943 int target, struct nouveau_gpuobj **); 944extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 945extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 946 u64 size, int target, int access, u32 type, 947 u32 comp, struct nouveau_gpuobj **pobj); 948extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 949 int class, u64 base, u64 size, int target, 950 int access, u32 type, u32 comp); 951extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 952 struct drm_file *); 953extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 954 struct drm_file *); 955 956/* nouveau_irq.c */ 957extern int nouveau_irq_init(struct drm_device *); 958extern void nouveau_irq_fini(struct drm_device *); 959extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 960extern void nouveau_irq_register(struct drm_device *, int status_bit, 961 void (*)(struct drm_device *)); 962extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 963extern void nouveau_irq_preinstall(struct drm_device *); 964extern int nouveau_irq_postinstall(struct drm_device *); 965extern void nouveau_irq_uninstall(struct drm_device *); 966 967/* nouveau_sgdma.c */ 968extern int nouveau_sgdma_init(struct drm_device *); 969extern void nouveau_sgdma_takedown(struct drm_device *); 970extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 971 uint32_t offset); 972extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 973 974/* nouveau_debugfs.c */ 975#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 976extern int nouveau_debugfs_init(struct drm_minor *); 977extern void nouveau_debugfs_takedown(struct drm_minor *); 978extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 979extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 980#else 981static inline int 982nouveau_debugfs_init(struct drm_minor *minor) 983{ 984 return 0; 985} 986 987static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 988{ 989} 990 991static inline int 992nouveau_debugfs_channel_init(struct nouveau_channel *chan) 993{ 994 return 0; 995} 996 997static inline void 998nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 999{ 1000} 1001#endif 1002 1003/* nouveau_dma.c */ 1004extern void nouveau_dma_pre_init(struct nouveau_channel *); 1005extern int nouveau_dma_init(struct nouveau_channel *); 1006extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1007 1008/* nouveau_acpi.c */ 1009#define ROM_BIOS_PAGE 4096 1010#if defined(CONFIG_ACPI) 1011void nouveau_register_dsm_handler(void); 1012void nouveau_unregister_dsm_handler(void); 1013int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1014bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1015int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1016#else 1017static inline void nouveau_register_dsm_handler(void) {} 1018static inline void nouveau_unregister_dsm_handler(void) {} 1019static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1020static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1021static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1022#endif 1023 1024/* nouveau_backlight.c */ 1025#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1026extern int nouveau_backlight_init(struct drm_connector *); 1027extern void nouveau_backlight_exit(struct drm_connector *); 1028#else 1029static inline int nouveau_backlight_init(struct drm_connector *dev) 1030{ 1031 return 0; 1032} 1033 1034static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1035#endif 1036 1037/* nouveau_bios.c */ 1038extern int nouveau_bios_init(struct drm_device *); 1039extern void nouveau_bios_takedown(struct drm_device *dev); 1040extern int nouveau_run_vbios_init(struct drm_device *); 1041extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1042 struct dcb_entry *); 1043extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1044 enum dcb_gpio_tag); 1045extern struct dcb_connector_table_entry * 1046nouveau_bios_connector_entry(struct drm_device *, int index); 1047extern u32 get_pll_register(struct drm_device *, enum pll_types); 1048extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1049 struct pll_lims *); 1050extern int nouveau_bios_run_display_table(struct drm_device *, 1051 struct dcb_entry *, 1052 uint32_t script, int pxclk); 1053extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1054 int *length); 1055extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1056extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1057extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1058 bool *dl, bool *if_is_24bit); 1059extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1060 int head, int pxclk); 1061extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1062 enum LVDS_script, int pxclk); 1063 1064/* nouveau_ttm.c */ 1065int nouveau_ttm_global_init(struct drm_nouveau_private *); 1066void nouveau_ttm_global_release(struct drm_nouveau_private *); 1067int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1068 1069/* nouveau_dp.c */ 1070int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1071 uint8_t *data, int data_nr); 1072bool nouveau_dp_detect(struct drm_encoder *); 1073bool nouveau_dp_link_train(struct drm_encoder *); 1074 1075/* nv04_fb.c */ 1076extern int nv04_fb_init(struct drm_device *); 1077extern void nv04_fb_takedown(struct drm_device *); 1078 1079/* nv10_fb.c */ 1080extern int nv10_fb_init(struct drm_device *); 1081extern void nv10_fb_takedown(struct drm_device *); 1082extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1083 uint32_t addr, uint32_t size, 1084 uint32_t pitch, uint32_t flags); 1085extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1086extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1087 1088/* nv30_fb.c */ 1089extern int nv30_fb_init(struct drm_device *); 1090extern void nv30_fb_takedown(struct drm_device *); 1091extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1092 uint32_t addr, uint32_t size, 1093 uint32_t pitch, uint32_t flags); 1094extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1095 1096/* nv40_fb.c */ 1097extern int nv40_fb_init(struct drm_device *); 1098extern void nv40_fb_takedown(struct drm_device *); 1099extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1100 1101/* nv50_fb.c */ 1102extern int nv50_fb_init(struct drm_device *); 1103extern void nv50_fb_takedown(struct drm_device *); 1104extern void nv50_fb_vm_trap(struct drm_device *, int display); 1105 1106/* nvc0_fb.c */ 1107extern int nvc0_fb_init(struct drm_device *); 1108extern void nvc0_fb_takedown(struct drm_device *); 1109 1110/* nv04_fifo.c */ 1111extern int nv04_fifo_init(struct drm_device *); 1112extern void nv04_fifo_fini(struct drm_device *); 1113extern void nv04_fifo_disable(struct drm_device *); 1114extern void nv04_fifo_enable(struct drm_device *); 1115extern bool nv04_fifo_reassign(struct drm_device *, bool); 1116extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1117extern int nv04_fifo_channel_id(struct drm_device *); 1118extern int nv04_fifo_create_context(struct nouveau_channel *); 1119extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1120extern int nv04_fifo_load_context(struct nouveau_channel *); 1121extern int nv04_fifo_unload_context(struct drm_device *); 1122extern void nv04_fifo_isr(struct drm_device *); 1123 1124/* nv10_fifo.c */ 1125extern int nv10_fifo_init(struct drm_device *); 1126extern int nv10_fifo_channel_id(struct drm_device *); 1127extern int nv10_fifo_create_context(struct nouveau_channel *); 1128extern int nv10_fifo_load_context(struct nouveau_channel *); 1129extern int nv10_fifo_unload_context(struct drm_device *); 1130 1131/* nv40_fifo.c */ 1132extern int nv40_fifo_init(struct drm_device *); 1133extern int nv40_fifo_create_context(struct nouveau_channel *); 1134extern int nv40_fifo_load_context(struct nouveau_channel *); 1135extern int nv40_fifo_unload_context(struct drm_device *); 1136 1137/* nv50_fifo.c */ 1138extern int nv50_fifo_init(struct drm_device *); 1139extern void nv50_fifo_takedown(struct drm_device *); 1140extern int nv50_fifo_channel_id(struct drm_device *); 1141extern int nv50_fifo_create_context(struct nouveau_channel *); 1142extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1143extern int nv50_fifo_load_context(struct nouveau_channel *); 1144extern int nv50_fifo_unload_context(struct drm_device *); 1145extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1146 1147/* nvc0_fifo.c */ 1148extern int nvc0_fifo_init(struct drm_device *); 1149extern void nvc0_fifo_takedown(struct drm_device *); 1150extern void nvc0_fifo_disable(struct drm_device *); 1151extern void nvc0_fifo_enable(struct drm_device *); 1152extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1153extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1154extern int nvc0_fifo_channel_id(struct drm_device *); 1155extern int nvc0_fifo_create_context(struct nouveau_channel *); 1156extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1157extern int nvc0_fifo_load_context(struct nouveau_channel *); 1158extern int nvc0_fifo_unload_context(struct drm_device *); 1159 1160/* nv04_graph.c */ 1161extern int nv04_graph_create(struct drm_device *); 1162extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1163extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1164 u32 class, u32 mthd, u32 data); 1165extern struct nouveau_bitfield nv04_graph_nsource[]; 1166 1167/* nv10_graph.c */ 1168extern int nv10_graph_create(struct drm_device *); 1169extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1170extern struct nouveau_bitfield nv10_graph_intr[]; 1171extern struct nouveau_bitfield nv10_graph_nstatus[]; 1172 1173/* nv20_graph.c */ 1174extern int nv20_graph_create(struct drm_device *); 1175 1176/* nv40_graph.c */ 1177extern int nv40_graph_create(struct drm_device *); 1178extern void nv40_grctx_init(struct nouveau_grctx *); 1179 1180/* nv50_graph.c */ 1181extern int nv50_graph_create(struct drm_device *); 1182extern int nv50_grctx_init(struct nouveau_grctx *); 1183extern struct nouveau_enum nv50_data_error_names[]; 1184extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1185 1186/* nvc0_graph.c */ 1187extern int nvc0_graph_create(struct drm_device *); 1188extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1189 1190/* nv84_crypt.c */ 1191extern int nv84_crypt_create(struct drm_device *); 1192 1193/* nva3_copy.c */ 1194extern int nva3_copy_create(struct drm_device *dev); 1195 1196/* nvc0_copy.c */ 1197extern int nvc0_copy_create(struct drm_device *dev, int engine); 1198 1199/* nv31_mpeg.c */ 1200extern int nv31_mpeg_create(struct drm_device *dev); 1201 1202/* nv50_mpeg.c */ 1203extern int nv50_mpeg_create(struct drm_device *dev); 1204 1205/* nv04_instmem.c */ 1206extern int nv04_instmem_init(struct drm_device *); 1207extern void nv04_instmem_takedown(struct drm_device *); 1208extern int nv04_instmem_suspend(struct drm_device *); 1209extern void nv04_instmem_resume(struct drm_device *); 1210extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1211 u32 size, u32 align); 1212extern void nv04_instmem_put(struct nouveau_gpuobj *); 1213extern int nv04_instmem_map(struct nouveau_gpuobj *); 1214extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1215extern void nv04_instmem_flush(struct drm_device *); 1216 1217/* nv50_instmem.c */ 1218extern int nv50_instmem_init(struct drm_device *); 1219extern void nv50_instmem_takedown(struct drm_device *); 1220extern int nv50_instmem_suspend(struct drm_device *); 1221extern void nv50_instmem_resume(struct drm_device *); 1222extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1223 u32 size, u32 align); 1224extern void nv50_instmem_put(struct nouveau_gpuobj *); 1225extern int nv50_instmem_map(struct nouveau_gpuobj *); 1226extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1227extern void nv50_instmem_flush(struct drm_device *); 1228extern void nv84_instmem_flush(struct drm_device *); 1229 1230/* nvc0_instmem.c */ 1231extern int nvc0_instmem_init(struct drm_device *); 1232extern void nvc0_instmem_takedown(struct drm_device *); 1233extern int nvc0_instmem_suspend(struct drm_device *); 1234extern void nvc0_instmem_resume(struct drm_device *); 1235 1236/* nv04_mc.c */ 1237extern int nv04_mc_init(struct drm_device *); 1238extern void nv04_mc_takedown(struct drm_device *); 1239 1240/* nv40_mc.c */ 1241extern int nv40_mc_init(struct drm_device *); 1242extern void nv40_mc_takedown(struct drm_device *); 1243 1244/* nv50_mc.c */ 1245extern int nv50_mc_init(struct drm_device *); 1246extern void nv50_mc_takedown(struct drm_device *); 1247 1248/* nv04_timer.c */ 1249extern int nv04_timer_init(struct drm_device *); 1250extern uint64_t nv04_timer_read(struct drm_device *); 1251extern void nv04_timer_takedown(struct drm_device *); 1252 1253extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1254 unsigned long arg); 1255 1256/* nv04_dac.c */ 1257extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1258extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1259extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1260extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1261extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1262 1263/* nv04_dfp.c */ 1264extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1265extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1266extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1267 int head, bool dl); 1268extern void nv04_dfp_disable(struct drm_device *dev, int head); 1269extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1270 1271/* nv04_tv.c */ 1272extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1273extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1274 1275/* nv17_tv.c */ 1276extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1277 1278/* nv04_display.c */ 1279extern int nv04_display_early_init(struct drm_device *); 1280extern void nv04_display_late_takedown(struct drm_device *); 1281extern int nv04_display_create(struct drm_device *); 1282extern int nv04_display_init(struct drm_device *); 1283extern void nv04_display_destroy(struct drm_device *); 1284 1285/* nv04_crtc.c */ 1286extern int nv04_crtc_create(struct drm_device *, int index); 1287 1288/* nouveau_bo.c */ 1289extern struct ttm_bo_driver nouveau_bo_driver; 1290extern int nouveau_bo_new(struct drm_device *, int size, int align, 1291 uint32_t flags, uint32_t tile_mode, 1292 uint32_t tile_flags, struct nouveau_bo **); 1293extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1294extern int nouveau_bo_unpin(struct nouveau_bo *); 1295extern int nouveau_bo_map(struct nouveau_bo *); 1296extern void nouveau_bo_unmap(struct nouveau_bo *); 1297extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1298 uint32_t busy); 1299extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1300extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1301extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1302extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1303extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1304extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1305 bool no_wait_reserve, bool no_wait_gpu); 1306 1307extern struct nouveau_vma * 1308nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1309extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1310 struct nouveau_vma *); 1311extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1312 1313/* nouveau_fence.c */ 1314struct nouveau_fence; 1315extern int nouveau_fence_init(struct drm_device *); 1316extern void nouveau_fence_fini(struct drm_device *); 1317extern int nouveau_fence_channel_init(struct nouveau_channel *); 1318extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1319extern void nouveau_fence_update(struct nouveau_channel *); 1320extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1321 bool emit); 1322extern int nouveau_fence_emit(struct nouveau_fence *); 1323extern void nouveau_fence_work(struct nouveau_fence *fence, 1324 void (*work)(void *priv, bool signalled), 1325 void *priv); 1326struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1327 1328extern bool __nouveau_fence_signalled(void *obj, void *arg); 1329extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1330extern int __nouveau_fence_flush(void *obj, void *arg); 1331extern void __nouveau_fence_unref(void **obj); 1332extern void *__nouveau_fence_ref(void *obj); 1333 1334static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1335{ 1336 return __nouveau_fence_signalled(obj, NULL); 1337} 1338static inline int 1339nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1340{ 1341 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1342} 1343extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1344static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1345{ 1346 return __nouveau_fence_flush(obj, NULL); 1347} 1348static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1349{ 1350 __nouveau_fence_unref((void **)obj); 1351} 1352static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1353{ 1354 return __nouveau_fence_ref(obj); 1355} 1356 1357/* nouveau_gem.c */ 1358extern int nouveau_gem_new(struct drm_device *, int size, int align, 1359 uint32_t domain, uint32_t tile_mode, 1360 uint32_t tile_flags, struct nouveau_bo **); 1361extern int nouveau_gem_object_new(struct drm_gem_object *); 1362extern void nouveau_gem_object_del(struct drm_gem_object *); 1363extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1364extern void nouveau_gem_object_close(struct drm_gem_object *, 1365 struct drm_file *); 1366extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1367 struct drm_file *); 1368extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1369 struct drm_file *); 1370extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1371 struct drm_file *); 1372extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1373 struct drm_file *); 1374extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1375 struct drm_file *); 1376 1377/* nouveau_display.c */ 1378int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1379void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1380int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1381 struct drm_pending_vblank_event *event); 1382int nouveau_finish_page_flip(struct nouveau_channel *, 1383 struct nouveau_page_flip_state *); 1384 1385/* nv10_gpio.c */ 1386int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1387int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1388 1389/* nv50_gpio.c */ 1390int nv50_gpio_init(struct drm_device *dev); 1391void nv50_gpio_fini(struct drm_device *dev); 1392int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1393int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1394int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1395 void (*)(void *, int), void *); 1396void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1397 void (*)(void *, int), void *); 1398bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1399 1400/* nv50_calc. */ 1401int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1402 int *N1, int *M1, int *N2, int *M2, int *P); 1403int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1404 int clk, int *N, int *fN, int *M, int *P); 1405 1406#ifndef ioread32_native 1407#ifdef __BIG_ENDIAN 1408#define ioread16_native ioread16be 1409#define iowrite16_native iowrite16be 1410#define ioread32_native ioread32be 1411#define iowrite32_native iowrite32be 1412#else /* def __BIG_ENDIAN */ 1413#define ioread16_native ioread16 1414#define iowrite16_native iowrite16 1415#define ioread32_native ioread32 1416#define iowrite32_native iowrite32 1417#endif /* def __BIG_ENDIAN else */ 1418#endif /* !ioread32_native */ 1419 1420/* channel control reg access */ 1421static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1422{ 1423 return ioread32_native(chan->user + reg); 1424} 1425 1426static inline void nvchan_wr32(struct nouveau_channel *chan, 1427 unsigned reg, u32 val) 1428{ 1429 iowrite32_native(val, chan->user + reg); 1430} 1431 1432/* register access */ 1433static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1434{ 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 return ioread32_native(dev_priv->mmio + reg); 1437} 1438 1439static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1440{ 1441 struct drm_nouveau_private *dev_priv = dev->dev_private; 1442 iowrite32_native(val, dev_priv->mmio + reg); 1443} 1444 1445static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1446{ 1447 u32 tmp = nv_rd32(dev, reg); 1448 nv_wr32(dev, reg, (tmp & ~mask) | val); 1449 return tmp; 1450} 1451 1452static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1453{ 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 return ioread8(dev_priv->mmio + reg); 1456} 1457 1458static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1459{ 1460 struct drm_nouveau_private *dev_priv = dev->dev_private; 1461 iowrite8(val, dev_priv->mmio + reg); 1462} 1463 1464#define nv_wait(dev, reg, mask, val) \ 1465 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1466#define nv_wait_ne(dev, reg, mask, val) \ 1467 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1468#define nv_wait_cb(dev, func, data) \ 1469 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1470 1471/* PRAMIN access */ 1472static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1473{ 1474 struct drm_nouveau_private *dev_priv = dev->dev_private; 1475 return ioread32_native(dev_priv->ramin + offset); 1476} 1477 1478static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1479{ 1480 struct drm_nouveau_private *dev_priv = dev->dev_private; 1481 iowrite32_native(val, dev_priv->ramin + offset); 1482} 1483 1484/* object access */ 1485extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1486extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1487 1488/* 1489 * Logging 1490 * Argument d is (struct drm_device *). 1491 */ 1492#define NV_PRINTK(level, d, fmt, arg...) \ 1493 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1494 pci_name(d->pdev), ##arg) 1495#ifndef NV_DEBUG_NOTRACE 1496#define NV_DEBUG(d, fmt, arg...) do { \ 1497 if (drm_debug & DRM_UT_DRIVER) { \ 1498 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1499 __LINE__, ##arg); \ 1500 } \ 1501} while (0) 1502#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1503 if (drm_debug & DRM_UT_KMS) { \ 1504 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1505 __LINE__, ##arg); \ 1506 } \ 1507} while (0) 1508#else 1509#define NV_DEBUG(d, fmt, arg...) do { \ 1510 if (drm_debug & DRM_UT_DRIVER) \ 1511 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1512} while (0) 1513#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1514 if (drm_debug & DRM_UT_KMS) \ 1515 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1516} while (0) 1517#endif 1518#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1519#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1520#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1521#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1522#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1523 1524/* nouveau_reg_debug bitmask */ 1525enum { 1526 NOUVEAU_REG_DEBUG_MC = 0x1, 1527 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1528 NOUVEAU_REG_DEBUG_FB = 0x4, 1529 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1530 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1531 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1532 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1533 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1534 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1535 NOUVEAU_REG_DEBUG_EVO = 0x200, 1536}; 1537 1538#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1539 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1540 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1541} while (0) 1542 1543static inline bool 1544nv_two_heads(struct drm_device *dev) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 const int impl = dev->pci_device & 0x0ff0; 1548 1549 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1550 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1551 return true; 1552 1553 return false; 1554} 1555 1556static inline bool 1557nv_gf4_disp_arch(struct drm_device *dev) 1558{ 1559 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1560} 1561 1562static inline bool 1563nv_two_reg_pll(struct drm_device *dev) 1564{ 1565 struct drm_nouveau_private *dev_priv = dev->dev_private; 1566 const int impl = dev->pci_device & 0x0ff0; 1567 1568 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1569 return true; 1570 return false; 1571} 1572 1573static inline bool 1574nv_match_device(struct drm_device *dev, unsigned device, 1575 unsigned sub_vendor, unsigned sub_device) 1576{ 1577 return dev->pdev->device == device && 1578 dev->pdev->subsystem_vendor == sub_vendor && 1579 dev->pdev->subsystem_device == sub_device; 1580} 1581 1582static inline void * 1583nv_engine(struct drm_device *dev, int engine) 1584{ 1585 struct drm_nouveau_private *dev_priv = dev->dev_private; 1586 return (void *)dev_priv->eng[engine]; 1587} 1588 1589/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1590 * helpful to determine a number of other hardware features 1591 */ 1592static inline int 1593nv44_graph_class(struct drm_device *dev) 1594{ 1595 struct drm_nouveau_private *dev_priv = dev->dev_private; 1596 1597 if ((dev_priv->chipset & 0xf0) == 0x60) 1598 return 1; 1599 1600 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1601} 1602 1603/* memory type/access flags, do not match hardware values */ 1604#define NV_MEM_ACCESS_RO 1 1605#define NV_MEM_ACCESS_WO 2 1606#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1607#define NV_MEM_ACCESS_SYS 4 1608#define NV_MEM_ACCESS_VM 8 1609 1610#define NV_MEM_TARGET_VRAM 0 1611#define NV_MEM_TARGET_PCI 1 1612#define NV_MEM_TARGET_PCI_NOSNOOP 2 1613#define NV_MEM_TARGET_VM 3 1614#define NV_MEM_TARGET_GART 4 1615 1616#define NV_MEM_TYPE_VM 0x7f 1617#define NV_MEM_COMP_VM 0x03 1618 1619/* NV_SW object class */ 1620#define NV_SW 0x0000506e 1621#define NV_SW_DMA_SEMAPHORE 0x00000060 1622#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1623#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1624#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1625#define NV_SW_YIELD 0x00000080 1626#define NV_SW_DMA_VBLSEM 0x0000018c 1627#define NV_SW_VBLSEM_OFFSET 0x00000400 1628#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1629#define NV_SW_VBLSEM_RELEASE 0x00000408 1630#define NV_SW_PAGE_FLIP 0x00000500 1631 1632#endif /* __NOUVEAU_DRV_H__ */ 1633