nouveau_drv.h revision 323dcac552b39884cdeff26a38d5dd80854795a1
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_100220; 433 u32 reg_100224; 434 u32 reg_100228; 435 u32 reg_10022c; 436 u32 reg_100230; 437 u32 reg_100234; 438 u32 reg_100238; 439 u32 reg_10023c; 440 u32 reg_100240; 441}; 442 443#define NOUVEAU_PM_MAX_LEVEL 8 444struct nouveau_pm_level { 445 struct device_attribute dev_attr; 446 char name[32]; 447 int id; 448 449 u32 core; 450 u32 memory; 451 u32 shader; 452 u32 rop; 453 u32 copy; 454 u32 daemon; 455 u32 vdec; 456 u32 unk05; /* nv50:nva3, roughly.. */ 457 u32 unka0; /* nva3:nvc0 */ 458 u32 hub01; /* nvc0- */ 459 u32 hub06; /* nvc0- */ 460 u32 hub07; /* nvc0- */ 461 462 u32 volt_min; /* microvolts */ 463 u32 volt_max; 464 u8 fanspeed; 465 466 u16 memscript; 467 struct nouveau_pm_memtiming *timing; 468}; 469 470struct nouveau_pm_temp_sensor_constants { 471 u16 offset_constant; 472 s16 offset_mult; 473 s16 offset_div; 474 s16 slope_mult; 475 s16 slope_div; 476}; 477 478struct nouveau_pm_threshold_temp { 479 s16 critical; 480 s16 down_clock; 481 s16 fan_boost; 482}; 483 484struct nouveau_pm_memtimings { 485 bool supported; 486 struct nouveau_pm_memtiming *timing; 487 int nr_timing; 488}; 489 490struct nouveau_pm_engine { 491 struct nouveau_pm_voltage voltage; 492 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 493 int nr_perflvl; 494 struct nouveau_pm_memtimings memtimings; 495 struct nouveau_pm_temp_sensor_constants sensor_constants; 496 struct nouveau_pm_threshold_temp threshold_temp; 497 498 struct nouveau_pm_level boot; 499 struct nouveau_pm_level *cur; 500 501 struct device *hwmon; 502 struct notifier_block acpi_nb; 503 504 int (*clock_get)(struct drm_device *, u32 id); 505 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 506 u32 id, int khz); 507 void (*clock_set)(struct drm_device *, void *); 508 509 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 510 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 511 void (*clocks_set)(struct drm_device *, void *); 512 513 int (*voltage_get)(struct drm_device *); 514 int (*voltage_set)(struct drm_device *, int voltage); 515 int (*fanspeed_get)(struct drm_device *); 516 int (*fanspeed_set)(struct drm_device *, int fanspeed); 517 int (*temp_get)(struct drm_device *); 518}; 519 520struct nouveau_vram_engine { 521 struct nouveau_mm *mm; 522 523 int (*init)(struct drm_device *); 524 void (*takedown)(struct drm_device *dev); 525 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 526 u32 type, struct nouveau_mem **); 527 void (*put)(struct drm_device *, struct nouveau_mem **); 528 529 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 530}; 531 532struct nouveau_engine { 533 struct nouveau_instmem_engine instmem; 534 struct nouveau_mc_engine mc; 535 struct nouveau_timer_engine timer; 536 struct nouveau_fb_engine fb; 537 struct nouveau_fifo_engine fifo; 538 struct nouveau_display_engine display; 539 struct nouveau_gpio_engine gpio; 540 struct nouveau_pm_engine pm; 541 struct nouveau_vram_engine vram; 542}; 543 544struct nouveau_pll_vals { 545 union { 546 struct { 547#ifdef __BIG_ENDIAN 548 uint8_t N1, M1, N2, M2; 549#else 550 uint8_t M1, N1, M2, N2; 551#endif 552 }; 553 struct { 554 uint16_t NM1, NM2; 555 } __attribute__((packed)); 556 }; 557 int log2P; 558 559 int refclk; 560}; 561 562enum nv04_fp_display_regs { 563 FP_DISPLAY_END, 564 FP_TOTAL, 565 FP_CRTC, 566 FP_SYNC_START, 567 FP_SYNC_END, 568 FP_VALID_START, 569 FP_VALID_END 570}; 571 572struct nv04_crtc_reg { 573 unsigned char MiscOutReg; 574 uint8_t CRTC[0xa0]; 575 uint8_t CR58[0x10]; 576 uint8_t Sequencer[5]; 577 uint8_t Graphics[9]; 578 uint8_t Attribute[21]; 579 unsigned char DAC[768]; 580 581 /* PCRTC regs */ 582 uint32_t fb_start; 583 uint32_t crtc_cfg; 584 uint32_t cursor_cfg; 585 uint32_t gpio_ext; 586 uint32_t crtc_830; 587 uint32_t crtc_834; 588 uint32_t crtc_850; 589 uint32_t crtc_eng_ctrl; 590 591 /* PRAMDAC regs */ 592 uint32_t nv10_cursync; 593 struct nouveau_pll_vals pllvals; 594 uint32_t ramdac_gen_ctrl; 595 uint32_t ramdac_630; 596 uint32_t ramdac_634; 597 uint32_t tv_setup; 598 uint32_t tv_vtotal; 599 uint32_t tv_vskew; 600 uint32_t tv_vsync_delay; 601 uint32_t tv_htotal; 602 uint32_t tv_hskew; 603 uint32_t tv_hsync_delay; 604 uint32_t tv_hsync_delay2; 605 uint32_t fp_horiz_regs[7]; 606 uint32_t fp_vert_regs[7]; 607 uint32_t dither; 608 uint32_t fp_control; 609 uint32_t dither_regs[6]; 610 uint32_t fp_debug_0; 611 uint32_t fp_debug_1; 612 uint32_t fp_debug_2; 613 uint32_t fp_margin_color; 614 uint32_t ramdac_8c0; 615 uint32_t ramdac_a20; 616 uint32_t ramdac_a24; 617 uint32_t ramdac_a34; 618 uint32_t ctv_regs[38]; 619}; 620 621struct nv04_output_reg { 622 uint32_t output; 623 int head; 624}; 625 626struct nv04_mode_state { 627 struct nv04_crtc_reg crtc_reg[2]; 628 uint32_t pllsel; 629 uint32_t sel_clk; 630}; 631 632enum nouveau_card_type { 633 NV_04 = 0x00, 634 NV_10 = 0x10, 635 NV_20 = 0x20, 636 NV_30 = 0x30, 637 NV_40 = 0x40, 638 NV_50 = 0x50, 639 NV_C0 = 0xc0, 640}; 641 642struct drm_nouveau_private { 643 struct drm_device *dev; 644 bool noaccel; 645 646 /* the card type, takes NV_* as values */ 647 enum nouveau_card_type card_type; 648 /* exact chipset, derived from NV_PMC_BOOT_0 */ 649 int chipset; 650 int stepping; 651 int flags; 652 653 void __iomem *mmio; 654 655 spinlock_t ramin_lock; 656 void __iomem *ramin; 657 u32 ramin_size; 658 u32 ramin_base; 659 bool ramin_available; 660 struct drm_mm ramin_heap; 661 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 662 struct list_head gpuobj_list; 663 struct list_head classes; 664 665 struct nouveau_bo *vga_ram; 666 667 /* interrupt handling */ 668 void (*irq_handler[32])(struct drm_device *); 669 bool msi_enabled; 670 671 struct list_head vbl_waiting; 672 673 struct { 674 struct drm_global_reference mem_global_ref; 675 struct ttm_bo_global_ref bo_global_ref; 676 struct ttm_bo_device bdev; 677 atomic_t validate_sequence; 678 } ttm; 679 680 struct { 681 spinlock_t lock; 682 struct drm_mm heap; 683 struct nouveau_bo *bo; 684 } fence; 685 686 struct { 687 spinlock_t lock; 688 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 689 } channels; 690 691 struct nouveau_engine engine; 692 struct nouveau_channel *channel; 693 694 /* For PFIFO and PGRAPH. */ 695 spinlock_t context_switch_lock; 696 697 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 698 spinlock_t vm_lock; 699 700 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 701 struct nouveau_ramht *ramht; 702 struct nouveau_gpuobj *ramfc; 703 struct nouveau_gpuobj *ramro; 704 705 uint32_t ramin_rsvd_vram; 706 707 struct { 708 enum { 709 NOUVEAU_GART_NONE = 0, 710 NOUVEAU_GART_AGP, /* AGP */ 711 NOUVEAU_GART_PDMA, /* paged dma object */ 712 NOUVEAU_GART_HW /* on-chip gart/vm */ 713 } type; 714 uint64_t aper_base; 715 uint64_t aper_size; 716 uint64_t aper_free; 717 718 struct ttm_backend_func *func; 719 720 struct { 721 struct page *page; 722 dma_addr_t addr; 723 } dummy; 724 725 struct nouveau_gpuobj *sg_ctxdma; 726 } gart_info; 727 728 /* nv10-nv40 tiling regions */ 729 struct { 730 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 731 spinlock_t lock; 732 } tile; 733 734 /* VRAM/fb configuration */ 735 uint64_t vram_size; 736 uint64_t vram_sys_base; 737 738 uint64_t fb_phys; 739 uint64_t fb_available_size; 740 uint64_t fb_mappable_pages; 741 uint64_t fb_aper_free; 742 int fb_mtrr; 743 744 /* BAR control (NV50-) */ 745 struct nouveau_vm *bar1_vm; 746 struct nouveau_vm *bar3_vm; 747 748 /* G8x/G9x virtual address space */ 749 struct nouveau_vm *chan_vm; 750 751 struct nvbios vbios; 752 753 struct nv04_mode_state mode_reg; 754 struct nv04_mode_state saved_reg; 755 uint32_t saved_vga_font[4][16384]; 756 uint32_t crtc_owner; 757 uint32_t dac_users[4]; 758 759 struct backlight_device *backlight; 760 761 struct { 762 struct dentry *channel_root; 763 } debugfs; 764 765 struct nouveau_fbdev *nfbdev; 766 struct apertures_struct *apertures; 767}; 768 769static inline struct drm_nouveau_private * 770nouveau_private(struct drm_device *dev) 771{ 772 return dev->dev_private; 773} 774 775static inline struct drm_nouveau_private * 776nouveau_bdev(struct ttm_bo_device *bd) 777{ 778 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 779} 780 781static inline int 782nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 783{ 784 struct nouveau_bo *prev; 785 786 if (!pnvbo) 787 return -EINVAL; 788 prev = *pnvbo; 789 790 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 791 if (prev) { 792 struct ttm_buffer_object *bo = &prev->bo; 793 794 ttm_bo_unref(&bo); 795 } 796 797 return 0; 798} 799 800/* nouveau_drv.c */ 801extern int nouveau_agpmode; 802extern int nouveau_duallink; 803extern int nouveau_uscript_lvds; 804extern int nouveau_uscript_tmds; 805extern int nouveau_vram_pushbuf; 806extern int nouveau_vram_notify; 807extern int nouveau_fbpercrtc; 808extern int nouveau_tv_disable; 809extern char *nouveau_tv_norm; 810extern int nouveau_reg_debug; 811extern char *nouveau_vbios; 812extern int nouveau_ignorelid; 813extern int nouveau_nofbaccel; 814extern int nouveau_noaccel; 815extern int nouveau_force_post; 816extern int nouveau_override_conntype; 817extern char *nouveau_perflvl; 818extern int nouveau_perflvl_wr; 819extern int nouveau_msi; 820extern int nouveau_ctxfw; 821 822extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 823extern int nouveau_pci_resume(struct pci_dev *pdev); 824 825/* nouveau_state.c */ 826extern int nouveau_open(struct drm_device *, struct drm_file *); 827extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 828extern void nouveau_postclose(struct drm_device *, struct drm_file *); 829extern int nouveau_load(struct drm_device *, unsigned long flags); 830extern int nouveau_firstopen(struct drm_device *); 831extern void nouveau_lastclose(struct drm_device *); 832extern int nouveau_unload(struct drm_device *); 833extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 834 struct drm_file *); 835extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 836 struct drm_file *); 837extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 838 uint32_t reg, uint32_t mask, uint32_t val); 839extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 840 uint32_t reg, uint32_t mask, uint32_t val); 841extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 842 bool (*cond)(void *), void *); 843extern bool nouveau_wait_for_idle(struct drm_device *); 844extern int nouveau_card_init(struct drm_device *); 845 846/* nouveau_mem.c */ 847extern int nouveau_mem_vram_init(struct drm_device *); 848extern void nouveau_mem_vram_fini(struct drm_device *); 849extern int nouveau_mem_gart_init(struct drm_device *); 850extern void nouveau_mem_gart_fini(struct drm_device *); 851extern int nouveau_mem_init_agp(struct drm_device *); 852extern int nouveau_mem_reset_agp(struct drm_device *); 853extern void nouveau_mem_close(struct drm_device *); 854extern int nouveau_mem_detect(struct drm_device *); 855extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 856extern struct nouveau_tile_reg *nv10_mem_set_tiling( 857 struct drm_device *dev, uint32_t addr, uint32_t size, 858 uint32_t pitch, uint32_t flags); 859extern void nv10_mem_put_tile_region(struct drm_device *dev, 860 struct nouveau_tile_reg *tile, 861 struct nouveau_fence *fence); 862extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 863extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 864 865/* nouveau_notifier.c */ 866extern int nouveau_notifier_init_channel(struct nouveau_channel *); 867extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 868extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 869 int cout, uint32_t start, uint32_t end, 870 uint32_t *offset); 871extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 872extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 873 struct drm_file *); 874extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 875 struct drm_file *); 876 877/* nouveau_channel.c */ 878extern struct drm_ioctl_desc nouveau_ioctls[]; 879extern int nouveau_max_ioctl; 880extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 881extern int nouveau_channel_alloc(struct drm_device *dev, 882 struct nouveau_channel **chan, 883 struct drm_file *file_priv, 884 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 885extern struct nouveau_channel * 886nouveau_channel_get_unlocked(struct nouveau_channel *); 887extern struct nouveau_channel * 888nouveau_channel_get(struct drm_file *, int id); 889extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 890extern void nouveau_channel_put(struct nouveau_channel **); 891extern void nouveau_channel_ref(struct nouveau_channel *chan, 892 struct nouveau_channel **pchan); 893extern void nouveau_channel_idle(struct nouveau_channel *chan); 894 895/* nouveau_object.c */ 896#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 897 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 898 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 899} while (0) 900 901#define NVOBJ_ENGINE_DEL(d, e) do { \ 902 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 903 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 904} while (0) 905 906#define NVOBJ_CLASS(d, c, e) do { \ 907 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 908 if (ret) \ 909 return ret; \ 910} while (0) 911 912#define NVOBJ_MTHD(d, c, m, e) do { \ 913 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 914 if (ret) \ 915 return ret; \ 916} while (0) 917 918extern int nouveau_gpuobj_early_init(struct drm_device *); 919extern int nouveau_gpuobj_init(struct drm_device *); 920extern void nouveau_gpuobj_takedown(struct drm_device *); 921extern int nouveau_gpuobj_suspend(struct drm_device *dev); 922extern void nouveau_gpuobj_resume(struct drm_device *dev); 923extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 924extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 925 int (*exec)(struct nouveau_channel *, 926 u32 class, u32 mthd, u32 data)); 927extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 928extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 929extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 930 uint32_t vram_h, uint32_t tt_h); 931extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 932extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 933 uint32_t size, int align, uint32_t flags, 934 struct nouveau_gpuobj **); 935extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 936 struct nouveau_gpuobj **); 937extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 938 u32 size, u32 flags, 939 struct nouveau_gpuobj **); 940extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 941 uint64_t offset, uint64_t size, int access, 942 int target, struct nouveau_gpuobj **); 943extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 944extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 945 u64 size, int target, int access, u32 type, 946 u32 comp, struct nouveau_gpuobj **pobj); 947extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 948 int class, u64 base, u64 size, int target, 949 int access, u32 type, u32 comp); 950extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 951 struct drm_file *); 952extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 953 struct drm_file *); 954 955/* nouveau_irq.c */ 956extern int nouveau_irq_init(struct drm_device *); 957extern void nouveau_irq_fini(struct drm_device *); 958extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 959extern void nouveau_irq_register(struct drm_device *, int status_bit, 960 void (*)(struct drm_device *)); 961extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 962extern void nouveau_irq_preinstall(struct drm_device *); 963extern int nouveau_irq_postinstall(struct drm_device *); 964extern void nouveau_irq_uninstall(struct drm_device *); 965 966/* nouveau_sgdma.c */ 967extern int nouveau_sgdma_init(struct drm_device *); 968extern void nouveau_sgdma_takedown(struct drm_device *); 969extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 970 uint32_t offset); 971extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 972 973/* nouveau_debugfs.c */ 974#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 975extern int nouveau_debugfs_init(struct drm_minor *); 976extern void nouveau_debugfs_takedown(struct drm_minor *); 977extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 978extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 979#else 980static inline int 981nouveau_debugfs_init(struct drm_minor *minor) 982{ 983 return 0; 984} 985 986static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 987{ 988} 989 990static inline int 991nouveau_debugfs_channel_init(struct nouveau_channel *chan) 992{ 993 return 0; 994} 995 996static inline void 997nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 998{ 999} 1000#endif 1001 1002/* nouveau_dma.c */ 1003extern void nouveau_dma_pre_init(struct nouveau_channel *); 1004extern int nouveau_dma_init(struct nouveau_channel *); 1005extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1006 1007/* nouveau_acpi.c */ 1008#define ROM_BIOS_PAGE 4096 1009#if defined(CONFIG_ACPI) 1010void nouveau_register_dsm_handler(void); 1011void nouveau_unregister_dsm_handler(void); 1012int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1013bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1014int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1015#else 1016static inline void nouveau_register_dsm_handler(void) {} 1017static inline void nouveau_unregister_dsm_handler(void) {} 1018static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1019static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1020static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1021#endif 1022 1023/* nouveau_backlight.c */ 1024#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1025extern int nouveau_backlight_init(struct drm_connector *); 1026extern void nouveau_backlight_exit(struct drm_connector *); 1027#else 1028static inline int nouveau_backlight_init(struct drm_connector *dev) 1029{ 1030 return 0; 1031} 1032 1033static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1034#endif 1035 1036/* nouveau_bios.c */ 1037extern int nouveau_bios_init(struct drm_device *); 1038extern void nouveau_bios_takedown(struct drm_device *dev); 1039extern int nouveau_run_vbios_init(struct drm_device *); 1040extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1041 struct dcb_entry *); 1042extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1043 enum dcb_gpio_tag); 1044extern struct dcb_connector_table_entry * 1045nouveau_bios_connector_entry(struct drm_device *, int index); 1046extern u32 get_pll_register(struct drm_device *, enum pll_types); 1047extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1048 struct pll_lims *); 1049extern int nouveau_bios_run_display_table(struct drm_device *, 1050 struct dcb_entry *, 1051 uint32_t script, int pxclk); 1052extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1053 int *length); 1054extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1055extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1056extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1057 bool *dl, bool *if_is_24bit); 1058extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1059 int head, int pxclk); 1060extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1061 enum LVDS_script, int pxclk); 1062 1063/* nouveau_ttm.c */ 1064int nouveau_ttm_global_init(struct drm_nouveau_private *); 1065void nouveau_ttm_global_release(struct drm_nouveau_private *); 1066int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1067 1068/* nouveau_dp.c */ 1069int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1070 uint8_t *data, int data_nr); 1071bool nouveau_dp_detect(struct drm_encoder *); 1072bool nouveau_dp_link_train(struct drm_encoder *); 1073 1074/* nv04_fb.c */ 1075extern int nv04_fb_init(struct drm_device *); 1076extern void nv04_fb_takedown(struct drm_device *); 1077 1078/* nv10_fb.c */ 1079extern int nv10_fb_init(struct drm_device *); 1080extern void nv10_fb_takedown(struct drm_device *); 1081extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1082 uint32_t addr, uint32_t size, 1083 uint32_t pitch, uint32_t flags); 1084extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1085extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1086 1087/* nv30_fb.c */ 1088extern int nv30_fb_init(struct drm_device *); 1089extern void nv30_fb_takedown(struct drm_device *); 1090extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1091 uint32_t addr, uint32_t size, 1092 uint32_t pitch, uint32_t flags); 1093extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1094 1095/* nv40_fb.c */ 1096extern int nv40_fb_init(struct drm_device *); 1097extern void nv40_fb_takedown(struct drm_device *); 1098extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1099 1100/* nv50_fb.c */ 1101extern int nv50_fb_init(struct drm_device *); 1102extern void nv50_fb_takedown(struct drm_device *); 1103extern void nv50_fb_vm_trap(struct drm_device *, int display); 1104 1105/* nvc0_fb.c */ 1106extern int nvc0_fb_init(struct drm_device *); 1107extern void nvc0_fb_takedown(struct drm_device *); 1108 1109/* nv04_fifo.c */ 1110extern int nv04_fifo_init(struct drm_device *); 1111extern void nv04_fifo_fini(struct drm_device *); 1112extern void nv04_fifo_disable(struct drm_device *); 1113extern void nv04_fifo_enable(struct drm_device *); 1114extern bool nv04_fifo_reassign(struct drm_device *, bool); 1115extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1116extern int nv04_fifo_channel_id(struct drm_device *); 1117extern int nv04_fifo_create_context(struct nouveau_channel *); 1118extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1119extern int nv04_fifo_load_context(struct nouveau_channel *); 1120extern int nv04_fifo_unload_context(struct drm_device *); 1121extern void nv04_fifo_isr(struct drm_device *); 1122 1123/* nv10_fifo.c */ 1124extern int nv10_fifo_init(struct drm_device *); 1125extern int nv10_fifo_channel_id(struct drm_device *); 1126extern int nv10_fifo_create_context(struct nouveau_channel *); 1127extern int nv10_fifo_load_context(struct nouveau_channel *); 1128extern int nv10_fifo_unload_context(struct drm_device *); 1129 1130/* nv40_fifo.c */ 1131extern int nv40_fifo_init(struct drm_device *); 1132extern int nv40_fifo_create_context(struct nouveau_channel *); 1133extern int nv40_fifo_load_context(struct nouveau_channel *); 1134extern int nv40_fifo_unload_context(struct drm_device *); 1135 1136/* nv50_fifo.c */ 1137extern int nv50_fifo_init(struct drm_device *); 1138extern void nv50_fifo_takedown(struct drm_device *); 1139extern int nv50_fifo_channel_id(struct drm_device *); 1140extern int nv50_fifo_create_context(struct nouveau_channel *); 1141extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1142extern int nv50_fifo_load_context(struct nouveau_channel *); 1143extern int nv50_fifo_unload_context(struct drm_device *); 1144extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1145 1146/* nvc0_fifo.c */ 1147extern int nvc0_fifo_init(struct drm_device *); 1148extern void nvc0_fifo_takedown(struct drm_device *); 1149extern void nvc0_fifo_disable(struct drm_device *); 1150extern void nvc0_fifo_enable(struct drm_device *); 1151extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1152extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1153extern int nvc0_fifo_channel_id(struct drm_device *); 1154extern int nvc0_fifo_create_context(struct nouveau_channel *); 1155extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1156extern int nvc0_fifo_load_context(struct nouveau_channel *); 1157extern int nvc0_fifo_unload_context(struct drm_device *); 1158 1159/* nv04_graph.c */ 1160extern int nv04_graph_create(struct drm_device *); 1161extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1162extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1163 u32 class, u32 mthd, u32 data); 1164extern struct nouveau_bitfield nv04_graph_nsource[]; 1165 1166/* nv10_graph.c */ 1167extern int nv10_graph_create(struct drm_device *); 1168extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1169extern struct nouveau_bitfield nv10_graph_intr[]; 1170extern struct nouveau_bitfield nv10_graph_nstatus[]; 1171 1172/* nv20_graph.c */ 1173extern int nv20_graph_create(struct drm_device *); 1174 1175/* nv40_graph.c */ 1176extern int nv40_graph_create(struct drm_device *); 1177extern void nv40_grctx_init(struct nouveau_grctx *); 1178 1179/* nv50_graph.c */ 1180extern int nv50_graph_create(struct drm_device *); 1181extern int nv50_grctx_init(struct nouveau_grctx *); 1182extern struct nouveau_enum nv50_data_error_names[]; 1183extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1184 1185/* nvc0_graph.c */ 1186extern int nvc0_graph_create(struct drm_device *); 1187extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1188 1189/* nv84_crypt.c */ 1190extern int nv84_crypt_create(struct drm_device *); 1191 1192/* nva3_copy.c */ 1193extern int nva3_copy_create(struct drm_device *dev); 1194 1195/* nvc0_copy.c */ 1196extern int nvc0_copy_create(struct drm_device *dev, int engine); 1197 1198/* nv31_mpeg.c */ 1199extern int nv31_mpeg_create(struct drm_device *dev); 1200 1201/* nv50_mpeg.c */ 1202extern int nv50_mpeg_create(struct drm_device *dev); 1203 1204/* nv04_instmem.c */ 1205extern int nv04_instmem_init(struct drm_device *); 1206extern void nv04_instmem_takedown(struct drm_device *); 1207extern int nv04_instmem_suspend(struct drm_device *); 1208extern void nv04_instmem_resume(struct drm_device *); 1209extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1210 u32 size, u32 align); 1211extern void nv04_instmem_put(struct nouveau_gpuobj *); 1212extern int nv04_instmem_map(struct nouveau_gpuobj *); 1213extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1214extern void nv04_instmem_flush(struct drm_device *); 1215 1216/* nv50_instmem.c */ 1217extern int nv50_instmem_init(struct drm_device *); 1218extern void nv50_instmem_takedown(struct drm_device *); 1219extern int nv50_instmem_suspend(struct drm_device *); 1220extern void nv50_instmem_resume(struct drm_device *); 1221extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1222 u32 size, u32 align); 1223extern void nv50_instmem_put(struct nouveau_gpuobj *); 1224extern int nv50_instmem_map(struct nouveau_gpuobj *); 1225extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1226extern void nv50_instmem_flush(struct drm_device *); 1227extern void nv84_instmem_flush(struct drm_device *); 1228 1229/* nvc0_instmem.c */ 1230extern int nvc0_instmem_init(struct drm_device *); 1231extern void nvc0_instmem_takedown(struct drm_device *); 1232extern int nvc0_instmem_suspend(struct drm_device *); 1233extern void nvc0_instmem_resume(struct drm_device *); 1234 1235/* nv04_mc.c */ 1236extern int nv04_mc_init(struct drm_device *); 1237extern void nv04_mc_takedown(struct drm_device *); 1238 1239/* nv40_mc.c */ 1240extern int nv40_mc_init(struct drm_device *); 1241extern void nv40_mc_takedown(struct drm_device *); 1242 1243/* nv50_mc.c */ 1244extern int nv50_mc_init(struct drm_device *); 1245extern void nv50_mc_takedown(struct drm_device *); 1246 1247/* nv04_timer.c */ 1248extern int nv04_timer_init(struct drm_device *); 1249extern uint64_t nv04_timer_read(struct drm_device *); 1250extern void nv04_timer_takedown(struct drm_device *); 1251 1252extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1253 unsigned long arg); 1254 1255/* nv04_dac.c */ 1256extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1257extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1258extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1259extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1260extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1261 1262/* nv04_dfp.c */ 1263extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1264extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1265extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1266 int head, bool dl); 1267extern void nv04_dfp_disable(struct drm_device *dev, int head); 1268extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1269 1270/* nv04_tv.c */ 1271extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1272extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1273 1274/* nv17_tv.c */ 1275extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1276 1277/* nv04_display.c */ 1278extern int nv04_display_early_init(struct drm_device *); 1279extern void nv04_display_late_takedown(struct drm_device *); 1280extern int nv04_display_create(struct drm_device *); 1281extern int nv04_display_init(struct drm_device *); 1282extern void nv04_display_destroy(struct drm_device *); 1283 1284/* nv04_crtc.c */ 1285extern int nv04_crtc_create(struct drm_device *, int index); 1286 1287/* nouveau_bo.c */ 1288extern struct ttm_bo_driver nouveau_bo_driver; 1289extern int nouveau_bo_new(struct drm_device *, int size, int align, 1290 uint32_t flags, uint32_t tile_mode, 1291 uint32_t tile_flags, struct nouveau_bo **); 1292extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1293extern int nouveau_bo_unpin(struct nouveau_bo *); 1294extern int nouveau_bo_map(struct nouveau_bo *); 1295extern void nouveau_bo_unmap(struct nouveau_bo *); 1296extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1297 uint32_t busy); 1298extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1299extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1300extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1301extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1302extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1303extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1304 bool no_wait_reserve, bool no_wait_gpu); 1305 1306extern struct nouveau_vma * 1307nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1308extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1309 struct nouveau_vma *); 1310extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1311 1312/* nouveau_fence.c */ 1313struct nouveau_fence; 1314extern int nouveau_fence_init(struct drm_device *); 1315extern void nouveau_fence_fini(struct drm_device *); 1316extern int nouveau_fence_channel_init(struct nouveau_channel *); 1317extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1318extern void nouveau_fence_update(struct nouveau_channel *); 1319extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1320 bool emit); 1321extern int nouveau_fence_emit(struct nouveau_fence *); 1322extern void nouveau_fence_work(struct nouveau_fence *fence, 1323 void (*work)(void *priv, bool signalled), 1324 void *priv); 1325struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1326 1327extern bool __nouveau_fence_signalled(void *obj, void *arg); 1328extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1329extern int __nouveau_fence_flush(void *obj, void *arg); 1330extern void __nouveau_fence_unref(void **obj); 1331extern void *__nouveau_fence_ref(void *obj); 1332 1333static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1334{ 1335 return __nouveau_fence_signalled(obj, NULL); 1336} 1337static inline int 1338nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1339{ 1340 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1341} 1342extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1343static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1344{ 1345 return __nouveau_fence_flush(obj, NULL); 1346} 1347static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1348{ 1349 __nouveau_fence_unref((void **)obj); 1350} 1351static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1352{ 1353 return __nouveau_fence_ref(obj); 1354} 1355 1356/* nouveau_gem.c */ 1357extern int nouveau_gem_new(struct drm_device *, int size, int align, 1358 uint32_t domain, uint32_t tile_mode, 1359 uint32_t tile_flags, struct nouveau_bo **); 1360extern int nouveau_gem_object_new(struct drm_gem_object *); 1361extern void nouveau_gem_object_del(struct drm_gem_object *); 1362extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1363extern void nouveau_gem_object_close(struct drm_gem_object *, 1364 struct drm_file *); 1365extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1366 struct drm_file *); 1367extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1368 struct drm_file *); 1369extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1370 struct drm_file *); 1371extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1372 struct drm_file *); 1373extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1374 struct drm_file *); 1375 1376/* nouveau_display.c */ 1377int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1378void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1379int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1380 struct drm_pending_vblank_event *event); 1381int nouveau_finish_page_flip(struct nouveau_channel *, 1382 struct nouveau_page_flip_state *); 1383 1384/* nv10_gpio.c */ 1385int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1386int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1387 1388/* nv50_gpio.c */ 1389int nv50_gpio_init(struct drm_device *dev); 1390void nv50_gpio_fini(struct drm_device *dev); 1391int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1392int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1393int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1394 void (*)(void *, int), void *); 1395void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1396 void (*)(void *, int), void *); 1397bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1398 1399/* nv50_calc. */ 1400int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1401 int *N1, int *M1, int *N2, int *M2, int *P); 1402int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1403 int clk, int *N, int *fN, int *M, int *P); 1404 1405#ifndef ioread32_native 1406#ifdef __BIG_ENDIAN 1407#define ioread16_native ioread16be 1408#define iowrite16_native iowrite16be 1409#define ioread32_native ioread32be 1410#define iowrite32_native iowrite32be 1411#else /* def __BIG_ENDIAN */ 1412#define ioread16_native ioread16 1413#define iowrite16_native iowrite16 1414#define ioread32_native ioread32 1415#define iowrite32_native iowrite32 1416#endif /* def __BIG_ENDIAN else */ 1417#endif /* !ioread32_native */ 1418 1419/* channel control reg access */ 1420static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1421{ 1422 return ioread32_native(chan->user + reg); 1423} 1424 1425static inline void nvchan_wr32(struct nouveau_channel *chan, 1426 unsigned reg, u32 val) 1427{ 1428 iowrite32_native(val, chan->user + reg); 1429} 1430 1431/* register access */ 1432static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1433{ 1434 struct drm_nouveau_private *dev_priv = dev->dev_private; 1435 return ioread32_native(dev_priv->mmio + reg); 1436} 1437 1438static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 iowrite32_native(val, dev_priv->mmio + reg); 1442} 1443 1444static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1445{ 1446 u32 tmp = nv_rd32(dev, reg); 1447 nv_wr32(dev, reg, (tmp & ~mask) | val); 1448 return tmp; 1449} 1450 1451static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1452{ 1453 struct drm_nouveau_private *dev_priv = dev->dev_private; 1454 return ioread8(dev_priv->mmio + reg); 1455} 1456 1457static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1458{ 1459 struct drm_nouveau_private *dev_priv = dev->dev_private; 1460 iowrite8(val, dev_priv->mmio + reg); 1461} 1462 1463#define nv_wait(dev, reg, mask, val) \ 1464 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1465#define nv_wait_ne(dev, reg, mask, val) \ 1466 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1467#define nv_wait_cb(dev, func, data) \ 1468 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1469 1470/* PRAMIN access */ 1471static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1472{ 1473 struct drm_nouveau_private *dev_priv = dev->dev_private; 1474 return ioread32_native(dev_priv->ramin + offset); 1475} 1476 1477static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1478{ 1479 struct drm_nouveau_private *dev_priv = dev->dev_private; 1480 iowrite32_native(val, dev_priv->ramin + offset); 1481} 1482 1483/* object access */ 1484extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1485extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1486 1487/* 1488 * Logging 1489 * Argument d is (struct drm_device *). 1490 */ 1491#define NV_PRINTK(level, d, fmt, arg...) \ 1492 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1493 pci_name(d->pdev), ##arg) 1494#ifndef NV_DEBUG_NOTRACE 1495#define NV_DEBUG(d, fmt, arg...) do { \ 1496 if (drm_debug & DRM_UT_DRIVER) { \ 1497 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1498 __LINE__, ##arg); \ 1499 } \ 1500} while (0) 1501#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1502 if (drm_debug & DRM_UT_KMS) { \ 1503 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1504 __LINE__, ##arg); \ 1505 } \ 1506} while (0) 1507#else 1508#define NV_DEBUG(d, fmt, arg...) do { \ 1509 if (drm_debug & DRM_UT_DRIVER) \ 1510 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1511} while (0) 1512#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1513 if (drm_debug & DRM_UT_KMS) \ 1514 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1515} while (0) 1516#endif 1517#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1518#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1519#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1520#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1521#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1522 1523/* nouveau_reg_debug bitmask */ 1524enum { 1525 NOUVEAU_REG_DEBUG_MC = 0x1, 1526 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1527 NOUVEAU_REG_DEBUG_FB = 0x4, 1528 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1529 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1530 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1531 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1532 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1533 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1534 NOUVEAU_REG_DEBUG_EVO = 0x200, 1535}; 1536 1537#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1538 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1539 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1540} while (0) 1541 1542static inline bool 1543nv_two_heads(struct drm_device *dev) 1544{ 1545 struct drm_nouveau_private *dev_priv = dev->dev_private; 1546 const int impl = dev->pci_device & 0x0ff0; 1547 1548 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1549 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1550 return true; 1551 1552 return false; 1553} 1554 1555static inline bool 1556nv_gf4_disp_arch(struct drm_device *dev) 1557{ 1558 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1559} 1560 1561static inline bool 1562nv_two_reg_pll(struct drm_device *dev) 1563{ 1564 struct drm_nouveau_private *dev_priv = dev->dev_private; 1565 const int impl = dev->pci_device & 0x0ff0; 1566 1567 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1568 return true; 1569 return false; 1570} 1571 1572static inline bool 1573nv_match_device(struct drm_device *dev, unsigned device, 1574 unsigned sub_vendor, unsigned sub_device) 1575{ 1576 return dev->pdev->device == device && 1577 dev->pdev->subsystem_vendor == sub_vendor && 1578 dev->pdev->subsystem_device == sub_device; 1579} 1580 1581static inline void * 1582nv_engine(struct drm_device *dev, int engine) 1583{ 1584 struct drm_nouveau_private *dev_priv = dev->dev_private; 1585 return (void *)dev_priv->eng[engine]; 1586} 1587 1588/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1589 * helpful to determine a number of other hardware features 1590 */ 1591static inline int 1592nv44_graph_class(struct drm_device *dev) 1593{ 1594 struct drm_nouveau_private *dev_priv = dev->dev_private; 1595 1596 if ((dev_priv->chipset & 0xf0) == 0x60) 1597 return 1; 1598 1599 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1600} 1601 1602/* memory type/access flags, do not match hardware values */ 1603#define NV_MEM_ACCESS_RO 1 1604#define NV_MEM_ACCESS_WO 2 1605#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1606#define NV_MEM_ACCESS_SYS 4 1607#define NV_MEM_ACCESS_VM 8 1608 1609#define NV_MEM_TARGET_VRAM 0 1610#define NV_MEM_TARGET_PCI 1 1611#define NV_MEM_TARGET_PCI_NOSNOOP 2 1612#define NV_MEM_TARGET_VM 3 1613#define NV_MEM_TARGET_GART 4 1614 1615#define NV_MEM_TYPE_VM 0x7f 1616#define NV_MEM_COMP_VM 0x03 1617 1618/* NV_SW object class */ 1619#define NV_SW 0x0000506e 1620#define NV_SW_DMA_SEMAPHORE 0x00000060 1621#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1622#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1623#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1624#define NV_SW_YIELD 0x00000080 1625#define NV_SW_DMA_VBLSEM 0x0000018c 1626#define NV_SW_VBLSEM_OFFSET 0x00000400 1627#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1628#define NV_SW_VBLSEM_RELEASE 0x00000408 1629#define NV_SW_PAGE_FLIP 0x00000500 1630 1631#endif /* __NOUVEAU_DRV_H__ */ 1632