nouveau_drv.h revision 332b242f47786d1a43bd7a19a0513dd5d493db8e
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 int pin_refcnt; 100}; 101 102#define nouveau_bo_tile_layout(nvbo) \ 103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 104 105static inline struct nouveau_bo * 106nouveau_bo(struct ttm_buffer_object *bo) 107{ 108 return container_of(bo, struct nouveau_bo, bo); 109} 110 111static inline struct nouveau_bo * 112nouveau_gem_object(struct drm_gem_object *gem) 113{ 114 return gem ? gem->driver_private : NULL; 115} 116 117/* TODO: submit equivalent to TTM generic API upstream? */ 118static inline void __iomem * 119nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 120{ 121 bool is_iomem; 122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 123 &nvbo->kmap, &is_iomem); 124 WARN_ON_ONCE(ioptr && !is_iomem); 125 return ioptr; 126} 127 128enum nouveau_flags { 129 NV_NFORCE = 0x10000000, 130 NV_NFORCE2 = 0x20000000 131}; 132 133#define NVOBJ_ENGINE_SW 0 134#define NVOBJ_ENGINE_GR 1 135#define NVOBJ_ENGINE_PPP 2 136#define NVOBJ_ENGINE_COPY 3 137#define NVOBJ_ENGINE_VP 4 138#define NVOBJ_ENGINE_CRYPT 5 139#define NVOBJ_ENGINE_BSP 6 140#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 141#define NVOBJ_ENGINE_INT 0xdeadbeef 142 143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 144#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 145struct nouveau_gpuobj { 146 struct drm_device *dev; 147 struct kref refcount; 148 struct list_head list; 149 150 struct drm_mm_node *im_pramin; 151 struct nouveau_bo *im_backing; 152 uint32_t *im_backing_suspend; 153 int im_bound; 154 155 uint32_t flags; 156 157 u32 size; 158 u32 pinst; 159 u32 cinst; 160 u64 vinst; 161 162 uint32_t engine; 163 uint32_t class; 164 165 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 166 void *priv; 167}; 168 169struct nouveau_page_flip_state { 170 struct list_head head; 171 struct drm_pending_vblank_event *event; 172 int crtc, bpp, pitch, x, y; 173 uint64_t offset; 174}; 175 176struct nouveau_channel { 177 struct drm_device *dev; 178 int id; 179 180 /* references to the channel data structure */ 181 struct kref ref; 182 /* users of the hardware channel resources, the hardware 183 * context will be kicked off when it reaches zero. */ 184 atomic_t users; 185 struct mutex mutex; 186 187 /* owner of this fifo */ 188 struct drm_file *file_priv; 189 /* mapping of the fifo itself */ 190 struct drm_local_map *map; 191 192 /* mapping of the regs controling the fifo */ 193 void __iomem *user; 194 uint32_t user_get; 195 uint32_t user_put; 196 197 /* Fencing */ 198 struct { 199 /* lock protects the pending list only */ 200 spinlock_t lock; 201 struct list_head pending; 202 uint32_t sequence; 203 uint32_t sequence_ack; 204 atomic_t last_sequence_irq; 205 } fence; 206 207 /* DMA push buffer */ 208 struct nouveau_gpuobj *pushbuf; 209 struct nouveau_bo *pushbuf_bo; 210 uint32_t pushbuf_base; 211 212 /* Notifier memory */ 213 struct nouveau_bo *notifier_bo; 214 struct drm_mm notifier_heap; 215 216 /* PFIFO context */ 217 struct nouveau_gpuobj *ramfc; 218 struct nouveau_gpuobj *cache; 219 220 /* PGRAPH context */ 221 /* XXX may be merge 2 pointers as private data ??? */ 222 struct nouveau_gpuobj *ramin_grctx; 223 struct nouveau_gpuobj *crypt_ctx; 224 void *pgraph_ctx; 225 226 /* NV50 VM */ 227 struct nouveau_gpuobj *vm_pd; 228 struct nouveau_gpuobj *vm_gart_pt; 229 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 230 231 /* Objects */ 232 struct nouveau_gpuobj *ramin; /* Private instmem */ 233 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 234 struct nouveau_ramht *ramht; /* Hash table */ 235 236 /* GPU object info for stuff used in-kernel (mm_enabled) */ 237 uint32_t m2mf_ntfy; 238 uint32_t vram_handle; 239 uint32_t gart_handle; 240 bool accel_done; 241 242 /* Push buffer state (only for drm's channel on !mm_enabled) */ 243 struct { 244 int max; 245 int free; 246 int cur; 247 int put; 248 /* access via pushbuf_bo */ 249 250 int ib_base; 251 int ib_max; 252 int ib_free; 253 int ib_put; 254 } dma; 255 256 uint32_t sw_subchannel[8]; 257 258 struct { 259 struct nouveau_gpuobj *vblsem; 260 uint32_t vblsem_offset; 261 uint32_t vblsem_rval; 262 struct list_head vbl_wait; 263 struct list_head flip; 264 } nvsw; 265 266 struct { 267 bool active; 268 char name[32]; 269 struct drm_info_list info; 270 } debugfs; 271}; 272 273struct nouveau_instmem_engine { 274 void *priv; 275 276 int (*init)(struct drm_device *dev); 277 void (*takedown)(struct drm_device *dev); 278 int (*suspend)(struct drm_device *dev); 279 void (*resume)(struct drm_device *dev); 280 281 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 282 u32 *size, u32 align); 283 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 284 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 285 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 286 void (*flush)(struct drm_device *); 287}; 288 289struct nouveau_mc_engine { 290 int (*init)(struct drm_device *dev); 291 void (*takedown)(struct drm_device *dev); 292}; 293 294struct nouveau_timer_engine { 295 int (*init)(struct drm_device *dev); 296 void (*takedown)(struct drm_device *dev); 297 uint64_t (*read)(struct drm_device *dev); 298}; 299 300struct nouveau_fb_engine { 301 int num_tiles; 302 303 int (*init)(struct drm_device *dev); 304 void (*takedown)(struct drm_device *dev); 305 306 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 307 uint32_t size, uint32_t pitch); 308}; 309 310struct nouveau_fifo_engine { 311 int channels; 312 313 struct nouveau_gpuobj *playlist[2]; 314 int cur_playlist; 315 316 int (*init)(struct drm_device *); 317 void (*takedown)(struct drm_device *); 318 319 void (*disable)(struct drm_device *); 320 void (*enable)(struct drm_device *); 321 bool (*reassign)(struct drm_device *, bool enable); 322 bool (*cache_pull)(struct drm_device *dev, bool enable); 323 324 int (*channel_id)(struct drm_device *); 325 326 int (*create_context)(struct nouveau_channel *); 327 void (*destroy_context)(struct nouveau_channel *); 328 int (*load_context)(struct nouveau_channel *); 329 int (*unload_context)(struct drm_device *); 330 void (*tlb_flush)(struct drm_device *dev); 331}; 332 333struct nouveau_pgraph_engine { 334 bool accel_blocked; 335 bool registered; 336 int grctx_size; 337 338 /* NV2x/NV3x context table (0x400780) */ 339 struct nouveau_gpuobj *ctx_table; 340 341 int (*init)(struct drm_device *); 342 void (*takedown)(struct drm_device *); 343 344 void (*fifo_access)(struct drm_device *, bool); 345 346 struct nouveau_channel *(*channel)(struct drm_device *); 347 int (*create_context)(struct nouveau_channel *); 348 void (*destroy_context)(struct nouveau_channel *); 349 int (*load_context)(struct nouveau_channel *); 350 int (*unload_context)(struct drm_device *); 351 void (*tlb_flush)(struct drm_device *dev); 352 353 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 354 uint32_t size, uint32_t pitch); 355}; 356 357struct nouveau_display_engine { 358 int (*early_init)(struct drm_device *); 359 void (*late_takedown)(struct drm_device *); 360 int (*create)(struct drm_device *); 361 int (*init)(struct drm_device *); 362 void (*destroy)(struct drm_device *); 363}; 364 365struct nouveau_gpio_engine { 366 int (*init)(struct drm_device *); 367 void (*takedown)(struct drm_device *); 368 369 int (*get)(struct drm_device *, enum dcb_gpio_tag); 370 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 371 372 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 373}; 374 375struct nouveau_pm_voltage_level { 376 u8 voltage; 377 u8 vid; 378}; 379 380struct nouveau_pm_voltage { 381 bool supported; 382 u8 vid_mask; 383 384 struct nouveau_pm_voltage_level *level; 385 int nr_level; 386}; 387 388#define NOUVEAU_PM_MAX_LEVEL 8 389struct nouveau_pm_level { 390 struct device_attribute dev_attr; 391 char name[32]; 392 int id; 393 394 u32 core; 395 u32 memory; 396 u32 shader; 397 u32 unk05; 398 399 u8 voltage; 400 u8 fanspeed; 401 402 u16 memscript; 403}; 404 405struct nouveau_pm_temp_sensor_constants { 406 u16 offset_constant; 407 s16 offset_mult; 408 u16 offset_div; 409 u16 slope_mult; 410 u16 slope_div; 411}; 412 413struct nouveau_pm_threshold_temp { 414 s16 critical; 415 s16 down_clock; 416 s16 fan_boost; 417}; 418 419struct nouveau_pm_memtiming { 420 u32 reg_100220; 421 u32 reg_100224; 422 u32 reg_100228; 423 u32 reg_10022c; 424 u32 reg_100230; 425 u32 reg_100234; 426 u32 reg_100238; 427 u32 reg_10023c; 428}; 429 430struct nouveau_pm_memtimings { 431 bool supported; 432 struct nouveau_pm_memtiming *timing; 433 int nr_timing; 434}; 435 436struct nouveau_pm_engine { 437 struct nouveau_pm_voltage voltage; 438 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 439 int nr_perflvl; 440 struct nouveau_pm_memtimings memtimings; 441 struct nouveau_pm_temp_sensor_constants sensor_constants; 442 struct nouveau_pm_threshold_temp threshold_temp; 443 444 struct nouveau_pm_level boot; 445 struct nouveau_pm_level *cur; 446 447 struct device *hwmon; 448 struct notifier_block acpi_nb; 449 450 int (*clock_get)(struct drm_device *, u32 id); 451 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 452 u32 id, int khz); 453 void (*clock_set)(struct drm_device *, void *); 454 int (*voltage_get)(struct drm_device *); 455 int (*voltage_set)(struct drm_device *, int voltage); 456 int (*fanspeed_get)(struct drm_device *); 457 int (*fanspeed_set)(struct drm_device *, int fanspeed); 458 int (*temp_get)(struct drm_device *); 459}; 460 461struct nouveau_crypt_engine { 462 bool registered; 463 464 int (*init)(struct drm_device *); 465 void (*takedown)(struct drm_device *); 466 int (*create_context)(struct nouveau_channel *); 467 void (*destroy_context)(struct nouveau_channel *); 468 void (*tlb_flush)(struct drm_device *dev); 469}; 470 471struct nouveau_engine { 472 struct nouveau_instmem_engine instmem; 473 struct nouveau_mc_engine mc; 474 struct nouveau_timer_engine timer; 475 struct nouveau_fb_engine fb; 476 struct nouveau_pgraph_engine graph; 477 struct nouveau_fifo_engine fifo; 478 struct nouveau_display_engine display; 479 struct nouveau_gpio_engine gpio; 480 struct nouveau_pm_engine pm; 481 struct nouveau_crypt_engine crypt; 482}; 483 484struct nouveau_pll_vals { 485 union { 486 struct { 487#ifdef __BIG_ENDIAN 488 uint8_t N1, M1, N2, M2; 489#else 490 uint8_t M1, N1, M2, N2; 491#endif 492 }; 493 struct { 494 uint16_t NM1, NM2; 495 } __attribute__((packed)); 496 }; 497 int log2P; 498 499 int refclk; 500}; 501 502enum nv04_fp_display_regs { 503 FP_DISPLAY_END, 504 FP_TOTAL, 505 FP_CRTC, 506 FP_SYNC_START, 507 FP_SYNC_END, 508 FP_VALID_START, 509 FP_VALID_END 510}; 511 512struct nv04_crtc_reg { 513 unsigned char MiscOutReg; 514 uint8_t CRTC[0xa0]; 515 uint8_t CR58[0x10]; 516 uint8_t Sequencer[5]; 517 uint8_t Graphics[9]; 518 uint8_t Attribute[21]; 519 unsigned char DAC[768]; 520 521 /* PCRTC regs */ 522 uint32_t fb_start; 523 uint32_t crtc_cfg; 524 uint32_t cursor_cfg; 525 uint32_t gpio_ext; 526 uint32_t crtc_830; 527 uint32_t crtc_834; 528 uint32_t crtc_850; 529 uint32_t crtc_eng_ctrl; 530 531 /* PRAMDAC regs */ 532 uint32_t nv10_cursync; 533 struct nouveau_pll_vals pllvals; 534 uint32_t ramdac_gen_ctrl; 535 uint32_t ramdac_630; 536 uint32_t ramdac_634; 537 uint32_t tv_setup; 538 uint32_t tv_vtotal; 539 uint32_t tv_vskew; 540 uint32_t tv_vsync_delay; 541 uint32_t tv_htotal; 542 uint32_t tv_hskew; 543 uint32_t tv_hsync_delay; 544 uint32_t tv_hsync_delay2; 545 uint32_t fp_horiz_regs[7]; 546 uint32_t fp_vert_regs[7]; 547 uint32_t dither; 548 uint32_t fp_control; 549 uint32_t dither_regs[6]; 550 uint32_t fp_debug_0; 551 uint32_t fp_debug_1; 552 uint32_t fp_debug_2; 553 uint32_t fp_margin_color; 554 uint32_t ramdac_8c0; 555 uint32_t ramdac_a20; 556 uint32_t ramdac_a24; 557 uint32_t ramdac_a34; 558 uint32_t ctv_regs[38]; 559}; 560 561struct nv04_output_reg { 562 uint32_t output; 563 int head; 564}; 565 566struct nv04_mode_state { 567 struct nv04_crtc_reg crtc_reg[2]; 568 uint32_t pllsel; 569 uint32_t sel_clk; 570}; 571 572enum nouveau_card_type { 573 NV_04 = 0x00, 574 NV_10 = 0x10, 575 NV_20 = 0x20, 576 NV_30 = 0x30, 577 NV_40 = 0x40, 578 NV_50 = 0x50, 579 NV_C0 = 0xc0, 580}; 581 582struct drm_nouveau_private { 583 struct drm_device *dev; 584 585 /* the card type, takes NV_* as values */ 586 enum nouveau_card_type card_type; 587 /* exact chipset, derived from NV_PMC_BOOT_0 */ 588 int chipset; 589 int flags; 590 591 void __iomem *mmio; 592 593 spinlock_t ramin_lock; 594 void __iomem *ramin; 595 u32 ramin_size; 596 u32 ramin_base; 597 bool ramin_available; 598 struct drm_mm ramin_heap; 599 struct list_head gpuobj_list; 600 struct list_head classes; 601 602 struct nouveau_bo *vga_ram; 603 604 /* interrupt handling */ 605 bool msi_enabled; 606 struct workqueue_struct *wq; 607 struct work_struct irq_work; 608 struct work_struct hpd_work; 609 610 struct { 611 spinlock_t lock; 612 uint32_t hpd0_bits; 613 uint32_t hpd1_bits; 614 } hpd_state; 615 616 struct list_head vbl_waiting; 617 618 struct { 619 struct drm_global_reference mem_global_ref; 620 struct ttm_bo_global_ref bo_global_ref; 621 struct ttm_bo_device bdev; 622 atomic_t validate_sequence; 623 } ttm; 624 625 struct { 626 spinlock_t lock; 627 struct drm_mm heap; 628 struct nouveau_bo *bo; 629 } fence; 630 631 struct { 632 spinlock_t lock; 633 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 634 } channels; 635 636 struct nouveau_engine engine; 637 struct nouveau_channel *channel; 638 639 /* For PFIFO and PGRAPH. */ 640 spinlock_t context_switch_lock; 641 642 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 643 struct nouveau_ramht *ramht; 644 struct nouveau_gpuobj *ramfc; 645 struct nouveau_gpuobj *ramro; 646 647 uint32_t ramin_rsvd_vram; 648 649 struct { 650 enum { 651 NOUVEAU_GART_NONE = 0, 652 NOUVEAU_GART_AGP, 653 NOUVEAU_GART_SGDMA 654 } type; 655 uint64_t aper_base; 656 uint64_t aper_size; 657 uint64_t aper_free; 658 659 struct nouveau_gpuobj *sg_ctxdma; 660 struct page *sg_dummy_page; 661 dma_addr_t sg_dummy_bus; 662 } gart_info; 663 664 /* nv10-nv40 tiling regions */ 665 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 666 667 /* VRAM/fb configuration */ 668 uint64_t vram_size; 669 uint64_t vram_sys_base; 670 u32 vram_rblock_size; 671 672 uint64_t fb_phys; 673 uint64_t fb_available_size; 674 uint64_t fb_mappable_pages; 675 uint64_t fb_aper_free; 676 int fb_mtrr; 677 678 /* G8x/G9x virtual address space */ 679 uint64_t vm_gart_base; 680 uint64_t vm_gart_size; 681 uint64_t vm_vram_base; 682 uint64_t vm_vram_size; 683 uint64_t vm_end; 684 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 685 int vm_vram_pt_nr; 686 687 struct nvbios vbios; 688 689 struct nv04_mode_state mode_reg; 690 struct nv04_mode_state saved_reg; 691 uint32_t saved_vga_font[4][16384]; 692 uint32_t crtc_owner; 693 uint32_t dac_users[4]; 694 695 struct nouveau_suspend_resume { 696 uint32_t *ramin_copy; 697 } susres; 698 699 struct backlight_device *backlight; 700 701 struct nouveau_channel *evo; 702 u32 evo_alloc; 703 struct { 704 struct dcb_entry *dcb; 705 u16 script; 706 u32 pclk; 707 } evo_irq; 708 709 struct { 710 struct dentry *channel_root; 711 } debugfs; 712 713 struct nouveau_fbdev *nfbdev; 714 struct apertures_struct *apertures; 715}; 716 717static inline struct drm_nouveau_private * 718nouveau_private(struct drm_device *dev) 719{ 720 return dev->dev_private; 721} 722 723static inline struct drm_nouveau_private * 724nouveau_bdev(struct ttm_bo_device *bd) 725{ 726 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 727} 728 729static inline int 730nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 731{ 732 struct nouveau_bo *prev; 733 734 if (!pnvbo) 735 return -EINVAL; 736 prev = *pnvbo; 737 738 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 739 if (prev) { 740 struct ttm_buffer_object *bo = &prev->bo; 741 742 ttm_bo_unref(&bo); 743 } 744 745 return 0; 746} 747 748/* nouveau_drv.c */ 749extern int nouveau_agpmode; 750extern int nouveau_duallink; 751extern int nouveau_uscript_lvds; 752extern int nouveau_uscript_tmds; 753extern int nouveau_vram_pushbuf; 754extern int nouveau_vram_notify; 755extern int nouveau_fbpercrtc; 756extern int nouveau_tv_disable; 757extern char *nouveau_tv_norm; 758extern int nouveau_reg_debug; 759extern char *nouveau_vbios; 760extern int nouveau_ignorelid; 761extern int nouveau_nofbaccel; 762extern int nouveau_noaccel; 763extern int nouveau_force_post; 764extern int nouveau_override_conntype; 765extern char *nouveau_perflvl; 766extern int nouveau_perflvl_wr; 767extern int nouveau_msi; 768 769extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 770extern int nouveau_pci_resume(struct pci_dev *pdev); 771 772/* nouveau_state.c */ 773extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 774extern int nouveau_load(struct drm_device *, unsigned long flags); 775extern int nouveau_firstopen(struct drm_device *); 776extern void nouveau_lastclose(struct drm_device *); 777extern int nouveau_unload(struct drm_device *); 778extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 779 struct drm_file *); 780extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 781 struct drm_file *); 782extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 783 uint32_t reg, uint32_t mask, uint32_t val); 784extern bool nouveau_wait_for_idle(struct drm_device *); 785extern int nouveau_card_init(struct drm_device *); 786 787/* nouveau_mem.c */ 788extern int nouveau_mem_vram_init(struct drm_device *); 789extern void nouveau_mem_vram_fini(struct drm_device *); 790extern int nouveau_mem_gart_init(struct drm_device *); 791extern void nouveau_mem_gart_fini(struct drm_device *); 792extern int nouveau_mem_init_agp(struct drm_device *); 793extern int nouveau_mem_reset_agp(struct drm_device *); 794extern void nouveau_mem_close(struct drm_device *); 795extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 796 uint32_t addr, 797 uint32_t size, 798 uint32_t pitch); 799extern void nv10_mem_expire_tiling(struct drm_device *dev, 800 struct nouveau_tile_reg *tile, 801 struct nouveau_fence *fence); 802extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 803 uint32_t size, uint32_t flags, 804 uint64_t phys); 805extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 806 uint32_t size); 807 808/* nouveau_notifier.c */ 809extern int nouveau_notifier_init_channel(struct nouveau_channel *); 810extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 811extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 812 int cout, uint32_t *offset); 813extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 814extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 815 struct drm_file *); 816extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 817 struct drm_file *); 818 819/* nouveau_channel.c */ 820extern struct drm_ioctl_desc nouveau_ioctls[]; 821extern int nouveau_max_ioctl; 822extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 823extern int nouveau_channel_alloc(struct drm_device *dev, 824 struct nouveau_channel **chan, 825 struct drm_file *file_priv, 826 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 827extern struct nouveau_channel * 828nouveau_channel_get_unlocked(struct nouveau_channel *); 829extern struct nouveau_channel * 830nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 831extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 832extern void nouveau_channel_put(struct nouveau_channel **); 833extern void nouveau_channel_ref(struct nouveau_channel *chan, 834 struct nouveau_channel **pchan); 835 836/* nouveau_object.c */ 837#define NVOBJ_CLASS(d,c,e) do { \ 838 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 839 if (ret) \ 840 return ret; \ 841} while(0) 842 843#define NVOBJ_MTHD(d,c,m,e) do { \ 844 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 845 if (ret) \ 846 return ret; \ 847} while(0) 848 849extern int nouveau_gpuobj_early_init(struct drm_device *); 850extern int nouveau_gpuobj_init(struct drm_device *); 851extern void nouveau_gpuobj_takedown(struct drm_device *); 852extern int nouveau_gpuobj_suspend(struct drm_device *dev); 853extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 854extern void nouveau_gpuobj_resume(struct drm_device *dev); 855extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 856extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 857 int (*exec)(struct nouveau_channel *, 858 u32 class, u32 mthd, u32 data)); 859extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 860extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 861 uint32_t vram_h, uint32_t tt_h); 862extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 863extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 864 uint32_t size, int align, uint32_t flags, 865 struct nouveau_gpuobj **); 866extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 867 struct nouveau_gpuobj **); 868extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 869 u32 size, u32 flags, 870 struct nouveau_gpuobj **); 871extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 872 uint64_t offset, uint64_t size, int access, 873 int target, struct nouveau_gpuobj **); 874extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 875 uint64_t offset, uint64_t size, 876 int access, struct nouveau_gpuobj **, 877 uint32_t *o_ret); 878extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 879 struct nouveau_gpuobj **); 880extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 881 struct drm_file *); 882extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 883 struct drm_file *); 884 885/* nouveau_irq.c */ 886extern int nouveau_irq_init(struct drm_device *); 887extern void nouveau_irq_fini(struct drm_device *); 888extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 889extern void nouveau_irq_preinstall(struct drm_device *); 890extern int nouveau_irq_postinstall(struct drm_device *); 891extern void nouveau_irq_uninstall(struct drm_device *); 892 893/* nouveau_sgdma.c */ 894extern int nouveau_sgdma_init(struct drm_device *); 895extern void nouveau_sgdma_takedown(struct drm_device *); 896extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 897 uint32_t *page); 898extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 899 900/* nouveau_debugfs.c */ 901#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 902extern int nouveau_debugfs_init(struct drm_minor *); 903extern void nouveau_debugfs_takedown(struct drm_minor *); 904extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 905extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 906#else 907static inline int 908nouveau_debugfs_init(struct drm_minor *minor) 909{ 910 return 0; 911} 912 913static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 914{ 915} 916 917static inline int 918nouveau_debugfs_channel_init(struct nouveau_channel *chan) 919{ 920 return 0; 921} 922 923static inline void 924nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 925{ 926} 927#endif 928 929/* nouveau_dma.c */ 930extern void nouveau_dma_pre_init(struct nouveau_channel *); 931extern int nouveau_dma_init(struct nouveau_channel *); 932extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 933 934/* nouveau_acpi.c */ 935#define ROM_BIOS_PAGE 4096 936#if defined(CONFIG_ACPI) 937void nouveau_register_dsm_handler(void); 938void nouveau_unregister_dsm_handler(void); 939int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 940bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 941int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 942#else 943static inline void nouveau_register_dsm_handler(void) {} 944static inline void nouveau_unregister_dsm_handler(void) {} 945static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 946static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 947static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 948#endif 949 950/* nouveau_backlight.c */ 951#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 952extern int nouveau_backlight_init(struct drm_device *); 953extern void nouveau_backlight_exit(struct drm_device *); 954#else 955static inline int nouveau_backlight_init(struct drm_device *dev) 956{ 957 return 0; 958} 959 960static inline void nouveau_backlight_exit(struct drm_device *dev) { } 961#endif 962 963/* nouveau_bios.c */ 964extern int nouveau_bios_init(struct drm_device *); 965extern void nouveau_bios_takedown(struct drm_device *dev); 966extern int nouveau_run_vbios_init(struct drm_device *); 967extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 968 struct dcb_entry *); 969extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 970 enum dcb_gpio_tag); 971extern struct dcb_connector_table_entry * 972nouveau_bios_connector_entry(struct drm_device *, int index); 973extern u32 get_pll_register(struct drm_device *, enum pll_types); 974extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 975 struct pll_lims *); 976extern int nouveau_bios_run_display_table(struct drm_device *, 977 struct dcb_entry *, 978 uint32_t script, int pxclk); 979extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 980 int *length); 981extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 982extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 983extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 984 bool *dl, bool *if_is_24bit); 985extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 986 int head, int pxclk); 987extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 988 enum LVDS_script, int pxclk); 989 990/* nouveau_ttm.c */ 991int nouveau_ttm_global_init(struct drm_nouveau_private *); 992void nouveau_ttm_global_release(struct drm_nouveau_private *); 993int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 994 995/* nouveau_dp.c */ 996int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 997 uint8_t *data, int data_nr); 998bool nouveau_dp_detect(struct drm_encoder *); 999bool nouveau_dp_link_train(struct drm_encoder *); 1000 1001/* nv04_fb.c */ 1002extern int nv04_fb_init(struct drm_device *); 1003extern void nv04_fb_takedown(struct drm_device *); 1004 1005/* nv10_fb.c */ 1006extern int nv10_fb_init(struct drm_device *); 1007extern void nv10_fb_takedown(struct drm_device *); 1008extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 1009 uint32_t, uint32_t); 1010 1011/* nv30_fb.c */ 1012extern int nv30_fb_init(struct drm_device *); 1013extern void nv30_fb_takedown(struct drm_device *); 1014 1015/* nv40_fb.c */ 1016extern int nv40_fb_init(struct drm_device *); 1017extern void nv40_fb_takedown(struct drm_device *); 1018extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 1019 uint32_t, uint32_t); 1020/* nv50_fb.c */ 1021extern int nv50_fb_init(struct drm_device *); 1022extern void nv50_fb_takedown(struct drm_device *); 1023extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1024 1025/* nvc0_fb.c */ 1026extern int nvc0_fb_init(struct drm_device *); 1027extern void nvc0_fb_takedown(struct drm_device *); 1028 1029/* nv04_fifo.c */ 1030extern int nv04_fifo_init(struct drm_device *); 1031extern void nv04_fifo_disable(struct drm_device *); 1032extern void nv04_fifo_enable(struct drm_device *); 1033extern bool nv04_fifo_reassign(struct drm_device *, bool); 1034extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1035extern int nv04_fifo_channel_id(struct drm_device *); 1036extern int nv04_fifo_create_context(struct nouveau_channel *); 1037extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1038extern int nv04_fifo_load_context(struct nouveau_channel *); 1039extern int nv04_fifo_unload_context(struct drm_device *); 1040 1041/* nv10_fifo.c */ 1042extern int nv10_fifo_init(struct drm_device *); 1043extern int nv10_fifo_channel_id(struct drm_device *); 1044extern int nv10_fifo_create_context(struct nouveau_channel *); 1045extern int nv10_fifo_load_context(struct nouveau_channel *); 1046extern int nv10_fifo_unload_context(struct drm_device *); 1047 1048/* nv40_fifo.c */ 1049extern int nv40_fifo_init(struct drm_device *); 1050extern int nv40_fifo_create_context(struct nouveau_channel *); 1051extern int nv40_fifo_load_context(struct nouveau_channel *); 1052extern int nv40_fifo_unload_context(struct drm_device *); 1053 1054/* nv50_fifo.c */ 1055extern int nv50_fifo_init(struct drm_device *); 1056extern void nv50_fifo_takedown(struct drm_device *); 1057extern int nv50_fifo_channel_id(struct drm_device *); 1058extern int nv50_fifo_create_context(struct nouveau_channel *); 1059extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1060extern int nv50_fifo_load_context(struct nouveau_channel *); 1061extern int nv50_fifo_unload_context(struct drm_device *); 1062extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1063 1064/* nvc0_fifo.c */ 1065extern int nvc0_fifo_init(struct drm_device *); 1066extern void nvc0_fifo_takedown(struct drm_device *); 1067extern void nvc0_fifo_disable(struct drm_device *); 1068extern void nvc0_fifo_enable(struct drm_device *); 1069extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1070extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1071extern int nvc0_fifo_channel_id(struct drm_device *); 1072extern int nvc0_fifo_create_context(struct nouveau_channel *); 1073extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1074extern int nvc0_fifo_load_context(struct nouveau_channel *); 1075extern int nvc0_fifo_unload_context(struct drm_device *); 1076 1077/* nv04_graph.c */ 1078extern int nv04_graph_init(struct drm_device *); 1079extern void nv04_graph_takedown(struct drm_device *); 1080extern void nv04_graph_fifo_access(struct drm_device *, bool); 1081extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1082extern int nv04_graph_create_context(struct nouveau_channel *); 1083extern void nv04_graph_destroy_context(struct nouveau_channel *); 1084extern int nv04_graph_load_context(struct nouveau_channel *); 1085extern int nv04_graph_unload_context(struct drm_device *); 1086extern void nv04_graph_context_switch(struct drm_device *); 1087extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1088 u32 class, u32 mthd, u32 data); 1089 1090/* nv10_graph.c */ 1091extern int nv10_graph_init(struct drm_device *); 1092extern void nv10_graph_takedown(struct drm_device *); 1093extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1094extern int nv10_graph_create_context(struct nouveau_channel *); 1095extern void nv10_graph_destroy_context(struct nouveau_channel *); 1096extern int nv10_graph_load_context(struct nouveau_channel *); 1097extern int nv10_graph_unload_context(struct drm_device *); 1098extern void nv10_graph_context_switch(struct drm_device *); 1099extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1100 uint32_t, uint32_t); 1101 1102/* nv20_graph.c */ 1103extern int nv20_graph_create_context(struct nouveau_channel *); 1104extern void nv20_graph_destroy_context(struct nouveau_channel *); 1105extern int nv20_graph_load_context(struct nouveau_channel *); 1106extern int nv20_graph_unload_context(struct drm_device *); 1107extern int nv20_graph_init(struct drm_device *); 1108extern void nv20_graph_takedown(struct drm_device *); 1109extern int nv30_graph_init(struct drm_device *); 1110extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1111 uint32_t, uint32_t); 1112 1113/* nv40_graph.c */ 1114extern int nv40_graph_init(struct drm_device *); 1115extern void nv40_graph_takedown(struct drm_device *); 1116extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1117extern int nv40_graph_create_context(struct nouveau_channel *); 1118extern void nv40_graph_destroy_context(struct nouveau_channel *); 1119extern int nv40_graph_load_context(struct nouveau_channel *); 1120extern int nv40_graph_unload_context(struct drm_device *); 1121extern void nv40_grctx_init(struct nouveau_grctx *); 1122extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1123 uint32_t, uint32_t); 1124 1125/* nv50_graph.c */ 1126extern int nv50_graph_init(struct drm_device *); 1127extern void nv50_graph_takedown(struct drm_device *); 1128extern void nv50_graph_fifo_access(struct drm_device *, bool); 1129extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1130extern int nv50_graph_create_context(struct nouveau_channel *); 1131extern void nv50_graph_destroy_context(struct nouveau_channel *); 1132extern int nv50_graph_load_context(struct nouveau_channel *); 1133extern int nv50_graph_unload_context(struct drm_device *); 1134extern void nv50_graph_context_switch(struct drm_device *); 1135extern int nv50_grctx_init(struct nouveau_grctx *); 1136extern void nv50_graph_tlb_flush(struct drm_device *dev); 1137extern void nv86_graph_tlb_flush(struct drm_device *dev); 1138 1139/* nvc0_graph.c */ 1140extern int nvc0_graph_init(struct drm_device *); 1141extern void nvc0_graph_takedown(struct drm_device *); 1142extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1143extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1144extern int nvc0_graph_create_context(struct nouveau_channel *); 1145extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1146extern int nvc0_graph_load_context(struct nouveau_channel *); 1147extern int nvc0_graph_unload_context(struct drm_device *); 1148 1149/* nv84_crypt.c */ 1150extern int nv84_crypt_init(struct drm_device *dev); 1151extern void nv84_crypt_fini(struct drm_device *dev); 1152extern int nv84_crypt_create_context(struct nouveau_channel *); 1153extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1154extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1155 1156/* nv04_instmem.c */ 1157extern int nv04_instmem_init(struct drm_device *); 1158extern void nv04_instmem_takedown(struct drm_device *); 1159extern int nv04_instmem_suspend(struct drm_device *); 1160extern void nv04_instmem_resume(struct drm_device *); 1161extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1162 u32 *size, u32 align); 1163extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1164extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1165extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1166extern void nv04_instmem_flush(struct drm_device *); 1167 1168/* nv50_instmem.c */ 1169extern int nv50_instmem_init(struct drm_device *); 1170extern void nv50_instmem_takedown(struct drm_device *); 1171extern int nv50_instmem_suspend(struct drm_device *); 1172extern void nv50_instmem_resume(struct drm_device *); 1173extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1174 u32 *size, u32 align); 1175extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1176extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1177extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1178extern void nv50_instmem_flush(struct drm_device *); 1179extern void nv84_instmem_flush(struct drm_device *); 1180extern void nv50_vm_flush(struct drm_device *, int engine); 1181 1182/* nvc0_instmem.c */ 1183extern int nvc0_instmem_init(struct drm_device *); 1184extern void nvc0_instmem_takedown(struct drm_device *); 1185extern int nvc0_instmem_suspend(struct drm_device *); 1186extern void nvc0_instmem_resume(struct drm_device *); 1187extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1188 u32 *size, u32 align); 1189extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1190extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1191extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1192extern void nvc0_instmem_flush(struct drm_device *); 1193 1194/* nv04_mc.c */ 1195extern int nv04_mc_init(struct drm_device *); 1196extern void nv04_mc_takedown(struct drm_device *); 1197 1198/* nv40_mc.c */ 1199extern int nv40_mc_init(struct drm_device *); 1200extern void nv40_mc_takedown(struct drm_device *); 1201 1202/* nv50_mc.c */ 1203extern int nv50_mc_init(struct drm_device *); 1204extern void nv50_mc_takedown(struct drm_device *); 1205 1206/* nv04_timer.c */ 1207extern int nv04_timer_init(struct drm_device *); 1208extern uint64_t nv04_timer_read(struct drm_device *); 1209extern void nv04_timer_takedown(struct drm_device *); 1210 1211extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1212 unsigned long arg); 1213 1214/* nv04_dac.c */ 1215extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1216extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1217extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1218extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1219extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1220 1221/* nv04_dfp.c */ 1222extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1223extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1224extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1225 int head, bool dl); 1226extern void nv04_dfp_disable(struct drm_device *dev, int head); 1227extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1228 1229/* nv04_tv.c */ 1230extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1231extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1232 1233/* nv17_tv.c */ 1234extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1235 1236/* nv04_display.c */ 1237extern int nv04_display_early_init(struct drm_device *); 1238extern void nv04_display_late_takedown(struct drm_device *); 1239extern int nv04_display_create(struct drm_device *); 1240extern int nv04_display_init(struct drm_device *); 1241extern void nv04_display_destroy(struct drm_device *); 1242 1243/* nv04_crtc.c */ 1244extern int nv04_crtc_create(struct drm_device *, int index); 1245 1246/* nouveau_bo.c */ 1247extern struct ttm_bo_driver nouveau_bo_driver; 1248extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1249 int size, int align, uint32_t flags, 1250 uint32_t tile_mode, uint32_t tile_flags, 1251 bool no_vm, bool mappable, struct nouveau_bo **); 1252extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1253extern int nouveau_bo_unpin(struct nouveau_bo *); 1254extern int nouveau_bo_map(struct nouveau_bo *); 1255extern void nouveau_bo_unmap(struct nouveau_bo *); 1256extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1257 uint32_t busy); 1258extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1259extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1260extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1261extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1262extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1263 1264/* nouveau_fence.c */ 1265struct nouveau_fence; 1266extern int nouveau_fence_init(struct drm_device *); 1267extern void nouveau_fence_fini(struct drm_device *); 1268extern int nouveau_fence_channel_init(struct nouveau_channel *); 1269extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1270extern void nouveau_fence_update(struct nouveau_channel *); 1271extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1272 bool emit); 1273extern int nouveau_fence_emit(struct nouveau_fence *); 1274extern void nouveau_fence_work(struct nouveau_fence *fence, 1275 void (*work)(void *priv, bool signalled), 1276 void *priv); 1277struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1278 1279extern bool __nouveau_fence_signalled(void *obj, void *arg); 1280extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1281extern int __nouveau_fence_flush(void *obj, void *arg); 1282extern void __nouveau_fence_unref(void **obj); 1283extern void *__nouveau_fence_ref(void *obj); 1284 1285static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1286{ 1287 return __nouveau_fence_signalled(obj, NULL); 1288} 1289static inline int 1290nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1291{ 1292 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1293} 1294extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1295static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1296{ 1297 return __nouveau_fence_flush(obj, NULL); 1298} 1299static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1300{ 1301 __nouveau_fence_unref((void **)obj); 1302} 1303static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1304{ 1305 return __nouveau_fence_ref(obj); 1306} 1307 1308/* nouveau_gem.c */ 1309extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1310 int size, int align, uint32_t flags, 1311 uint32_t tile_mode, uint32_t tile_flags, 1312 bool no_vm, bool mappable, struct nouveau_bo **); 1313extern int nouveau_gem_object_new(struct drm_gem_object *); 1314extern void nouveau_gem_object_del(struct drm_gem_object *); 1315extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1316 struct drm_file *); 1317extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1318 struct drm_file *); 1319extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1320 struct drm_file *); 1321extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1322 struct drm_file *); 1323extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1324 struct drm_file *); 1325 1326/* nouveau_display.c */ 1327int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1328void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1329int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1330 struct drm_pending_vblank_event *event); 1331int nouveau_finish_page_flip(struct nouveau_channel *, 1332 struct nouveau_page_flip_state *); 1333 1334/* nv10_gpio.c */ 1335int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1336int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1337 1338/* nv50_gpio.c */ 1339int nv50_gpio_init(struct drm_device *dev); 1340int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1341int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1342void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1343 1344/* nv50_calc. */ 1345int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1346 int *N1, int *M1, int *N2, int *M2, int *P); 1347int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1348 int clk, int *N, int *fN, int *M, int *P); 1349 1350#ifndef ioread32_native 1351#ifdef __BIG_ENDIAN 1352#define ioread16_native ioread16be 1353#define iowrite16_native iowrite16be 1354#define ioread32_native ioread32be 1355#define iowrite32_native iowrite32be 1356#else /* def __BIG_ENDIAN */ 1357#define ioread16_native ioread16 1358#define iowrite16_native iowrite16 1359#define ioread32_native ioread32 1360#define iowrite32_native iowrite32 1361#endif /* def __BIG_ENDIAN else */ 1362#endif /* !ioread32_native */ 1363 1364/* channel control reg access */ 1365static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1366{ 1367 return ioread32_native(chan->user + reg); 1368} 1369 1370static inline void nvchan_wr32(struct nouveau_channel *chan, 1371 unsigned reg, u32 val) 1372{ 1373 iowrite32_native(val, chan->user + reg); 1374} 1375 1376/* register access */ 1377static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1378{ 1379 struct drm_nouveau_private *dev_priv = dev->dev_private; 1380 return ioread32_native(dev_priv->mmio + reg); 1381} 1382 1383static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1384{ 1385 struct drm_nouveau_private *dev_priv = dev->dev_private; 1386 iowrite32_native(val, dev_priv->mmio + reg); 1387} 1388 1389static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1390{ 1391 u32 tmp = nv_rd32(dev, reg); 1392 nv_wr32(dev, reg, (tmp & ~mask) | val); 1393 return tmp; 1394} 1395 1396static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1397{ 1398 struct drm_nouveau_private *dev_priv = dev->dev_private; 1399 return ioread8(dev_priv->mmio + reg); 1400} 1401 1402static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1403{ 1404 struct drm_nouveau_private *dev_priv = dev->dev_private; 1405 iowrite8(val, dev_priv->mmio + reg); 1406} 1407 1408#define nv_wait(dev, reg, mask, val) \ 1409 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1410 1411/* PRAMIN access */ 1412static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1413{ 1414 struct drm_nouveau_private *dev_priv = dev->dev_private; 1415 return ioread32_native(dev_priv->ramin + offset); 1416} 1417 1418static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1419{ 1420 struct drm_nouveau_private *dev_priv = dev->dev_private; 1421 iowrite32_native(val, dev_priv->ramin + offset); 1422} 1423 1424/* object access */ 1425extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1426extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1427 1428/* 1429 * Logging 1430 * Argument d is (struct drm_device *). 1431 */ 1432#define NV_PRINTK(level, d, fmt, arg...) \ 1433 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1434 pci_name(d->pdev), ##arg) 1435#ifndef NV_DEBUG_NOTRACE 1436#define NV_DEBUG(d, fmt, arg...) do { \ 1437 if (drm_debug & DRM_UT_DRIVER) { \ 1438 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1439 __LINE__, ##arg); \ 1440 } \ 1441} while (0) 1442#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1443 if (drm_debug & DRM_UT_KMS) { \ 1444 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1445 __LINE__, ##arg); \ 1446 } \ 1447} while (0) 1448#else 1449#define NV_DEBUG(d, fmt, arg...) do { \ 1450 if (drm_debug & DRM_UT_DRIVER) \ 1451 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1452} while (0) 1453#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1454 if (drm_debug & DRM_UT_KMS) \ 1455 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1456} while (0) 1457#endif 1458#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1459#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1460#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1461#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1462#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1463 1464/* nouveau_reg_debug bitmask */ 1465enum { 1466 NOUVEAU_REG_DEBUG_MC = 0x1, 1467 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1468 NOUVEAU_REG_DEBUG_FB = 0x4, 1469 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1470 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1471 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1472 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1473 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1474 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1475 NOUVEAU_REG_DEBUG_EVO = 0x200, 1476}; 1477 1478#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1479 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1480 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1481} while (0) 1482 1483static inline bool 1484nv_two_heads(struct drm_device *dev) 1485{ 1486 struct drm_nouveau_private *dev_priv = dev->dev_private; 1487 const int impl = dev->pci_device & 0x0ff0; 1488 1489 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1490 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1491 return true; 1492 1493 return false; 1494} 1495 1496static inline bool 1497nv_gf4_disp_arch(struct drm_device *dev) 1498{ 1499 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1500} 1501 1502static inline bool 1503nv_two_reg_pll(struct drm_device *dev) 1504{ 1505 struct drm_nouveau_private *dev_priv = dev->dev_private; 1506 const int impl = dev->pci_device & 0x0ff0; 1507 1508 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1509 return true; 1510 return false; 1511} 1512 1513static inline bool 1514nv_match_device(struct drm_device *dev, unsigned device, 1515 unsigned sub_vendor, unsigned sub_device) 1516{ 1517 return dev->pdev->device == device && 1518 dev->pdev->subsystem_vendor == sub_vendor && 1519 dev->pdev->subsystem_device == sub_device; 1520} 1521 1522#define NV_SW 0x0000506e 1523#define NV_SW_DMA_SEMAPHORE 0x00000060 1524#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1525#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1526#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1527#define NV_SW_YIELD 0x00000080 1528#define NV_SW_DMA_VBLSEM 0x0000018c 1529#define NV_SW_VBLSEM_OFFSET 0x00000400 1530#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1531#define NV_SW_VBLSEM_RELEASE 0x00000408 1532#define NV_SW_PAGE_FLIP 0x00000500 1533 1534#endif /* __NOUVEAU_DRV_H__ */ 1535