nouveau_drv.h revision 35bb5089cc74e6d64cf0171b55c93e1bf8b8198d
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401}; 402 403struct nouveau_gpio_engine { 404 void *priv; 405 406 int (*init)(struct drm_device *); 407 void (*takedown)(struct drm_device *); 408 409 int (*get)(struct drm_device *, enum dcb_gpio_tag); 410 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 411 412 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 413 void (*)(void *, int), void *); 414 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 415 void (*)(void *, int), void *); 416 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 417}; 418 419struct nouveau_pm_voltage_level { 420 u32 voltage; /* microvolts */ 421 u8 vid; 422}; 423 424struct nouveau_pm_voltage { 425 bool supported; 426 u8 version; 427 u8 vid_mask; 428 429 struct nouveau_pm_voltage_level *level; 430 int nr_level; 431}; 432 433struct nouveau_pm_memtiming { 434 int id; 435 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 436 u32 reg_1; 437 u32 reg_2; 438 u32 reg_3; 439 u32 reg_4; 440 u32 reg_5; 441 u32 reg_6; 442 u32 reg_7; 443 u32 reg_8; 444 /* To be written to 0x1002c0 */ 445 u8 CL; 446 u8 WR; 447}; 448 449struct nouveau_pm_tbl_header{ 450 u8 version; 451 u8 header_len; 452 u8 entry_cnt; 453 u8 entry_len; 454}; 455 456struct nouveau_pm_tbl_entry{ 457 u8 tWR; 458 u8 tUNK_1; 459 u8 tCL; 460 u8 tRP; /* Byte 3 */ 461 u8 empty_4; 462 u8 tRAS; /* Byte 5 */ 463 u8 empty_6; 464 u8 tRFC; /* Byte 7 */ 465 u8 empty_8; 466 u8 tRC; /* Byte 9 */ 467 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 468 u8 empty_15,empty_16,empty_17; 469 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 470}; 471 472/* nouveau_mem.c */ 473void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 474 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 475 struct nouveau_pm_memtiming *timing); 476 477#define NOUVEAU_PM_MAX_LEVEL 8 478struct nouveau_pm_level { 479 struct device_attribute dev_attr; 480 char name[32]; 481 int id; 482 483 u32 core; 484 u32 memory; 485 u32 shader; 486 u32 rop; 487 u32 copy; 488 u32 daemon; 489 u32 vdec; 490 u32 unka0; /* nva3:nvc0 */ 491 u32 hub01; /* nvc0- */ 492 u32 hub06; /* nvc0- */ 493 u32 hub07; /* nvc0- */ 494 495 u32 volt_min; /* microvolts */ 496 u32 volt_max; 497 u8 fanspeed; 498 499 u16 memscript; 500 struct nouveau_pm_memtiming *timing; 501}; 502 503struct nouveau_pm_temp_sensor_constants { 504 u16 offset_constant; 505 s16 offset_mult; 506 s16 offset_div; 507 s16 slope_mult; 508 s16 slope_div; 509}; 510 511struct nouveau_pm_threshold_temp { 512 s16 critical; 513 s16 down_clock; 514 s16 fan_boost; 515}; 516 517struct nouveau_pm_memtimings { 518 bool supported; 519 struct nouveau_pm_memtiming *timing; 520 int nr_timing; 521}; 522 523struct nouveau_pm_fan { 524 u32 min_duty; 525 u32 max_duty; 526 u32 pwm_freq; 527}; 528 529struct nouveau_pm_engine { 530 struct nouveau_pm_voltage voltage; 531 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 532 int nr_perflvl; 533 struct nouveau_pm_memtimings memtimings; 534 struct nouveau_pm_temp_sensor_constants sensor_constants; 535 struct nouveau_pm_threshold_temp threshold_temp; 536 struct nouveau_pm_fan fan; 537 u32 pwm_divisor; 538 539 struct nouveau_pm_level boot; 540 struct nouveau_pm_level *cur; 541 542 struct device *hwmon; 543 struct notifier_block acpi_nb; 544 545 int (*clock_get)(struct drm_device *, u32 id); 546 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 547 u32 id, int khz); 548 void (*clock_set)(struct drm_device *, void *); 549 550 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 551 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 552 void (*clocks_set)(struct drm_device *, void *); 553 554 int (*voltage_get)(struct drm_device *); 555 int (*voltage_set)(struct drm_device *, int voltage); 556 int (*pwm_get)(struct drm_device *, struct dcb_gpio_entry*, u32*, u32*); 557 int (*pwm_set)(struct drm_device *, struct dcb_gpio_entry*, u32, u32); 558 int (*temp_get)(struct drm_device *); 559}; 560 561struct nouveau_vram_engine { 562 struct nouveau_mm mm; 563 564 int (*init)(struct drm_device *); 565 void (*takedown)(struct drm_device *dev); 566 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 567 u32 type, struct nouveau_mem **); 568 void (*put)(struct drm_device *, struct nouveau_mem **); 569 570 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 571}; 572 573struct nouveau_engine { 574 struct nouveau_instmem_engine instmem; 575 struct nouveau_mc_engine mc; 576 struct nouveau_timer_engine timer; 577 struct nouveau_fb_engine fb; 578 struct nouveau_fifo_engine fifo; 579 struct nouveau_display_engine display; 580 struct nouveau_gpio_engine gpio; 581 struct nouveau_pm_engine pm; 582 struct nouveau_vram_engine vram; 583}; 584 585struct nouveau_pll_vals { 586 union { 587 struct { 588#ifdef __BIG_ENDIAN 589 uint8_t N1, M1, N2, M2; 590#else 591 uint8_t M1, N1, M2, N2; 592#endif 593 }; 594 struct { 595 uint16_t NM1, NM2; 596 } __attribute__((packed)); 597 }; 598 int log2P; 599 600 int refclk; 601}; 602 603enum nv04_fp_display_regs { 604 FP_DISPLAY_END, 605 FP_TOTAL, 606 FP_CRTC, 607 FP_SYNC_START, 608 FP_SYNC_END, 609 FP_VALID_START, 610 FP_VALID_END 611}; 612 613struct nv04_crtc_reg { 614 unsigned char MiscOutReg; 615 uint8_t CRTC[0xa0]; 616 uint8_t CR58[0x10]; 617 uint8_t Sequencer[5]; 618 uint8_t Graphics[9]; 619 uint8_t Attribute[21]; 620 unsigned char DAC[768]; 621 622 /* PCRTC regs */ 623 uint32_t fb_start; 624 uint32_t crtc_cfg; 625 uint32_t cursor_cfg; 626 uint32_t gpio_ext; 627 uint32_t crtc_830; 628 uint32_t crtc_834; 629 uint32_t crtc_850; 630 uint32_t crtc_eng_ctrl; 631 632 /* PRAMDAC regs */ 633 uint32_t nv10_cursync; 634 struct nouveau_pll_vals pllvals; 635 uint32_t ramdac_gen_ctrl; 636 uint32_t ramdac_630; 637 uint32_t ramdac_634; 638 uint32_t tv_setup; 639 uint32_t tv_vtotal; 640 uint32_t tv_vskew; 641 uint32_t tv_vsync_delay; 642 uint32_t tv_htotal; 643 uint32_t tv_hskew; 644 uint32_t tv_hsync_delay; 645 uint32_t tv_hsync_delay2; 646 uint32_t fp_horiz_regs[7]; 647 uint32_t fp_vert_regs[7]; 648 uint32_t dither; 649 uint32_t fp_control; 650 uint32_t dither_regs[6]; 651 uint32_t fp_debug_0; 652 uint32_t fp_debug_1; 653 uint32_t fp_debug_2; 654 uint32_t fp_margin_color; 655 uint32_t ramdac_8c0; 656 uint32_t ramdac_a20; 657 uint32_t ramdac_a24; 658 uint32_t ramdac_a34; 659 uint32_t ctv_regs[38]; 660}; 661 662struct nv04_output_reg { 663 uint32_t output; 664 int head; 665}; 666 667struct nv04_mode_state { 668 struct nv04_crtc_reg crtc_reg[2]; 669 uint32_t pllsel; 670 uint32_t sel_clk; 671}; 672 673enum nouveau_card_type { 674 NV_04 = 0x00, 675 NV_10 = 0x10, 676 NV_20 = 0x20, 677 NV_30 = 0x30, 678 NV_40 = 0x40, 679 NV_50 = 0x50, 680 NV_C0 = 0xc0, 681 NV_D0 = 0xd0 682}; 683 684struct drm_nouveau_private { 685 struct drm_device *dev; 686 bool noaccel; 687 688 /* the card type, takes NV_* as values */ 689 enum nouveau_card_type card_type; 690 /* exact chipset, derived from NV_PMC_BOOT_0 */ 691 int chipset; 692 int flags; 693 u32 crystal; 694 695 void __iomem *mmio; 696 697 spinlock_t ramin_lock; 698 void __iomem *ramin; 699 u32 ramin_size; 700 u32 ramin_base; 701 bool ramin_available; 702 struct drm_mm ramin_heap; 703 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 704 struct list_head gpuobj_list; 705 struct list_head classes; 706 707 struct nouveau_bo *vga_ram; 708 709 /* interrupt handling */ 710 void (*irq_handler[32])(struct drm_device *); 711 bool msi_enabled; 712 713 struct list_head vbl_waiting; 714 715 struct { 716 struct drm_global_reference mem_global_ref; 717 struct ttm_bo_global_ref bo_global_ref; 718 struct ttm_bo_device bdev; 719 atomic_t validate_sequence; 720 } ttm; 721 722 struct { 723 spinlock_t lock; 724 struct drm_mm heap; 725 struct nouveau_bo *bo; 726 } fence; 727 728 struct { 729 spinlock_t lock; 730 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 731 } channels; 732 733 struct nouveau_engine engine; 734 struct nouveau_channel *channel; 735 736 /* For PFIFO and PGRAPH. */ 737 spinlock_t context_switch_lock; 738 739 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 740 spinlock_t vm_lock; 741 742 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 743 struct nouveau_ramht *ramht; 744 struct nouveau_gpuobj *ramfc; 745 struct nouveau_gpuobj *ramro; 746 747 uint32_t ramin_rsvd_vram; 748 749 struct { 750 enum { 751 NOUVEAU_GART_NONE = 0, 752 NOUVEAU_GART_AGP, /* AGP */ 753 NOUVEAU_GART_PDMA, /* paged dma object */ 754 NOUVEAU_GART_HW /* on-chip gart/vm */ 755 } type; 756 uint64_t aper_base; 757 uint64_t aper_size; 758 uint64_t aper_free; 759 760 struct ttm_backend_func *func; 761 762 struct { 763 struct page *page; 764 dma_addr_t addr; 765 } dummy; 766 767 struct nouveau_gpuobj *sg_ctxdma; 768 } gart_info; 769 770 /* nv10-nv40 tiling regions */ 771 struct { 772 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 773 spinlock_t lock; 774 } tile; 775 776 /* VRAM/fb configuration */ 777 uint64_t vram_size; 778 uint64_t vram_sys_base; 779 780 uint64_t fb_available_size; 781 uint64_t fb_mappable_pages; 782 uint64_t fb_aper_free; 783 int fb_mtrr; 784 785 /* BAR control (NV50-) */ 786 struct nouveau_vm *bar1_vm; 787 struct nouveau_vm *bar3_vm; 788 789 /* G8x/G9x virtual address space */ 790 struct nouveau_vm *chan_vm; 791 792 struct nvbios vbios; 793 794 struct nv04_mode_state mode_reg; 795 struct nv04_mode_state saved_reg; 796 uint32_t saved_vga_font[4][16384]; 797 uint32_t crtc_owner; 798 uint32_t dac_users[4]; 799 800 struct backlight_device *backlight; 801 802 struct { 803 struct dentry *channel_root; 804 } debugfs; 805 806 struct nouveau_fbdev *nfbdev; 807 struct apertures_struct *apertures; 808}; 809 810static inline struct drm_nouveau_private * 811nouveau_private(struct drm_device *dev) 812{ 813 return dev->dev_private; 814} 815 816static inline struct drm_nouveau_private * 817nouveau_bdev(struct ttm_bo_device *bd) 818{ 819 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 820} 821 822static inline int 823nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 824{ 825 struct nouveau_bo *prev; 826 827 if (!pnvbo) 828 return -EINVAL; 829 prev = *pnvbo; 830 831 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 832 if (prev) { 833 struct ttm_buffer_object *bo = &prev->bo; 834 835 ttm_bo_unref(&bo); 836 } 837 838 return 0; 839} 840 841/* nouveau_drv.c */ 842extern int nouveau_modeset; 843extern int nouveau_agpmode; 844extern int nouveau_duallink; 845extern int nouveau_uscript_lvds; 846extern int nouveau_uscript_tmds; 847extern int nouveau_vram_pushbuf; 848extern int nouveau_vram_notify; 849extern int nouveau_fbpercrtc; 850extern int nouveau_tv_disable; 851extern char *nouveau_tv_norm; 852extern int nouveau_reg_debug; 853extern char *nouveau_vbios; 854extern int nouveau_ignorelid; 855extern int nouveau_nofbaccel; 856extern int nouveau_noaccel; 857extern int nouveau_force_post; 858extern int nouveau_override_conntype; 859extern char *nouveau_perflvl; 860extern int nouveau_perflvl_wr; 861extern int nouveau_msi; 862extern int nouveau_ctxfw; 863 864extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 865extern int nouveau_pci_resume(struct pci_dev *pdev); 866 867/* nouveau_state.c */ 868extern int nouveau_open(struct drm_device *, struct drm_file *); 869extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 870extern void nouveau_postclose(struct drm_device *, struct drm_file *); 871extern int nouveau_load(struct drm_device *, unsigned long flags); 872extern int nouveau_firstopen(struct drm_device *); 873extern void nouveau_lastclose(struct drm_device *); 874extern int nouveau_unload(struct drm_device *); 875extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 876 struct drm_file *); 877extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 878 struct drm_file *); 879extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 880 uint32_t reg, uint32_t mask, uint32_t val); 881extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 882 uint32_t reg, uint32_t mask, uint32_t val); 883extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 884 bool (*cond)(void *), void *); 885extern bool nouveau_wait_for_idle(struct drm_device *); 886extern int nouveau_card_init(struct drm_device *); 887 888/* nouveau_mem.c */ 889extern int nouveau_mem_vram_init(struct drm_device *); 890extern void nouveau_mem_vram_fini(struct drm_device *); 891extern int nouveau_mem_gart_init(struct drm_device *); 892extern void nouveau_mem_gart_fini(struct drm_device *); 893extern int nouveau_mem_init_agp(struct drm_device *); 894extern int nouveau_mem_reset_agp(struct drm_device *); 895extern void nouveau_mem_close(struct drm_device *); 896extern int nouveau_mem_detect(struct drm_device *); 897extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 898extern struct nouveau_tile_reg *nv10_mem_set_tiling( 899 struct drm_device *dev, uint32_t addr, uint32_t size, 900 uint32_t pitch, uint32_t flags); 901extern void nv10_mem_put_tile_region(struct drm_device *dev, 902 struct nouveau_tile_reg *tile, 903 struct nouveau_fence *fence); 904extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 905extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 906 907/* nouveau_notifier.c */ 908extern int nouveau_notifier_init_channel(struct nouveau_channel *); 909extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 910extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 911 int cout, uint32_t start, uint32_t end, 912 uint32_t *offset); 913extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 914extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 915 struct drm_file *); 916extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 917 struct drm_file *); 918 919/* nouveau_channel.c */ 920extern struct drm_ioctl_desc nouveau_ioctls[]; 921extern int nouveau_max_ioctl; 922extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 923extern int nouveau_channel_alloc(struct drm_device *dev, 924 struct nouveau_channel **chan, 925 struct drm_file *file_priv, 926 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 927extern struct nouveau_channel * 928nouveau_channel_get_unlocked(struct nouveau_channel *); 929extern struct nouveau_channel * 930nouveau_channel_get(struct drm_file *, int id); 931extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 932extern void nouveau_channel_put(struct nouveau_channel **); 933extern void nouveau_channel_ref(struct nouveau_channel *chan, 934 struct nouveau_channel **pchan); 935extern void nouveau_channel_idle(struct nouveau_channel *chan); 936 937/* nouveau_object.c */ 938#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 939 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 940 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 941} while (0) 942 943#define NVOBJ_ENGINE_DEL(d, e) do { \ 944 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 945 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 946} while (0) 947 948#define NVOBJ_CLASS(d, c, e) do { \ 949 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 950 if (ret) \ 951 return ret; \ 952} while (0) 953 954#define NVOBJ_MTHD(d, c, m, e) do { \ 955 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 956 if (ret) \ 957 return ret; \ 958} while (0) 959 960extern int nouveau_gpuobj_early_init(struct drm_device *); 961extern int nouveau_gpuobj_init(struct drm_device *); 962extern void nouveau_gpuobj_takedown(struct drm_device *); 963extern int nouveau_gpuobj_suspend(struct drm_device *dev); 964extern void nouveau_gpuobj_resume(struct drm_device *dev); 965extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 966extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 967 int (*exec)(struct nouveau_channel *, 968 u32 class, u32 mthd, u32 data)); 969extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 970extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 971extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 972 uint32_t vram_h, uint32_t tt_h); 973extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 974extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 975 uint32_t size, int align, uint32_t flags, 976 struct nouveau_gpuobj **); 977extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 978 struct nouveau_gpuobj **); 979extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 980 u32 size, u32 flags, 981 struct nouveau_gpuobj **); 982extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 983 uint64_t offset, uint64_t size, int access, 984 int target, struct nouveau_gpuobj **); 985extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 986extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 987 u64 size, int target, int access, u32 type, 988 u32 comp, struct nouveau_gpuobj **pobj); 989extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 990 int class, u64 base, u64 size, int target, 991 int access, u32 type, u32 comp); 992extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 993 struct drm_file *); 994extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 995 struct drm_file *); 996 997/* nouveau_irq.c */ 998extern int nouveau_irq_init(struct drm_device *); 999extern void nouveau_irq_fini(struct drm_device *); 1000extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1001extern void nouveau_irq_register(struct drm_device *, int status_bit, 1002 void (*)(struct drm_device *)); 1003extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1004extern void nouveau_irq_preinstall(struct drm_device *); 1005extern int nouveau_irq_postinstall(struct drm_device *); 1006extern void nouveau_irq_uninstall(struct drm_device *); 1007 1008/* nouveau_sgdma.c */ 1009extern int nouveau_sgdma_init(struct drm_device *); 1010extern void nouveau_sgdma_takedown(struct drm_device *); 1011extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1012 uint32_t offset); 1013extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1014 unsigned long size, 1015 uint32_t page_flags, 1016 struct page *dummy_read_page); 1017 1018/* nouveau_debugfs.c */ 1019#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1020extern int nouveau_debugfs_init(struct drm_minor *); 1021extern void nouveau_debugfs_takedown(struct drm_minor *); 1022extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1023extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1024#else 1025static inline int 1026nouveau_debugfs_init(struct drm_minor *minor) 1027{ 1028 return 0; 1029} 1030 1031static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1032{ 1033} 1034 1035static inline int 1036nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1037{ 1038 return 0; 1039} 1040 1041static inline void 1042nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1043{ 1044} 1045#endif 1046 1047/* nouveau_dma.c */ 1048extern void nouveau_dma_pre_init(struct nouveau_channel *); 1049extern int nouveau_dma_init(struct nouveau_channel *); 1050extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1051 1052/* nouveau_acpi.c */ 1053#define ROM_BIOS_PAGE 4096 1054#if defined(CONFIG_ACPI) 1055void nouveau_register_dsm_handler(void); 1056void nouveau_unregister_dsm_handler(void); 1057int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1058bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1059int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1060#else 1061static inline void nouveau_register_dsm_handler(void) {} 1062static inline void nouveau_unregister_dsm_handler(void) {} 1063static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1064static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1065static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1066#endif 1067 1068/* nouveau_backlight.c */ 1069#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1070extern int nouveau_backlight_init(struct drm_device *); 1071extern void nouveau_backlight_exit(struct drm_device *); 1072#else 1073static inline int nouveau_backlight_init(struct drm_device *dev) 1074{ 1075 return 0; 1076} 1077 1078static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1079#endif 1080 1081/* nouveau_bios.c */ 1082extern int nouveau_bios_init(struct drm_device *); 1083extern void nouveau_bios_takedown(struct drm_device *dev); 1084extern int nouveau_run_vbios_init(struct drm_device *); 1085extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1086 struct dcb_entry *, int crtc); 1087extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1088extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1089 enum dcb_gpio_tag); 1090extern struct dcb_connector_table_entry * 1091nouveau_bios_connector_entry(struct drm_device *, int index); 1092extern u32 get_pll_register(struct drm_device *, enum pll_types); 1093extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1094 struct pll_lims *); 1095extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1096 struct dcb_entry *, int crtc); 1097extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1098extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1099extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1100 bool *dl, bool *if_is_24bit); 1101extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1102 int head, int pxclk); 1103extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1104 enum LVDS_script, int pxclk); 1105bool bios_encoder_match(struct dcb_entry *, u32 hash); 1106 1107/* nouveau_ttm.c */ 1108int nouveau_ttm_global_init(struct drm_nouveau_private *); 1109void nouveau_ttm_global_release(struct drm_nouveau_private *); 1110int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1111 1112/* nouveau_dp.c */ 1113int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1114 uint8_t *data, int data_nr); 1115bool nouveau_dp_detect(struct drm_encoder *); 1116bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1117void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1118u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1119 1120/* nv04_fb.c */ 1121extern int nv04_fb_init(struct drm_device *); 1122extern void nv04_fb_takedown(struct drm_device *); 1123 1124/* nv10_fb.c */ 1125extern int nv10_fb_init(struct drm_device *); 1126extern void nv10_fb_takedown(struct drm_device *); 1127extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1128 uint32_t addr, uint32_t size, 1129 uint32_t pitch, uint32_t flags); 1130extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1131extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1132 1133/* nv30_fb.c */ 1134extern int nv30_fb_init(struct drm_device *); 1135extern void nv30_fb_takedown(struct drm_device *); 1136extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1137 uint32_t addr, uint32_t size, 1138 uint32_t pitch, uint32_t flags); 1139extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1140 1141/* nv40_fb.c */ 1142extern int nv40_fb_init(struct drm_device *); 1143extern void nv40_fb_takedown(struct drm_device *); 1144extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1145 1146/* nv50_fb.c */ 1147extern int nv50_fb_init(struct drm_device *); 1148extern void nv50_fb_takedown(struct drm_device *); 1149extern void nv50_fb_vm_trap(struct drm_device *, int display); 1150 1151/* nvc0_fb.c */ 1152extern int nvc0_fb_init(struct drm_device *); 1153extern void nvc0_fb_takedown(struct drm_device *); 1154 1155/* nv04_fifo.c */ 1156extern int nv04_fifo_init(struct drm_device *); 1157extern void nv04_fifo_fini(struct drm_device *); 1158extern void nv04_fifo_disable(struct drm_device *); 1159extern void nv04_fifo_enable(struct drm_device *); 1160extern bool nv04_fifo_reassign(struct drm_device *, bool); 1161extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1162extern int nv04_fifo_channel_id(struct drm_device *); 1163extern int nv04_fifo_create_context(struct nouveau_channel *); 1164extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1165extern int nv04_fifo_load_context(struct nouveau_channel *); 1166extern int nv04_fifo_unload_context(struct drm_device *); 1167extern void nv04_fifo_isr(struct drm_device *); 1168 1169/* nv10_fifo.c */ 1170extern int nv10_fifo_init(struct drm_device *); 1171extern int nv10_fifo_channel_id(struct drm_device *); 1172extern int nv10_fifo_create_context(struct nouveau_channel *); 1173extern int nv10_fifo_load_context(struct nouveau_channel *); 1174extern int nv10_fifo_unload_context(struct drm_device *); 1175 1176/* nv40_fifo.c */ 1177extern int nv40_fifo_init(struct drm_device *); 1178extern int nv40_fifo_create_context(struct nouveau_channel *); 1179extern int nv40_fifo_load_context(struct nouveau_channel *); 1180extern int nv40_fifo_unload_context(struct drm_device *); 1181 1182/* nv50_fifo.c */ 1183extern int nv50_fifo_init(struct drm_device *); 1184extern void nv50_fifo_takedown(struct drm_device *); 1185extern int nv50_fifo_channel_id(struct drm_device *); 1186extern int nv50_fifo_create_context(struct nouveau_channel *); 1187extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1188extern int nv50_fifo_load_context(struct nouveau_channel *); 1189extern int nv50_fifo_unload_context(struct drm_device *); 1190extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1191 1192/* nvc0_fifo.c */ 1193extern int nvc0_fifo_init(struct drm_device *); 1194extern void nvc0_fifo_takedown(struct drm_device *); 1195extern void nvc0_fifo_disable(struct drm_device *); 1196extern void nvc0_fifo_enable(struct drm_device *); 1197extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1198extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1199extern int nvc0_fifo_channel_id(struct drm_device *); 1200extern int nvc0_fifo_create_context(struct nouveau_channel *); 1201extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1202extern int nvc0_fifo_load_context(struct nouveau_channel *); 1203extern int nvc0_fifo_unload_context(struct drm_device *); 1204 1205/* nv04_graph.c */ 1206extern int nv04_graph_create(struct drm_device *); 1207extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1208extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1209 u32 class, u32 mthd, u32 data); 1210extern struct nouveau_bitfield nv04_graph_nsource[]; 1211 1212/* nv10_graph.c */ 1213extern int nv10_graph_create(struct drm_device *); 1214extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1215extern struct nouveau_bitfield nv10_graph_intr[]; 1216extern struct nouveau_bitfield nv10_graph_nstatus[]; 1217 1218/* nv20_graph.c */ 1219extern int nv20_graph_create(struct drm_device *); 1220 1221/* nv40_graph.c */ 1222extern int nv40_graph_create(struct drm_device *); 1223extern void nv40_grctx_init(struct nouveau_grctx *); 1224 1225/* nv50_graph.c */ 1226extern int nv50_graph_create(struct drm_device *); 1227extern int nv50_grctx_init(struct nouveau_grctx *); 1228extern struct nouveau_enum nv50_data_error_names[]; 1229extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1230 1231/* nvc0_graph.c */ 1232extern int nvc0_graph_create(struct drm_device *); 1233extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1234 1235/* nv84_crypt.c */ 1236extern int nv84_crypt_create(struct drm_device *); 1237 1238/* nv98_crypt.c */ 1239extern int nv98_crypt_create(struct drm_device *dev); 1240 1241/* nva3_copy.c */ 1242extern int nva3_copy_create(struct drm_device *dev); 1243 1244/* nvc0_copy.c */ 1245extern int nvc0_copy_create(struct drm_device *dev, int engine); 1246 1247/* nv31_mpeg.c */ 1248extern int nv31_mpeg_create(struct drm_device *dev); 1249 1250/* nv50_mpeg.c */ 1251extern int nv50_mpeg_create(struct drm_device *dev); 1252 1253/* nv84_bsp.c */ 1254/* nv98_bsp.c */ 1255extern int nv84_bsp_create(struct drm_device *dev); 1256 1257/* nv84_vp.c */ 1258/* nv98_vp.c */ 1259extern int nv84_vp_create(struct drm_device *dev); 1260 1261/* nv98_ppp.c */ 1262extern int nv98_ppp_create(struct drm_device *dev); 1263 1264/* nv04_instmem.c */ 1265extern int nv04_instmem_init(struct drm_device *); 1266extern void nv04_instmem_takedown(struct drm_device *); 1267extern int nv04_instmem_suspend(struct drm_device *); 1268extern void nv04_instmem_resume(struct drm_device *); 1269extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1270 u32 size, u32 align); 1271extern void nv04_instmem_put(struct nouveau_gpuobj *); 1272extern int nv04_instmem_map(struct nouveau_gpuobj *); 1273extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1274extern void nv04_instmem_flush(struct drm_device *); 1275 1276/* nv50_instmem.c */ 1277extern int nv50_instmem_init(struct drm_device *); 1278extern void nv50_instmem_takedown(struct drm_device *); 1279extern int nv50_instmem_suspend(struct drm_device *); 1280extern void nv50_instmem_resume(struct drm_device *); 1281extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1282 u32 size, u32 align); 1283extern void nv50_instmem_put(struct nouveau_gpuobj *); 1284extern int nv50_instmem_map(struct nouveau_gpuobj *); 1285extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1286extern void nv50_instmem_flush(struct drm_device *); 1287extern void nv84_instmem_flush(struct drm_device *); 1288 1289/* nvc0_instmem.c */ 1290extern int nvc0_instmem_init(struct drm_device *); 1291extern void nvc0_instmem_takedown(struct drm_device *); 1292extern int nvc0_instmem_suspend(struct drm_device *); 1293extern void nvc0_instmem_resume(struct drm_device *); 1294 1295/* nv04_mc.c */ 1296extern int nv04_mc_init(struct drm_device *); 1297extern void nv04_mc_takedown(struct drm_device *); 1298 1299/* nv40_mc.c */ 1300extern int nv40_mc_init(struct drm_device *); 1301extern void nv40_mc_takedown(struct drm_device *); 1302 1303/* nv50_mc.c */ 1304extern int nv50_mc_init(struct drm_device *); 1305extern void nv50_mc_takedown(struct drm_device *); 1306 1307/* nv04_timer.c */ 1308extern int nv04_timer_init(struct drm_device *); 1309extern uint64_t nv04_timer_read(struct drm_device *); 1310extern void nv04_timer_takedown(struct drm_device *); 1311 1312extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1313 unsigned long arg); 1314 1315/* nv04_dac.c */ 1316extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1317extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1318extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1319extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1320extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1321 1322/* nv04_dfp.c */ 1323extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1324extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1325extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1326 int head, bool dl); 1327extern void nv04_dfp_disable(struct drm_device *dev, int head); 1328extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1329 1330/* nv04_tv.c */ 1331extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1332extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1333 1334/* nv17_tv.c */ 1335extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1336 1337/* nv04_display.c */ 1338extern int nv04_display_early_init(struct drm_device *); 1339extern void nv04_display_late_takedown(struct drm_device *); 1340extern int nv04_display_create(struct drm_device *); 1341extern int nv04_display_init(struct drm_device *); 1342extern void nv04_display_destroy(struct drm_device *); 1343 1344/* nvd0_display.c */ 1345extern int nvd0_display_create(struct drm_device *); 1346extern int nvd0_display_init(struct drm_device *); 1347extern void nvd0_display_destroy(struct drm_device *); 1348 1349/* nv04_crtc.c */ 1350extern int nv04_crtc_create(struct drm_device *, int index); 1351 1352/* nouveau_bo.c */ 1353extern struct ttm_bo_driver nouveau_bo_driver; 1354extern int nouveau_bo_new(struct drm_device *, int size, int align, 1355 uint32_t flags, uint32_t tile_mode, 1356 uint32_t tile_flags, struct nouveau_bo **); 1357extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1358extern int nouveau_bo_unpin(struct nouveau_bo *); 1359extern int nouveau_bo_map(struct nouveau_bo *); 1360extern void nouveau_bo_unmap(struct nouveau_bo *); 1361extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1362 uint32_t busy); 1363extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1364extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1365extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1366extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1367extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1368extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1369 bool no_wait_reserve, bool no_wait_gpu); 1370 1371extern struct nouveau_vma * 1372nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1373extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1374 struct nouveau_vma *); 1375extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1376 1377/* nouveau_fence.c */ 1378struct nouveau_fence; 1379extern int nouveau_fence_init(struct drm_device *); 1380extern void nouveau_fence_fini(struct drm_device *); 1381extern int nouveau_fence_channel_init(struct nouveau_channel *); 1382extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1383extern void nouveau_fence_update(struct nouveau_channel *); 1384extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1385 bool emit); 1386extern int nouveau_fence_emit(struct nouveau_fence *); 1387extern void nouveau_fence_work(struct nouveau_fence *fence, 1388 void (*work)(void *priv, bool signalled), 1389 void *priv); 1390struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1391 1392extern bool __nouveau_fence_signalled(void *obj, void *arg); 1393extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1394extern int __nouveau_fence_flush(void *obj, void *arg); 1395extern void __nouveau_fence_unref(void **obj); 1396extern void *__nouveau_fence_ref(void *obj); 1397 1398static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1399{ 1400 return __nouveau_fence_signalled(obj, NULL); 1401} 1402static inline int 1403nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1404{ 1405 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1406} 1407extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1408static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1409{ 1410 return __nouveau_fence_flush(obj, NULL); 1411} 1412static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1413{ 1414 __nouveau_fence_unref((void **)obj); 1415} 1416static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1417{ 1418 return __nouveau_fence_ref(obj); 1419} 1420 1421/* nouveau_gem.c */ 1422extern int nouveau_gem_new(struct drm_device *, int size, int align, 1423 uint32_t domain, uint32_t tile_mode, 1424 uint32_t tile_flags, struct nouveau_bo **); 1425extern int nouveau_gem_object_new(struct drm_gem_object *); 1426extern void nouveau_gem_object_del(struct drm_gem_object *); 1427extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1428extern void nouveau_gem_object_close(struct drm_gem_object *, 1429 struct drm_file *); 1430extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1431 struct drm_file *); 1432extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1433 struct drm_file *); 1434extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1435 struct drm_file *); 1436extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1437 struct drm_file *); 1438extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1439 struct drm_file *); 1440 1441/* nouveau_display.c */ 1442int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1443void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1444int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1445 struct drm_pending_vblank_event *event); 1446int nouveau_finish_page_flip(struct nouveau_channel *, 1447 struct nouveau_page_flip_state *); 1448int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1449 struct drm_mode_create_dumb *args); 1450int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1451 uint32_t handle, uint64_t *offset); 1452int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1453 uint32_t handle); 1454 1455/* nv10_gpio.c */ 1456int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1457int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1458 1459/* nv50_gpio.c */ 1460int nv50_gpio_init(struct drm_device *dev); 1461void nv50_gpio_fini(struct drm_device *dev); 1462int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1463int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1464int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1465int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1466int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1467 void (*)(void *, int), void *); 1468void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1469 void (*)(void *, int), void *); 1470bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1471 1472/* nv50_calc. */ 1473int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1474 int *N1, int *M1, int *N2, int *M2, int *P); 1475int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1476 int clk, int *N, int *fN, int *M, int *P); 1477 1478#ifndef ioread32_native 1479#ifdef __BIG_ENDIAN 1480#define ioread16_native ioread16be 1481#define iowrite16_native iowrite16be 1482#define ioread32_native ioread32be 1483#define iowrite32_native iowrite32be 1484#else /* def __BIG_ENDIAN */ 1485#define ioread16_native ioread16 1486#define iowrite16_native iowrite16 1487#define ioread32_native ioread32 1488#define iowrite32_native iowrite32 1489#endif /* def __BIG_ENDIAN else */ 1490#endif /* !ioread32_native */ 1491 1492/* channel control reg access */ 1493static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1494{ 1495 return ioread32_native(chan->user + reg); 1496} 1497 1498static inline void nvchan_wr32(struct nouveau_channel *chan, 1499 unsigned reg, u32 val) 1500{ 1501 iowrite32_native(val, chan->user + reg); 1502} 1503 1504/* register access */ 1505static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1506{ 1507 struct drm_nouveau_private *dev_priv = dev->dev_private; 1508 return ioread32_native(dev_priv->mmio + reg); 1509} 1510 1511static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1512{ 1513 struct drm_nouveau_private *dev_priv = dev->dev_private; 1514 iowrite32_native(val, dev_priv->mmio + reg); 1515} 1516 1517static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1518{ 1519 u32 tmp = nv_rd32(dev, reg); 1520 nv_wr32(dev, reg, (tmp & ~mask) | val); 1521 return tmp; 1522} 1523 1524static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1525{ 1526 struct drm_nouveau_private *dev_priv = dev->dev_private; 1527 return ioread8(dev_priv->mmio + reg); 1528} 1529 1530static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1531{ 1532 struct drm_nouveau_private *dev_priv = dev->dev_private; 1533 iowrite8(val, dev_priv->mmio + reg); 1534} 1535 1536#define nv_wait(dev, reg, mask, val) \ 1537 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1538#define nv_wait_ne(dev, reg, mask, val) \ 1539 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1540#define nv_wait_cb(dev, func, data) \ 1541 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1542 1543/* PRAMIN access */ 1544static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 return ioread32_native(dev_priv->ramin + offset); 1548} 1549 1550static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1551{ 1552 struct drm_nouveau_private *dev_priv = dev->dev_private; 1553 iowrite32_native(val, dev_priv->ramin + offset); 1554} 1555 1556/* object access */ 1557extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1558extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1559 1560/* 1561 * Logging 1562 * Argument d is (struct drm_device *). 1563 */ 1564#define NV_PRINTK(level, d, fmt, arg...) \ 1565 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1566 pci_name(d->pdev), ##arg) 1567#ifndef NV_DEBUG_NOTRACE 1568#define NV_DEBUG(d, fmt, arg...) do { \ 1569 if (drm_debug & DRM_UT_DRIVER) { \ 1570 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1571 __LINE__, ##arg); \ 1572 } \ 1573} while (0) 1574#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1575 if (drm_debug & DRM_UT_KMS) { \ 1576 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1577 __LINE__, ##arg); \ 1578 } \ 1579} while (0) 1580#else 1581#define NV_DEBUG(d, fmt, arg...) do { \ 1582 if (drm_debug & DRM_UT_DRIVER) \ 1583 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1584} while (0) 1585#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1586 if (drm_debug & DRM_UT_KMS) \ 1587 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1588} while (0) 1589#endif 1590#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1591#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1592#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1593#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1594#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1595 1596/* nouveau_reg_debug bitmask */ 1597enum { 1598 NOUVEAU_REG_DEBUG_MC = 0x1, 1599 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1600 NOUVEAU_REG_DEBUG_FB = 0x4, 1601 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1602 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1603 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1604 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1605 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1606 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1607 NOUVEAU_REG_DEBUG_EVO = 0x200, 1608 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1609}; 1610 1611#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1612 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1613 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1614} while (0) 1615 1616static inline bool 1617nv_two_heads(struct drm_device *dev) 1618{ 1619 struct drm_nouveau_private *dev_priv = dev->dev_private; 1620 const int impl = dev->pci_device & 0x0ff0; 1621 1622 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1623 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1624 return true; 1625 1626 return false; 1627} 1628 1629static inline bool 1630nv_gf4_disp_arch(struct drm_device *dev) 1631{ 1632 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1633} 1634 1635static inline bool 1636nv_two_reg_pll(struct drm_device *dev) 1637{ 1638 struct drm_nouveau_private *dev_priv = dev->dev_private; 1639 const int impl = dev->pci_device & 0x0ff0; 1640 1641 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1642 return true; 1643 return false; 1644} 1645 1646static inline bool 1647nv_match_device(struct drm_device *dev, unsigned device, 1648 unsigned sub_vendor, unsigned sub_device) 1649{ 1650 return dev->pdev->device == device && 1651 dev->pdev->subsystem_vendor == sub_vendor && 1652 dev->pdev->subsystem_device == sub_device; 1653} 1654 1655static inline void * 1656nv_engine(struct drm_device *dev, int engine) 1657{ 1658 struct drm_nouveau_private *dev_priv = dev->dev_private; 1659 return (void *)dev_priv->eng[engine]; 1660} 1661 1662/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1663 * helpful to determine a number of other hardware features 1664 */ 1665static inline int 1666nv44_graph_class(struct drm_device *dev) 1667{ 1668 struct drm_nouveau_private *dev_priv = dev->dev_private; 1669 1670 if ((dev_priv->chipset & 0xf0) == 0x60) 1671 return 1; 1672 1673 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1674} 1675 1676/* memory type/access flags, do not match hardware values */ 1677#define NV_MEM_ACCESS_RO 1 1678#define NV_MEM_ACCESS_WO 2 1679#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1680#define NV_MEM_ACCESS_SYS 4 1681#define NV_MEM_ACCESS_VM 8 1682 1683#define NV_MEM_TARGET_VRAM 0 1684#define NV_MEM_TARGET_PCI 1 1685#define NV_MEM_TARGET_PCI_NOSNOOP 2 1686#define NV_MEM_TARGET_VM 3 1687#define NV_MEM_TARGET_GART 4 1688 1689#define NV_MEM_TYPE_VM 0x7f 1690#define NV_MEM_COMP_VM 0x03 1691 1692/* NV_SW object class */ 1693#define NV_SW 0x0000506e 1694#define NV_SW_DMA_SEMAPHORE 0x00000060 1695#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1696#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1697#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1698#define NV_SW_YIELD 0x00000080 1699#define NV_SW_DMA_VBLSEM 0x0000018c 1700#define NV_SW_VBLSEM_OFFSET 0x00000400 1701#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1702#define NV_SW_VBLSEM_RELEASE 0x00000408 1703#define NV_SW_PAGE_FLIP 0x00000500 1704 1705#endif /* __NOUVEAU_DRV_H__ */ 1706