nouveau_drv.h revision 3b5565ddfd8fe71f6470a5d240a6bb50ba90d4ff
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 vid_mask; 424 425 struct nouveau_pm_voltage_level *level; 426 int nr_level; 427}; 428 429struct nouveau_pm_memtiming { 430 int id; 431 u32 reg_100220; 432 u32 reg_100224; 433 u32 reg_100228; 434 u32 reg_10022c; 435 u32 reg_100230; 436 u32 reg_100234; 437 u32 reg_100238; 438 u32 reg_10023c; 439 u32 reg_100240; 440}; 441 442#define NOUVEAU_PM_MAX_LEVEL 8 443struct nouveau_pm_level { 444 struct device_attribute dev_attr; 445 char name[32]; 446 int id; 447 448 u32 core; 449 u32 memory; 450 u32 shader; 451 u32 unk05; 452 u32 unk0a; 453 454 u32 volt_min; /* microvolts */ 455 u32 volt_max; 456 u8 fanspeed; 457 458 u16 memscript; 459 struct nouveau_pm_memtiming *timing; 460}; 461 462struct nouveau_pm_temp_sensor_constants { 463 u16 offset_constant; 464 s16 offset_mult; 465 s16 offset_div; 466 s16 slope_mult; 467 s16 slope_div; 468}; 469 470struct nouveau_pm_threshold_temp { 471 s16 critical; 472 s16 down_clock; 473 s16 fan_boost; 474}; 475 476struct nouveau_pm_memtimings { 477 bool supported; 478 struct nouveau_pm_memtiming *timing; 479 int nr_timing; 480}; 481 482struct nouveau_pm_engine { 483 struct nouveau_pm_voltage voltage; 484 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 485 int nr_perflvl; 486 struct nouveau_pm_memtimings memtimings; 487 struct nouveau_pm_temp_sensor_constants sensor_constants; 488 struct nouveau_pm_threshold_temp threshold_temp; 489 490 struct nouveau_pm_level boot; 491 struct nouveau_pm_level *cur; 492 493 struct device *hwmon; 494 struct notifier_block acpi_nb; 495 496 int (*clock_get)(struct drm_device *, u32 id); 497 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 498 u32 id, int khz); 499 void (*clock_set)(struct drm_device *, void *); 500 int (*voltage_get)(struct drm_device *); 501 int (*voltage_set)(struct drm_device *, int voltage); 502 int (*fanspeed_get)(struct drm_device *); 503 int (*fanspeed_set)(struct drm_device *, int fanspeed); 504 int (*temp_get)(struct drm_device *); 505}; 506 507struct nouveau_vram_engine { 508 struct nouveau_mm *mm; 509 510 int (*init)(struct drm_device *); 511 void (*takedown)(struct drm_device *dev); 512 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 513 u32 type, struct nouveau_mem **); 514 void (*put)(struct drm_device *, struct nouveau_mem **); 515 516 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 517}; 518 519struct nouveau_engine { 520 struct nouveau_instmem_engine instmem; 521 struct nouveau_mc_engine mc; 522 struct nouveau_timer_engine timer; 523 struct nouveau_fb_engine fb; 524 struct nouveau_fifo_engine fifo; 525 struct nouveau_display_engine display; 526 struct nouveau_gpio_engine gpio; 527 struct nouveau_pm_engine pm; 528 struct nouveau_vram_engine vram; 529}; 530 531struct nouveau_pll_vals { 532 union { 533 struct { 534#ifdef __BIG_ENDIAN 535 uint8_t N1, M1, N2, M2; 536#else 537 uint8_t M1, N1, M2, N2; 538#endif 539 }; 540 struct { 541 uint16_t NM1, NM2; 542 } __attribute__((packed)); 543 }; 544 int log2P; 545 546 int refclk; 547}; 548 549enum nv04_fp_display_regs { 550 FP_DISPLAY_END, 551 FP_TOTAL, 552 FP_CRTC, 553 FP_SYNC_START, 554 FP_SYNC_END, 555 FP_VALID_START, 556 FP_VALID_END 557}; 558 559struct nv04_crtc_reg { 560 unsigned char MiscOutReg; 561 uint8_t CRTC[0xa0]; 562 uint8_t CR58[0x10]; 563 uint8_t Sequencer[5]; 564 uint8_t Graphics[9]; 565 uint8_t Attribute[21]; 566 unsigned char DAC[768]; 567 568 /* PCRTC regs */ 569 uint32_t fb_start; 570 uint32_t crtc_cfg; 571 uint32_t cursor_cfg; 572 uint32_t gpio_ext; 573 uint32_t crtc_830; 574 uint32_t crtc_834; 575 uint32_t crtc_850; 576 uint32_t crtc_eng_ctrl; 577 578 /* PRAMDAC regs */ 579 uint32_t nv10_cursync; 580 struct nouveau_pll_vals pllvals; 581 uint32_t ramdac_gen_ctrl; 582 uint32_t ramdac_630; 583 uint32_t ramdac_634; 584 uint32_t tv_setup; 585 uint32_t tv_vtotal; 586 uint32_t tv_vskew; 587 uint32_t tv_vsync_delay; 588 uint32_t tv_htotal; 589 uint32_t tv_hskew; 590 uint32_t tv_hsync_delay; 591 uint32_t tv_hsync_delay2; 592 uint32_t fp_horiz_regs[7]; 593 uint32_t fp_vert_regs[7]; 594 uint32_t dither; 595 uint32_t fp_control; 596 uint32_t dither_regs[6]; 597 uint32_t fp_debug_0; 598 uint32_t fp_debug_1; 599 uint32_t fp_debug_2; 600 uint32_t fp_margin_color; 601 uint32_t ramdac_8c0; 602 uint32_t ramdac_a20; 603 uint32_t ramdac_a24; 604 uint32_t ramdac_a34; 605 uint32_t ctv_regs[38]; 606}; 607 608struct nv04_output_reg { 609 uint32_t output; 610 int head; 611}; 612 613struct nv04_mode_state { 614 struct nv04_crtc_reg crtc_reg[2]; 615 uint32_t pllsel; 616 uint32_t sel_clk; 617}; 618 619enum nouveau_card_type { 620 NV_04 = 0x00, 621 NV_10 = 0x10, 622 NV_20 = 0x20, 623 NV_30 = 0x30, 624 NV_40 = 0x40, 625 NV_50 = 0x50, 626 NV_C0 = 0xc0, 627}; 628 629struct drm_nouveau_private { 630 struct drm_device *dev; 631 bool noaccel; 632 633 /* the card type, takes NV_* as values */ 634 enum nouveau_card_type card_type; 635 /* exact chipset, derived from NV_PMC_BOOT_0 */ 636 int chipset; 637 int stepping; 638 int flags; 639 640 void __iomem *mmio; 641 642 spinlock_t ramin_lock; 643 void __iomem *ramin; 644 u32 ramin_size; 645 u32 ramin_base; 646 bool ramin_available; 647 struct drm_mm ramin_heap; 648 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 649 struct list_head gpuobj_list; 650 struct list_head classes; 651 652 struct nouveau_bo *vga_ram; 653 654 /* interrupt handling */ 655 void (*irq_handler[32])(struct drm_device *); 656 bool msi_enabled; 657 658 struct list_head vbl_waiting; 659 660 struct { 661 struct drm_global_reference mem_global_ref; 662 struct ttm_bo_global_ref bo_global_ref; 663 struct ttm_bo_device bdev; 664 atomic_t validate_sequence; 665 } ttm; 666 667 struct { 668 spinlock_t lock; 669 struct drm_mm heap; 670 struct nouveau_bo *bo; 671 } fence; 672 673 struct { 674 spinlock_t lock; 675 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 676 } channels; 677 678 struct nouveau_engine engine; 679 struct nouveau_channel *channel; 680 681 /* For PFIFO and PGRAPH. */ 682 spinlock_t context_switch_lock; 683 684 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 685 spinlock_t vm_lock; 686 687 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 688 struct nouveau_ramht *ramht; 689 struct nouveau_gpuobj *ramfc; 690 struct nouveau_gpuobj *ramro; 691 692 uint32_t ramin_rsvd_vram; 693 694 struct { 695 enum { 696 NOUVEAU_GART_NONE = 0, 697 NOUVEAU_GART_AGP, /* AGP */ 698 NOUVEAU_GART_PDMA, /* paged dma object */ 699 NOUVEAU_GART_HW /* on-chip gart/vm */ 700 } type; 701 uint64_t aper_base; 702 uint64_t aper_size; 703 uint64_t aper_free; 704 705 struct ttm_backend_func *func; 706 707 struct { 708 struct page *page; 709 dma_addr_t addr; 710 } dummy; 711 712 struct nouveau_gpuobj *sg_ctxdma; 713 } gart_info; 714 715 /* nv10-nv40 tiling regions */ 716 struct { 717 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 718 spinlock_t lock; 719 } tile; 720 721 /* VRAM/fb configuration */ 722 uint64_t vram_size; 723 uint64_t vram_sys_base; 724 725 uint64_t fb_phys; 726 uint64_t fb_available_size; 727 uint64_t fb_mappable_pages; 728 uint64_t fb_aper_free; 729 int fb_mtrr; 730 731 /* BAR control (NV50-) */ 732 struct nouveau_vm *bar1_vm; 733 struct nouveau_vm *bar3_vm; 734 735 /* G8x/G9x virtual address space */ 736 struct nouveau_vm *chan_vm; 737 738 struct nvbios vbios; 739 740 struct nv04_mode_state mode_reg; 741 struct nv04_mode_state saved_reg; 742 uint32_t saved_vga_font[4][16384]; 743 uint32_t crtc_owner; 744 uint32_t dac_users[4]; 745 746 struct backlight_device *backlight; 747 748 struct { 749 struct dentry *channel_root; 750 } debugfs; 751 752 struct nouveau_fbdev *nfbdev; 753 struct apertures_struct *apertures; 754}; 755 756static inline struct drm_nouveau_private * 757nouveau_private(struct drm_device *dev) 758{ 759 return dev->dev_private; 760} 761 762static inline struct drm_nouveau_private * 763nouveau_bdev(struct ttm_bo_device *bd) 764{ 765 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 766} 767 768static inline int 769nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 770{ 771 struct nouveau_bo *prev; 772 773 if (!pnvbo) 774 return -EINVAL; 775 prev = *pnvbo; 776 777 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 778 if (prev) { 779 struct ttm_buffer_object *bo = &prev->bo; 780 781 ttm_bo_unref(&bo); 782 } 783 784 return 0; 785} 786 787/* nouveau_drv.c */ 788extern int nouveau_agpmode; 789extern int nouveau_duallink; 790extern int nouveau_uscript_lvds; 791extern int nouveau_uscript_tmds; 792extern int nouveau_vram_pushbuf; 793extern int nouveau_vram_notify; 794extern int nouveau_fbpercrtc; 795extern int nouveau_tv_disable; 796extern char *nouveau_tv_norm; 797extern int nouveau_reg_debug; 798extern char *nouveau_vbios; 799extern int nouveau_ignorelid; 800extern int nouveau_nofbaccel; 801extern int nouveau_noaccel; 802extern int nouveau_force_post; 803extern int nouveau_override_conntype; 804extern char *nouveau_perflvl; 805extern int nouveau_perflvl_wr; 806extern int nouveau_msi; 807extern int nouveau_ctxfw; 808 809extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 810extern int nouveau_pci_resume(struct pci_dev *pdev); 811 812/* nouveau_state.c */ 813extern int nouveau_open(struct drm_device *, struct drm_file *); 814extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 815extern void nouveau_postclose(struct drm_device *, struct drm_file *); 816extern int nouveau_load(struct drm_device *, unsigned long flags); 817extern int nouveau_firstopen(struct drm_device *); 818extern void nouveau_lastclose(struct drm_device *); 819extern int nouveau_unload(struct drm_device *); 820extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 821 struct drm_file *); 822extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 823 struct drm_file *); 824extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 825 uint32_t reg, uint32_t mask, uint32_t val); 826extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 827 uint32_t reg, uint32_t mask, uint32_t val); 828extern bool nouveau_wait_for_idle(struct drm_device *); 829extern int nouveau_card_init(struct drm_device *); 830 831/* nouveau_mem.c */ 832extern int nouveau_mem_vram_init(struct drm_device *); 833extern void nouveau_mem_vram_fini(struct drm_device *); 834extern int nouveau_mem_gart_init(struct drm_device *); 835extern void nouveau_mem_gart_fini(struct drm_device *); 836extern int nouveau_mem_init_agp(struct drm_device *); 837extern int nouveau_mem_reset_agp(struct drm_device *); 838extern void nouveau_mem_close(struct drm_device *); 839extern int nouveau_mem_detect(struct drm_device *); 840extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 841extern struct nouveau_tile_reg *nv10_mem_set_tiling( 842 struct drm_device *dev, uint32_t addr, uint32_t size, 843 uint32_t pitch, uint32_t flags); 844extern void nv10_mem_put_tile_region(struct drm_device *dev, 845 struct nouveau_tile_reg *tile, 846 struct nouveau_fence *fence); 847extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 848extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 849 850/* nouveau_notifier.c */ 851extern int nouveau_notifier_init_channel(struct nouveau_channel *); 852extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 853extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 854 int cout, uint32_t start, uint32_t end, 855 uint32_t *offset); 856extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 857extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 858 struct drm_file *); 859extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 860 struct drm_file *); 861 862/* nouveau_channel.c */ 863extern struct drm_ioctl_desc nouveau_ioctls[]; 864extern int nouveau_max_ioctl; 865extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 866extern int nouveau_channel_alloc(struct drm_device *dev, 867 struct nouveau_channel **chan, 868 struct drm_file *file_priv, 869 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 870extern struct nouveau_channel * 871nouveau_channel_get_unlocked(struct nouveau_channel *); 872extern struct nouveau_channel * 873nouveau_channel_get(struct drm_file *, int id); 874extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 875extern void nouveau_channel_put(struct nouveau_channel **); 876extern void nouveau_channel_ref(struct nouveau_channel *chan, 877 struct nouveau_channel **pchan); 878extern void nouveau_channel_idle(struct nouveau_channel *chan); 879 880/* nouveau_object.c */ 881#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 882 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 883 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 884} while (0) 885 886#define NVOBJ_ENGINE_DEL(d, e) do { \ 887 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 888 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 889} while (0) 890 891#define NVOBJ_CLASS(d, c, e) do { \ 892 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 893 if (ret) \ 894 return ret; \ 895} while (0) 896 897#define NVOBJ_MTHD(d, c, m, e) do { \ 898 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 899 if (ret) \ 900 return ret; \ 901} while (0) 902 903extern int nouveau_gpuobj_early_init(struct drm_device *); 904extern int nouveau_gpuobj_init(struct drm_device *); 905extern void nouveau_gpuobj_takedown(struct drm_device *); 906extern int nouveau_gpuobj_suspend(struct drm_device *dev); 907extern void nouveau_gpuobj_resume(struct drm_device *dev); 908extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 909extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 910 int (*exec)(struct nouveau_channel *, 911 u32 class, u32 mthd, u32 data)); 912extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 913extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 914extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 915 uint32_t vram_h, uint32_t tt_h); 916extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 917extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 918 uint32_t size, int align, uint32_t flags, 919 struct nouveau_gpuobj **); 920extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 921 struct nouveau_gpuobj **); 922extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 923 u32 size, u32 flags, 924 struct nouveau_gpuobj **); 925extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 926 uint64_t offset, uint64_t size, int access, 927 int target, struct nouveau_gpuobj **); 928extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 929extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 930 u64 size, int target, int access, u32 type, 931 u32 comp, struct nouveau_gpuobj **pobj); 932extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 933 int class, u64 base, u64 size, int target, 934 int access, u32 type, u32 comp); 935extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 936 struct drm_file *); 937extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 938 struct drm_file *); 939 940/* nouveau_irq.c */ 941extern int nouveau_irq_init(struct drm_device *); 942extern void nouveau_irq_fini(struct drm_device *); 943extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 944extern void nouveau_irq_register(struct drm_device *, int status_bit, 945 void (*)(struct drm_device *)); 946extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 947extern void nouveau_irq_preinstall(struct drm_device *); 948extern int nouveau_irq_postinstall(struct drm_device *); 949extern void nouveau_irq_uninstall(struct drm_device *); 950 951/* nouveau_sgdma.c */ 952extern int nouveau_sgdma_init(struct drm_device *); 953extern void nouveau_sgdma_takedown(struct drm_device *); 954extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 955 uint32_t offset); 956extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 957 958/* nouveau_debugfs.c */ 959#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 960extern int nouveau_debugfs_init(struct drm_minor *); 961extern void nouveau_debugfs_takedown(struct drm_minor *); 962extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 963extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 964#else 965static inline int 966nouveau_debugfs_init(struct drm_minor *minor) 967{ 968 return 0; 969} 970 971static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 972{ 973} 974 975static inline int 976nouveau_debugfs_channel_init(struct nouveau_channel *chan) 977{ 978 return 0; 979} 980 981static inline void 982nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 983{ 984} 985#endif 986 987/* nouveau_dma.c */ 988extern void nouveau_dma_pre_init(struct nouveau_channel *); 989extern int nouveau_dma_init(struct nouveau_channel *); 990extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 991 992/* nouveau_acpi.c */ 993#define ROM_BIOS_PAGE 4096 994#if defined(CONFIG_ACPI) 995void nouveau_register_dsm_handler(void); 996void nouveau_unregister_dsm_handler(void); 997int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 998bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 999int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1000#else 1001static inline void nouveau_register_dsm_handler(void) {} 1002static inline void nouveau_unregister_dsm_handler(void) {} 1003static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1004static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1005static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1006#endif 1007 1008/* nouveau_backlight.c */ 1009#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1010extern int nouveau_backlight_init(struct drm_connector *); 1011extern void nouveau_backlight_exit(struct drm_connector *); 1012#else 1013static inline int nouveau_backlight_init(struct drm_connector *dev) 1014{ 1015 return 0; 1016} 1017 1018static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1019#endif 1020 1021/* nouveau_bios.c */ 1022extern int nouveau_bios_init(struct drm_device *); 1023extern void nouveau_bios_takedown(struct drm_device *dev); 1024extern int nouveau_run_vbios_init(struct drm_device *); 1025extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1026 struct dcb_entry *); 1027extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1028 enum dcb_gpio_tag); 1029extern struct dcb_connector_table_entry * 1030nouveau_bios_connector_entry(struct drm_device *, int index); 1031extern u32 get_pll_register(struct drm_device *, enum pll_types); 1032extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1033 struct pll_lims *); 1034extern int nouveau_bios_run_display_table(struct drm_device *, 1035 struct dcb_entry *, 1036 uint32_t script, int pxclk); 1037extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1038 int *length); 1039extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1040extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1041extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1042 bool *dl, bool *if_is_24bit); 1043extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1044 int head, int pxclk); 1045extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1046 enum LVDS_script, int pxclk); 1047 1048/* nouveau_ttm.c */ 1049int nouveau_ttm_global_init(struct drm_nouveau_private *); 1050void nouveau_ttm_global_release(struct drm_nouveau_private *); 1051int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1052 1053/* nouveau_dp.c */ 1054int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1055 uint8_t *data, int data_nr); 1056bool nouveau_dp_detect(struct drm_encoder *); 1057bool nouveau_dp_link_train(struct drm_encoder *); 1058 1059/* nv04_fb.c */ 1060extern int nv04_fb_init(struct drm_device *); 1061extern void nv04_fb_takedown(struct drm_device *); 1062 1063/* nv10_fb.c */ 1064extern int nv10_fb_init(struct drm_device *); 1065extern void nv10_fb_takedown(struct drm_device *); 1066extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1067 uint32_t addr, uint32_t size, 1068 uint32_t pitch, uint32_t flags); 1069extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1070extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1071 1072/* nv30_fb.c */ 1073extern int nv30_fb_init(struct drm_device *); 1074extern void nv30_fb_takedown(struct drm_device *); 1075extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1076 uint32_t addr, uint32_t size, 1077 uint32_t pitch, uint32_t flags); 1078extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1079 1080/* nv40_fb.c */ 1081extern int nv40_fb_init(struct drm_device *); 1082extern void nv40_fb_takedown(struct drm_device *); 1083extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1084 1085/* nv50_fb.c */ 1086extern int nv50_fb_init(struct drm_device *); 1087extern void nv50_fb_takedown(struct drm_device *); 1088extern void nv50_fb_vm_trap(struct drm_device *, int display); 1089 1090/* nvc0_fb.c */ 1091extern int nvc0_fb_init(struct drm_device *); 1092extern void nvc0_fb_takedown(struct drm_device *); 1093 1094/* nv04_fifo.c */ 1095extern int nv04_fifo_init(struct drm_device *); 1096extern void nv04_fifo_fini(struct drm_device *); 1097extern void nv04_fifo_disable(struct drm_device *); 1098extern void nv04_fifo_enable(struct drm_device *); 1099extern bool nv04_fifo_reassign(struct drm_device *, bool); 1100extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1101extern int nv04_fifo_channel_id(struct drm_device *); 1102extern int nv04_fifo_create_context(struct nouveau_channel *); 1103extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1104extern int nv04_fifo_load_context(struct nouveau_channel *); 1105extern int nv04_fifo_unload_context(struct drm_device *); 1106extern void nv04_fifo_isr(struct drm_device *); 1107 1108/* nv10_fifo.c */ 1109extern int nv10_fifo_init(struct drm_device *); 1110extern int nv10_fifo_channel_id(struct drm_device *); 1111extern int nv10_fifo_create_context(struct nouveau_channel *); 1112extern int nv10_fifo_load_context(struct nouveau_channel *); 1113extern int nv10_fifo_unload_context(struct drm_device *); 1114 1115/* nv40_fifo.c */ 1116extern int nv40_fifo_init(struct drm_device *); 1117extern int nv40_fifo_create_context(struct nouveau_channel *); 1118extern int nv40_fifo_load_context(struct nouveau_channel *); 1119extern int nv40_fifo_unload_context(struct drm_device *); 1120 1121/* nv50_fifo.c */ 1122extern int nv50_fifo_init(struct drm_device *); 1123extern void nv50_fifo_takedown(struct drm_device *); 1124extern int nv50_fifo_channel_id(struct drm_device *); 1125extern int nv50_fifo_create_context(struct nouveau_channel *); 1126extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1127extern int nv50_fifo_load_context(struct nouveau_channel *); 1128extern int nv50_fifo_unload_context(struct drm_device *); 1129extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1130 1131/* nvc0_fifo.c */ 1132extern int nvc0_fifo_init(struct drm_device *); 1133extern void nvc0_fifo_takedown(struct drm_device *); 1134extern void nvc0_fifo_disable(struct drm_device *); 1135extern void nvc0_fifo_enable(struct drm_device *); 1136extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1137extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1138extern int nvc0_fifo_channel_id(struct drm_device *); 1139extern int nvc0_fifo_create_context(struct nouveau_channel *); 1140extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1141extern int nvc0_fifo_load_context(struct nouveau_channel *); 1142extern int nvc0_fifo_unload_context(struct drm_device *); 1143 1144/* nv04_graph.c */ 1145extern int nv04_graph_create(struct drm_device *); 1146extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1147extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1148 u32 class, u32 mthd, u32 data); 1149extern struct nouveau_bitfield nv04_graph_nsource[]; 1150 1151/* nv10_graph.c */ 1152extern int nv10_graph_create(struct drm_device *); 1153extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1154extern struct nouveau_bitfield nv10_graph_intr[]; 1155extern struct nouveau_bitfield nv10_graph_nstatus[]; 1156 1157/* nv20_graph.c */ 1158extern int nv20_graph_create(struct drm_device *); 1159 1160/* nv40_graph.c */ 1161extern int nv40_graph_create(struct drm_device *); 1162extern void nv40_grctx_init(struct nouveau_grctx *); 1163 1164/* nv50_graph.c */ 1165extern int nv50_graph_create(struct drm_device *); 1166extern int nv50_grctx_init(struct nouveau_grctx *); 1167extern struct nouveau_enum nv50_data_error_names[]; 1168extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1169 1170/* nvc0_graph.c */ 1171extern int nvc0_graph_create(struct drm_device *); 1172extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1173 1174/* nv84_crypt.c */ 1175extern int nv84_crypt_create(struct drm_device *); 1176 1177/* nva3_copy.c */ 1178extern int nva3_copy_create(struct drm_device *dev); 1179 1180/* nvc0_copy.c */ 1181extern int nvc0_copy_create(struct drm_device *dev, int engine); 1182 1183/* nv40_mpeg.c */ 1184extern int nv40_mpeg_create(struct drm_device *dev); 1185 1186/* nv50_mpeg.c */ 1187extern int nv50_mpeg_create(struct drm_device *dev); 1188 1189/* nv04_instmem.c */ 1190extern int nv04_instmem_init(struct drm_device *); 1191extern void nv04_instmem_takedown(struct drm_device *); 1192extern int nv04_instmem_suspend(struct drm_device *); 1193extern void nv04_instmem_resume(struct drm_device *); 1194extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1195 u32 size, u32 align); 1196extern void nv04_instmem_put(struct nouveau_gpuobj *); 1197extern int nv04_instmem_map(struct nouveau_gpuobj *); 1198extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1199extern void nv04_instmem_flush(struct drm_device *); 1200 1201/* nv50_instmem.c */ 1202extern int nv50_instmem_init(struct drm_device *); 1203extern void nv50_instmem_takedown(struct drm_device *); 1204extern int nv50_instmem_suspend(struct drm_device *); 1205extern void nv50_instmem_resume(struct drm_device *); 1206extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1207 u32 size, u32 align); 1208extern void nv50_instmem_put(struct nouveau_gpuobj *); 1209extern int nv50_instmem_map(struct nouveau_gpuobj *); 1210extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1211extern void nv50_instmem_flush(struct drm_device *); 1212extern void nv84_instmem_flush(struct drm_device *); 1213 1214/* nvc0_instmem.c */ 1215extern int nvc0_instmem_init(struct drm_device *); 1216extern void nvc0_instmem_takedown(struct drm_device *); 1217extern int nvc0_instmem_suspend(struct drm_device *); 1218extern void nvc0_instmem_resume(struct drm_device *); 1219 1220/* nv04_mc.c */ 1221extern int nv04_mc_init(struct drm_device *); 1222extern void nv04_mc_takedown(struct drm_device *); 1223 1224/* nv40_mc.c */ 1225extern int nv40_mc_init(struct drm_device *); 1226extern void nv40_mc_takedown(struct drm_device *); 1227 1228/* nv50_mc.c */ 1229extern int nv50_mc_init(struct drm_device *); 1230extern void nv50_mc_takedown(struct drm_device *); 1231 1232/* nv04_timer.c */ 1233extern int nv04_timer_init(struct drm_device *); 1234extern uint64_t nv04_timer_read(struct drm_device *); 1235extern void nv04_timer_takedown(struct drm_device *); 1236 1237extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1238 unsigned long arg); 1239 1240/* nv04_dac.c */ 1241extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1242extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1243extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1244extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1245extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1246 1247/* nv04_dfp.c */ 1248extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1249extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1250extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1251 int head, bool dl); 1252extern void nv04_dfp_disable(struct drm_device *dev, int head); 1253extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1254 1255/* nv04_tv.c */ 1256extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1257extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1258 1259/* nv17_tv.c */ 1260extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1261 1262/* nv04_display.c */ 1263extern int nv04_display_early_init(struct drm_device *); 1264extern void nv04_display_late_takedown(struct drm_device *); 1265extern int nv04_display_create(struct drm_device *); 1266extern int nv04_display_init(struct drm_device *); 1267extern void nv04_display_destroy(struct drm_device *); 1268 1269/* nv04_crtc.c */ 1270extern int nv04_crtc_create(struct drm_device *, int index); 1271 1272/* nouveau_bo.c */ 1273extern struct ttm_bo_driver nouveau_bo_driver; 1274extern int nouveau_bo_new(struct drm_device *, int size, int align, 1275 uint32_t flags, uint32_t tile_mode, 1276 uint32_t tile_flags, struct nouveau_bo **); 1277extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1278extern int nouveau_bo_unpin(struct nouveau_bo *); 1279extern int nouveau_bo_map(struct nouveau_bo *); 1280extern void nouveau_bo_unmap(struct nouveau_bo *); 1281extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1282 uint32_t busy); 1283extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1284extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1285extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1286extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1287extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1288extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1289 bool no_wait_reserve, bool no_wait_gpu); 1290 1291extern struct nouveau_vma * 1292nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1293extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1294 struct nouveau_vma *); 1295extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1296 1297/* nouveau_fence.c */ 1298struct nouveau_fence; 1299extern int nouveau_fence_init(struct drm_device *); 1300extern void nouveau_fence_fini(struct drm_device *); 1301extern int nouveau_fence_channel_init(struct nouveau_channel *); 1302extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1303extern void nouveau_fence_update(struct nouveau_channel *); 1304extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1305 bool emit); 1306extern int nouveau_fence_emit(struct nouveau_fence *); 1307extern void nouveau_fence_work(struct nouveau_fence *fence, 1308 void (*work)(void *priv, bool signalled), 1309 void *priv); 1310struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1311 1312extern bool __nouveau_fence_signalled(void *obj, void *arg); 1313extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1314extern int __nouveau_fence_flush(void *obj, void *arg); 1315extern void __nouveau_fence_unref(void **obj); 1316extern void *__nouveau_fence_ref(void *obj); 1317 1318static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1319{ 1320 return __nouveau_fence_signalled(obj, NULL); 1321} 1322static inline int 1323nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1324{ 1325 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1326} 1327extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1328static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1329{ 1330 return __nouveau_fence_flush(obj, NULL); 1331} 1332static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1333{ 1334 __nouveau_fence_unref((void **)obj); 1335} 1336static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1337{ 1338 return __nouveau_fence_ref(obj); 1339} 1340 1341/* nouveau_gem.c */ 1342extern int nouveau_gem_new(struct drm_device *, int size, int align, 1343 uint32_t domain, uint32_t tile_mode, 1344 uint32_t tile_flags, struct nouveau_bo **); 1345extern int nouveau_gem_object_new(struct drm_gem_object *); 1346extern void nouveau_gem_object_del(struct drm_gem_object *); 1347extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1348extern void nouveau_gem_object_close(struct drm_gem_object *, 1349 struct drm_file *); 1350extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1351 struct drm_file *); 1352extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1353 struct drm_file *); 1354extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1355 struct drm_file *); 1356extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1357 struct drm_file *); 1358extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1359 struct drm_file *); 1360 1361/* nouveau_display.c */ 1362int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1363void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1364int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1365 struct drm_pending_vblank_event *event); 1366int nouveau_finish_page_flip(struct nouveau_channel *, 1367 struct nouveau_page_flip_state *); 1368 1369/* nv10_gpio.c */ 1370int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1371int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1372 1373/* nv50_gpio.c */ 1374int nv50_gpio_init(struct drm_device *dev); 1375void nv50_gpio_fini(struct drm_device *dev); 1376int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1377int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1378int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1379 void (*)(void *, int), void *); 1380void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1381 void (*)(void *, int), void *); 1382bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1383 1384/* nv50_calc. */ 1385int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1386 int *N1, int *M1, int *N2, int *M2, int *P); 1387int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1388 int clk, int *N, int *fN, int *M, int *P); 1389 1390#ifndef ioread32_native 1391#ifdef __BIG_ENDIAN 1392#define ioread16_native ioread16be 1393#define iowrite16_native iowrite16be 1394#define ioread32_native ioread32be 1395#define iowrite32_native iowrite32be 1396#else /* def __BIG_ENDIAN */ 1397#define ioread16_native ioread16 1398#define iowrite16_native iowrite16 1399#define ioread32_native ioread32 1400#define iowrite32_native iowrite32 1401#endif /* def __BIG_ENDIAN else */ 1402#endif /* !ioread32_native */ 1403 1404/* channel control reg access */ 1405static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1406{ 1407 return ioread32_native(chan->user + reg); 1408} 1409 1410static inline void nvchan_wr32(struct nouveau_channel *chan, 1411 unsigned reg, u32 val) 1412{ 1413 iowrite32_native(val, chan->user + reg); 1414} 1415 1416/* register access */ 1417static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1418{ 1419 struct drm_nouveau_private *dev_priv = dev->dev_private; 1420 return ioread32_native(dev_priv->mmio + reg); 1421} 1422 1423static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1424{ 1425 struct drm_nouveau_private *dev_priv = dev->dev_private; 1426 iowrite32_native(val, dev_priv->mmio + reg); 1427} 1428 1429static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1430{ 1431 u32 tmp = nv_rd32(dev, reg); 1432 nv_wr32(dev, reg, (tmp & ~mask) | val); 1433 return tmp; 1434} 1435 1436static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1437{ 1438 struct drm_nouveau_private *dev_priv = dev->dev_private; 1439 return ioread8(dev_priv->mmio + reg); 1440} 1441 1442static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1443{ 1444 struct drm_nouveau_private *dev_priv = dev->dev_private; 1445 iowrite8(val, dev_priv->mmio + reg); 1446} 1447 1448#define nv_wait(dev, reg, mask, val) \ 1449 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1450#define nv_wait_ne(dev, reg, mask, val) \ 1451 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1452 1453/* PRAMIN access */ 1454static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1455{ 1456 struct drm_nouveau_private *dev_priv = dev->dev_private; 1457 return ioread32_native(dev_priv->ramin + offset); 1458} 1459 1460static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1461{ 1462 struct drm_nouveau_private *dev_priv = dev->dev_private; 1463 iowrite32_native(val, dev_priv->ramin + offset); 1464} 1465 1466/* object access */ 1467extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1468extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1469 1470/* 1471 * Logging 1472 * Argument d is (struct drm_device *). 1473 */ 1474#define NV_PRINTK(level, d, fmt, arg...) \ 1475 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1476 pci_name(d->pdev), ##arg) 1477#ifndef NV_DEBUG_NOTRACE 1478#define NV_DEBUG(d, fmt, arg...) do { \ 1479 if (drm_debug & DRM_UT_DRIVER) { \ 1480 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1481 __LINE__, ##arg); \ 1482 } \ 1483} while (0) 1484#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1485 if (drm_debug & DRM_UT_KMS) { \ 1486 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1487 __LINE__, ##arg); \ 1488 } \ 1489} while (0) 1490#else 1491#define NV_DEBUG(d, fmt, arg...) do { \ 1492 if (drm_debug & DRM_UT_DRIVER) \ 1493 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1494} while (0) 1495#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1496 if (drm_debug & DRM_UT_KMS) \ 1497 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1498} while (0) 1499#endif 1500#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1501#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1502#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1503#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1504#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1505 1506/* nouveau_reg_debug bitmask */ 1507enum { 1508 NOUVEAU_REG_DEBUG_MC = 0x1, 1509 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1510 NOUVEAU_REG_DEBUG_FB = 0x4, 1511 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1512 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1513 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1514 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1515 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1516 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1517 NOUVEAU_REG_DEBUG_EVO = 0x200, 1518}; 1519 1520#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1521 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1522 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1523} while (0) 1524 1525static inline bool 1526nv_two_heads(struct drm_device *dev) 1527{ 1528 struct drm_nouveau_private *dev_priv = dev->dev_private; 1529 const int impl = dev->pci_device & 0x0ff0; 1530 1531 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1532 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1533 return true; 1534 1535 return false; 1536} 1537 1538static inline bool 1539nv_gf4_disp_arch(struct drm_device *dev) 1540{ 1541 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1542} 1543 1544static inline bool 1545nv_two_reg_pll(struct drm_device *dev) 1546{ 1547 struct drm_nouveau_private *dev_priv = dev->dev_private; 1548 const int impl = dev->pci_device & 0x0ff0; 1549 1550 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1551 return true; 1552 return false; 1553} 1554 1555static inline bool 1556nv_match_device(struct drm_device *dev, unsigned device, 1557 unsigned sub_vendor, unsigned sub_device) 1558{ 1559 return dev->pdev->device == device && 1560 dev->pdev->subsystem_vendor == sub_vendor && 1561 dev->pdev->subsystem_device == sub_device; 1562} 1563 1564static inline void * 1565nv_engine(struct drm_device *dev, int engine) 1566{ 1567 struct drm_nouveau_private *dev_priv = dev->dev_private; 1568 return (void *)dev_priv->eng[engine]; 1569} 1570 1571/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1572 * helpful to determine a number of other hardware features 1573 */ 1574static inline int 1575nv44_graph_class(struct drm_device *dev) 1576{ 1577 struct drm_nouveau_private *dev_priv = dev->dev_private; 1578 1579 if ((dev_priv->chipset & 0xf0) == 0x60) 1580 return 1; 1581 1582 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1583} 1584 1585/* memory type/access flags, do not match hardware values */ 1586#define NV_MEM_ACCESS_RO 1 1587#define NV_MEM_ACCESS_WO 2 1588#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1589#define NV_MEM_ACCESS_SYS 4 1590#define NV_MEM_ACCESS_VM 8 1591 1592#define NV_MEM_TARGET_VRAM 0 1593#define NV_MEM_TARGET_PCI 1 1594#define NV_MEM_TARGET_PCI_NOSNOOP 2 1595#define NV_MEM_TARGET_VM 3 1596#define NV_MEM_TARGET_GART 4 1597 1598#define NV_MEM_TYPE_VM 0x7f 1599#define NV_MEM_COMP_VM 0x03 1600 1601/* NV_SW object class */ 1602#define NV_SW 0x0000506e 1603#define NV_SW_DMA_SEMAPHORE 0x00000060 1604#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1605#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1606#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1607#define NV_SW_YIELD 0x00000080 1608#define NV_SW_DMA_VBLSEM 0x0000018c 1609#define NV_SW_VBLSEM_OFFSET 0x00000400 1610#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1611#define NV_SW_VBLSEM_RELEASE 0x00000408 1612#define NV_SW_PAGE_FLIP 0x00000500 1613 1614#endif /* __NOUVEAU_DRV_H__ */ 1615