nouveau_drv.h revision 3f0a68d8f8ba9d6c0cd9df948fbba90944c3da62
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50}; 51 52static inline struct nouveau_fpriv * 53nouveau_fpriv(struct drm_file *file_priv) 54{ 55 return file_priv ? file_priv->driver_priv : NULL; 56} 57 58#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 59 60#include "nouveau_drm.h" 61#include "nouveau_reg.h" 62#include "nouveau_bios.h" 63#include "nouveau_util.h" 64 65struct nouveau_grctx; 66struct nouveau_mem; 67#include "nouveau_vm.h" 68 69#define MAX_NUM_DCB_ENTRIES 16 70 71#define NOUVEAU_MAX_CHANNEL_NR 128 72#define NOUVEAU_MAX_TILE_NR 15 73 74struct nouveau_mem { 75 struct drm_device *dev; 76 77 struct nouveau_vma bar_vma; 78 struct nouveau_vma tmp_vma; 79 u8 page_shift; 80 81 struct drm_mm_node *tag; 82 struct list_head regions; 83 dma_addr_t *pages; 84 u32 memtype; 85 u64 offset; 86 u64 size; 87}; 88 89struct nouveau_tile_reg { 90 bool used; 91 uint32_t addr; 92 uint32_t limit; 93 uint32_t pitch; 94 uint32_t zcomp; 95 struct drm_mm_node *tag_mem; 96 struct nouveau_fence *fence; 97}; 98 99struct nouveau_bo { 100 struct ttm_buffer_object bo; 101 struct ttm_placement placement; 102 u32 valid_domains; 103 u32 placements[3]; 104 u32 busy_placements[3]; 105 struct ttm_bo_kmap_obj kmap; 106 struct list_head head; 107 108 /* protected by ttm_bo_reserve() */ 109 struct drm_file *reserved_by; 110 struct list_head entry; 111 int pbbo_index; 112 bool validate_mapped; 113 114 struct nouveau_channel *channel; 115 116 struct nouveau_vma vma; 117 118 uint32_t tile_mode; 119 uint32_t tile_flags; 120 struct nouveau_tile_reg *tile; 121 122 struct drm_gem_object *gem; 123 int pin_refcnt; 124}; 125 126#define nouveau_bo_tile_layout(nvbo) \ 127 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 128 129static inline struct nouveau_bo * 130nouveau_bo(struct ttm_buffer_object *bo) 131{ 132 return container_of(bo, struct nouveau_bo, bo); 133} 134 135static inline struct nouveau_bo * 136nouveau_gem_object(struct drm_gem_object *gem) 137{ 138 return gem ? gem->driver_private : NULL; 139} 140 141/* TODO: submit equivalent to TTM generic API upstream? */ 142static inline void __iomem * 143nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 144{ 145 bool is_iomem; 146 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 147 &nvbo->kmap, &is_iomem); 148 WARN_ON_ONCE(ioptr && !is_iomem); 149 return ioptr; 150} 151 152enum nouveau_flags { 153 NV_NFORCE = 0x10000000, 154 NV_NFORCE2 = 0x20000000 155}; 156 157#define NVOBJ_ENGINE_SW 0 158#define NVOBJ_ENGINE_GR 1 159#define NVOBJ_ENGINE_CRYPT 2 160#define NVOBJ_ENGINE_COPY0 3 161#define NVOBJ_ENGINE_COPY1 4 162#define NVOBJ_ENGINE_MPEG 5 163#define NVOBJ_ENGINE_DISPLAY 15 164#define NVOBJ_ENGINE_NR 16 165 166#define NVOBJ_FLAG_DONT_MAP (1 << 0) 167#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 168#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 169#define NVOBJ_FLAG_VM (1 << 3) 170#define NVOBJ_FLAG_VM_USER (1 << 4) 171 172#define NVOBJ_CINST_GLOBAL 0xdeadbeef 173 174struct nouveau_gpuobj { 175 struct drm_device *dev; 176 struct kref refcount; 177 struct list_head list; 178 179 void *node; 180 u32 *suspend; 181 182 uint32_t flags; 183 184 u32 size; 185 u32 pinst; /* PRAMIN BAR offset */ 186 u32 cinst; /* Channel offset */ 187 u64 vinst; /* VRAM address */ 188 u64 linst; /* VM address */ 189 190 uint32_t engine; 191 uint32_t class; 192 193 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 194 void *priv; 195}; 196 197struct nouveau_page_flip_state { 198 struct list_head head; 199 struct drm_pending_vblank_event *event; 200 int crtc, bpp, pitch, x, y; 201 uint64_t offset; 202}; 203 204enum nouveau_channel_mutex_class { 205 NOUVEAU_UCHANNEL_MUTEX, 206 NOUVEAU_KCHANNEL_MUTEX 207}; 208 209struct nouveau_channel { 210 struct drm_device *dev; 211 int id; 212 213 /* references to the channel data structure */ 214 struct kref ref; 215 /* users of the hardware channel resources, the hardware 216 * context will be kicked off when it reaches zero. */ 217 atomic_t users; 218 struct mutex mutex; 219 220 /* owner of this fifo */ 221 struct drm_file *file_priv; 222 /* mapping of the fifo itself */ 223 struct drm_local_map *map; 224 225 /* mapping of the regs controlling the fifo */ 226 void __iomem *user; 227 uint32_t user_get; 228 uint32_t user_put; 229 230 /* Fencing */ 231 struct { 232 /* lock protects the pending list only */ 233 spinlock_t lock; 234 struct list_head pending; 235 uint32_t sequence; 236 uint32_t sequence_ack; 237 atomic_t last_sequence_irq; 238 } fence; 239 240 /* DMA push buffer */ 241 struct nouveau_gpuobj *pushbuf; 242 struct nouveau_bo *pushbuf_bo; 243 uint32_t pushbuf_base; 244 245 /* Notifier memory */ 246 struct nouveau_bo *notifier_bo; 247 struct drm_mm notifier_heap; 248 249 /* PFIFO context */ 250 struct nouveau_gpuobj *ramfc; 251 struct nouveau_gpuobj *cache; 252 void *fifo_priv; 253 254 /* Execution engine contexts */ 255 void *engctx[NVOBJ_ENGINE_NR]; 256 257 /* NV50 VM */ 258 struct nouveau_vm *vm; 259 struct nouveau_gpuobj *vm_pd; 260 261 /* Objects */ 262 struct nouveau_gpuobj *ramin; /* Private instmem */ 263 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 264 struct nouveau_ramht *ramht; /* Hash table */ 265 266 /* GPU object info for stuff used in-kernel (mm_enabled) */ 267 uint32_t m2mf_ntfy; 268 uint32_t vram_handle; 269 uint32_t gart_handle; 270 bool accel_done; 271 272 /* Push buffer state (only for drm's channel on !mm_enabled) */ 273 struct { 274 int max; 275 int free; 276 int cur; 277 int put; 278 /* access via pushbuf_bo */ 279 280 int ib_base; 281 int ib_max; 282 int ib_free; 283 int ib_put; 284 } dma; 285 286 uint32_t sw_subchannel[8]; 287 288 struct { 289 struct nouveau_gpuobj *vblsem; 290 uint32_t vblsem_head; 291 uint32_t vblsem_offset; 292 uint32_t vblsem_rval; 293 struct list_head vbl_wait; 294 struct list_head flip; 295 } nvsw; 296 297 struct { 298 bool active; 299 char name[32]; 300 struct drm_info_list info; 301 } debugfs; 302}; 303 304struct nouveau_exec_engine { 305 void (*destroy)(struct drm_device *, int engine); 306 int (*init)(struct drm_device *, int engine); 307 int (*fini)(struct drm_device *, int engine); 308 int (*context_new)(struct nouveau_channel *, int engine); 309 void (*context_del)(struct nouveau_channel *, int engine); 310 int (*object_new)(struct nouveau_channel *, int engine, 311 u32 handle, u16 class); 312 void (*set_tile_region)(struct drm_device *dev, int i); 313 void (*tlb_flush)(struct drm_device *, int engine); 314}; 315 316struct nouveau_instmem_engine { 317 void *priv; 318 319 int (*init)(struct drm_device *dev); 320 void (*takedown)(struct drm_device *dev); 321 int (*suspend)(struct drm_device *dev); 322 void (*resume)(struct drm_device *dev); 323 324 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 325 void (*put)(struct nouveau_gpuobj *); 326 int (*map)(struct nouveau_gpuobj *); 327 void (*unmap)(struct nouveau_gpuobj *); 328 329 void (*flush)(struct drm_device *); 330}; 331 332struct nouveau_mc_engine { 333 int (*init)(struct drm_device *dev); 334 void (*takedown)(struct drm_device *dev); 335}; 336 337struct nouveau_timer_engine { 338 int (*init)(struct drm_device *dev); 339 void (*takedown)(struct drm_device *dev); 340 uint64_t (*read)(struct drm_device *dev); 341}; 342 343struct nouveau_fb_engine { 344 int num_tiles; 345 struct drm_mm tag_heap; 346 void *priv; 347 348 int (*init)(struct drm_device *dev); 349 void (*takedown)(struct drm_device *dev); 350 351 void (*init_tile_region)(struct drm_device *dev, int i, 352 uint32_t addr, uint32_t size, 353 uint32_t pitch, uint32_t flags); 354 void (*set_tile_region)(struct drm_device *dev, int i); 355 void (*free_tile_region)(struct drm_device *dev, int i); 356}; 357 358struct nouveau_fifo_engine { 359 void *priv; 360 int channels; 361 362 struct nouveau_gpuobj *playlist[2]; 363 int cur_playlist; 364 365 int (*init)(struct drm_device *); 366 void (*takedown)(struct drm_device *); 367 368 void (*disable)(struct drm_device *); 369 void (*enable)(struct drm_device *); 370 bool (*reassign)(struct drm_device *, bool enable); 371 bool (*cache_pull)(struct drm_device *dev, bool enable); 372 373 int (*channel_id)(struct drm_device *); 374 375 int (*create_context)(struct nouveau_channel *); 376 void (*destroy_context)(struct nouveau_channel *); 377 int (*load_context)(struct nouveau_channel *); 378 int (*unload_context)(struct drm_device *); 379 void (*tlb_flush)(struct drm_device *dev); 380}; 381 382struct nouveau_display_engine { 383 void *priv; 384 int (*early_init)(struct drm_device *); 385 void (*late_takedown)(struct drm_device *); 386 int (*create)(struct drm_device *); 387 int (*init)(struct drm_device *); 388 void (*destroy)(struct drm_device *); 389}; 390 391struct nouveau_gpio_engine { 392 void *priv; 393 394 int (*init)(struct drm_device *); 395 void (*takedown)(struct drm_device *); 396 397 int (*get)(struct drm_device *, enum dcb_gpio_tag); 398 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 399 400 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 401 void (*)(void *, int), void *); 402 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 403 void (*)(void *, int), void *); 404 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 405}; 406 407struct nouveau_pm_voltage_level { 408 u8 voltage; 409 u8 vid; 410}; 411 412struct nouveau_pm_voltage { 413 bool supported; 414 u8 vid_mask; 415 416 struct nouveau_pm_voltage_level *level; 417 int nr_level; 418}; 419 420struct nouveau_pm_memtiming { 421 int id; 422 u32 reg_100220; 423 u32 reg_100224; 424 u32 reg_100228; 425 u32 reg_10022c; 426 u32 reg_100230; 427 u32 reg_100234; 428 u32 reg_100238; 429 u32 reg_10023c; 430 u32 reg_100240; 431}; 432 433#define NOUVEAU_PM_MAX_LEVEL 8 434struct nouveau_pm_level { 435 struct device_attribute dev_attr; 436 char name[32]; 437 int id; 438 439 u32 core; 440 u32 memory; 441 u32 shader; 442 u32 unk05; 443 u32 unk0a; 444 445 u8 voltage; 446 u8 fanspeed; 447 448 u16 memscript; 449 struct nouveau_pm_memtiming *timing; 450}; 451 452struct nouveau_pm_temp_sensor_constants { 453 u16 offset_constant; 454 s16 offset_mult; 455 u16 offset_div; 456 u16 slope_mult; 457 u16 slope_div; 458}; 459 460struct nouveau_pm_threshold_temp { 461 s16 critical; 462 s16 down_clock; 463 s16 fan_boost; 464}; 465 466struct nouveau_pm_memtimings { 467 bool supported; 468 struct nouveau_pm_memtiming *timing; 469 int nr_timing; 470}; 471 472struct nouveau_pm_engine { 473 struct nouveau_pm_voltage voltage; 474 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 475 int nr_perflvl; 476 struct nouveau_pm_memtimings memtimings; 477 struct nouveau_pm_temp_sensor_constants sensor_constants; 478 struct nouveau_pm_threshold_temp threshold_temp; 479 480 struct nouveau_pm_level boot; 481 struct nouveau_pm_level *cur; 482 483 struct device *hwmon; 484 struct notifier_block acpi_nb; 485 486 int (*clock_get)(struct drm_device *, u32 id); 487 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 488 u32 id, int khz); 489 void (*clock_set)(struct drm_device *, void *); 490 int (*voltage_get)(struct drm_device *); 491 int (*voltage_set)(struct drm_device *, int voltage); 492 int (*fanspeed_get)(struct drm_device *); 493 int (*fanspeed_set)(struct drm_device *, int fanspeed); 494 int (*temp_get)(struct drm_device *); 495}; 496 497struct nouveau_vram_engine { 498 int (*init)(struct drm_device *); 499 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 500 u32 type, struct nouveau_mem **); 501 void (*put)(struct drm_device *, struct nouveau_mem **); 502 503 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 504}; 505 506struct nouveau_engine { 507 struct nouveau_instmem_engine instmem; 508 struct nouveau_mc_engine mc; 509 struct nouveau_timer_engine timer; 510 struct nouveau_fb_engine fb; 511 struct nouveau_fifo_engine fifo; 512 struct nouveau_display_engine display; 513 struct nouveau_gpio_engine gpio; 514 struct nouveau_pm_engine pm; 515 struct nouveau_vram_engine vram; 516}; 517 518struct nouveau_pll_vals { 519 union { 520 struct { 521#ifdef __BIG_ENDIAN 522 uint8_t N1, M1, N2, M2; 523#else 524 uint8_t M1, N1, M2, N2; 525#endif 526 }; 527 struct { 528 uint16_t NM1, NM2; 529 } __attribute__((packed)); 530 }; 531 int log2P; 532 533 int refclk; 534}; 535 536enum nv04_fp_display_regs { 537 FP_DISPLAY_END, 538 FP_TOTAL, 539 FP_CRTC, 540 FP_SYNC_START, 541 FP_SYNC_END, 542 FP_VALID_START, 543 FP_VALID_END 544}; 545 546struct nv04_crtc_reg { 547 unsigned char MiscOutReg; 548 uint8_t CRTC[0xa0]; 549 uint8_t CR58[0x10]; 550 uint8_t Sequencer[5]; 551 uint8_t Graphics[9]; 552 uint8_t Attribute[21]; 553 unsigned char DAC[768]; 554 555 /* PCRTC regs */ 556 uint32_t fb_start; 557 uint32_t crtc_cfg; 558 uint32_t cursor_cfg; 559 uint32_t gpio_ext; 560 uint32_t crtc_830; 561 uint32_t crtc_834; 562 uint32_t crtc_850; 563 uint32_t crtc_eng_ctrl; 564 565 /* PRAMDAC regs */ 566 uint32_t nv10_cursync; 567 struct nouveau_pll_vals pllvals; 568 uint32_t ramdac_gen_ctrl; 569 uint32_t ramdac_630; 570 uint32_t ramdac_634; 571 uint32_t tv_setup; 572 uint32_t tv_vtotal; 573 uint32_t tv_vskew; 574 uint32_t tv_vsync_delay; 575 uint32_t tv_htotal; 576 uint32_t tv_hskew; 577 uint32_t tv_hsync_delay; 578 uint32_t tv_hsync_delay2; 579 uint32_t fp_horiz_regs[7]; 580 uint32_t fp_vert_regs[7]; 581 uint32_t dither; 582 uint32_t fp_control; 583 uint32_t dither_regs[6]; 584 uint32_t fp_debug_0; 585 uint32_t fp_debug_1; 586 uint32_t fp_debug_2; 587 uint32_t fp_margin_color; 588 uint32_t ramdac_8c0; 589 uint32_t ramdac_a20; 590 uint32_t ramdac_a24; 591 uint32_t ramdac_a34; 592 uint32_t ctv_regs[38]; 593}; 594 595struct nv04_output_reg { 596 uint32_t output; 597 int head; 598}; 599 600struct nv04_mode_state { 601 struct nv04_crtc_reg crtc_reg[2]; 602 uint32_t pllsel; 603 uint32_t sel_clk; 604}; 605 606enum nouveau_card_type { 607 NV_04 = 0x00, 608 NV_10 = 0x10, 609 NV_20 = 0x20, 610 NV_30 = 0x30, 611 NV_40 = 0x40, 612 NV_50 = 0x50, 613 NV_C0 = 0xc0, 614}; 615 616struct drm_nouveau_private { 617 struct drm_device *dev; 618 bool noaccel; 619 620 /* the card type, takes NV_* as values */ 621 enum nouveau_card_type card_type; 622 /* exact chipset, derived from NV_PMC_BOOT_0 */ 623 int chipset; 624 int stepping; 625 int flags; 626 627 void __iomem *mmio; 628 629 spinlock_t ramin_lock; 630 void __iomem *ramin; 631 u32 ramin_size; 632 u32 ramin_base; 633 bool ramin_available; 634 struct drm_mm ramin_heap; 635 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 636 struct list_head gpuobj_list; 637 struct list_head classes; 638 639 struct nouveau_bo *vga_ram; 640 641 /* interrupt handling */ 642 void (*irq_handler[32])(struct drm_device *); 643 bool msi_enabled; 644 645 struct list_head vbl_waiting; 646 647 struct { 648 struct drm_global_reference mem_global_ref; 649 struct ttm_bo_global_ref bo_global_ref; 650 struct ttm_bo_device bdev; 651 atomic_t validate_sequence; 652 } ttm; 653 654 struct { 655 spinlock_t lock; 656 struct drm_mm heap; 657 struct nouveau_bo *bo; 658 } fence; 659 660 struct { 661 spinlock_t lock; 662 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 663 } channels; 664 665 struct nouveau_engine engine; 666 struct nouveau_channel *channel; 667 668 /* For PFIFO and PGRAPH. */ 669 spinlock_t context_switch_lock; 670 671 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 672 spinlock_t vm_lock; 673 674 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 675 struct nouveau_ramht *ramht; 676 struct nouveau_gpuobj *ramfc; 677 struct nouveau_gpuobj *ramro; 678 679 uint32_t ramin_rsvd_vram; 680 681 struct { 682 enum { 683 NOUVEAU_GART_NONE = 0, 684 NOUVEAU_GART_AGP, /* AGP */ 685 NOUVEAU_GART_PDMA, /* paged dma object */ 686 NOUVEAU_GART_HW /* on-chip gart/vm */ 687 } type; 688 uint64_t aper_base; 689 uint64_t aper_size; 690 uint64_t aper_free; 691 692 struct ttm_backend_func *func; 693 694 struct { 695 struct page *page; 696 dma_addr_t addr; 697 } dummy; 698 699 struct nouveau_gpuobj *sg_ctxdma; 700 } gart_info; 701 702 /* nv10-nv40 tiling regions */ 703 struct { 704 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 705 spinlock_t lock; 706 } tile; 707 708 /* VRAM/fb configuration */ 709 uint64_t vram_size; 710 uint64_t vram_sys_base; 711 u32 vram_rblock_size; 712 713 uint64_t fb_phys; 714 uint64_t fb_available_size; 715 uint64_t fb_mappable_pages; 716 uint64_t fb_aper_free; 717 int fb_mtrr; 718 719 /* BAR control (NV50-) */ 720 struct nouveau_vm *bar1_vm; 721 struct nouveau_vm *bar3_vm; 722 723 /* G8x/G9x virtual address space */ 724 struct nouveau_vm *chan_vm; 725 726 struct nvbios vbios; 727 728 struct nv04_mode_state mode_reg; 729 struct nv04_mode_state saved_reg; 730 uint32_t saved_vga_font[4][16384]; 731 uint32_t crtc_owner; 732 uint32_t dac_users[4]; 733 734 struct backlight_device *backlight; 735 736 struct { 737 struct dentry *channel_root; 738 } debugfs; 739 740 struct nouveau_fbdev *nfbdev; 741 struct apertures_struct *apertures; 742}; 743 744static inline struct drm_nouveau_private * 745nouveau_private(struct drm_device *dev) 746{ 747 return dev->dev_private; 748} 749 750static inline struct drm_nouveau_private * 751nouveau_bdev(struct ttm_bo_device *bd) 752{ 753 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 754} 755 756static inline int 757nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 758{ 759 struct nouveau_bo *prev; 760 761 if (!pnvbo) 762 return -EINVAL; 763 prev = *pnvbo; 764 765 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 766 if (prev) { 767 struct ttm_buffer_object *bo = &prev->bo; 768 769 ttm_bo_unref(&bo); 770 } 771 772 return 0; 773} 774 775/* nouveau_drv.c */ 776extern int nouveau_agpmode; 777extern int nouveau_duallink; 778extern int nouveau_uscript_lvds; 779extern int nouveau_uscript_tmds; 780extern int nouveau_vram_pushbuf; 781extern int nouveau_vram_notify; 782extern int nouveau_fbpercrtc; 783extern int nouveau_tv_disable; 784extern char *nouveau_tv_norm; 785extern int nouveau_reg_debug; 786extern char *nouveau_vbios; 787extern int nouveau_ignorelid; 788extern int nouveau_nofbaccel; 789extern int nouveau_noaccel; 790extern int nouveau_force_post; 791extern int nouveau_override_conntype; 792extern char *nouveau_perflvl; 793extern int nouveau_perflvl_wr; 794extern int nouveau_msi; 795extern int nouveau_ctxfw; 796 797extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 798extern int nouveau_pci_resume(struct pci_dev *pdev); 799 800/* nouveau_state.c */ 801extern int nouveau_open(struct drm_device *, struct drm_file *); 802extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 803extern void nouveau_postclose(struct drm_device *, struct drm_file *); 804extern int nouveau_load(struct drm_device *, unsigned long flags); 805extern int nouveau_firstopen(struct drm_device *); 806extern void nouveau_lastclose(struct drm_device *); 807extern int nouveau_unload(struct drm_device *); 808extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 809 struct drm_file *); 810extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 811 struct drm_file *); 812extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 813 uint32_t reg, uint32_t mask, uint32_t val); 814extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 815 uint32_t reg, uint32_t mask, uint32_t val); 816extern bool nouveau_wait_for_idle(struct drm_device *); 817extern int nouveau_card_init(struct drm_device *); 818 819/* nouveau_mem.c */ 820extern int nouveau_mem_vram_init(struct drm_device *); 821extern void nouveau_mem_vram_fini(struct drm_device *); 822extern int nouveau_mem_gart_init(struct drm_device *); 823extern void nouveau_mem_gart_fini(struct drm_device *); 824extern int nouveau_mem_init_agp(struct drm_device *); 825extern int nouveau_mem_reset_agp(struct drm_device *); 826extern void nouveau_mem_close(struct drm_device *); 827extern int nouveau_mem_detect(struct drm_device *); 828extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 829extern struct nouveau_tile_reg *nv10_mem_set_tiling( 830 struct drm_device *dev, uint32_t addr, uint32_t size, 831 uint32_t pitch, uint32_t flags); 832extern void nv10_mem_put_tile_region(struct drm_device *dev, 833 struct nouveau_tile_reg *tile, 834 struct nouveau_fence *fence); 835extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 836extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 837 838/* nouveau_notifier.c */ 839extern int nouveau_notifier_init_channel(struct nouveau_channel *); 840extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 841extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 842 int cout, uint32_t start, uint32_t end, 843 uint32_t *offset); 844extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 845extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 846 struct drm_file *); 847extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 848 struct drm_file *); 849 850/* nouveau_channel.c */ 851extern struct drm_ioctl_desc nouveau_ioctls[]; 852extern int nouveau_max_ioctl; 853extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 854extern int nouveau_channel_alloc(struct drm_device *dev, 855 struct nouveau_channel **chan, 856 struct drm_file *file_priv, 857 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 858extern struct nouveau_channel * 859nouveau_channel_get_unlocked(struct nouveau_channel *); 860extern struct nouveau_channel * 861nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 862extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 863extern void nouveau_channel_put(struct nouveau_channel **); 864extern void nouveau_channel_ref(struct nouveau_channel *chan, 865 struct nouveau_channel **pchan); 866extern void nouveau_channel_idle(struct nouveau_channel *chan); 867 868/* nouveau_object.c */ 869#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 870 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 871 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 872} while (0) 873 874#define NVOBJ_ENGINE_DEL(d, e) do { \ 875 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 876 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 877} while (0) 878 879#define NVOBJ_CLASS(d, c, e) do { \ 880 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 881 if (ret) \ 882 return ret; \ 883} while (0) 884 885#define NVOBJ_MTHD(d, c, m, e) do { \ 886 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 887 if (ret) \ 888 return ret; \ 889} while (0) 890 891extern int nouveau_gpuobj_early_init(struct drm_device *); 892extern int nouveau_gpuobj_init(struct drm_device *); 893extern void nouveau_gpuobj_takedown(struct drm_device *); 894extern int nouveau_gpuobj_suspend(struct drm_device *dev); 895extern void nouveau_gpuobj_resume(struct drm_device *dev); 896extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 897extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 898 int (*exec)(struct nouveau_channel *, 899 u32 class, u32 mthd, u32 data)); 900extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 901extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 902extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 903 uint32_t vram_h, uint32_t tt_h); 904extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 905extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 906 uint32_t size, int align, uint32_t flags, 907 struct nouveau_gpuobj **); 908extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 909 struct nouveau_gpuobj **); 910extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 911 u32 size, u32 flags, 912 struct nouveau_gpuobj **); 913extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 914 uint64_t offset, uint64_t size, int access, 915 int target, struct nouveau_gpuobj **); 916extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 917extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 918 u64 size, int target, int access, u32 type, 919 u32 comp, struct nouveau_gpuobj **pobj); 920extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 921 int class, u64 base, u64 size, int target, 922 int access, u32 type, u32 comp); 923extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 924 struct drm_file *); 925extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 926 struct drm_file *); 927 928/* nouveau_irq.c */ 929extern int nouveau_irq_init(struct drm_device *); 930extern void nouveau_irq_fini(struct drm_device *); 931extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 932extern void nouveau_irq_register(struct drm_device *, int status_bit, 933 void (*)(struct drm_device *)); 934extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 935extern void nouveau_irq_preinstall(struct drm_device *); 936extern int nouveau_irq_postinstall(struct drm_device *); 937extern void nouveau_irq_uninstall(struct drm_device *); 938 939/* nouveau_sgdma.c */ 940extern int nouveau_sgdma_init(struct drm_device *); 941extern void nouveau_sgdma_takedown(struct drm_device *); 942extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 943 uint32_t offset); 944extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 945 946/* nouveau_debugfs.c */ 947#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 948extern int nouveau_debugfs_init(struct drm_minor *); 949extern void nouveau_debugfs_takedown(struct drm_minor *); 950extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 951extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 952#else 953static inline int 954nouveau_debugfs_init(struct drm_minor *minor) 955{ 956 return 0; 957} 958 959static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 960{ 961} 962 963static inline int 964nouveau_debugfs_channel_init(struct nouveau_channel *chan) 965{ 966 return 0; 967} 968 969static inline void 970nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 971{ 972} 973#endif 974 975/* nouveau_dma.c */ 976extern void nouveau_dma_pre_init(struct nouveau_channel *); 977extern int nouveau_dma_init(struct nouveau_channel *); 978extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 979 980/* nouveau_acpi.c */ 981#define ROM_BIOS_PAGE 4096 982#if defined(CONFIG_ACPI) 983void nouveau_register_dsm_handler(void); 984void nouveau_unregister_dsm_handler(void); 985int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 986bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 987int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 988#else 989static inline void nouveau_register_dsm_handler(void) {} 990static inline void nouveau_unregister_dsm_handler(void) {} 991static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 992static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 993static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 994#endif 995 996/* nouveau_backlight.c */ 997#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 998extern int nouveau_backlight_init(struct drm_connector *); 999extern void nouveau_backlight_exit(struct drm_connector *); 1000#else 1001static inline int nouveau_backlight_init(struct drm_connector *dev) 1002{ 1003 return 0; 1004} 1005 1006static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1007#endif 1008 1009/* nouveau_bios.c */ 1010extern int nouveau_bios_init(struct drm_device *); 1011extern void nouveau_bios_takedown(struct drm_device *dev); 1012extern int nouveau_run_vbios_init(struct drm_device *); 1013extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1014 struct dcb_entry *); 1015extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1016 enum dcb_gpio_tag); 1017extern struct dcb_connector_table_entry * 1018nouveau_bios_connector_entry(struct drm_device *, int index); 1019extern u32 get_pll_register(struct drm_device *, enum pll_types); 1020extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1021 struct pll_lims *); 1022extern int nouveau_bios_run_display_table(struct drm_device *, 1023 struct dcb_entry *, 1024 uint32_t script, int pxclk); 1025extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1026 int *length); 1027extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1028extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1029extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1030 bool *dl, bool *if_is_24bit); 1031extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1032 int head, int pxclk); 1033extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1034 enum LVDS_script, int pxclk); 1035 1036/* nouveau_ttm.c */ 1037int nouveau_ttm_global_init(struct drm_nouveau_private *); 1038void nouveau_ttm_global_release(struct drm_nouveau_private *); 1039int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1040 1041/* nouveau_dp.c */ 1042int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1043 uint8_t *data, int data_nr); 1044bool nouveau_dp_detect(struct drm_encoder *); 1045bool nouveau_dp_link_train(struct drm_encoder *); 1046 1047/* nv04_fb.c */ 1048extern int nv04_fb_init(struct drm_device *); 1049extern void nv04_fb_takedown(struct drm_device *); 1050 1051/* nv10_fb.c */ 1052extern int nv10_fb_init(struct drm_device *); 1053extern void nv10_fb_takedown(struct drm_device *); 1054extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1055 uint32_t addr, uint32_t size, 1056 uint32_t pitch, uint32_t flags); 1057extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1058extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1059 1060/* nv30_fb.c */ 1061extern int nv30_fb_init(struct drm_device *); 1062extern void nv30_fb_takedown(struct drm_device *); 1063extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1064 uint32_t addr, uint32_t size, 1065 uint32_t pitch, uint32_t flags); 1066extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1067 1068/* nv40_fb.c */ 1069extern int nv40_fb_init(struct drm_device *); 1070extern void nv40_fb_takedown(struct drm_device *); 1071extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1072 1073/* nv50_fb.c */ 1074extern int nv50_fb_init(struct drm_device *); 1075extern void nv50_fb_takedown(struct drm_device *); 1076extern void nv50_fb_vm_trap(struct drm_device *, int display); 1077 1078/* nvc0_fb.c */ 1079extern int nvc0_fb_init(struct drm_device *); 1080extern void nvc0_fb_takedown(struct drm_device *); 1081 1082/* nv04_fifo.c */ 1083extern int nv04_fifo_init(struct drm_device *); 1084extern void nv04_fifo_fini(struct drm_device *); 1085extern void nv04_fifo_disable(struct drm_device *); 1086extern void nv04_fifo_enable(struct drm_device *); 1087extern bool nv04_fifo_reassign(struct drm_device *, bool); 1088extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1089extern int nv04_fifo_channel_id(struct drm_device *); 1090extern int nv04_fifo_create_context(struct nouveau_channel *); 1091extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1092extern int nv04_fifo_load_context(struct nouveau_channel *); 1093extern int nv04_fifo_unload_context(struct drm_device *); 1094extern void nv04_fifo_isr(struct drm_device *); 1095 1096/* nv10_fifo.c */ 1097extern int nv10_fifo_init(struct drm_device *); 1098extern int nv10_fifo_channel_id(struct drm_device *); 1099extern int nv10_fifo_create_context(struct nouveau_channel *); 1100extern int nv10_fifo_load_context(struct nouveau_channel *); 1101extern int nv10_fifo_unload_context(struct drm_device *); 1102 1103/* nv40_fifo.c */ 1104extern int nv40_fifo_init(struct drm_device *); 1105extern int nv40_fifo_create_context(struct nouveau_channel *); 1106extern int nv40_fifo_load_context(struct nouveau_channel *); 1107extern int nv40_fifo_unload_context(struct drm_device *); 1108 1109/* nv50_fifo.c */ 1110extern int nv50_fifo_init(struct drm_device *); 1111extern void nv50_fifo_takedown(struct drm_device *); 1112extern int nv50_fifo_channel_id(struct drm_device *); 1113extern int nv50_fifo_create_context(struct nouveau_channel *); 1114extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1115extern int nv50_fifo_load_context(struct nouveau_channel *); 1116extern int nv50_fifo_unload_context(struct drm_device *); 1117extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1118 1119/* nvc0_fifo.c */ 1120extern int nvc0_fifo_init(struct drm_device *); 1121extern void nvc0_fifo_takedown(struct drm_device *); 1122extern void nvc0_fifo_disable(struct drm_device *); 1123extern void nvc0_fifo_enable(struct drm_device *); 1124extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1125extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1126extern int nvc0_fifo_channel_id(struct drm_device *); 1127extern int nvc0_fifo_create_context(struct nouveau_channel *); 1128extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1129extern int nvc0_fifo_load_context(struct nouveau_channel *); 1130extern int nvc0_fifo_unload_context(struct drm_device *); 1131 1132/* nv04_graph.c */ 1133extern int nv04_graph_create(struct drm_device *); 1134extern void nv04_graph_fifo_access(struct drm_device *, bool); 1135extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1136extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1137 u32 class, u32 mthd, u32 data); 1138extern struct nouveau_bitfield nv04_graph_nsource[]; 1139 1140/* nv10_graph.c */ 1141extern int nv10_graph_create(struct drm_device *); 1142extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1143extern struct nouveau_bitfield nv10_graph_intr[]; 1144extern struct nouveau_bitfield nv10_graph_nstatus[]; 1145 1146/* nv20_graph.c */ 1147extern int nv20_graph_create(struct drm_device *); 1148 1149/* nv40_graph.c */ 1150extern int nv40_graph_create(struct drm_device *); 1151extern void nv40_grctx_init(struct nouveau_grctx *); 1152 1153/* nv50_graph.c */ 1154extern int nv50_graph_create(struct drm_device *); 1155extern int nv50_grctx_init(struct nouveau_grctx *); 1156extern struct nouveau_enum nv50_data_error_names[]; 1157extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1158 1159/* nvc0_graph.c */ 1160extern int nvc0_graph_create(struct drm_device *); 1161extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1162 1163/* nv84_crypt.c */ 1164extern int nv84_crypt_create(struct drm_device *); 1165 1166/* nva3_copy.c */ 1167extern int nva3_copy_create(struct drm_device *dev); 1168 1169/* nvc0_copy.c */ 1170extern int nvc0_copy_create(struct drm_device *dev, int engine); 1171 1172/* nv40_mpeg.c */ 1173extern int nv40_mpeg_create(struct drm_device *dev); 1174 1175/* nv50_mpeg.c */ 1176extern int nv50_mpeg_create(struct drm_device *dev); 1177 1178/* nv04_instmem.c */ 1179extern int nv04_instmem_init(struct drm_device *); 1180extern void nv04_instmem_takedown(struct drm_device *); 1181extern int nv04_instmem_suspend(struct drm_device *); 1182extern void nv04_instmem_resume(struct drm_device *); 1183extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1184extern void nv04_instmem_put(struct nouveau_gpuobj *); 1185extern int nv04_instmem_map(struct nouveau_gpuobj *); 1186extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1187extern void nv04_instmem_flush(struct drm_device *); 1188 1189/* nv50_instmem.c */ 1190extern int nv50_instmem_init(struct drm_device *); 1191extern void nv50_instmem_takedown(struct drm_device *); 1192extern int nv50_instmem_suspend(struct drm_device *); 1193extern void nv50_instmem_resume(struct drm_device *); 1194extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1195extern void nv50_instmem_put(struct nouveau_gpuobj *); 1196extern int nv50_instmem_map(struct nouveau_gpuobj *); 1197extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1198extern void nv50_instmem_flush(struct drm_device *); 1199extern void nv84_instmem_flush(struct drm_device *); 1200 1201/* nvc0_instmem.c */ 1202extern int nvc0_instmem_init(struct drm_device *); 1203extern void nvc0_instmem_takedown(struct drm_device *); 1204extern int nvc0_instmem_suspend(struct drm_device *); 1205extern void nvc0_instmem_resume(struct drm_device *); 1206 1207/* nv04_mc.c */ 1208extern int nv04_mc_init(struct drm_device *); 1209extern void nv04_mc_takedown(struct drm_device *); 1210 1211/* nv40_mc.c */ 1212extern int nv40_mc_init(struct drm_device *); 1213extern void nv40_mc_takedown(struct drm_device *); 1214 1215/* nv50_mc.c */ 1216extern int nv50_mc_init(struct drm_device *); 1217extern void nv50_mc_takedown(struct drm_device *); 1218 1219/* nv04_timer.c */ 1220extern int nv04_timer_init(struct drm_device *); 1221extern uint64_t nv04_timer_read(struct drm_device *); 1222extern void nv04_timer_takedown(struct drm_device *); 1223 1224extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1225 unsigned long arg); 1226 1227/* nv04_dac.c */ 1228extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1229extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1230extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1231extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1232extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1233 1234/* nv04_dfp.c */ 1235extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1236extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1237extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1238 int head, bool dl); 1239extern void nv04_dfp_disable(struct drm_device *dev, int head); 1240extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1241 1242/* nv04_tv.c */ 1243extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1244extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1245 1246/* nv17_tv.c */ 1247extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1248 1249/* nv04_display.c */ 1250extern int nv04_display_early_init(struct drm_device *); 1251extern void nv04_display_late_takedown(struct drm_device *); 1252extern int nv04_display_create(struct drm_device *); 1253extern int nv04_display_init(struct drm_device *); 1254extern void nv04_display_destroy(struct drm_device *); 1255 1256/* nv04_crtc.c */ 1257extern int nv04_crtc_create(struct drm_device *, int index); 1258 1259/* nouveau_bo.c */ 1260extern struct ttm_bo_driver nouveau_bo_driver; 1261extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1262 int size, int align, uint32_t flags, 1263 uint32_t tile_mode, uint32_t tile_flags, 1264 struct nouveau_bo **); 1265extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1266extern int nouveau_bo_unpin(struct nouveau_bo *); 1267extern int nouveau_bo_map(struct nouveau_bo *); 1268extern void nouveau_bo_unmap(struct nouveau_bo *); 1269extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1270 uint32_t busy); 1271extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1272extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1273extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1274extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1275extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1276extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1277 bool no_wait_reserve, bool no_wait_gpu); 1278 1279/* nouveau_fence.c */ 1280struct nouveau_fence; 1281extern int nouveau_fence_init(struct drm_device *); 1282extern void nouveau_fence_fini(struct drm_device *); 1283extern int nouveau_fence_channel_init(struct nouveau_channel *); 1284extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1285extern void nouveau_fence_update(struct nouveau_channel *); 1286extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1287 bool emit); 1288extern int nouveau_fence_emit(struct nouveau_fence *); 1289extern void nouveau_fence_work(struct nouveau_fence *fence, 1290 void (*work)(void *priv, bool signalled), 1291 void *priv); 1292struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1293 1294extern bool __nouveau_fence_signalled(void *obj, void *arg); 1295extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1296extern int __nouveau_fence_flush(void *obj, void *arg); 1297extern void __nouveau_fence_unref(void **obj); 1298extern void *__nouveau_fence_ref(void *obj); 1299 1300static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1301{ 1302 return __nouveau_fence_signalled(obj, NULL); 1303} 1304static inline int 1305nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1306{ 1307 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1308} 1309extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1310static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1311{ 1312 return __nouveau_fence_flush(obj, NULL); 1313} 1314static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1315{ 1316 __nouveau_fence_unref((void **)obj); 1317} 1318static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1319{ 1320 return __nouveau_fence_ref(obj); 1321} 1322 1323/* nouveau_gem.c */ 1324extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1325 int size, int align, uint32_t domain, 1326 uint32_t tile_mode, uint32_t tile_flags, 1327 struct nouveau_bo **); 1328extern int nouveau_gem_object_new(struct drm_gem_object *); 1329extern void nouveau_gem_object_del(struct drm_gem_object *); 1330extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1331 struct drm_file *); 1332extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1333 struct drm_file *); 1334extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1335 struct drm_file *); 1336extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1337 struct drm_file *); 1338extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1339 struct drm_file *); 1340 1341/* nouveau_display.c */ 1342int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1343void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1344int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1345 struct drm_pending_vblank_event *event); 1346int nouveau_finish_page_flip(struct nouveau_channel *, 1347 struct nouveau_page_flip_state *); 1348 1349/* nv10_gpio.c */ 1350int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1351int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1352 1353/* nv50_gpio.c */ 1354int nv50_gpio_init(struct drm_device *dev); 1355void nv50_gpio_fini(struct drm_device *dev); 1356int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1357int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1358int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1359 void (*)(void *, int), void *); 1360void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1361 void (*)(void *, int), void *); 1362bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1363 1364/* nv50_calc. */ 1365int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1366 int *N1, int *M1, int *N2, int *M2, int *P); 1367int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1368 int clk, int *N, int *fN, int *M, int *P); 1369 1370#ifndef ioread32_native 1371#ifdef __BIG_ENDIAN 1372#define ioread16_native ioread16be 1373#define iowrite16_native iowrite16be 1374#define ioread32_native ioread32be 1375#define iowrite32_native iowrite32be 1376#else /* def __BIG_ENDIAN */ 1377#define ioread16_native ioread16 1378#define iowrite16_native iowrite16 1379#define ioread32_native ioread32 1380#define iowrite32_native iowrite32 1381#endif /* def __BIG_ENDIAN else */ 1382#endif /* !ioread32_native */ 1383 1384/* channel control reg access */ 1385static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1386{ 1387 return ioread32_native(chan->user + reg); 1388} 1389 1390static inline void nvchan_wr32(struct nouveau_channel *chan, 1391 unsigned reg, u32 val) 1392{ 1393 iowrite32_native(val, chan->user + reg); 1394} 1395 1396/* register access */ 1397static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1398{ 1399 struct drm_nouveau_private *dev_priv = dev->dev_private; 1400 return ioread32_native(dev_priv->mmio + reg); 1401} 1402 1403static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1404{ 1405 struct drm_nouveau_private *dev_priv = dev->dev_private; 1406 iowrite32_native(val, dev_priv->mmio + reg); 1407} 1408 1409static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1410{ 1411 u32 tmp = nv_rd32(dev, reg); 1412 nv_wr32(dev, reg, (tmp & ~mask) | val); 1413 return tmp; 1414} 1415 1416static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1417{ 1418 struct drm_nouveau_private *dev_priv = dev->dev_private; 1419 return ioread8(dev_priv->mmio + reg); 1420} 1421 1422static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1423{ 1424 struct drm_nouveau_private *dev_priv = dev->dev_private; 1425 iowrite8(val, dev_priv->mmio + reg); 1426} 1427 1428#define nv_wait(dev, reg, mask, val) \ 1429 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1430#define nv_wait_ne(dev, reg, mask, val) \ 1431 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1432 1433/* PRAMIN access */ 1434static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1435{ 1436 struct drm_nouveau_private *dev_priv = dev->dev_private; 1437 return ioread32_native(dev_priv->ramin + offset); 1438} 1439 1440static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1441{ 1442 struct drm_nouveau_private *dev_priv = dev->dev_private; 1443 iowrite32_native(val, dev_priv->ramin + offset); 1444} 1445 1446/* object access */ 1447extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1448extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1449 1450/* 1451 * Logging 1452 * Argument d is (struct drm_device *). 1453 */ 1454#define NV_PRINTK(level, d, fmt, arg...) \ 1455 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1456 pci_name(d->pdev), ##arg) 1457#ifndef NV_DEBUG_NOTRACE 1458#define NV_DEBUG(d, fmt, arg...) do { \ 1459 if (drm_debug & DRM_UT_DRIVER) { \ 1460 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1461 __LINE__, ##arg); \ 1462 } \ 1463} while (0) 1464#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1465 if (drm_debug & DRM_UT_KMS) { \ 1466 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1467 __LINE__, ##arg); \ 1468 } \ 1469} while (0) 1470#else 1471#define NV_DEBUG(d, fmt, arg...) do { \ 1472 if (drm_debug & DRM_UT_DRIVER) \ 1473 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1474} while (0) 1475#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1476 if (drm_debug & DRM_UT_KMS) \ 1477 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1478} while (0) 1479#endif 1480#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1481#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1482#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1483#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1484#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1485 1486/* nouveau_reg_debug bitmask */ 1487enum { 1488 NOUVEAU_REG_DEBUG_MC = 0x1, 1489 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1490 NOUVEAU_REG_DEBUG_FB = 0x4, 1491 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1492 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1493 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1494 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1495 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1496 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1497 NOUVEAU_REG_DEBUG_EVO = 0x200, 1498}; 1499 1500#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1501 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1502 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1503} while (0) 1504 1505static inline bool 1506nv_two_heads(struct drm_device *dev) 1507{ 1508 struct drm_nouveau_private *dev_priv = dev->dev_private; 1509 const int impl = dev->pci_device & 0x0ff0; 1510 1511 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1512 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1513 return true; 1514 1515 return false; 1516} 1517 1518static inline bool 1519nv_gf4_disp_arch(struct drm_device *dev) 1520{ 1521 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1522} 1523 1524static inline bool 1525nv_two_reg_pll(struct drm_device *dev) 1526{ 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 const int impl = dev->pci_device & 0x0ff0; 1529 1530 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1531 return true; 1532 return false; 1533} 1534 1535static inline bool 1536nv_match_device(struct drm_device *dev, unsigned device, 1537 unsigned sub_vendor, unsigned sub_device) 1538{ 1539 return dev->pdev->device == device && 1540 dev->pdev->subsystem_vendor == sub_vendor && 1541 dev->pdev->subsystem_device == sub_device; 1542} 1543 1544static inline void * 1545nv_engine(struct drm_device *dev, int engine) 1546{ 1547 struct drm_nouveau_private *dev_priv = dev->dev_private; 1548 return (void *)dev_priv->eng[engine]; 1549} 1550 1551/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1552 * helpful to determine a number of other hardware features 1553 */ 1554static inline int 1555nv44_graph_class(struct drm_device *dev) 1556{ 1557 struct drm_nouveau_private *dev_priv = dev->dev_private; 1558 1559 if ((dev_priv->chipset & 0xf0) == 0x60) 1560 return 1; 1561 1562 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1563} 1564 1565/* memory type/access flags, do not match hardware values */ 1566#define NV_MEM_ACCESS_RO 1 1567#define NV_MEM_ACCESS_WO 2 1568#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1569#define NV_MEM_ACCESS_SYS 4 1570#define NV_MEM_ACCESS_VM 8 1571 1572#define NV_MEM_TARGET_VRAM 0 1573#define NV_MEM_TARGET_PCI 1 1574#define NV_MEM_TARGET_PCI_NOSNOOP 2 1575#define NV_MEM_TARGET_VM 3 1576#define NV_MEM_TARGET_GART 4 1577 1578#define NV_MEM_TYPE_VM 0x7f 1579#define NV_MEM_COMP_VM 0x03 1580 1581/* NV_SW object class */ 1582#define NV_SW 0x0000506e 1583#define NV_SW_DMA_SEMAPHORE 0x00000060 1584#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1585#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1586#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1587#define NV_SW_YIELD 0x00000080 1588#define NV_SW_DMA_VBLSEM 0x0000018c 1589#define NV_SW_VBLSEM_OFFSET 0x00000400 1590#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1591#define NV_SW_VBLSEM_RELEASE 0x00000408 1592#define NV_SW_PAGE_FLIP 0x00000500 1593 1594#endif /* __NOUVEAU_DRV_H__ */ 1595