nouveau_drv.h revision 415e6186f17136075f7cc825ba3835d005773637
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 138#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 139#define NVOBJ_FLAG_FAKE (1 << 3) 140struct nouveau_gpuobj { 141 struct list_head list; 142 143 struct nouveau_channel *im_channel; 144 struct drm_mm_node *im_pramin; 145 struct nouveau_bo *im_backing; 146 uint32_t im_backing_start; 147 uint32_t *im_backing_suspend; 148 int im_bound; 149 150 uint32_t flags; 151 int refcount; 152 153 uint32_t engine; 154 uint32_t class; 155 156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 157 void *priv; 158}; 159 160struct nouveau_gpuobj_ref { 161 struct list_head list; 162 163 struct nouveau_gpuobj *gpuobj; 164 uint32_t instance; 165 166 struct nouveau_channel *channel; 167 int handle; 168}; 169 170struct nouveau_channel { 171 struct drm_device *dev; 172 int id; 173 174 /* owner of this fifo */ 175 struct drm_file *file_priv; 176 /* mapping of the fifo itself */ 177 struct drm_local_map *map; 178 179 /* mapping of the regs controling the fifo */ 180 void __iomem *user; 181 uint32_t user_get; 182 uint32_t user_put; 183 184 /* Fencing */ 185 struct { 186 /* lock protects the pending list only */ 187 spinlock_t lock; 188 struct list_head pending; 189 uint32_t sequence; 190 uint32_t sequence_ack; 191 atomic_t last_sequence_irq; 192 } fence; 193 194 /* DMA push buffer */ 195 struct nouveau_gpuobj_ref *pushbuf; 196 struct nouveau_bo *pushbuf_bo; 197 uint32_t pushbuf_base; 198 199 /* Notifier memory */ 200 struct nouveau_bo *notifier_bo; 201 struct drm_mm notifier_heap; 202 203 /* PFIFO context */ 204 struct nouveau_gpuobj_ref *ramfc; 205 struct nouveau_gpuobj_ref *cache; 206 207 /* PGRAPH context */ 208 /* XXX may be merge 2 pointers as private data ??? */ 209 struct nouveau_gpuobj_ref *ramin_grctx; 210 void *pgraph_ctx; 211 212 /* NV50 VM */ 213 struct nouveau_gpuobj *vm_pd; 214 struct nouveau_gpuobj_ref *vm_gart_pt; 215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 216 217 /* Objects */ 218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 221 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 222 223 /* GPU object info for stuff used in-kernel (mm_enabled) */ 224 uint32_t m2mf_ntfy; 225 uint32_t vram_handle; 226 uint32_t gart_handle; 227 bool accel_done; 228 229 /* Push buffer state (only for drm's channel on !mm_enabled) */ 230 struct { 231 int max; 232 int free; 233 int cur; 234 int put; 235 /* access via pushbuf_bo */ 236 237 int ib_base; 238 int ib_max; 239 int ib_free; 240 int ib_put; 241 } dma; 242 243 uint32_t sw_subchannel[8]; 244 245 struct { 246 struct nouveau_gpuobj *vblsem; 247 uint32_t vblsem_offset; 248 uint32_t vblsem_rval; 249 struct list_head vbl_wait; 250 } nvsw; 251 252 struct { 253 bool active; 254 char name[32]; 255 struct drm_info_list info; 256 } debugfs; 257}; 258 259struct nouveau_instmem_engine { 260 void *priv; 261 262 int (*init)(struct drm_device *dev); 263 void (*takedown)(struct drm_device *dev); 264 int (*suspend)(struct drm_device *dev); 265 void (*resume)(struct drm_device *dev); 266 267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 268 uint32_t *size); 269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 272 void (*flush)(struct drm_device *); 273}; 274 275struct nouveau_mc_engine { 276 int (*init)(struct drm_device *dev); 277 void (*takedown)(struct drm_device *dev); 278}; 279 280struct nouveau_timer_engine { 281 int (*init)(struct drm_device *dev); 282 void (*takedown)(struct drm_device *dev); 283 uint64_t (*read)(struct drm_device *dev); 284}; 285 286struct nouveau_fb_engine { 287 int num_tiles; 288 289 int (*init)(struct drm_device *dev); 290 void (*takedown)(struct drm_device *dev); 291 292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 293 uint32_t size, uint32_t pitch); 294}; 295 296struct nouveau_fifo_engine { 297 int channels; 298 299 struct nouveau_gpuobj_ref *playlist[2]; 300 int cur_playlist; 301 302 int (*init)(struct drm_device *); 303 void (*takedown)(struct drm_device *); 304 305 void (*disable)(struct drm_device *); 306 void (*enable)(struct drm_device *); 307 bool (*reassign)(struct drm_device *, bool enable); 308 bool (*cache_flush)(struct drm_device *dev); 309 bool (*cache_pull)(struct drm_device *dev, bool enable); 310 311 int (*channel_id)(struct drm_device *); 312 313 int (*create_context)(struct nouveau_channel *); 314 void (*destroy_context)(struct nouveau_channel *); 315 int (*load_context)(struct nouveau_channel *); 316 int (*unload_context)(struct drm_device *); 317}; 318 319struct nouveau_pgraph_object_method { 320 int id; 321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 322 uint32_t data); 323}; 324 325struct nouveau_pgraph_object_class { 326 int id; 327 bool software; 328 struct nouveau_pgraph_object_method *methods; 329}; 330 331struct nouveau_pgraph_engine { 332 struct nouveau_pgraph_object_class *grclass; 333 bool accel_blocked; 334 int grctx_size; 335 336 /* NV2x/NV3x context table (0x400780) */ 337 struct nouveau_gpuobj_ref *ctx_table; 338 339 int (*init)(struct drm_device *); 340 void (*takedown)(struct drm_device *); 341 342 void (*fifo_access)(struct drm_device *, bool); 343 344 struct nouveau_channel *(*channel)(struct drm_device *); 345 int (*create_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *); 348 int (*unload_context)(struct drm_device *); 349 350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 351 uint32_t size, uint32_t pitch); 352}; 353 354struct nouveau_display_engine { 355 int (*early_init)(struct drm_device *); 356 void (*late_takedown)(struct drm_device *); 357 int (*create)(struct drm_device *); 358 int (*init)(struct drm_device *); 359 void (*destroy)(struct drm_device *); 360}; 361 362struct nouveau_gpio_engine { 363 int (*init)(struct drm_device *); 364 void (*takedown)(struct drm_device *); 365 366 int (*get)(struct drm_device *, enum dcb_gpio_tag); 367 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 368 369 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 370}; 371 372struct nouveau_engine { 373 struct nouveau_instmem_engine instmem; 374 struct nouveau_mc_engine mc; 375 struct nouveau_timer_engine timer; 376 struct nouveau_fb_engine fb; 377 struct nouveau_pgraph_engine graph; 378 struct nouveau_fifo_engine fifo; 379 struct nouveau_display_engine display; 380 struct nouveau_gpio_engine gpio; 381}; 382 383struct nouveau_pll_vals { 384 union { 385 struct { 386#ifdef __BIG_ENDIAN 387 uint8_t N1, M1, N2, M2; 388#else 389 uint8_t M1, N1, M2, N2; 390#endif 391 }; 392 struct { 393 uint16_t NM1, NM2; 394 } __attribute__((packed)); 395 }; 396 int log2P; 397 398 int refclk; 399}; 400 401enum nv04_fp_display_regs { 402 FP_DISPLAY_END, 403 FP_TOTAL, 404 FP_CRTC, 405 FP_SYNC_START, 406 FP_SYNC_END, 407 FP_VALID_START, 408 FP_VALID_END 409}; 410 411struct nv04_crtc_reg { 412 unsigned char MiscOutReg; /* */ 413 uint8_t CRTC[0xa0]; 414 uint8_t CR58[0x10]; 415 uint8_t Sequencer[5]; 416 uint8_t Graphics[9]; 417 uint8_t Attribute[21]; 418 unsigned char DAC[768]; /* Internal Colorlookuptable */ 419 420 /* PCRTC regs */ 421 uint32_t fb_start; 422 uint32_t crtc_cfg; 423 uint32_t cursor_cfg; 424 uint32_t gpio_ext; 425 uint32_t crtc_830; 426 uint32_t crtc_834; 427 uint32_t crtc_850; 428 uint32_t crtc_eng_ctrl; 429 430 /* PRAMDAC regs */ 431 uint32_t nv10_cursync; 432 struct nouveau_pll_vals pllvals; 433 uint32_t ramdac_gen_ctrl; 434 uint32_t ramdac_630; 435 uint32_t ramdac_634; 436 uint32_t tv_setup; 437 uint32_t tv_vtotal; 438 uint32_t tv_vskew; 439 uint32_t tv_vsync_delay; 440 uint32_t tv_htotal; 441 uint32_t tv_hskew; 442 uint32_t tv_hsync_delay; 443 uint32_t tv_hsync_delay2; 444 uint32_t fp_horiz_regs[7]; 445 uint32_t fp_vert_regs[7]; 446 uint32_t dither; 447 uint32_t fp_control; 448 uint32_t dither_regs[6]; 449 uint32_t fp_debug_0; 450 uint32_t fp_debug_1; 451 uint32_t fp_debug_2; 452 uint32_t fp_margin_color; 453 uint32_t ramdac_8c0; 454 uint32_t ramdac_a20; 455 uint32_t ramdac_a24; 456 uint32_t ramdac_a34; 457 uint32_t ctv_regs[38]; 458}; 459 460struct nv04_output_reg { 461 uint32_t output; 462 int head; 463}; 464 465struct nv04_mode_state { 466 uint32_t bpp; 467 uint32_t width; 468 uint32_t height; 469 uint32_t interlace; 470 uint32_t repaint0; 471 uint32_t repaint1; 472 uint32_t screen; 473 uint32_t scale; 474 uint32_t dither; 475 uint32_t extra; 476 uint32_t fifo; 477 uint32_t pixel; 478 uint32_t horiz; 479 int arbitration0; 480 int arbitration1; 481 uint32_t pll; 482 uint32_t pllB; 483 uint32_t vpll; 484 uint32_t vpll2; 485 uint32_t vpllB; 486 uint32_t vpll2B; 487 uint32_t pllsel; 488 uint32_t sel_clk; 489 uint32_t general; 490 uint32_t crtcOwner; 491 uint32_t head; 492 uint32_t head2; 493 uint32_t cursorConfig; 494 uint32_t cursor0; 495 uint32_t cursor1; 496 uint32_t cursor2; 497 uint32_t timingH; 498 uint32_t timingV; 499 uint32_t displayV; 500 uint32_t crtcSync; 501 502 struct nv04_crtc_reg crtc_reg[2]; 503}; 504 505enum nouveau_card_type { 506 NV_04 = 0x00, 507 NV_10 = 0x10, 508 NV_20 = 0x20, 509 NV_30 = 0x30, 510 NV_40 = 0x40, 511 NV_50 = 0x50, 512 NV_C0 = 0xc0, 513}; 514 515struct drm_nouveau_private { 516 struct drm_device *dev; 517 518 /* the card type, takes NV_* as values */ 519 enum nouveau_card_type card_type; 520 /* exact chipset, derived from NV_PMC_BOOT_0 */ 521 int chipset; 522 int flags; 523 524 void __iomem *mmio; 525 void __iomem *ramin; 526 uint32_t ramin_size; 527 528 struct nouveau_bo *vga_ram; 529 530 struct workqueue_struct *wq; 531 struct work_struct irq_work; 532 struct work_struct hpd_work; 533 534 struct list_head vbl_waiting; 535 536 struct { 537 struct drm_global_reference mem_global_ref; 538 struct ttm_bo_global_ref bo_global_ref; 539 struct ttm_bo_device bdev; 540 atomic_t validate_sequence; 541 } ttm; 542 543 int fifo_alloc_count; 544 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 545 546 struct nouveau_engine engine; 547 struct nouveau_channel *channel; 548 549 /* For PFIFO and PGRAPH. */ 550 spinlock_t context_switch_lock; 551 552 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 553 struct nouveau_gpuobj *ramht; 554 uint32_t ramin_rsvd_vram; 555 uint32_t ramht_offset; 556 uint32_t ramht_size; 557 uint32_t ramht_bits; 558 uint32_t ramfc_offset; 559 uint32_t ramfc_size; 560 uint32_t ramro_offset; 561 uint32_t ramro_size; 562 563 struct { 564 enum { 565 NOUVEAU_GART_NONE = 0, 566 NOUVEAU_GART_AGP, 567 NOUVEAU_GART_SGDMA 568 } type; 569 uint64_t aper_base; 570 uint64_t aper_size; 571 uint64_t aper_free; 572 573 struct nouveau_gpuobj *sg_ctxdma; 574 struct page *sg_dummy_page; 575 dma_addr_t sg_dummy_bus; 576 } gart_info; 577 578 /* nv10-nv40 tiling regions */ 579 struct { 580 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 581 spinlock_t lock; 582 } tile; 583 584 /* VRAM/fb configuration */ 585 uint64_t vram_size; 586 uint64_t vram_sys_base; 587 588 uint64_t fb_phys; 589 uint64_t fb_available_size; 590 uint64_t fb_mappable_pages; 591 uint64_t fb_aper_free; 592 int fb_mtrr; 593 594 /* G8x/G9x virtual address space */ 595 uint64_t vm_gart_base; 596 uint64_t vm_gart_size; 597 uint64_t vm_vram_base; 598 uint64_t vm_vram_size; 599 uint64_t vm_end; 600 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 601 int vm_vram_pt_nr; 602 603 struct drm_mm ramin_heap; 604 605 struct list_head gpuobj_list; 606 607 struct nvbios vbios; 608 609 struct nv04_mode_state mode_reg; 610 struct nv04_mode_state saved_reg; 611 uint32_t saved_vga_font[4][16384]; 612 uint32_t crtc_owner; 613 uint32_t dac_users[4]; 614 615 struct nouveau_suspend_resume { 616 uint32_t *ramin_copy; 617 } susres; 618 619 struct backlight_device *backlight; 620 621 struct nouveau_channel *evo; 622 struct { 623 struct dcb_entry *dcb; 624 u16 script; 625 u32 pclk; 626 } evo_irq; 627 628 struct { 629 struct dentry *channel_root; 630 } debugfs; 631 632 struct nouveau_fbdev *nfbdev; 633 struct apertures_struct *apertures; 634}; 635 636static inline struct drm_nouveau_private * 637nouveau_bdev(struct ttm_bo_device *bd) 638{ 639 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 640} 641 642static inline int 643nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 644{ 645 struct nouveau_bo *prev; 646 647 if (!pnvbo) 648 return -EINVAL; 649 prev = *pnvbo; 650 651 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 652 if (prev) { 653 struct ttm_buffer_object *bo = &prev->bo; 654 655 ttm_bo_unref(&bo); 656 } 657 658 return 0; 659} 660 661#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 662 struct drm_nouveau_private *nv = dev->dev_private; \ 663 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 664 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 665 DRM_CURRENTPID, (id)); \ 666 return -EPERM; \ 667 } \ 668 (ch) = nv->fifos[(id)]; \ 669} while (0) 670 671/* nouveau_drv.c */ 672extern int nouveau_noagp; 673extern int nouveau_duallink; 674extern int nouveau_uscript_lvds; 675extern int nouveau_uscript_tmds; 676extern int nouveau_vram_pushbuf; 677extern int nouveau_vram_notify; 678extern int nouveau_fbpercrtc; 679extern int nouveau_tv_disable; 680extern char *nouveau_tv_norm; 681extern int nouveau_reg_debug; 682extern char *nouveau_vbios; 683extern int nouveau_ignorelid; 684extern int nouveau_nofbaccel; 685extern int nouveau_noaccel; 686extern int nouveau_override_conntype; 687 688extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 689extern int nouveau_pci_resume(struct pci_dev *pdev); 690 691/* nouveau_state.c */ 692extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 693extern int nouveau_load(struct drm_device *, unsigned long flags); 694extern int nouveau_firstopen(struct drm_device *); 695extern void nouveau_lastclose(struct drm_device *); 696extern int nouveau_unload(struct drm_device *); 697extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 698 struct drm_file *); 699extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 700 struct drm_file *); 701extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 702 uint32_t reg, uint32_t mask, uint32_t val); 703extern bool nouveau_wait_for_idle(struct drm_device *); 704extern int nouveau_card_init(struct drm_device *); 705 706/* nouveau_mem.c */ 707extern int nouveau_mem_detect(struct drm_device *dev); 708extern int nouveau_mem_init(struct drm_device *); 709extern int nouveau_mem_init_agp(struct drm_device *); 710extern int nouveau_mem_reset_agp(struct drm_device *); 711extern void nouveau_mem_close(struct drm_device *); 712extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 713 uint32_t addr, 714 uint32_t size, 715 uint32_t pitch); 716extern void nv10_mem_expire_tiling(struct drm_device *dev, 717 struct nouveau_tile_reg *tile, 718 struct nouveau_fence *fence); 719extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 720 uint32_t size, uint32_t flags, 721 uint64_t phys); 722extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 723 uint32_t size); 724 725/* nouveau_notifier.c */ 726extern int nouveau_notifier_init_channel(struct nouveau_channel *); 727extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 728extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 729 int cout, uint32_t *offset); 730extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 731extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 732 struct drm_file *); 733extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 734 struct drm_file *); 735 736/* nouveau_channel.c */ 737extern struct drm_ioctl_desc nouveau_ioctls[]; 738extern int nouveau_max_ioctl; 739extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 740extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 741 int channel); 742extern int nouveau_channel_alloc(struct drm_device *dev, 743 struct nouveau_channel **chan, 744 struct drm_file *file_priv, 745 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 746extern void nouveau_channel_free(struct nouveau_channel *); 747 748/* nouveau_object.c */ 749extern int nouveau_gpuobj_early_init(struct drm_device *); 750extern int nouveau_gpuobj_init(struct drm_device *); 751extern void nouveau_gpuobj_takedown(struct drm_device *); 752extern void nouveau_gpuobj_late_takedown(struct drm_device *); 753extern int nouveau_gpuobj_suspend(struct drm_device *dev); 754extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 755extern void nouveau_gpuobj_resume(struct drm_device *dev); 756extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 757 uint32_t vram_h, uint32_t tt_h); 758extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 759extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 760 uint32_t size, int align, uint32_t flags, 761 struct nouveau_gpuobj **); 762extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 763extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 764 uint32_t handle, struct nouveau_gpuobj *, 765 struct nouveau_gpuobj_ref **); 766extern int nouveau_gpuobj_ref_del(struct drm_device *, 767 struct nouveau_gpuobj_ref **); 768extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 769 struct nouveau_gpuobj_ref **ref_ret); 770extern int nouveau_gpuobj_new_ref(struct drm_device *, 771 struct nouveau_channel *alloc_chan, 772 struct nouveau_channel *ref_chan, 773 uint32_t handle, uint32_t size, int align, 774 uint32_t flags, struct nouveau_gpuobj_ref **); 775extern int nouveau_gpuobj_new_fake(struct drm_device *, 776 uint32_t p_offset, uint32_t b_offset, 777 uint32_t size, uint32_t flags, 778 struct nouveau_gpuobj **, 779 struct nouveau_gpuobj_ref**); 780extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 781 uint64_t offset, uint64_t size, int access, 782 int target, struct nouveau_gpuobj **); 783extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 784 uint64_t offset, uint64_t size, 785 int access, struct nouveau_gpuobj **, 786 uint32_t *o_ret); 787extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 788 struct nouveau_gpuobj **); 789extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 790 struct nouveau_gpuobj **); 791extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 792 struct drm_file *); 793extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 794 struct drm_file *); 795 796/* nouveau_irq.c */ 797extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 798extern void nouveau_irq_preinstall(struct drm_device *); 799extern int nouveau_irq_postinstall(struct drm_device *); 800extern void nouveau_irq_uninstall(struct drm_device *); 801 802/* nouveau_sgdma.c */ 803extern int nouveau_sgdma_init(struct drm_device *); 804extern void nouveau_sgdma_takedown(struct drm_device *); 805extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 806 uint32_t *page); 807extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 808 809/* nouveau_debugfs.c */ 810#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 811extern int nouveau_debugfs_init(struct drm_minor *); 812extern void nouveau_debugfs_takedown(struct drm_minor *); 813extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 814extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 815#else 816static inline int 817nouveau_debugfs_init(struct drm_minor *minor) 818{ 819 return 0; 820} 821 822static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 823{ 824} 825 826static inline int 827nouveau_debugfs_channel_init(struct nouveau_channel *chan) 828{ 829 return 0; 830} 831 832static inline void 833nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 834{ 835} 836#endif 837 838/* nouveau_dma.c */ 839extern void nouveau_dma_pre_init(struct nouveau_channel *); 840extern int nouveau_dma_init(struct nouveau_channel *); 841extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 842 843/* nouveau_acpi.c */ 844#define ROM_BIOS_PAGE 4096 845#if defined(CONFIG_ACPI) 846void nouveau_register_dsm_handler(void); 847void nouveau_unregister_dsm_handler(void); 848int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 849bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 850int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 851#else 852static inline void nouveau_register_dsm_handler(void) {} 853static inline void nouveau_unregister_dsm_handler(void) {} 854static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 855static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 856static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 857#endif 858 859/* nouveau_backlight.c */ 860#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 861extern int nouveau_backlight_init(struct drm_device *); 862extern void nouveau_backlight_exit(struct drm_device *); 863#else 864static inline int nouveau_backlight_init(struct drm_device *dev) 865{ 866 return 0; 867} 868 869static inline void nouveau_backlight_exit(struct drm_device *dev) { } 870#endif 871 872/* nouveau_bios.c */ 873extern int nouveau_bios_init(struct drm_device *); 874extern void nouveau_bios_takedown(struct drm_device *dev); 875extern int nouveau_run_vbios_init(struct drm_device *); 876extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 877 struct dcb_entry *); 878extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 879 enum dcb_gpio_tag); 880extern struct dcb_connector_table_entry * 881nouveau_bios_connector_entry(struct drm_device *, int index); 882extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 883 struct pll_lims *); 884extern int nouveau_bios_run_display_table(struct drm_device *, 885 struct dcb_entry *, 886 uint32_t script, int pxclk); 887extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 888 int *length); 889extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 890extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 891extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 892 bool *dl, bool *if_is_24bit); 893extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 894 int head, int pxclk); 895extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 896 enum LVDS_script, int pxclk); 897 898/* nouveau_ttm.c */ 899int nouveau_ttm_global_init(struct drm_nouveau_private *); 900void nouveau_ttm_global_release(struct drm_nouveau_private *); 901int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 902 903/* nouveau_dp.c */ 904int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 905 uint8_t *data, int data_nr); 906bool nouveau_dp_detect(struct drm_encoder *); 907bool nouveau_dp_link_train(struct drm_encoder *); 908 909/* nv04_fb.c */ 910extern int nv04_fb_init(struct drm_device *); 911extern void nv04_fb_takedown(struct drm_device *); 912 913/* nv10_fb.c */ 914extern int nv10_fb_init(struct drm_device *); 915extern void nv10_fb_takedown(struct drm_device *); 916extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 917 uint32_t, uint32_t); 918 919/* nv30_fb.c */ 920extern int nv30_fb_init(struct drm_device *); 921extern void nv30_fb_takedown(struct drm_device *); 922 923/* nv40_fb.c */ 924extern int nv40_fb_init(struct drm_device *); 925extern void nv40_fb_takedown(struct drm_device *); 926extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 927 uint32_t, uint32_t); 928 929/* nv50_fb.c */ 930extern int nv50_fb_init(struct drm_device *); 931extern void nv50_fb_takedown(struct drm_device *); 932 933/* nvc0_fb.c */ 934extern int nvc0_fb_init(struct drm_device *); 935extern void nvc0_fb_takedown(struct drm_device *); 936 937/* nv04_fifo.c */ 938extern int nv04_fifo_init(struct drm_device *); 939extern void nv04_fifo_disable(struct drm_device *); 940extern void nv04_fifo_enable(struct drm_device *); 941extern bool nv04_fifo_reassign(struct drm_device *, bool); 942extern bool nv04_fifo_cache_flush(struct drm_device *); 943extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 944extern int nv04_fifo_channel_id(struct drm_device *); 945extern int nv04_fifo_create_context(struct nouveau_channel *); 946extern void nv04_fifo_destroy_context(struct nouveau_channel *); 947extern int nv04_fifo_load_context(struct nouveau_channel *); 948extern int nv04_fifo_unload_context(struct drm_device *); 949 950/* nv10_fifo.c */ 951extern int nv10_fifo_init(struct drm_device *); 952extern int nv10_fifo_channel_id(struct drm_device *); 953extern int nv10_fifo_create_context(struct nouveau_channel *); 954extern void nv10_fifo_destroy_context(struct nouveau_channel *); 955extern int nv10_fifo_load_context(struct nouveau_channel *); 956extern int nv10_fifo_unload_context(struct drm_device *); 957 958/* nv40_fifo.c */ 959extern int nv40_fifo_init(struct drm_device *); 960extern int nv40_fifo_create_context(struct nouveau_channel *); 961extern void nv40_fifo_destroy_context(struct nouveau_channel *); 962extern int nv40_fifo_load_context(struct nouveau_channel *); 963extern int nv40_fifo_unload_context(struct drm_device *); 964 965/* nv50_fifo.c */ 966extern int nv50_fifo_init(struct drm_device *); 967extern void nv50_fifo_takedown(struct drm_device *); 968extern int nv50_fifo_channel_id(struct drm_device *); 969extern int nv50_fifo_create_context(struct nouveau_channel *); 970extern void nv50_fifo_destroy_context(struct nouveau_channel *); 971extern int nv50_fifo_load_context(struct nouveau_channel *); 972extern int nv50_fifo_unload_context(struct drm_device *); 973 974/* nvc0_fifo.c */ 975extern int nvc0_fifo_init(struct drm_device *); 976extern void nvc0_fifo_takedown(struct drm_device *); 977extern void nvc0_fifo_disable(struct drm_device *); 978extern void nvc0_fifo_enable(struct drm_device *); 979extern bool nvc0_fifo_reassign(struct drm_device *, bool); 980extern bool nvc0_fifo_cache_flush(struct drm_device *); 981extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 982extern int nvc0_fifo_channel_id(struct drm_device *); 983extern int nvc0_fifo_create_context(struct nouveau_channel *); 984extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 985extern int nvc0_fifo_load_context(struct nouveau_channel *); 986extern int nvc0_fifo_unload_context(struct drm_device *); 987 988/* nv04_graph.c */ 989extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 990extern int nv04_graph_init(struct drm_device *); 991extern void nv04_graph_takedown(struct drm_device *); 992extern void nv04_graph_fifo_access(struct drm_device *, bool); 993extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 994extern int nv04_graph_create_context(struct nouveau_channel *); 995extern void nv04_graph_destroy_context(struct nouveau_channel *); 996extern int nv04_graph_load_context(struct nouveau_channel *); 997extern int nv04_graph_unload_context(struct drm_device *); 998extern void nv04_graph_context_switch(struct drm_device *); 999 1000/* nv10_graph.c */ 1001extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1002extern int nv10_graph_init(struct drm_device *); 1003extern void nv10_graph_takedown(struct drm_device *); 1004extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1005extern int nv10_graph_create_context(struct nouveau_channel *); 1006extern void nv10_graph_destroy_context(struct nouveau_channel *); 1007extern int nv10_graph_load_context(struct nouveau_channel *); 1008extern int nv10_graph_unload_context(struct drm_device *); 1009extern void nv10_graph_context_switch(struct drm_device *); 1010extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1011 uint32_t, uint32_t); 1012 1013/* nv20_graph.c */ 1014extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1015extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1016extern int nv20_graph_create_context(struct nouveau_channel *); 1017extern void nv20_graph_destroy_context(struct nouveau_channel *); 1018extern int nv20_graph_load_context(struct nouveau_channel *); 1019extern int nv20_graph_unload_context(struct drm_device *); 1020extern int nv20_graph_init(struct drm_device *); 1021extern void nv20_graph_takedown(struct drm_device *); 1022extern int nv30_graph_init(struct drm_device *); 1023extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1024 uint32_t, uint32_t); 1025 1026/* nv40_graph.c */ 1027extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1028extern int nv40_graph_init(struct drm_device *); 1029extern void nv40_graph_takedown(struct drm_device *); 1030extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1031extern int nv40_graph_create_context(struct nouveau_channel *); 1032extern void nv40_graph_destroy_context(struct nouveau_channel *); 1033extern int nv40_graph_load_context(struct nouveau_channel *); 1034extern int nv40_graph_unload_context(struct drm_device *); 1035extern void nv40_grctx_init(struct nouveau_grctx *); 1036extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1037 uint32_t, uint32_t); 1038 1039/* nv50_graph.c */ 1040extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1041extern int nv50_graph_init(struct drm_device *); 1042extern void nv50_graph_takedown(struct drm_device *); 1043extern void nv50_graph_fifo_access(struct drm_device *, bool); 1044extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1045extern int nv50_graph_create_context(struct nouveau_channel *); 1046extern void nv50_graph_destroy_context(struct nouveau_channel *); 1047extern int nv50_graph_load_context(struct nouveau_channel *); 1048extern int nv50_graph_unload_context(struct drm_device *); 1049extern void nv50_graph_context_switch(struct drm_device *); 1050extern int nv50_grctx_init(struct nouveau_grctx *); 1051 1052/* nvc0_graph.c */ 1053extern int nvc0_graph_init(struct drm_device *); 1054extern void nvc0_graph_takedown(struct drm_device *); 1055extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1056extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1057extern int nvc0_graph_create_context(struct nouveau_channel *); 1058extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1059extern int nvc0_graph_load_context(struct nouveau_channel *); 1060extern int nvc0_graph_unload_context(struct drm_device *); 1061 1062/* nv04_instmem.c */ 1063extern int nv04_instmem_init(struct drm_device *); 1064extern void nv04_instmem_takedown(struct drm_device *); 1065extern int nv04_instmem_suspend(struct drm_device *); 1066extern void nv04_instmem_resume(struct drm_device *); 1067extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1068 uint32_t *size); 1069extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1070extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1071extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1072extern void nv04_instmem_flush(struct drm_device *); 1073 1074/* nv50_instmem.c */ 1075extern int nv50_instmem_init(struct drm_device *); 1076extern void nv50_instmem_takedown(struct drm_device *); 1077extern int nv50_instmem_suspend(struct drm_device *); 1078extern void nv50_instmem_resume(struct drm_device *); 1079extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1080 uint32_t *size); 1081extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1082extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1083extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1084extern void nv50_instmem_flush(struct drm_device *); 1085extern void nv84_instmem_flush(struct drm_device *); 1086extern void nv50_vm_flush(struct drm_device *, int engine); 1087 1088/* nvc0_instmem.c */ 1089extern int nvc0_instmem_init(struct drm_device *); 1090extern void nvc0_instmem_takedown(struct drm_device *); 1091extern int nvc0_instmem_suspend(struct drm_device *); 1092extern void nvc0_instmem_resume(struct drm_device *); 1093extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1094 uint32_t *size); 1095extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1096extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1097extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1098extern void nvc0_instmem_flush(struct drm_device *); 1099 1100/* nv04_mc.c */ 1101extern int nv04_mc_init(struct drm_device *); 1102extern void nv04_mc_takedown(struct drm_device *); 1103 1104/* nv40_mc.c */ 1105extern int nv40_mc_init(struct drm_device *); 1106extern void nv40_mc_takedown(struct drm_device *); 1107 1108/* nv50_mc.c */ 1109extern int nv50_mc_init(struct drm_device *); 1110extern void nv50_mc_takedown(struct drm_device *); 1111 1112/* nv04_timer.c */ 1113extern int nv04_timer_init(struct drm_device *); 1114extern uint64_t nv04_timer_read(struct drm_device *); 1115extern void nv04_timer_takedown(struct drm_device *); 1116 1117extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1118 unsigned long arg); 1119 1120/* nv04_dac.c */ 1121extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1122extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1123extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1124extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1125extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1126 1127/* nv04_dfp.c */ 1128extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1129extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1130extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1131 int head, bool dl); 1132extern void nv04_dfp_disable(struct drm_device *dev, int head); 1133extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1134 1135/* nv04_tv.c */ 1136extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1137extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1138 1139/* nv17_tv.c */ 1140extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1141 1142/* nv04_display.c */ 1143extern int nv04_display_early_init(struct drm_device *); 1144extern void nv04_display_late_takedown(struct drm_device *); 1145extern int nv04_display_create(struct drm_device *); 1146extern int nv04_display_init(struct drm_device *); 1147extern void nv04_display_destroy(struct drm_device *); 1148 1149/* nv04_crtc.c */ 1150extern int nv04_crtc_create(struct drm_device *, int index); 1151 1152/* nouveau_bo.c */ 1153extern struct ttm_bo_driver nouveau_bo_driver; 1154extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1155 int size, int align, uint32_t flags, 1156 uint32_t tile_mode, uint32_t tile_flags, 1157 bool no_vm, bool mappable, struct nouveau_bo **); 1158extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1159extern int nouveau_bo_unpin(struct nouveau_bo *); 1160extern int nouveau_bo_map(struct nouveau_bo *); 1161extern void nouveau_bo_unmap(struct nouveau_bo *); 1162extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1163 uint32_t busy); 1164extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1165extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1166extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1167extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1168extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1169 1170/* nouveau_fence.c */ 1171struct nouveau_fence; 1172extern int nouveau_fence_init(struct nouveau_channel *); 1173extern void nouveau_fence_fini(struct nouveau_channel *); 1174extern void nouveau_fence_update(struct nouveau_channel *); 1175extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1176 bool emit); 1177extern int nouveau_fence_emit(struct nouveau_fence *); 1178struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1179extern bool nouveau_fence_signalled(void *obj, void *arg); 1180extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1181extern int nouveau_fence_flush(void *obj, void *arg); 1182extern void nouveau_fence_unref(void **obj); 1183extern void *nouveau_fence_ref(void *obj); 1184 1185/* nouveau_gem.c */ 1186extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1187 int size, int align, uint32_t flags, 1188 uint32_t tile_mode, uint32_t tile_flags, 1189 bool no_vm, bool mappable, struct nouveau_bo **); 1190extern int nouveau_gem_object_new(struct drm_gem_object *); 1191extern void nouveau_gem_object_del(struct drm_gem_object *); 1192extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1193 struct drm_file *); 1194extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1195 struct drm_file *); 1196extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1197 struct drm_file *); 1198extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1199 struct drm_file *); 1200extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1201 struct drm_file *); 1202 1203/* nv10_gpio.c */ 1204int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1205int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1206 1207/* nv50_gpio.c */ 1208int nv50_gpio_init(struct drm_device *dev); 1209int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1210int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1211void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1212 1213/* nv50_calc. */ 1214int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1215 int *N1, int *M1, int *N2, int *M2, int *P); 1216int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1217 int clk, int *N, int *fN, int *M, int *P); 1218 1219#ifndef ioread32_native 1220#ifdef __BIG_ENDIAN 1221#define ioread16_native ioread16be 1222#define iowrite16_native iowrite16be 1223#define ioread32_native ioread32be 1224#define iowrite32_native iowrite32be 1225#else /* def __BIG_ENDIAN */ 1226#define ioread16_native ioread16 1227#define iowrite16_native iowrite16 1228#define ioread32_native ioread32 1229#define iowrite32_native iowrite32 1230#endif /* def __BIG_ENDIAN else */ 1231#endif /* !ioread32_native */ 1232 1233/* channel control reg access */ 1234static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1235{ 1236 return ioread32_native(chan->user + reg); 1237} 1238 1239static inline void nvchan_wr32(struct nouveau_channel *chan, 1240 unsigned reg, u32 val) 1241{ 1242 iowrite32_native(val, chan->user + reg); 1243} 1244 1245/* register access */ 1246static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1247{ 1248 struct drm_nouveau_private *dev_priv = dev->dev_private; 1249 return ioread32_native(dev_priv->mmio + reg); 1250} 1251 1252static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1253{ 1254 struct drm_nouveau_private *dev_priv = dev->dev_private; 1255 iowrite32_native(val, dev_priv->mmio + reg); 1256} 1257 1258static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1259{ 1260 u32 tmp = nv_rd32(dev, reg); 1261 tmp &= ~mask; 1262 tmp |= val; 1263 nv_wr32(dev, reg, tmp); 1264} 1265 1266static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1267{ 1268 struct drm_nouveau_private *dev_priv = dev->dev_private; 1269 return ioread8(dev_priv->mmio + reg); 1270} 1271 1272static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1273{ 1274 struct drm_nouveau_private *dev_priv = dev->dev_private; 1275 iowrite8(val, dev_priv->mmio + reg); 1276} 1277 1278#define nv_wait(reg, mask, val) \ 1279 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1280 1281/* PRAMIN access */ 1282static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1283{ 1284 struct drm_nouveau_private *dev_priv = dev->dev_private; 1285 return ioread32_native(dev_priv->ramin + offset); 1286} 1287 1288static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1289{ 1290 struct drm_nouveau_private *dev_priv = dev->dev_private; 1291 iowrite32_native(val, dev_priv->ramin + offset); 1292} 1293 1294/* object access */ 1295static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1296 unsigned index) 1297{ 1298 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1299} 1300 1301static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1302 unsigned index, u32 val) 1303{ 1304 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1305} 1306 1307/* 1308 * Logging 1309 * Argument d is (struct drm_device *). 1310 */ 1311#define NV_PRINTK(level, d, fmt, arg...) \ 1312 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1313 pci_name(d->pdev), ##arg) 1314#ifndef NV_DEBUG_NOTRACE 1315#define NV_DEBUG(d, fmt, arg...) do { \ 1316 if (drm_debug & DRM_UT_DRIVER) { \ 1317 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1318 __LINE__, ##arg); \ 1319 } \ 1320} while (0) 1321#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1322 if (drm_debug & DRM_UT_KMS) { \ 1323 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1324 __LINE__, ##arg); \ 1325 } \ 1326} while (0) 1327#else 1328#define NV_DEBUG(d, fmt, arg...) do { \ 1329 if (drm_debug & DRM_UT_DRIVER) \ 1330 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1331} while (0) 1332#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1333 if (drm_debug & DRM_UT_KMS) \ 1334 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1335} while (0) 1336#endif 1337#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1338#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1339#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1340#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1341#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1342 1343/* nouveau_reg_debug bitmask */ 1344enum { 1345 NOUVEAU_REG_DEBUG_MC = 0x1, 1346 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1347 NOUVEAU_REG_DEBUG_FB = 0x4, 1348 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1349 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1350 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1351 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1352 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1353 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1354 NOUVEAU_REG_DEBUG_EVO = 0x200, 1355}; 1356 1357#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1358 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1359 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1360} while (0) 1361 1362static inline bool 1363nv_two_heads(struct drm_device *dev) 1364{ 1365 struct drm_nouveau_private *dev_priv = dev->dev_private; 1366 const int impl = dev->pci_device & 0x0ff0; 1367 1368 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1369 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1370 return true; 1371 1372 return false; 1373} 1374 1375static inline bool 1376nv_gf4_disp_arch(struct drm_device *dev) 1377{ 1378 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1379} 1380 1381static inline bool 1382nv_two_reg_pll(struct drm_device *dev) 1383{ 1384 struct drm_nouveau_private *dev_priv = dev->dev_private; 1385 const int impl = dev->pci_device & 0x0ff0; 1386 1387 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1388 return true; 1389 return false; 1390} 1391 1392#define NV_SW 0x0000506e 1393#define NV_SW_DMA_SEMAPHORE 0x00000060 1394#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1395#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1396#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1397#define NV_SW_DMA_VBLSEM 0x0000018c 1398#define NV_SW_VBLSEM_OFFSET 0x00000400 1399#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1400#define NV_SW_VBLSEM_RELEASE 0x00000408 1401 1402#endif /* __NOUVEAU_DRV_H__ */ 1403