nouveau_drv.h revision 4976986bd4f51368890f57b964176ec532972543
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_CRYPT 2 154#define NVOBJ_ENGINE_DISPLAY 15 155#define NVOBJ_ENGINE_NR 16 156 157#define NVOBJ_FLAG_DONT_MAP (1 << 0) 158#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 159#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 160#define NVOBJ_FLAG_VM (1 << 3) 161#define NVOBJ_FLAG_VM_USER (1 << 4) 162 163#define NVOBJ_CINST_GLOBAL 0xdeadbeef 164 165struct nouveau_gpuobj { 166 struct drm_device *dev; 167 struct kref refcount; 168 struct list_head list; 169 170 void *node; 171 u32 *suspend; 172 173 uint32_t flags; 174 175 u32 size; 176 u32 pinst; 177 u32 cinst; 178 u64 vinst; 179 180 uint32_t engine; 181 uint32_t class; 182 183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 184 void *priv; 185}; 186 187struct nouveau_page_flip_state { 188 struct list_head head; 189 struct drm_pending_vblank_event *event; 190 int crtc, bpp, pitch, x, y; 191 uint64_t offset; 192}; 193 194enum nouveau_channel_mutex_class { 195 NOUVEAU_UCHANNEL_MUTEX, 196 NOUVEAU_KCHANNEL_MUTEX 197}; 198 199struct nouveau_channel { 200 struct drm_device *dev; 201 int id; 202 203 /* references to the channel data structure */ 204 struct kref ref; 205 /* users of the hardware channel resources, the hardware 206 * context will be kicked off when it reaches zero. */ 207 atomic_t users; 208 struct mutex mutex; 209 210 /* owner of this fifo */ 211 struct drm_file *file_priv; 212 /* mapping of the fifo itself */ 213 struct drm_local_map *map; 214 215 /* mapping of the regs controlling the fifo */ 216 void __iomem *user; 217 uint32_t user_get; 218 uint32_t user_put; 219 220 /* Fencing */ 221 struct { 222 /* lock protects the pending list only */ 223 spinlock_t lock; 224 struct list_head pending; 225 uint32_t sequence; 226 uint32_t sequence_ack; 227 atomic_t last_sequence_irq; 228 } fence; 229 230 /* DMA push buffer */ 231 struct nouveau_gpuobj *pushbuf; 232 struct nouveau_bo *pushbuf_bo; 233 uint32_t pushbuf_base; 234 235 /* Notifier memory */ 236 struct nouveau_bo *notifier_bo; 237 struct drm_mm notifier_heap; 238 239 /* PFIFO context */ 240 struct nouveau_gpuobj *ramfc; 241 struct nouveau_gpuobj *cache; 242 void *fifo_priv; 243 244 /* PGRAPH context */ 245 /* XXX may be merge 2 pointers as private data ??? */ 246 struct nouveau_gpuobj *ramin_grctx; 247 void *pgraph_ctx; 248 void *engctx[NVOBJ_ENGINE_NR]; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295}; 296 297struct nouveau_exec_engine { 298 void (*destroy)(struct drm_device *, int engine); 299 int (*init)(struct drm_device *, int engine); 300 int (*fini)(struct drm_device *, int engine); 301 int (*context_new)(struct nouveau_channel *, int engine); 302 void (*context_del)(struct nouveau_channel *, int engine); 303 int (*object_new)(struct nouveau_channel *, int engine, 304 u32 handle, u16 class); 305 void (*tlb_flush)(struct drm_device *, int engine); 306}; 307 308struct nouveau_instmem_engine { 309 void *priv; 310 311 int (*init)(struct drm_device *dev); 312 void (*takedown)(struct drm_device *dev); 313 int (*suspend)(struct drm_device *dev); 314 void (*resume)(struct drm_device *dev); 315 316 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 317 void (*put)(struct nouveau_gpuobj *); 318 int (*map)(struct nouveau_gpuobj *); 319 void (*unmap)(struct nouveau_gpuobj *); 320 321 void (*flush)(struct drm_device *); 322}; 323 324struct nouveau_mc_engine { 325 int (*init)(struct drm_device *dev); 326 void (*takedown)(struct drm_device *dev); 327}; 328 329struct nouveau_timer_engine { 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 uint64_t (*read)(struct drm_device *dev); 333}; 334 335struct nouveau_fb_engine { 336 int num_tiles; 337 struct drm_mm tag_heap; 338 void *priv; 339 340 int (*init)(struct drm_device *dev); 341 void (*takedown)(struct drm_device *dev); 342 343 void (*init_tile_region)(struct drm_device *dev, int i, 344 uint32_t addr, uint32_t size, 345 uint32_t pitch, uint32_t flags); 346 void (*set_tile_region)(struct drm_device *dev, int i); 347 void (*free_tile_region)(struct drm_device *dev, int i); 348}; 349 350struct nouveau_fifo_engine { 351 void *priv; 352 int channels; 353 354 struct nouveau_gpuobj *playlist[2]; 355 int cur_playlist; 356 357 int (*init)(struct drm_device *); 358 void (*takedown)(struct drm_device *); 359 360 void (*disable)(struct drm_device *); 361 void (*enable)(struct drm_device *); 362 bool (*reassign)(struct drm_device *, bool enable); 363 bool (*cache_pull)(struct drm_device *dev, bool enable); 364 365 int (*channel_id)(struct drm_device *); 366 367 int (*create_context)(struct nouveau_channel *); 368 void (*destroy_context)(struct nouveau_channel *); 369 int (*load_context)(struct nouveau_channel *); 370 int (*unload_context)(struct drm_device *); 371 void (*tlb_flush)(struct drm_device *dev); 372}; 373 374struct nouveau_pgraph_engine { 375 bool accel_blocked; 376 bool registered; 377 int grctx_size; 378 void *priv; 379 380 /* NV2x/NV3x context table (0x400780) */ 381 struct nouveau_gpuobj *ctx_table; 382 383 int (*init)(struct drm_device *); 384 void (*takedown)(struct drm_device *); 385 386 void (*fifo_access)(struct drm_device *, bool); 387 388 struct nouveau_channel *(*channel)(struct drm_device *); 389 int (*create_context)(struct nouveau_channel *); 390 void (*destroy_context)(struct nouveau_channel *); 391 int (*load_context)(struct nouveau_channel *); 392 int (*unload_context)(struct drm_device *); 393 int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class); 394 void (*tlb_flush)(struct drm_device *dev); 395 396 void (*set_tile_region)(struct drm_device *dev, int i); 397}; 398 399struct nouveau_display_engine { 400 void *priv; 401 int (*early_init)(struct drm_device *); 402 void (*late_takedown)(struct drm_device *); 403 int (*create)(struct drm_device *); 404 int (*init)(struct drm_device *); 405 void (*destroy)(struct drm_device *); 406}; 407 408struct nouveau_gpio_engine { 409 void *priv; 410 411 int (*init)(struct drm_device *); 412 void (*takedown)(struct drm_device *); 413 414 int (*get)(struct drm_device *, enum dcb_gpio_tag); 415 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 416 417 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 418 void (*)(void *, int), void *); 419 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 420 void (*)(void *, int), void *); 421 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 422}; 423 424struct nouveau_pm_voltage_level { 425 u8 voltage; 426 u8 vid; 427}; 428 429struct nouveau_pm_voltage { 430 bool supported; 431 u8 vid_mask; 432 433 struct nouveau_pm_voltage_level *level; 434 int nr_level; 435}; 436 437#define NOUVEAU_PM_MAX_LEVEL 8 438struct nouveau_pm_level { 439 struct device_attribute dev_attr; 440 char name[32]; 441 int id; 442 443 u32 core; 444 u32 memory; 445 u32 shader; 446 u32 unk05; 447 448 u8 voltage; 449 u8 fanspeed; 450 451 u16 memscript; 452}; 453 454struct nouveau_pm_temp_sensor_constants { 455 u16 offset_constant; 456 s16 offset_mult; 457 u16 offset_div; 458 u16 slope_mult; 459 u16 slope_div; 460}; 461 462struct nouveau_pm_threshold_temp { 463 s16 critical; 464 s16 down_clock; 465 s16 fan_boost; 466}; 467 468struct nouveau_pm_memtiming { 469 u32 reg_100220; 470 u32 reg_100224; 471 u32 reg_100228; 472 u32 reg_10022c; 473 u32 reg_100230; 474 u32 reg_100234; 475 u32 reg_100238; 476 u32 reg_10023c; 477 u32 reg_100240; 478}; 479 480struct nouveau_pm_memtimings { 481 bool supported; 482 struct nouveau_pm_memtiming *timing; 483 int nr_timing; 484}; 485 486struct nouveau_pm_engine { 487 struct nouveau_pm_voltage voltage; 488 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 489 int nr_perflvl; 490 struct nouveau_pm_memtimings memtimings; 491 struct nouveau_pm_temp_sensor_constants sensor_constants; 492 struct nouveau_pm_threshold_temp threshold_temp; 493 494 struct nouveau_pm_level boot; 495 struct nouveau_pm_level *cur; 496 497 struct device *hwmon; 498 struct notifier_block acpi_nb; 499 500 int (*clock_get)(struct drm_device *, u32 id); 501 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 502 u32 id, int khz); 503 void (*clock_set)(struct drm_device *, void *); 504 int (*voltage_get)(struct drm_device *); 505 int (*voltage_set)(struct drm_device *, int voltage); 506 int (*fanspeed_get)(struct drm_device *); 507 int (*fanspeed_set)(struct drm_device *, int fanspeed); 508 int (*temp_get)(struct drm_device *); 509}; 510 511struct nouveau_vram_engine { 512 int (*init)(struct drm_device *); 513 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 514 u32 type, struct nouveau_mem **); 515 void (*put)(struct drm_device *, struct nouveau_mem **); 516 517 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 518}; 519 520struct nouveau_engine { 521 struct nouveau_instmem_engine instmem; 522 struct nouveau_mc_engine mc; 523 struct nouveau_timer_engine timer; 524 struct nouveau_fb_engine fb; 525 struct nouveau_pgraph_engine graph; 526 struct nouveau_fifo_engine fifo; 527 struct nouveau_display_engine display; 528 struct nouveau_gpio_engine gpio; 529 struct nouveau_pm_engine pm; 530 struct nouveau_vram_engine vram; 531}; 532 533struct nouveau_pll_vals { 534 union { 535 struct { 536#ifdef __BIG_ENDIAN 537 uint8_t N1, M1, N2, M2; 538#else 539 uint8_t M1, N1, M2, N2; 540#endif 541 }; 542 struct { 543 uint16_t NM1, NM2; 544 } __attribute__((packed)); 545 }; 546 int log2P; 547 548 int refclk; 549}; 550 551enum nv04_fp_display_regs { 552 FP_DISPLAY_END, 553 FP_TOTAL, 554 FP_CRTC, 555 FP_SYNC_START, 556 FP_SYNC_END, 557 FP_VALID_START, 558 FP_VALID_END 559}; 560 561struct nv04_crtc_reg { 562 unsigned char MiscOutReg; 563 uint8_t CRTC[0xa0]; 564 uint8_t CR58[0x10]; 565 uint8_t Sequencer[5]; 566 uint8_t Graphics[9]; 567 uint8_t Attribute[21]; 568 unsigned char DAC[768]; 569 570 /* PCRTC regs */ 571 uint32_t fb_start; 572 uint32_t crtc_cfg; 573 uint32_t cursor_cfg; 574 uint32_t gpio_ext; 575 uint32_t crtc_830; 576 uint32_t crtc_834; 577 uint32_t crtc_850; 578 uint32_t crtc_eng_ctrl; 579 580 /* PRAMDAC regs */ 581 uint32_t nv10_cursync; 582 struct nouveau_pll_vals pllvals; 583 uint32_t ramdac_gen_ctrl; 584 uint32_t ramdac_630; 585 uint32_t ramdac_634; 586 uint32_t tv_setup; 587 uint32_t tv_vtotal; 588 uint32_t tv_vskew; 589 uint32_t tv_vsync_delay; 590 uint32_t tv_htotal; 591 uint32_t tv_hskew; 592 uint32_t tv_hsync_delay; 593 uint32_t tv_hsync_delay2; 594 uint32_t fp_horiz_regs[7]; 595 uint32_t fp_vert_regs[7]; 596 uint32_t dither; 597 uint32_t fp_control; 598 uint32_t dither_regs[6]; 599 uint32_t fp_debug_0; 600 uint32_t fp_debug_1; 601 uint32_t fp_debug_2; 602 uint32_t fp_margin_color; 603 uint32_t ramdac_8c0; 604 uint32_t ramdac_a20; 605 uint32_t ramdac_a24; 606 uint32_t ramdac_a34; 607 uint32_t ctv_regs[38]; 608}; 609 610struct nv04_output_reg { 611 uint32_t output; 612 int head; 613}; 614 615struct nv04_mode_state { 616 struct nv04_crtc_reg crtc_reg[2]; 617 uint32_t pllsel; 618 uint32_t sel_clk; 619}; 620 621enum nouveau_card_type { 622 NV_04 = 0x00, 623 NV_10 = 0x10, 624 NV_20 = 0x20, 625 NV_30 = 0x30, 626 NV_40 = 0x40, 627 NV_50 = 0x50, 628 NV_C0 = 0xc0, 629}; 630 631struct drm_nouveau_private { 632 struct drm_device *dev; 633 634 /* the card type, takes NV_* as values */ 635 enum nouveau_card_type card_type; 636 /* exact chipset, derived from NV_PMC_BOOT_0 */ 637 int chipset; 638 int stepping; 639 int flags; 640 641 void __iomem *mmio; 642 643 spinlock_t ramin_lock; 644 void __iomem *ramin; 645 u32 ramin_size; 646 u32 ramin_base; 647 bool ramin_available; 648 struct drm_mm ramin_heap; 649 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 650 struct list_head gpuobj_list; 651 struct list_head classes; 652 653 struct nouveau_bo *vga_ram; 654 655 /* interrupt handling */ 656 void (*irq_handler[32])(struct drm_device *); 657 bool msi_enabled; 658 659 struct list_head vbl_waiting; 660 661 struct { 662 struct drm_global_reference mem_global_ref; 663 struct ttm_bo_global_ref bo_global_ref; 664 struct ttm_bo_device bdev; 665 atomic_t validate_sequence; 666 } ttm; 667 668 struct { 669 spinlock_t lock; 670 struct drm_mm heap; 671 struct nouveau_bo *bo; 672 } fence; 673 674 struct { 675 spinlock_t lock; 676 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 677 } channels; 678 679 struct nouveau_engine engine; 680 struct nouveau_channel *channel; 681 682 /* For PFIFO and PGRAPH. */ 683 spinlock_t context_switch_lock; 684 685 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 686 spinlock_t vm_lock; 687 688 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 689 struct nouveau_ramht *ramht; 690 struct nouveau_gpuobj *ramfc; 691 struct nouveau_gpuobj *ramro; 692 693 uint32_t ramin_rsvd_vram; 694 695 struct { 696 enum { 697 NOUVEAU_GART_NONE = 0, 698 NOUVEAU_GART_AGP, /* AGP */ 699 NOUVEAU_GART_PDMA, /* paged dma object */ 700 NOUVEAU_GART_HW /* on-chip gart/vm */ 701 } type; 702 uint64_t aper_base; 703 uint64_t aper_size; 704 uint64_t aper_free; 705 706 struct ttm_backend_func *func; 707 708 struct { 709 struct page *page; 710 dma_addr_t addr; 711 } dummy; 712 713 struct nouveau_gpuobj *sg_ctxdma; 714 } gart_info; 715 716 /* nv10-nv40 tiling regions */ 717 struct { 718 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 719 spinlock_t lock; 720 } tile; 721 722 /* VRAM/fb configuration */ 723 uint64_t vram_size; 724 uint64_t vram_sys_base; 725 u32 vram_rblock_size; 726 727 uint64_t fb_phys; 728 uint64_t fb_available_size; 729 uint64_t fb_mappable_pages; 730 uint64_t fb_aper_free; 731 int fb_mtrr; 732 733 /* BAR control (NV50-) */ 734 struct nouveau_vm *bar1_vm; 735 struct nouveau_vm *bar3_vm; 736 737 /* G8x/G9x virtual address space */ 738 struct nouveau_vm *chan_vm; 739 740 struct nvbios vbios; 741 742 struct nv04_mode_state mode_reg; 743 struct nv04_mode_state saved_reg; 744 uint32_t saved_vga_font[4][16384]; 745 uint32_t crtc_owner; 746 uint32_t dac_users[4]; 747 748 struct backlight_device *backlight; 749 750 struct { 751 struct dentry *channel_root; 752 } debugfs; 753 754 struct nouveau_fbdev *nfbdev; 755 struct apertures_struct *apertures; 756}; 757 758static inline struct drm_nouveau_private * 759nouveau_private(struct drm_device *dev) 760{ 761 return dev->dev_private; 762} 763 764static inline struct drm_nouveau_private * 765nouveau_bdev(struct ttm_bo_device *bd) 766{ 767 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 768} 769 770static inline int 771nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 772{ 773 struct nouveau_bo *prev; 774 775 if (!pnvbo) 776 return -EINVAL; 777 prev = *pnvbo; 778 779 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 780 if (prev) { 781 struct ttm_buffer_object *bo = &prev->bo; 782 783 ttm_bo_unref(&bo); 784 } 785 786 return 0; 787} 788 789/* nouveau_drv.c */ 790extern int nouveau_agpmode; 791extern int nouveau_duallink; 792extern int nouveau_uscript_lvds; 793extern int nouveau_uscript_tmds; 794extern int nouveau_vram_pushbuf; 795extern int nouveau_vram_notify; 796extern int nouveau_fbpercrtc; 797extern int nouveau_tv_disable; 798extern char *nouveau_tv_norm; 799extern int nouveau_reg_debug; 800extern char *nouveau_vbios; 801extern int nouveau_ignorelid; 802extern int nouveau_nofbaccel; 803extern int nouveau_noaccel; 804extern int nouveau_force_post; 805extern int nouveau_override_conntype; 806extern char *nouveau_perflvl; 807extern int nouveau_perflvl_wr; 808extern int nouveau_msi; 809 810extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 811extern int nouveau_pci_resume(struct pci_dev *pdev); 812 813/* nouveau_state.c */ 814extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 815extern int nouveau_load(struct drm_device *, unsigned long flags); 816extern int nouveau_firstopen(struct drm_device *); 817extern void nouveau_lastclose(struct drm_device *); 818extern int nouveau_unload(struct drm_device *); 819extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 820 struct drm_file *); 821extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 822 struct drm_file *); 823extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 824 uint32_t reg, uint32_t mask, uint32_t val); 825extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 826 uint32_t reg, uint32_t mask, uint32_t val); 827extern bool nouveau_wait_for_idle(struct drm_device *); 828extern int nouveau_card_init(struct drm_device *); 829 830/* nouveau_mem.c */ 831extern int nouveau_mem_vram_init(struct drm_device *); 832extern void nouveau_mem_vram_fini(struct drm_device *); 833extern int nouveau_mem_gart_init(struct drm_device *); 834extern void nouveau_mem_gart_fini(struct drm_device *); 835extern int nouveau_mem_init_agp(struct drm_device *); 836extern int nouveau_mem_reset_agp(struct drm_device *); 837extern void nouveau_mem_close(struct drm_device *); 838extern int nouveau_mem_detect(struct drm_device *); 839extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 840extern struct nouveau_tile_reg *nv10_mem_set_tiling( 841 struct drm_device *dev, uint32_t addr, uint32_t size, 842 uint32_t pitch, uint32_t flags); 843extern void nv10_mem_put_tile_region(struct drm_device *dev, 844 struct nouveau_tile_reg *tile, 845 struct nouveau_fence *fence); 846extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 847extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 848 849/* nouveau_notifier.c */ 850extern int nouveau_notifier_init_channel(struct nouveau_channel *); 851extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 852extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 853 int cout, uint32_t start, uint32_t end, 854 uint32_t *offset); 855extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 856extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 857 struct drm_file *); 858extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 859 struct drm_file *); 860 861/* nouveau_channel.c */ 862extern struct drm_ioctl_desc nouveau_ioctls[]; 863extern int nouveau_max_ioctl; 864extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 865extern int nouveau_channel_alloc(struct drm_device *dev, 866 struct nouveau_channel **chan, 867 struct drm_file *file_priv, 868 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 869extern struct nouveau_channel * 870nouveau_channel_get_unlocked(struct nouveau_channel *); 871extern struct nouveau_channel * 872nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 873extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 874extern void nouveau_channel_put(struct nouveau_channel **); 875extern void nouveau_channel_ref(struct nouveau_channel *chan, 876 struct nouveau_channel **pchan); 877extern void nouveau_channel_idle(struct nouveau_channel *chan); 878 879/* nouveau_object.c */ 880#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 881 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 882 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 883} while (0) 884 885#define NVOBJ_ENGINE_DEL(d, e) do { \ 886 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 887 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 888} while (0) 889 890#define NVOBJ_CLASS(d, c, e) do { \ 891 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 892 if (ret) \ 893 return ret; \ 894} while (0) 895 896#define NVOBJ_MTHD(d, c, m, e) do { \ 897 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 898 if (ret) \ 899 return ret; \ 900} while (0) 901 902extern int nouveau_gpuobj_early_init(struct drm_device *); 903extern int nouveau_gpuobj_init(struct drm_device *); 904extern void nouveau_gpuobj_takedown(struct drm_device *); 905extern int nouveau_gpuobj_suspend(struct drm_device *dev); 906extern void nouveau_gpuobj_resume(struct drm_device *dev); 907extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 908extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 909 int (*exec)(struct nouveau_channel *, 910 u32 class, u32 mthd, u32 data)); 911extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 912extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 913extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 914 uint32_t vram_h, uint32_t tt_h); 915extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 916extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 917 uint32_t size, int align, uint32_t flags, 918 struct nouveau_gpuobj **); 919extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 920 struct nouveau_gpuobj **); 921extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 922 u32 size, u32 flags, 923 struct nouveau_gpuobj **); 924extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 925 uint64_t offset, uint64_t size, int access, 926 int target, struct nouveau_gpuobj **); 927extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 928extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 929 u64 size, int target, int access, u32 type, 930 u32 comp, struct nouveau_gpuobj **pobj); 931extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 932 int class, u64 base, u64 size, int target, 933 int access, u32 type, u32 comp); 934extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 935 struct drm_file *); 936extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 937 struct drm_file *); 938 939/* nouveau_irq.c */ 940extern int nouveau_irq_init(struct drm_device *); 941extern void nouveau_irq_fini(struct drm_device *); 942extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 943extern void nouveau_irq_register(struct drm_device *, int status_bit, 944 void (*)(struct drm_device *)); 945extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 946extern void nouveau_irq_preinstall(struct drm_device *); 947extern int nouveau_irq_postinstall(struct drm_device *); 948extern void nouveau_irq_uninstall(struct drm_device *); 949 950/* nouveau_sgdma.c */ 951extern int nouveau_sgdma_init(struct drm_device *); 952extern void nouveau_sgdma_takedown(struct drm_device *); 953extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 954 uint32_t offset); 955extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 956 957/* nouveau_debugfs.c */ 958#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 959extern int nouveau_debugfs_init(struct drm_minor *); 960extern void nouveau_debugfs_takedown(struct drm_minor *); 961extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 962extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 963#else 964static inline int 965nouveau_debugfs_init(struct drm_minor *minor) 966{ 967 return 0; 968} 969 970static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 971{ 972} 973 974static inline int 975nouveau_debugfs_channel_init(struct nouveau_channel *chan) 976{ 977 return 0; 978} 979 980static inline void 981nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 982{ 983} 984#endif 985 986/* nouveau_dma.c */ 987extern void nouveau_dma_pre_init(struct nouveau_channel *); 988extern int nouveau_dma_init(struct nouveau_channel *); 989extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 990 991/* nouveau_acpi.c */ 992#define ROM_BIOS_PAGE 4096 993#if defined(CONFIG_ACPI) 994void nouveau_register_dsm_handler(void); 995void nouveau_unregister_dsm_handler(void); 996int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 997bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 998int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 999#else 1000static inline void nouveau_register_dsm_handler(void) {} 1001static inline void nouveau_unregister_dsm_handler(void) {} 1002static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1003static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1004static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1005#endif 1006 1007/* nouveau_backlight.c */ 1008#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1009extern int nouveau_backlight_init(struct drm_connector *); 1010extern void nouveau_backlight_exit(struct drm_connector *); 1011#else 1012static inline int nouveau_backlight_init(struct drm_connector *dev) 1013{ 1014 return 0; 1015} 1016 1017static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1018#endif 1019 1020/* nouveau_bios.c */ 1021extern int nouveau_bios_init(struct drm_device *); 1022extern void nouveau_bios_takedown(struct drm_device *dev); 1023extern int nouveau_run_vbios_init(struct drm_device *); 1024extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1025 struct dcb_entry *); 1026extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1027 enum dcb_gpio_tag); 1028extern struct dcb_connector_table_entry * 1029nouveau_bios_connector_entry(struct drm_device *, int index); 1030extern u32 get_pll_register(struct drm_device *, enum pll_types); 1031extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1032 struct pll_lims *); 1033extern int nouveau_bios_run_display_table(struct drm_device *, 1034 struct dcb_entry *, 1035 uint32_t script, int pxclk); 1036extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1037 int *length); 1038extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1039extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1040extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1041 bool *dl, bool *if_is_24bit); 1042extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1043 int head, int pxclk); 1044extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1045 enum LVDS_script, int pxclk); 1046 1047/* nouveau_ttm.c */ 1048int nouveau_ttm_global_init(struct drm_nouveau_private *); 1049void nouveau_ttm_global_release(struct drm_nouveau_private *); 1050int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1051 1052/* nouveau_dp.c */ 1053int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1054 uint8_t *data, int data_nr); 1055bool nouveau_dp_detect(struct drm_encoder *); 1056bool nouveau_dp_link_train(struct drm_encoder *); 1057 1058/* nv04_fb.c */ 1059extern int nv04_fb_init(struct drm_device *); 1060extern void nv04_fb_takedown(struct drm_device *); 1061 1062/* nv10_fb.c */ 1063extern int nv10_fb_init(struct drm_device *); 1064extern void nv10_fb_takedown(struct drm_device *); 1065extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1066 uint32_t addr, uint32_t size, 1067 uint32_t pitch, uint32_t flags); 1068extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1069extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1070 1071/* nv30_fb.c */ 1072extern int nv30_fb_init(struct drm_device *); 1073extern void nv30_fb_takedown(struct drm_device *); 1074extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1075 uint32_t addr, uint32_t size, 1076 uint32_t pitch, uint32_t flags); 1077extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1078 1079/* nv40_fb.c */ 1080extern int nv40_fb_init(struct drm_device *); 1081extern void nv40_fb_takedown(struct drm_device *); 1082extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1083 1084/* nv50_fb.c */ 1085extern int nv50_fb_init(struct drm_device *); 1086extern void nv50_fb_takedown(struct drm_device *); 1087extern void nv50_fb_vm_trap(struct drm_device *, int display); 1088 1089/* nvc0_fb.c */ 1090extern int nvc0_fb_init(struct drm_device *); 1091extern void nvc0_fb_takedown(struct drm_device *); 1092 1093/* nv04_fifo.c */ 1094extern int nv04_fifo_init(struct drm_device *); 1095extern void nv04_fifo_fini(struct drm_device *); 1096extern void nv04_fifo_disable(struct drm_device *); 1097extern void nv04_fifo_enable(struct drm_device *); 1098extern bool nv04_fifo_reassign(struct drm_device *, bool); 1099extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1100extern int nv04_fifo_channel_id(struct drm_device *); 1101extern int nv04_fifo_create_context(struct nouveau_channel *); 1102extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1103extern int nv04_fifo_load_context(struct nouveau_channel *); 1104extern int nv04_fifo_unload_context(struct drm_device *); 1105extern void nv04_fifo_isr(struct drm_device *); 1106 1107/* nv10_fifo.c */ 1108extern int nv10_fifo_init(struct drm_device *); 1109extern int nv10_fifo_channel_id(struct drm_device *); 1110extern int nv10_fifo_create_context(struct nouveau_channel *); 1111extern int nv10_fifo_load_context(struct nouveau_channel *); 1112extern int nv10_fifo_unload_context(struct drm_device *); 1113 1114/* nv40_fifo.c */ 1115extern int nv40_fifo_init(struct drm_device *); 1116extern int nv40_fifo_create_context(struct nouveau_channel *); 1117extern int nv40_fifo_load_context(struct nouveau_channel *); 1118extern int nv40_fifo_unload_context(struct drm_device *); 1119 1120/* nv50_fifo.c */ 1121extern int nv50_fifo_init(struct drm_device *); 1122extern void nv50_fifo_takedown(struct drm_device *); 1123extern int nv50_fifo_channel_id(struct drm_device *); 1124extern int nv50_fifo_create_context(struct nouveau_channel *); 1125extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1126extern int nv50_fifo_load_context(struct nouveau_channel *); 1127extern int nv50_fifo_unload_context(struct drm_device *); 1128extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1129 1130/* nvc0_fifo.c */ 1131extern int nvc0_fifo_init(struct drm_device *); 1132extern void nvc0_fifo_takedown(struct drm_device *); 1133extern void nvc0_fifo_disable(struct drm_device *); 1134extern void nvc0_fifo_enable(struct drm_device *); 1135extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1136extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1137extern int nvc0_fifo_channel_id(struct drm_device *); 1138extern int nvc0_fifo_create_context(struct nouveau_channel *); 1139extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1140extern int nvc0_fifo_load_context(struct nouveau_channel *); 1141extern int nvc0_fifo_unload_context(struct drm_device *); 1142 1143/* nv04_graph.c */ 1144extern int nv04_graph_create(struct drm_device *); 1145extern void nv04_graph_fifo_access(struct drm_device *, bool); 1146extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1147extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1148 u32 class, u32 mthd, u32 data); 1149extern struct nouveau_bitfield nv04_graph_nsource[]; 1150 1151/* nv10_graph.c */ 1152extern int nv10_graph_create(struct drm_device *); 1153extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1154extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1155extern struct nouveau_bitfield nv10_graph_intr[]; 1156extern struct nouveau_bitfield nv10_graph_nstatus[]; 1157 1158/* nv20_graph.c */ 1159extern int nv20_graph_create(struct drm_device *); 1160extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1161 1162/* nv40_graph.c */ 1163extern int nv40_graph_create(struct drm_device *); 1164extern void nv40_grctx_init(struct nouveau_grctx *); 1165extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1166 1167/* nv50_graph.c */ 1168extern int nv50_graph_create(struct drm_device *); 1169extern int nv50_grctx_init(struct nouveau_grctx *); 1170extern struct nouveau_enum nv50_data_error_names[]; 1171 1172/* nvc0_graph.c */ 1173extern int nvc0_graph_create(struct drm_device *); 1174extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1175extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1176 1177/* nv84_crypt.c */ 1178extern int nv84_crypt_create(struct drm_device *); 1179 1180/* nv04_instmem.c */ 1181extern int nv04_instmem_init(struct drm_device *); 1182extern void nv04_instmem_takedown(struct drm_device *); 1183extern int nv04_instmem_suspend(struct drm_device *); 1184extern void nv04_instmem_resume(struct drm_device *); 1185extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1186extern void nv04_instmem_put(struct nouveau_gpuobj *); 1187extern int nv04_instmem_map(struct nouveau_gpuobj *); 1188extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1189extern void nv04_instmem_flush(struct drm_device *); 1190 1191/* nv50_instmem.c */ 1192extern int nv50_instmem_init(struct drm_device *); 1193extern void nv50_instmem_takedown(struct drm_device *); 1194extern int nv50_instmem_suspend(struct drm_device *); 1195extern void nv50_instmem_resume(struct drm_device *); 1196extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1197extern void nv50_instmem_put(struct nouveau_gpuobj *); 1198extern int nv50_instmem_map(struct nouveau_gpuobj *); 1199extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1200extern void nv50_instmem_flush(struct drm_device *); 1201extern void nv84_instmem_flush(struct drm_device *); 1202 1203/* nvc0_instmem.c */ 1204extern int nvc0_instmem_init(struct drm_device *); 1205extern void nvc0_instmem_takedown(struct drm_device *); 1206extern int nvc0_instmem_suspend(struct drm_device *); 1207extern void nvc0_instmem_resume(struct drm_device *); 1208 1209/* nv04_mc.c */ 1210extern int nv04_mc_init(struct drm_device *); 1211extern void nv04_mc_takedown(struct drm_device *); 1212 1213/* nv40_mc.c */ 1214extern int nv40_mc_init(struct drm_device *); 1215extern void nv40_mc_takedown(struct drm_device *); 1216 1217/* nv50_mc.c */ 1218extern int nv50_mc_init(struct drm_device *); 1219extern void nv50_mc_takedown(struct drm_device *); 1220 1221/* nv04_timer.c */ 1222extern int nv04_timer_init(struct drm_device *); 1223extern uint64_t nv04_timer_read(struct drm_device *); 1224extern void nv04_timer_takedown(struct drm_device *); 1225 1226extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1227 unsigned long arg); 1228 1229/* nv04_dac.c */ 1230extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1231extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1232extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1233extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1234extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1235 1236/* nv04_dfp.c */ 1237extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1238extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1239extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1240 int head, bool dl); 1241extern void nv04_dfp_disable(struct drm_device *dev, int head); 1242extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1243 1244/* nv04_tv.c */ 1245extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1246extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1247 1248/* nv17_tv.c */ 1249extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1250 1251/* nv04_display.c */ 1252extern int nv04_display_early_init(struct drm_device *); 1253extern void nv04_display_late_takedown(struct drm_device *); 1254extern int nv04_display_create(struct drm_device *); 1255extern int nv04_display_init(struct drm_device *); 1256extern void nv04_display_destroy(struct drm_device *); 1257 1258/* nv04_crtc.c */ 1259extern int nv04_crtc_create(struct drm_device *, int index); 1260 1261/* nouveau_bo.c */ 1262extern struct ttm_bo_driver nouveau_bo_driver; 1263extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1264 int size, int align, uint32_t flags, 1265 uint32_t tile_mode, uint32_t tile_flags, 1266 struct nouveau_bo **); 1267extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1268extern int nouveau_bo_unpin(struct nouveau_bo *); 1269extern int nouveau_bo_map(struct nouveau_bo *); 1270extern void nouveau_bo_unmap(struct nouveau_bo *); 1271extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1272 uint32_t busy); 1273extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1274extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1275extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1276extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1277extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1278extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1279 bool no_wait_reserve, bool no_wait_gpu); 1280 1281/* nouveau_fence.c */ 1282struct nouveau_fence; 1283extern int nouveau_fence_init(struct drm_device *); 1284extern void nouveau_fence_fini(struct drm_device *); 1285extern int nouveau_fence_channel_init(struct nouveau_channel *); 1286extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1287extern void nouveau_fence_update(struct nouveau_channel *); 1288extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1289 bool emit); 1290extern int nouveau_fence_emit(struct nouveau_fence *); 1291extern void nouveau_fence_work(struct nouveau_fence *fence, 1292 void (*work)(void *priv, bool signalled), 1293 void *priv); 1294struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1295 1296extern bool __nouveau_fence_signalled(void *obj, void *arg); 1297extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1298extern int __nouveau_fence_flush(void *obj, void *arg); 1299extern void __nouveau_fence_unref(void **obj); 1300extern void *__nouveau_fence_ref(void *obj); 1301 1302static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1303{ 1304 return __nouveau_fence_signalled(obj, NULL); 1305} 1306static inline int 1307nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1308{ 1309 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1310} 1311extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1312static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1313{ 1314 return __nouveau_fence_flush(obj, NULL); 1315} 1316static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1317{ 1318 __nouveau_fence_unref((void **)obj); 1319} 1320static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1321{ 1322 return __nouveau_fence_ref(obj); 1323} 1324 1325/* nouveau_gem.c */ 1326extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1327 int size, int align, uint32_t domain, 1328 uint32_t tile_mode, uint32_t tile_flags, 1329 struct nouveau_bo **); 1330extern int nouveau_gem_object_new(struct drm_gem_object *); 1331extern void nouveau_gem_object_del(struct drm_gem_object *); 1332extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1333 struct drm_file *); 1334extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1335 struct drm_file *); 1336extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1337 struct drm_file *); 1338extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1339 struct drm_file *); 1340extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1341 struct drm_file *); 1342 1343/* nouveau_display.c */ 1344int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1345void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1346int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1347 struct drm_pending_vblank_event *event); 1348int nouveau_finish_page_flip(struct nouveau_channel *, 1349 struct nouveau_page_flip_state *); 1350 1351/* nv10_gpio.c */ 1352int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1353int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1354 1355/* nv50_gpio.c */ 1356int nv50_gpio_init(struct drm_device *dev); 1357void nv50_gpio_fini(struct drm_device *dev); 1358int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1359int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1360int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1361 void (*)(void *, int), void *); 1362void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1363 void (*)(void *, int), void *); 1364bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1365 1366/* nv50_calc. */ 1367int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1368 int *N1, int *M1, int *N2, int *M2, int *P); 1369int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1370 int clk, int *N, int *fN, int *M, int *P); 1371 1372#ifndef ioread32_native 1373#ifdef __BIG_ENDIAN 1374#define ioread16_native ioread16be 1375#define iowrite16_native iowrite16be 1376#define ioread32_native ioread32be 1377#define iowrite32_native iowrite32be 1378#else /* def __BIG_ENDIAN */ 1379#define ioread16_native ioread16 1380#define iowrite16_native iowrite16 1381#define ioread32_native ioread32 1382#define iowrite32_native iowrite32 1383#endif /* def __BIG_ENDIAN else */ 1384#endif /* !ioread32_native */ 1385 1386/* channel control reg access */ 1387static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1388{ 1389 return ioread32_native(chan->user + reg); 1390} 1391 1392static inline void nvchan_wr32(struct nouveau_channel *chan, 1393 unsigned reg, u32 val) 1394{ 1395 iowrite32_native(val, chan->user + reg); 1396} 1397 1398/* register access */ 1399static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1400{ 1401 struct drm_nouveau_private *dev_priv = dev->dev_private; 1402 return ioread32_native(dev_priv->mmio + reg); 1403} 1404 1405static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1406{ 1407 struct drm_nouveau_private *dev_priv = dev->dev_private; 1408 iowrite32_native(val, dev_priv->mmio + reg); 1409} 1410 1411static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1412{ 1413 u32 tmp = nv_rd32(dev, reg); 1414 nv_wr32(dev, reg, (tmp & ~mask) | val); 1415 return tmp; 1416} 1417 1418static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1419{ 1420 struct drm_nouveau_private *dev_priv = dev->dev_private; 1421 return ioread8(dev_priv->mmio + reg); 1422} 1423 1424static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1425{ 1426 struct drm_nouveau_private *dev_priv = dev->dev_private; 1427 iowrite8(val, dev_priv->mmio + reg); 1428} 1429 1430#define nv_wait(dev, reg, mask, val) \ 1431 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1432#define nv_wait_ne(dev, reg, mask, val) \ 1433 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1434 1435/* PRAMIN access */ 1436static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1437{ 1438 struct drm_nouveau_private *dev_priv = dev->dev_private; 1439 return ioread32_native(dev_priv->ramin + offset); 1440} 1441 1442static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1443{ 1444 struct drm_nouveau_private *dev_priv = dev->dev_private; 1445 iowrite32_native(val, dev_priv->ramin + offset); 1446} 1447 1448/* object access */ 1449extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1450extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1451 1452/* 1453 * Logging 1454 * Argument d is (struct drm_device *). 1455 */ 1456#define NV_PRINTK(level, d, fmt, arg...) \ 1457 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1458 pci_name(d->pdev), ##arg) 1459#ifndef NV_DEBUG_NOTRACE 1460#define NV_DEBUG(d, fmt, arg...) do { \ 1461 if (drm_debug & DRM_UT_DRIVER) { \ 1462 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1463 __LINE__, ##arg); \ 1464 } \ 1465} while (0) 1466#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1467 if (drm_debug & DRM_UT_KMS) { \ 1468 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1469 __LINE__, ##arg); \ 1470 } \ 1471} while (0) 1472#else 1473#define NV_DEBUG(d, fmt, arg...) do { \ 1474 if (drm_debug & DRM_UT_DRIVER) \ 1475 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1476} while (0) 1477#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1478 if (drm_debug & DRM_UT_KMS) \ 1479 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1480} while (0) 1481#endif 1482#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1483#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1484#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1485#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1486#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1487 1488/* nouveau_reg_debug bitmask */ 1489enum { 1490 NOUVEAU_REG_DEBUG_MC = 0x1, 1491 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1492 NOUVEAU_REG_DEBUG_FB = 0x4, 1493 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1494 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1495 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1496 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1497 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1498 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1499 NOUVEAU_REG_DEBUG_EVO = 0x200, 1500}; 1501 1502#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1503 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1504 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1505} while (0) 1506 1507static inline bool 1508nv_two_heads(struct drm_device *dev) 1509{ 1510 struct drm_nouveau_private *dev_priv = dev->dev_private; 1511 const int impl = dev->pci_device & 0x0ff0; 1512 1513 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1514 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1515 return true; 1516 1517 return false; 1518} 1519 1520static inline bool 1521nv_gf4_disp_arch(struct drm_device *dev) 1522{ 1523 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1524} 1525 1526static inline bool 1527nv_two_reg_pll(struct drm_device *dev) 1528{ 1529 struct drm_nouveau_private *dev_priv = dev->dev_private; 1530 const int impl = dev->pci_device & 0x0ff0; 1531 1532 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1533 return true; 1534 return false; 1535} 1536 1537static inline bool 1538nv_match_device(struct drm_device *dev, unsigned device, 1539 unsigned sub_vendor, unsigned sub_device) 1540{ 1541 return dev->pdev->device == device && 1542 dev->pdev->subsystem_vendor == sub_vendor && 1543 dev->pdev->subsystem_device == sub_device; 1544} 1545 1546static inline void * 1547nv_engine(struct drm_device *dev, int engine) 1548{ 1549 struct drm_nouveau_private *dev_priv = dev->dev_private; 1550 return (void *)dev_priv->eng[engine]; 1551} 1552 1553/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1554 * helpful to determine a number of other hardware features 1555 */ 1556static inline int 1557nv44_graph_class(struct drm_device *dev) 1558{ 1559 struct drm_nouveau_private *dev_priv = dev->dev_private; 1560 1561 if ((dev_priv->chipset & 0xf0) == 0x60) 1562 return 1; 1563 1564 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1565} 1566 1567/* memory type/access flags, do not match hardware values */ 1568#define NV_MEM_ACCESS_RO 1 1569#define NV_MEM_ACCESS_WO 2 1570#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1571#define NV_MEM_ACCESS_SYS 4 1572#define NV_MEM_ACCESS_VM 8 1573 1574#define NV_MEM_TARGET_VRAM 0 1575#define NV_MEM_TARGET_PCI 1 1576#define NV_MEM_TARGET_PCI_NOSNOOP 2 1577#define NV_MEM_TARGET_VM 3 1578#define NV_MEM_TARGET_GART 4 1579 1580#define NV_MEM_TYPE_VM 0x7f 1581#define NV_MEM_COMP_VM 0x03 1582 1583/* NV_SW object class */ 1584#define NV_SW 0x0000506e 1585#define NV_SW_DMA_SEMAPHORE 0x00000060 1586#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1587#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1588#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1589#define NV_SW_YIELD 0x00000080 1590#define NV_SW_DMA_VBLSEM 0x0000018c 1591#define NV_SW_VBLSEM_OFFSET 0x00000400 1592#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1593#define NV_SW_VBLSEM_RELEASE 0x00000408 1594#define NV_SW_PAGE_FLIP 0x00000500 1595 1596#endif /* __NOUVEAU_DRV_H__ */ 1597